Texas Instruments | UCC5390-Q1 Single-Channel Isolated Gate Driver for SiC/IGBT and Automotive Applications (Rev. A) | Datasheet | Texas Instruments UCC5390-Q1 Single-Channel Isolated Gate Driver for SiC/IGBT and Automotive Applications (Rev. A) Datasheet

Texas Instruments UCC5390-Q1 Single-Channel Isolated Gate Driver for SiC/IGBT and Automotive Applications (Rev. A) Datasheet
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UCC5390-Q1
SLUSDR3A – OCTOBER 2019 – REVISED NOVEMBER 2019
UCC5390-Q1 Single-Channel Isolated Gate Driver
for SiC/IGBT and Automotive Applications
1 Features
2 Applications
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5-kVRMS single channel isolated gate driver
AEC-Q100 qualified for automotive applications
– Temperature grade 1
– HBM ESD classification level H2
– CDM ESD classification level C6
12-V UVLO referenced to GND2
8-pin DWV (8.5mm creepage) package
60-ns (typical) propagation delay
Small part-to-part skew in propagation delay
100-V/ns minimum CMTI
10-A minimum peak current
3-V to 15-V input supply voltage
Up to 33-V driver supply voltage
Negative 5-V handling capability on input pins
Safety-related certifications:
– 7000-VPK isolation (DWV) per DIN V VDE V
0884-11:2017-01 (planned)
– 5000-VRMS (DWV) isolation rating for 1 minute
per UL 1577
– CQC Certification per GB4943.1-2011
CMOS inputs
Operating junction temperature: –40°C to +150°C
On-board charger
Traction inverter for EVs
DC charging stations
3 Description
The UCC5390-Q1 is a single-channel, isolated gate
driver with 10-A source and 10-A sink peak current
designed to drive MOSFETs, IGBTs, and SiC
MOSFETs. The UCC5390-Q1 has its UVLO2
referenced to GND2, which facilitates bipolar supplies
and optimizes SiC and IGBT switching behavior and
robustness.
The UCC5390-Q1 is available in 8.5 mm SOIC-8
(DWV) package and can support isolation voltage up
to 5-kVRMS. The input side is isolated from the output
side with SiO2 capacitive isolation technology with
longer than 40 years isolation barrier lifetime. With its
high drive strength and true UVLO detection, this
device is a good fit for driving IGBTs and SiC
MOSFETs in applications such as on-board chargers
and traction inverters.
Compared to an optocoupler, the UCC5390-Q1 has
lower part-to-part skew, lower propagation delay,
higher operating temperature, and higher CMTI.
4 Functional Block Diagram
5V
VCC2
VCC1
15V
UVLO2
IN±
GND1
UVLO
and
Input
Logic
ISOLATION
IN+
BARRIER
VCC2
Rest of
Circuit
UVLO,
Level
Shift
and
text
Control
Logic
OUT
GND2
VEE2 -8V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC5390-Q1
SLUSDR3A – OCTOBER 2019 – REVISED NOVEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Functional Block Diagram ....................................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications for DWV Package.............. 6
Safety-Related Certifications For DWV Package...... 6
Safety Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ........................... 9
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 12
8.1 Propagation Delay, Inverting, and Noninverting
Configuration............................................................ 12
9
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
18
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 20
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
12.3 PCB Material ......................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Documentation Support ........................................
Certifications .........................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
30
30
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2019) to Revision A
•
2
Page
Changed marketing status from Advance Information to production data. ........................................................................... 1
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6 Pin Configuration and Function
UCC5390-Q1
8-Pin SOIC
Top View
VCC1
1
8
VEE2
IN+
2
7
GND2
IN±
3
6
OUT
GND1
4
5
VCC2
Not to scale
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
GND1
4
G
Input ground. All signals on the input side are referenced to this ground.
GND2
7
G
Gate-drive common pin. Connect this pin to the IGBT emitter or MOSFET source. UVLO
referenced to GND2.
IN+
2
I
Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin
is pulled low internally if left open. Use Table 4 to understand the input and output logic of these
devices.
IN–
3
I
Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is
pulled high internally if left open. Use Table 4 to understand the input and output logic of these
devices.
OUT
6
O
Gate-drive output.
VCC1
1
P
Input supply voltage. Connect a locally decoupled capacitor to GND1. Use a low-ESR or ESL
capacitor located as close to the device as possible.
VCC2
5
P
Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or
ESL capacitor located as close to the device as possible.
VEE2
8
P
Negative output supply rail. Connect a locally decoupled capacitor to GND2. Use a low-ESR or
ESL capacitor located as close to the device as possible.
(1)
P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free air temperature range (unless otherwise noted) (1)
Input bias pin supply voltage
VCC1 – GND1
Driver bias supply
VCC2 – VEE2
VEE2 bipolar supply voltage
VEE2 – GND2
Output signal voltage
VOUT – VEE2
Input signal voltage
VIN+ – GND1, VIN– – GND1
MIN
MAX
UNIT
GND1 – 0.3
18
V
–0.3
35
V
–17.5
0.3
V
VEE2 – 0.3
VCC2 + 0.3
V
GND1 – 5
VCC1 + 0.3
V
Junction temperature, TJ (2)
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VCC1
Supply voltage, input side
VCC2
Positive supply voltage output side (VCC2 – GND2)
VEE2
Negative supply voltage output side (VEE2 – GND2)
VSUP2
Total supply voltage output side (VCC2 – VEE2)
TJ
Junction Temperature
-40
4
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NOM
MAX
UNIT
3
15
V
13.2
33
V
–16
0
V
13.2
33
V
150
°C
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7.4 Thermal Information
UCC5390-Q1
THERMAL METRIC (1)
DWV (SOIC)
UNIT
8 PINS
RθJA
Junction–to-ambient thermal resistance
119.8
°C/W
RθJC(top)
Junction–to-case (top) thermal resistance
64.1
°C/W
RθJB
Junction–to-board thermal resistance
65.4
°C/W
ΨJT
Junction–to-top characterization parameter
37.6
°C/W
ΨJB
Junction–to-board characterization parameter
63.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.04
W
0.05
W
0.99
W
DWV Package
PD
PD1
PD2
Maximum power dissipation on input and
VCC1 = 15 V, VCC2 = 15 V, f = 1.9-MHz,
output
50% duty cycle, square wave, 2.2-nF
Maximum input power dissipation
load
Maximum output power dissipation
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7.6 Insulation Specifications for DWV Package
PARAMETER
VALUE
TEST CONDITIONS
DWV
UNIT
External Clearance (1)
Shortest pin–to-pin distance through air
≥ 8.5
mm
CPG
External Creepage (1)
Shortest pin–to-pin distance across the package
surface
≥ 8.5
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
> 21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303–11); IEC 60112
> 600
V
Material Group
According to IEC 60664–1
CLR
Overvoltage category per IEC 60664-1
DIN V VDE 0884–11: 2017–01
I-III
Rated mains voltage ≤ 1000 VRMS
I-II
(2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum isolation working
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage (3)
qpd
I
Rated mains voltage ≤ 600 VRMS
Apparent charge
(4)
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output (5)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test
1500
VRMS
DC Voltage
2121
VDC
VTEST = VIOTM, t = 60 s (qualification) ;
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
7000
VPK
Test method per IEC 62368-1, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
1.2
VIO = 500 V, TA = 25°C
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 ×
VISO, t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
7.7 Safety-Related Certifications For DWV Package
6
VDE
UL
CQC
Plan to certify according to DIN V VDE V
0884–11:2017–01 and DIN EN 61010-1
Recognized under UL 1577
Component Recognition Program
Certified according to GB 4943.1–2011
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Safety-Related Certifications For DWV Package (continued)
VDE
UL
CQC
Reinforced Insulation
Maximum Transient Isolation Overvoltage, 7000 VPK;
Maximum Repetitive Peak Isolation Voltage, 2121 VPK;
Maximum Surge Isolation Voltage, 8000 VPK
Single protection, 5000 VRMS
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate
Certification planned
File Number: E181974
Certification Number: CQC19001226950
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DWV PACKAGE
IS
PS
TS
(1)
Safety input, output,
or supply current
Safety input, output,
or total power
RθJA = 119.8°C/W, VI = 15 V, TJ = 150°C, TA = 25°C, see
Output side
Figure 1
66
RθJA = 119.8°C/W, VI = 30 V, TJ = 150°C, TA = 25°C, see
Output side
Figure 1
33
RθJA = 119.8°C/W, TJ = 150°C, TA = 25°C, see Figure 2
mA
Input side
0.05
Output side
0.99
Total
1.04
Maximum safety
temperature (1)
150
W
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ =
–40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.67
2.4
mA
1.1
1.8
mA
2.6
2.8
V
SUPPLY CURRENTS
IVCC1
Input supply quiescent current
IVCC2
Output supply quiescent
current
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1)
VCC1 Positive-going UVLO
threshold voltage
VIT– (UVLO1)
VCC1 Negative-going UVLO
threshold voltage
Vhys(UVLO1)
VCC1 UVLO threshold
hysteresis
2.4
2.5
V
0.1
V
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO2)
VCC2 Positive-going UVLO
threshold voltage
VIT–(UVLO2)
VCC2 Negative-going UVLO
threshold voltage
Vhys(UVLO2)
VCC2 UVLO threshold voltage
hysteresis
12
10.3
13
V
11
V
1
V
LOGIC I/O
VIT+(IN)
Positive-going input threshold
voltage (IN+, IN–)
VIT–(IN)
Negative-going input threshold
voltage (IN+, IN–)
Vhys(IN)
Input hysteresis voltage (IN+,
IN–)
IIH
High-level input leakage at IN+ IN+ = VCC1
IIL
Low-level input leakage at IN–
0.3 × VCC1
0.55 × VCC1 0.7 × VCC1
V
0.45 × VCC1
V
0.1 × VCC1
V
40
240
µA
IN– = GND1
–240
–40
IN– = GND1 – 5 V
–310
–80
VCC2 – 0.1
VCC2 – 0.24
2
3
mV
µA
GATE DRIVER STAGE
VOH
High-level output voltage
(OUT)
IOUT = –20 mA
VOL
Low level output voltage
(OUT)
IN+ = low, IN– = high; IO = 20 mA
IOH
Peak source current
IN+ = high, IN– = low
10
17
A
IOL
Peak sink current
IN+ = low, IN– = high
10
17
A
V
SHORT CIRCUIT CLAMPING
VCLP-OUT
Clamping voltage
(VOUT –VCC2)
VCLP-OUT
Clamping voltage
( VEE2 – VOUT)
IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUT= 500 mA
1
IN+ = low, IN– = high, tCLAMP = 10 µs,
IOUT = –500 mA
1.5
IN+ = low, IN– = high,
IOUT = –20 mA
0.9
1
IOUT = 0.1 × IOUT(typ), VCC2 = open
1.8
2.5
1.3
V
V
ACTIVE PULLDOWN
VOUTSD
8
Active pulldown voltage on
OUT
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7.10 Switching Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TJ = –40°C to
+125°C, (unless otherwise noted)
TYP
MAX
tr
Output-signal rise time
PARAMETER
CLOAD = 1 nF
10
26
ns
tf
Output-signal fall time
CLOAD = 1 nF
10
22
ns
tPLH
Propagation delay, high
CLOAD = 100 pF
65
100
ns
tPHL
Propagation delay, low
CLOAD = 100 pF
65
100
tUVLO1_rec
UVLO recovery delay of VCC1
30
µs
tUVLO2_rec
UVLO recovery delay of VCC2
50
µs
tPWD
Pulse width distortion
|tPHL – tPLH|
CLOAD = 100 pF
1
20
ns
tsk(pp)
Part-to-part skew (1)
CLOAD = 100 pF
1
25
ns
CMTI
Common-mode transient
immunity
PWM is tied to GND or VCC1, VCM = 1200 V
(1)
TEST CONDITIONS
MIN
100
120
UNIT
ns
kV/µs
tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.
7.11 Insulation Characteristics Curves
1500
80
Safety Limiting Power (mW)
Safety Limiting Current (mA)
VCC2=15V
VCC2=30V
60
40
20
1200
900
600
300
0
0
0
50
100
150
Ambient Temperature (qC)
0
200
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DWV Package
50
100
150
Ambient Temperature (qC)
200
Figure 2. Thermal Derating Curve for Limiting Power per
VDE for DWV Package
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7.12 Typical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TJ =
–40°C to +125°C, (unless otherwise noted)
24
Peak Output Current Low IOL (A)
Peak Output Current High IOH (A)
25
22
19
16
13
10
14
17
20
23
26
VCC2 (V)
29
32
21
18
15
12
14
34
17
20
23
26
VCC2 (V)
29
32
34
CLOAD = 150 nF
Figure 3. Output-High Drive Current vs Output Voltage
Figure 4. Output-Low Drive Current vs Output Voltage
2.7
2.7
2.4
2.4
ICC1 Supply Current (mA)
ICC1 Supply Current (mA)
CLOAD = 150 nF
2.1
1.8
1.5
1.2
-40
-20
0
IN+ = L
20
40
60
80
Temperature (qC)
100
120
1.5
1.2
0.6
-60
140
IN– = H
-40
-20
0
IN+ = H
Figure 5. ICC1 Supply Current vs Temperature
3
1.79
2.6
1.76
1.73
1.7
1.67
20
40
60
80
Temperature (qC)
100
120
140
IN– = L
Figure 6. ICC1 Supply Current vs Temperature
1.82
ICC2 Supply Current (mA)
ICC1 Supply Current (mA)
1.8
0.9
0.9
0.6
-60
2.1
2.2
1.8
1.4
1
1.64
1.61
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (MHz)
Duty Cycle = 50%
0.8
0.9
0.6
-60
1
-40
-20
T = 25°C
0
20
40
60
80
Temperature (qC)
100
120
140
IN+ = L
Figure 7. ICC1 Supply Current vs Input Frequency
IN– = H
Figure 8. ICC2 Supply Current vs Temperature
1.68
3
ICC2 Supply Current (mA)
ICC2 Supply Current (mA)
2.6
2.2
1.8
1.4
1.56
1.44
1.32
1
0.6
-60
-40
-20
0
20
40
60
80
Temperature (qC)
IN+ = H
100
120
1.2
0.1
140
IN– = L
Figure 9. ICC2 Supply Current vs Temperature
10
Duty Cycle = 50%
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (MHz)
0.8
0.9
1
T = 25°C
Figure 10. ICC2 Supply Current vs Input Frequency
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Typical Characteristics (continued)
2.26
12.5
2.08
11.5
1.9
Rise Time tr (ns)
Output-side Supply Current (mA)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TJ =
–40°C to +125°C, (unless otherwise noted)
1.72
1.54
10.5
1.36
9.5
8.5
7.5
1.18
6.5
-60
1
0
2
4
6
Load Capacitance (nF)
8
10
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
fSW = 1 kHz
Figure 12. Rise Time vs Temperature
11.5
65
10.5
61
Propagation Delay tPLH (ns)
Fall Time tf (ns)
Figure 11. ICC2 Supply Current vs Load Capacitance
9.5
8.5
7.5
6.5
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
53
49
45
-60
140
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
Figure 14. Propagation Delay tPLH vs Temperature
Figure 13. Fall Time vs Temperature
28
56
24
54.5
Rise Time tr (ns)
Propagation Delay tPHL (ns)
57
53
20
16
12
51.5
8
50
-60
4
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
fSW = 1 kHz
Figure 15. Propagation Delay tPHL vs Temperature
2
4
6
Load Capacitance (nF)
8
RGH = 0 Ω
10
RGL = 0 Ω
Figure 16. Rise Time vs Load Capacitance
40
36
Rise Time tf (ns)
32
28
24
20
16
12
8
4
0
fSW = 1 kHz
2
4
6
Load Capacitance (nF)
8
10
RGH = 0 Ω
RGL = 0 Ω
Figure 17. Fall Time vs Load Capacitance
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8 Parameter Measurement Information
8.1 Propagation Delay, Inverting, and Noninverting Configuration
Figure 18 shows the propagation delay for noninverting configurations. Figure 19 shows the propagation delay
with the inverting configuration. These figures also demonstrate the method used to measure the rise (tr) and fall
(tf) times.
0V
IN±
50%
tf
tr
IN+
90%
50%
OUT
10%
tPLH
tPHL
Figure 18. Propagation Delay, Noninverting Configuration
IN±
50%
IN+
tf
tr
90%
50%
OUT
10%
tPLH
tPHL
Figure 19. Propagation Delay, Inverting Configuration
12
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Propagation Delay, Inverting, and Noninverting Configuration (continued)
8.1.1 CMTI Testing
Figure 20 is a simplified diagram of the CMTI testing configuration.
15 V
5V
VCC2
VCC1
C3
ISOLATION B ARRIER
C2
C1
GND1
PWM
IN+
C4
OUT
GND2
IN±
VEE2
+
VCM
±
Figure 20. CMTI Test Circuit for UCC5390-Q1
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9 Detailed Description
9.1 Overview
The isolation inside the UCC5390-Q1 is implemented with high-voltage SiO2-based capacitors. The signal across
the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide
based isolation barrier (see Figure 22). The transmitter sends a high-frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. The UCC5390-Q1 also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions from the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 21, shows a functional block diagram of a typical channel. Figure 22 shows a
conceptual detail of how the OOK scheme works.
Figure 21 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK)
and signal conditioning.
9.2 Functional Block Diagram
Transmitter
TX IN
Receiver
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Figure 21. Conceptual Block Diagram of a Capacitive Data Channel
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 22. On-Off Keying (OOK) Based Modulation Scheme
14
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Functional Block Diagram (continued)
VCC1
BARRIER
VCC2
Level
Shifting
and
Control
Logic
ISOLATION
IN+
VCC2
UVLO2
UVLO1
IN±
OUT
GND2
GND1
VEE2
Figure 23. Functional Block Diagram — UVLO With Respect to GND2 (UCC5390-Q1)
9.3 Feature Description
9.3.1 Power Supply
The VCC1 input power supply supports a wide voltage range from 3 V to 15 V and the VCC2 output supply
supports a voltage range from 9.5 V to 33 V. For operation with bipolar supplies, the power device is turned off
with a negative voltage on the gate with respect to the emitter or source. This configuration prevents the power
device from unintentionally turning on because of current induced from the Miller effect. The typical values of the
VCC2 and VEE2 output supplies for bipolar operation are 15 V and –8 V with respect to GND2 for IGBTs and 20 V
and –5 V for SiC MOSFETs.
For operation with unipolar supply, the VCC2 supply is connected to 15 V with respect to VEE2 for IGBTs, and 20
V for SiC MOSFETs. The VEE2 supply is connected to 0 V.
9.3.2 Input Stage
The input pins (IN+ and IN–) of the UCC5390-Q1 are based on CMOS-compatible input-threshold logic that is
completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals
(such as those from 3.3-V microcontrollers), because the UCC5390-Q1 has a typical high threshold (VIT+(IN)) of
0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good
noise immunity and stable operation. If any of the inputs are left open, 128 kΩ of internal pulldown resistance
forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding
an input or tying to VCC1 if it is not being used for improved noise immunity.
Because the input side of the UCC5390-Q1 is isolated from the output driver, the input signal amplitude can be
larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows greater
flexibility when integrating the gate-driver with control signal sources and allows the user to choose the most
efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a voltage
higher than VCC1.
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Feature Description (continued)
9.3.3 Output Stage
The output stage of the UCC5390-Q1 features a pullup structure that delivers the highest peak-source current
when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the
power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a Pchannel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing
states from low to high. Table 1 lists the typical internal resistance values of the pullup and pulldown structure.
Table 1. UCC5390-Q1 On-Resistance
DEVICE OPTION
RNMOS
ROH
ROL
UNIT
UCC5390-Q1
0.76
12
0.13
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device
only. This parameter is only for the P-channel device, because the pullup N-channel device is held in the OFF
state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.
Therefore, the effective resistance of the UCC5390-Q1 pullup stage during this brief turnon phase is much lower
than what is represented by the ROH parameter, which yields a faster turnon. The turnon-phase output resistance
is the parallel combination ROH || RNMOS.
The pulldown structure in the UCC5390-Q1 is simply composed of an N-channel MOSFET. The output of the
UCC5390-Q1 is capable of delivering, or sinking, 10-A peak current pulses. The output voltage swing between
VCC2 and VEE2 provides rail-to-rail operation because of the MOS-out stage which delivers very low dropout.
UVLO2
Level
Shifting
and
Control
Logic
VCC2
ROH
RNMOS
OUT
ROL
GND2
VEE2
Figure 24. Output Stage
9.3.4 Protection Features
9.3.4.1 Undervoltage Lockout (UVLO)
UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2
and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO)
at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected
output low, regardless of the input pins (IN+ and IN–) as shown in Table 2. The VCC UVLO protection has a
hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise;
this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and
operating current consumption increases suddenly. Figure 25 shows the UVLO functions.
16
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Table 2. UCC5390-Q1 VCC1 UVLO Logic
INPUTS
CONDITION
IN+
VCC1 – GND1 < VIT+(UVLO1) during device start-up
VCC1 – GND1 < VIT–(UVLO1) after device start-up
OUTPUT
IN–
OUT
H
L
L
L
H
L
H
H
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
L
Table 3. UCC5390-Q1 VCC2 UVLO Logic
INPUTS
CONDITION
VCC2 – VEE2 < VIT+(UVLO2) during device start-up
VCC2 – VEE2 < VIT–(UVLO2) after device start-up
OUTPUT
IN+
IN–
OUT
H
L
L
L
H
L
H
H
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
L
When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the
output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. Figure 25 shows this delay.
IN+
VCC1
IN+
VIT+ (UVLO1)
VIT±(UVLO1)
VCC1
VCC2
VCC2
VIT+ (UVLO2)
VIT± (UVLO2)
tUVLO2_rec
tUVLO1_rec
VOUT
VOUT
Figure 25. UVLO Functions
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9.3.4.2 Active Pulldown
The active pulldown function is used to pull the IGBT or MOSFET gate to the low state when no power is
connected to the VCC2 supply. This feature prevents false IGBT and MOSFET turnon on the OUT pin by
clamping the output to approximately 2 V.
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is
resistively held off by a pullup resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ
resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS
device, which is approximately 1.5 V when no bias power is available.
9.3.4.3 Short-Circuit Clamping
The short-circuit clamping function is used to clamp voltages at the driver output slightly higher than the VCC2
voltage during short-circuit conditions. The short-circuit clamping function helps protect the IGBT or MOSFET
gate from overvoltage breakdown or degradation. The short-circuit clamping function is implemented by adding a
diode connection between the dedicated pins and the VCC2 pin inside the driver. The internal diodes can conduct
up to 500-mA current for a duration of 10 µs and a continuous current of 20 mA. Use external Schottky diodes to
improve current conduction capability as needed.
9.4 Device Functional Modes
lists the functional modes for the UCC5390-Q1 assuming VCC1 and VCC2 are in the recommended range.
Table 4. Function Table
18
IN+
IN–
OUT
Low
X
Low
X
High
Low
High
Low
High
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9.4.1 ESD Structure
Figure 26 shows the multiple diodes involved in the ESD protection components of the UCC5390-Q1. This
provides pictorial representation of the absolute maximum rating for the device.
IN+
VCC1
VCC2
1
5
2
6
20 V
IN±
OUT
40 V
3
5.5 V
4
8
GND1
VEE2
Figure 26. ESD Structure
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCC5390-Q1 is a simple, isolated gate driver for power semiconductor devices, such as MOSFETs, IGBTs,
or SiC MOSFETs. The family of devices is intended for use in applications such as motor control, solar inverters,
switched-mode power supplies, and industrial inverters.
10.2 Typical Application
The circuit in Figure 27 show a typical application for driving IGBTs.
15 V
VCC2
5V
VCC1
C1
C3
C4
C2
GND1
RG
OUT
Rin
PWM
IN+
Cin
GND2
IN±
C5
C3
VEE2
±8V
Figure 27. Typical Application Circuit for UCC5390-Q1 to Drive IGBT
10.2.1 Design Requirements
Table 5 lists the recommended conditions to observe the input and output of the UCC5390-Q1 gate driver with
the IN– pin tied to the GND1 pin.
Table 5. UCC5390-Q1 Design Requirements
VALUE
UNIT
VCC1
PARAMETER
3.3
V
VCC2
18
V
VEE2
-3
V
IN+
3.3
V
IN–
GND1
-
Switching frequency
300
kHz
Gate Charge of Power Device
126
nC
10.2.2 Detailed Design Procedure
10.2.2.1 Designing IN+ and IN– Input Filter
TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the
signal at the output. However, a small input filter, RIN-CIN, can be used to filter out the ringing introduced by
nonideal layout or long PCB traces.
20
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Such a filter should use an RIN resistor with a value from 0 Ω to 100 Ω and a CIN capacitor with a value from 10
pF to 1000 pF. In the example, the selected value for RIN is 51 Ω and CIN is 33 pF, with a corner frequency of
approximately 100 MHz.
When selecting these components, pay attention to the trade-off between good noise immunity and propagation
delay.
10.2.2.2 Gate-Driver Output Resistor
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)
The output stage has a pullup structure consisting of a P-channel MOSFET and an N-channel MOSFET in
parallel. The combined peak source current is 17 A for UCC5390-Q1 . Use Equation 1 to estimate the peak
source current.
§
VCC2 VEE2
min ¨ 17 A,
¨
RNMOS || ROH RON RGFET _ Int
©
IOH
·
¸
¸
¹
where
•
•
RON is the external turnon resistance, which is 2.2 Ω in this example.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will
assume 1.8Ω for our example.
IOH is the peak source current which is the minimum value between 17 A, the gate-driver peak source current,
and the calculated value based on the gate-drive loop resistance.
(1)
•
In this example, the peak source current is approximately 4.45 A as calculated in Equation 2.
IOH
RNMOS
VCC2 VEE2
|| ROH RON RGFET _ Int
21 V
| 4.45 A
0.76 : || 12 : 2.2 : 1.8 :
(2)
Similarly, use Equation 3 to calculate the peak sink current.
§
VCC2 VEE2
min ¨ 17 A,
¨
ROL R OFF RGFET _ Int
©
IOL
·
¸
¸
¹
where
•
•
ROFF is the external turnoff resistance, which is 2.2 Ω in this example.
IOL is the peak sink current which is the minimum value between 17 A, the gate-driver peak sink current, and
the calculated value based on the gate-drive loop resistance.
(3)
In this example, the peak sink current is the minimum of Equation 4 and 17 A.
IOL
ROL
VCC2 VEE2
ROFF RGFET _ Int
21 V
| 5.08 A
0.13 : 2.2 : 1.8 :
(4)
NOTE
The estimated peak current is also influenced by PCB layout and load capacitance.
Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and
introduce overshoot and undershoot. Therefore, TI strongly recommends that the gatedriver loop should be minimized. Conversely, the peak source and sink current is
dominated by loop parasitics when the load capacitance (CISS) of the power transistor is
very small (typically less than 1 nF) because the rising and falling time is too small and
close to the parasitic ringing period.
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10.2.2.3 Estimate Gate-Driver Power Loss
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC5390-Q1 device and
the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC5390-Q1
device, and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is
measured on the bench with no load connected to the OUT pins at a given VCC1, VCC2, switching frequency, and
ambient temperature. In this example, VCC1 is 3.3V, VCC2 is 18 V and VEE2 is -3 V. The current on each power
supply, with PWM switching from 0 V to 3.3 V at 300 kHz, is measured to be ICC1 = 1.67 mA and ICC2 = 1.28 mA.
Therefore, use Equation 5 to calculate PGDQ.
PGDQ VCC1 u IVCC1 (VCC2
VEE2 ) u ICC2 | 32.4mW
(5)
The second component is the switching operation loss, PGDO, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Use Equation 6 to calculate the total dynamic loss
from load switching, PGSW.
PGSW
(VCC2
VEE2 ) u QG u fSW
where
•
QG is the gate charge of the power transistor at VCC2.
(6)
So, for this example application the total dynamic loss from load switching is approximately 793.8 mW as
calculated in Equation 7.
PGSW
21 V u 126 nC u 300 kHz
793.8 mW
(7)
QG represents the total gate charge of the power transistor, and is subject to change with different testing
conditions. The UCC5390-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if
the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss
will be dissipated inside the UCC5390-Q1. If an external turn-on and turn-off resistance exists, the total loss is
distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor
internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink
current is not saturated to 17 A, however, it will be non-linear if the source/sink current is saturated. Therefore,
PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
PGDO
PGSW
2
§
ROH || RNMOS
¨
¨ ROH || RNMOS RON RGFET _ Int
©
ROL
ROL
ROFF
RGFET _ Int
·
¸
¸
¹
(8)
In this design example, all the predicted source and sink currents are less than 17 A, therefore, use Equation 9
to estimate the UCC5390-Q1 gate-driver loss.
PGDO
793.8 mW §
12 : || 0.76 :
¨
2
© 12 : || 0.76 : 2.2 : 1.8 :
·
0.13 :
¸ | 72.66 mW
0.13 : 2.2 : 1.8 : ¹
(9)
Case 2 - Nonlinear Pull-Up/Down Resistor:
PGDO fSW
TR _ Sys
ª
«
VCC2
u 17 A u
«
0
«¬
³
TF _ Sys
VOUTH (t) dt 17 A u
³
0
º
(VOUTL (t) VEE2 )dt »
»
»¼
where
•
22
VOUTH/L(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is
saturated for some time, this value can be simplified as a constant-current source (17 A at turnon and turnoff)
charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and the TR_Sys and TF_Sys
can be easily predicted.
(10)
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For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is
a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based
on this discussion.
Use Equation 11 to calculate the total gate-driver loss dissipated in the UCC5390-Q1 gate driver, PGD.
PGD
PGDQ
PGDO
32.4mW
72.66mW
105.06mW
(11)
10.2.2.4 Estimating Junction Temperature
Use Equation 12 to estimate the junction temperature (TJ) of the UCC5390-Q1 family.
TJ TC < JT u PGD
where
•
•
TC is the UCC5390-Q1 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the table.
(12)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming
that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the
application environment. As long as the recommended layout guidelines are observed, junction temperature
estimations can be made accurately to within a few degrees Celsius.
10.2.3 Selecting VCC1 and VCC2 Capacitors
Bypass capacitors for the VCC1 and VCC2 supplies are essential for achieving reliable performance. TI
recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients, and capacitance tolerances.
NOTE
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,
1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.
10.2.3.1 Selecting a VCC1 Capacitor
A bypass capacitor connected to the VCC1 pin supports the transient current required for the primary logic and the
total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is
recommended for this application. If the bias power-supply output is located a relatively long distance from the
VCC1 pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the
MLCC.
10.2.3.2 Selecting a VCC2 Capacitor
A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC2 capacitor. If the bias power supply
output is located a relatively long distance from the VCC2 pin, a tantalum or electrolytic capacitor with a value
greater than 10 μF should be used in parallel with CVCC2.
10.2.3.3 Application Circuits With Output Stage Negative Bias
When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220
and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turnon and shoot-through
could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the
threshold. A few examples of implementing negative gate-drive bias follow.
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Figure 28 shows another example which uses two supplies (or single-input, double-output power supply). The
power supply across VCC2 and GND2 determines the positive drive output voltage and the power supply across
VEE2 and GND2 determines the negative turnoff voltage. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
VCC2
VCC1
CA1
+
±
GND1
RG
OUT
GND2
IN+
+
CA2
±
IN±
VEE2
Figure 28. Negative Bias With Two Iso-Bias Power Supplies
10.2.4 Application Curve
VCC2 = 20 V
VEE2 = GND fSW = 10 kHz
Figure 29. PWM Input And Gate Voltage Waveform
11 Power Supply Recommendations
The recommended input supply voltage (VCC1) for the UCC5390-Q1 device is from 3 V to 15 V. The lower limit of
the range of output bias-supply voltage (VCC2) is determined by the internal UVLO protection feature of the
device. The VCC1 and VCC2 voltages should not fall below their respective UVLO thresholds for normal operation,
or else the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature. For
more information on UVLO, see the Undervoltage Lockout (UVLO) section. The higher limit of the VCC2 range
depends on the maximum gate voltage of the power device that is driven by the UCC5390-Q1 device, and
should not exceed the recommended maximum VCC2 of 33 V. A local bypass capacitor should be placed
between the VCC2 and VEE2 pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an
additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both
capacitors should be positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors
are recommended. Similarly, a bypass capacitor should also be placed between the VCC1 and GND1 pins. Given
the small amount of current drawn by the logic circuitry within the input side of the UCC5390-Q1 device, this
bypass capacitor has a minimum recommended value of 100 nF.
24
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If only a single, primary-side power supply is available in an application, isolated power can be generated for the
secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet.
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12 Layout
12.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC5390-Q1. Some
key guidelines are:
• Component placement:
– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1
pins and between the VCC2 and VEE2 pins to bypass noise and to support high peak currents when turning
on the external power transistor.
– To avoid large negative transients on the VEE2 pins connected to the switch node, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• Grounding considerations:
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
• High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. A PCB cutout or groove is recommended in order to prevent
contamination that may compromise the isolation performance.
• Thermal considerations:
– A large amount of power may be dissipated by the UCC5390-Q1 if the driving voltage is high, the load is
heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss
section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-toboard thermal impedance (θJB).
– Increasing the PCB copper connecting to the VCC2 and VEE2 pins is recommended, with priority on
maximizing the connection to VEE2. However, the previously mentioned high-voltage PCB considerations
must be maintained.
– If the system has multiple layers, TI also recommends connecting the VCC2 and VEE2 pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the
IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different
high voltage planes are overlapping.
26
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12.2 Layout Example
Figure 30 shows a PCB layout example with the signals and key components labeled.
(1)
No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
Figure 30. Layout Example
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Layout Example (continued)
Figure 31 and Figure 32 show the top and bottom layer traces and copper.
Figure 31. Top-Layer Traces and Copper
Figure 32. Bottom-Layer Traces and Copper (Flipped)
28
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Layout Example (continued)
Figure 33 shows the 3D layout of the top view of the PCB.
Figure 33. 3-D PCB View
12.3 PCB Material
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the selfextinguishing flammability-characteristics.
Figure 34 shows the recommended layer stack.
High-speed traces
10 mils
Ground plane
40 mils
Keep this space
free from planes,
traces, pads, and
vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 34. Recommended Layer Stack
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Instruments, UCC53x0xD Evaluation Module user's guide
13.2 Certifications
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate
Number: 20170718-E181974,
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC5390ECQDWVQ1
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
5390ECQ
UCC5390ECQDWVRQ1
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
5390ECQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Nov-2019
OTHER QUALIFIED VERSIONS OF UCC5390-Q1 :
• Catalog: UCC5390
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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