Texas Instruments | UCD90160A 16-Rail Power Supply Sequencer and Monitor With ACPI Support (Rev. B) | Datasheet | Texas Instruments UCD90160A 16-Rail Power Supply Sequencer and Monitor With ACPI Support (Rev. B) Datasheet

Texas Instruments UCD90160A 16-Rail Power Supply Sequencer and Monitor With ACPI Support (Rev. B) Datasheet
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UCD90160A
SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
UCD90160A 16-Rail Power Supply Sequencer and Monitor With ACPI Support
1 Features
3 Description
•
The UCD90160A is a 16-rail PMBus/I2C addressable
power supply sequencer and monitor. The device
integrates a 12-bit ADC for monitoring up to 16 power
supply voltage inputs. Twenty-six GPIO pins can be
used for power supply enables, power-on reset
signals, external interrupts, cascading, or other
system functions. Twelve of these pins offer PWM
functionality. Using these pins, the UCD90160A offers
support for margining, and general-purpose PWM
functions.
1
•
•
•
•
•
•
•
•
•
•
Monitor and sequence 16 voltage rails
– All rails sampled every 400 μs
– 12-Bit ADC with 2.5-V, 0.5% internal VREF
– Sequence based on time, rail and pin
dependencies
– Four programmable undervoltage and
overvoltage thresholds per monitor
Nonvolatile error and peak-value logging per
monitor (up to 12 fault detail entries)
Closed-loop margining for 10 rails
– Margin output adjusts rail voltage to match
user-defined margin thresholds
Programmable watchdog timer and system reset
Easily cascade multiple power sequencers and
take coordinated fault responses
Pin selected rail states for ACPI support
Flexible digital I/O configuration
Cascading multiple devices
Response and monitor to GPI-triggered fault
Multi-phase PWM clock generator
– Clock frequencies from 15.259 kHz to 125
MHz
– Capability to configure independent clock
outputs for synchronizing switch-mode power
supplies
JTAG and I2C/SMBus/PMBus™ interfaces
2 Applications
•
•
•
•
•
•
•
Wired networking
Wireless infrastructure
Datacom module
Data center and enterprise computing
Factory automation and control
Test and measurement
Medical
Specific power states can be achieved using the PinSelected Rail States feature. This feature allows with
the use of up to 3 GPIs to enable and disable any
rail. This is useful for implementing system low-power
modes and the Advanced Configuration and Power
Interface (ACPI) specification that is used for
hardware devices.
The Fault Pin feature enables easily cascading
multiple devices and coordinates among those
devices to take synchronized fault responses.
The TI Fusion Digital Power™ designer software is
provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive
interface for configuring, storing, and monitoring all
system operating parameters.
Device Information(1)
PART NUMBER
PACKAGE
UCD90160A
BODY SIZE (NOM)
VQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
12-V OUT
12 V
3.3-V Supply
12-V OUT
V33A
V33D
VMON
VOUT
3.3 V
VMON
VOUT
1.8 V
VMON
VOUT
0.8 V
VMON
GPIO
VOUT
3.3 V
GPIO
EN
VIN
VOUT
DC-DC1
VFB
UCD90160A
VMON
VMON
VMON
VMON
WDI from main
processor
GPIO
VIN
GPIO
EN
VOUT
VOUT
1.8 V
LDO1
WDO
GPIO
POWER_GOOD
GPIO
WARN_OV_ 0.8 V
or WARN_OV_12 V
GPIO
SYSTEM_RESET
GPIO
GPIO
EN
VIN
VOUT
VOUT
0.8 V
DC-DC2
VFB
Other sequencer
done (cascade input)
GPIO
I2C/PMBUS
2 MHz
PWM
JTAG
VMARG
Closed loop
margining
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD90160A
SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6
6
6
6
7
8
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
7.5 Programming........................................................... 40
8
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 45
9 Power Supply Recommendations...................... 48
10 Layout................................................................... 48
10.1 Layout Guidelines ................................................. 48
10.2 Layout Example .................................................... 49
11 Device and Documentation Support ................. 51
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
51
51
51
51
51
51
51
10
10
10
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 51
Changes from Revision A (February 2018) to Revision B
Page
4 Revision History
•
Changed Applications list ...................................................................................................................................................... 1
•
Changed "52" to "53" ............................................................................................................................................................. 5
Changes from Original (September 2016) to Revision A
Page
•
Changed the Timing Requirements table .............................................................................................................................. 8
•
Changed Figure 28 .............................................................................................................................................................. 38
2
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SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
5
MON5
TMS/GPIO22
39
6
MON6
TRST
40
55
MON7
56
MON8
GPIO1
11
57
MON9
GPIO2
12
58
MON10
GPIO3
13
59
MON11
GPIO4
14
NC1
MON14
AVSS1
49
MON16
50
MON7
54
51
MON8
55
NC2
MON9
56
MON15
MON10
57
52
MON11
58
38
PMBUS_ADDR1
TDI/GPIO21
59
MON4
PMBUS_ADDR0
4
60
37
MON12
TDO/GPIO20
61
MON3
MON13
36
3
62
10
TCK/GPIO19
AVSS3
TRCK
MON2
63
MON1
2
64
1
53
RGC Package
64-Pin VQFN
Top View
BPCAP
V33D
V33A
V33DIO1
V33DIO2
7 44 45 46 47
MON1
1
MON2
2
47
BPCap
MON3
3
46
V33A
48
AVSS2
MON4
4
45
V33D
MON5
5
44
V33DIO2
MON6
6
43
DVSS3
V33DIO1
7
42
PWM3/GPI3
DVSS1
8
41
PWM4/GPI4
RESET
9
40
TRST
TRCK
10
39
TMS/GPIO22
GPIO1
11
38
TDI/GPIO21
GPIO2
12
37
TDO/GPIO20
Thermal
Pad
21
FPWM6/GPIO10
22
FPWM7/GPIO11
23
FPWM8/GPIO12
24
RESET
9
PMBUS_ADDR0
60
PMBUS_ADDR1
31
PWM1/GPI1
32
PWM2/GPI2
42
PWM3/GPI3
41
PWM4/GPI4
51
NC1
53
NC2
AVSS3
61
DVSS1
PMBUS_CNTRL
32
20
FPWM5/GPIO9
28
PWM2/GPI2
19
FPWM4/GPIO8
PMBUS_ALERT
31
18
FPWM3/GPIO7
PMBUS_DATA
27
30
17
FPWM2/GPIO6
16
GPIO15
FPWM1/GPIO5
PMBUS_CLK
PWM1/GPI1
35
15
29
34
GPIO18
GPIO14
GPIO17
28
MON16
PMBUS_CNTRL
54
27
33
PMBALERT
GPIO16
26
MON15
DVSS2
GPIO16
52
25
33
GPIO13
16
24
PMBUS_DATA
FPWM8/GPIO12
GPIO17
30
23
34
GPIO15
FPWM7/GPIO11
15
MON14
22
PMBUS_CLK
50
FPWM6/GPIO10
GPIO18
21
35
FPWM5/GPIO9
14
20
GPIO4
FPWM4/GPIO8
29
19
GPIO14
FPWM3/GPIO7
MON13
18
TCK/GPIO19
63
17
36
FPWM2/GPIO6
13
FPWM1/GPIO5
GPIO3
AVSS1
25
AVSS2
GPIO13
DVSS3
MON12
DVSS2
62
8 26 43 48 49 64
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Pin Functions (1)
PIN
NAME
NO.
I/O
DESCRIPTION
ANALOG MONITOR INPUTS
MON1
1
I
Analog input (0 to 2.5 V)
MON2
2
I
Analog input (0 to 2.5 V)
MON3
3
I
Analog input (0 to 2.5 V)
MON4
4
I
Analog input (0 to 2.5 V)
MON5
5
I
Analog input (0 to 2.5 V)
MON6
6
I
Analog input (0 to 2.5 V)
MON7
55
I
Analog input (0 to 2.5 V)
MON8
56
I
Analog input (0 to 2.5 V)
MON9
57
I
Analog input (0 to 2.5 V)
MON10
58
I
Analog input (0 to 2.5 V)
MON11
59
I
Analog input (0 to 2.5 V)
MON12
62
I
Analog input (0 to 2.5 V)
MON13
63
I
Analog input (0 to 2.5 V)
MON14
50
I
Analog input (0.2 to 2.5 V)
MON15
52
I
Analog input (0.2 to 2.5 V)
MON16
54
I
Analog input (0.2 to 2.5 V)
GENERAL-PURPOSE INPUT AND OUTPUT
GPIO1
11
I/O
General-purpose discrete I/O
GPIO2
12
I/O
General-purpose discrete I/O
GPIO3
13
I/O
General-purpose discrete I/O
GPIO4
14
I/O
General-purpose discrete I/O
GPIO13
25
I/O
General-purpose discrete I/O
GPIO14
29
I/O
General-purpose discrete I/O
GPIO15
30
I/O
General-purpose discrete I/O
GPIO16
33
I/O
General-purpose discrete I/O
GPIO17
34
I/O
General-purpose discrete I/O
GPIO18
35
I/O
General-purpose discrete I/O
FPWM1/GPIO5
17
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6
18
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7
19
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8
20
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9
21
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10
22
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11
23
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12
24
I/O/PWM
PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1
31
I/PWM
Fixed 10-kHz PWM output or GPI
PWM2/GPI2
32
I/PWM
Fixed 1-kHz PWM output or GPI
PWM3/GPI3
42
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM4/GPI4
41
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM OUTPUTS
(1)
4
The maximum number of configurable rails is 16. The maximum number of configurable GPIs is 8. The maximum number of
configurable Boolean Logic GPOs is 16.
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SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
Pin Functions(1) (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
PMBus COMM INTERFACE
PMBUS_CLK
15
I/O
PMBus clock (must have pullup to 3.3 V)
PMBUS_DATA
16
I/O
PMBus data (must have pullup to 3.3 V)
PMBALERT
27
O
PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBUS_CNTRL
28
I
PMBus control
PMBUS_ADDR0
61
I
PMBus analog address input. Least-significant address bit
PMBUS_ADDR1
60
I
PMBus analog address input. Most-significant address bit
JTAG
TRCK
10
O
Test return clock
TCK/GPIO19
36
I/O
Test clock or GPIO
TDO/GPIO20
37
I/O
Test data out or GPIO
TDI/GPIO21
38
I/O
Test data in (tie to VDD with 10-kΩ resistor) or GPIO
TMS/GPIO22
39
I/O
Test mode select (tie to VDD with 10-kΩ resistor) or GPIO
TRST
40
I
Test reset. Tie to ground with 10-kΩ resistor
INPUT POWER AND GROUNDS
RESET
9
Active-low device reset input. Hold low for at least 2 μs to reset the device. Refer to the
Device Reset section.
V33A
46
Analog 3.3-V supply. Refer to the Layout Guidelines section.
V33D
45
Digital core 3.3-V supply. Refer to the Layout Guidelines section.
V33DIO1
7
Digital I/O 3.3-V supply. Refer to the Layout Guidelines section.
V33DIO2
44
Digital I/O 3.3-V supply. Refer to the Layout Guidelines section.
BPCap
47
1.8-V bypass capacitor. Refer to the Layout Guidelines section.
AVSS1
49
Analog ground
AVSS2
48
Analog ground
AVSS3
64
Analog ground
DVSS1
8
Digital ground
DVSS2
26
Digital ground
DVSS3
43
Digital ground
NC1
51
No Connect
NC2
53
No Connect
QFP ground pad
NA
Thermal pad – tie to ground plane.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
Voltage applied at V33D to DVSS
–0.3
3.8
V
Voltage applied at V33A to AVSS
–0.3
3.8
V
–0.3
(V33A + 0.3)
V
–55
150
°C
Voltage applied to any other pin
(2)
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Supply voltage during operation (V33D, V33DIO, V33A)
Operating free-air temperature range, TA
MIN
NOM
MAX
3
3.3
3.6
V
110
°C
125
°C
–40
Junction temperature, TJ
UNIT
6.4 Thermal Information
UCD90160A
THERMAL METRIC (1)
RGC [VQFN]
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
26.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
21.2
°C/W
RθJB
Junction-to-board thermal resistance
1.7
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
8.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
1.7
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
SUPPLY CURRENT
IV33A
VV33A = 3.3 V
8
mA
IV33DIO
VV33DIO = 3.3 V
2
mA
VV33D = 3.3 V
40
mA
VV33D = 3.3 V, storing configuration parameters
in flash memory
50
mA
IV33D
Supply current (1)
IV33D
ANALOG INPUTS (MON1–MON16)
VMON
Input voltage range
MON1–MON13
MON14–MON16
0
2.5
0.2
2.5
V
V
INL
ADC integral nonlinearity
–4
4
LSB
DNL
ADC differential nonlinearity
-2
2
LSB
Ilkg
Input leakage current
3 V applied to pin
IOFFSET
Input offset current
1-kΩ source impedance
MON1–MON13, ground reference
RIN
Input impedance
CIN
Input capacitance
tCONVERT
ADC sample period
16 voltages sampled, 3.89 μsec/sample
VREF
ADC 2.5 V, internal reference
accuracy
0°C to 125°C
MON14–MON16, ground reference
100
–5
nA
5
μA
8
0.5
MΩ
1.5
3
MΩ
10
–40°C to 125°C
pF
400
μsec
–0.5%
0.5%
–1%
1%
9
11
ANALOG INPUT (PMBUS_ADDRx)
IBIAS
Bias current for PMBus Addr pins
VADDR_OPEN
Voltage – open pin
PMBUS_ADDR0, PMBUS_ADDR1 open
VADDR_SHORT
Voltage – shorted pin
PMBUS_ADDR0, PMBUS_ADDR1 short to
ground
μA
2.26
V
0.124
V
Dgnd +
0.25
V
DIGITAL INPUTS AND OUTPUTS
VOL
Low-level output voltage
IOL = 6 mA (2), V33DIO = 3 V
VOH
High-level output voltage
IOH = –6 mA (3), V33DIO = 3 V
VIH
High-level input voltage
V33DIO = 3 V
VIL
Low-level input voltage
V33DIO = 3.5 V
V33DIO
– 0.6
V
2.1
3.6
V
1.4
V
MARGINING OUTPUTS
TPWM_FREQ
MARGINING-PWM frequency
FPWM1-8
PWM3-4
DUTYPWM
MARGINING-PWM duty cycle range
15.260
125000
0.001
7800
0%
100%
kHz
SYSTEM PERFORMANCE
VDDSlew
Minimum VDD slew rate
VDD slew rate between 2.3 V and 2.9 V
VRESET
Supply voltage at which device
comes out of reset
For power-on reset (POR)
tRESET
Low-pulse duration needed at
RESET pin
To reset device during normal operation
f(PCLK)
Internal oscillator frequency
TA = 125°C, TA = 25°C
240
tretention
Retention of configuration
parameters
TJ = 25°C
100
Years
Write_Cycles
Number of nonvolatile erase/write
cycles
TJ = 25°C
20
K cycles
(1)
(2)
(3)
0.25
V/ms
2.4
V
2
μS
250
260
MHz
Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
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6.6 Timing Requirements
The timing characteristics and timing diagram for the communications interface that supports I2C/SMBus, and PMBus are
shown in Figure 1 and Figure 2.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB
SMBus/PMBus operating frequency
Slave mode, SMBC 50% duty cycle
10
400
kHz
fI2C
I2C operating frequency
Slave mode, SCL 50% duty cycle
10
400
kHz
t(BUF)
Bus free time between start and stop
1.3
μs
t(HD:STA)
Hold time after (repeated) start
0.6
μs
t(SU:STA)
Repeated start setup time
0.6
μs
t(SU:STO)
Stop setup time
0.6
μs
t(HD:DAT)
Data hold time
0
ns
t(SU:DAT)
Data setup time
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
Receive mode
100
See
(1)
1.3
t(HIGH)
Clock high period
See
(2)
t(LOW:SEXT)
Cumulative clock low slave extend time
See
(3)
tf
Clock/data fall time
Fall time tf = 0.9 VDD to (VILmax – 0.15)
tr
Clock/data rise time
Rise time tr = (VILmax – 0.15) to (VIHmin
+ 0.15)
Cb
Total capacitance of one bus line
(1)
(2)
(3)
(4)
ns
35
ms
μs
0.6
μs
25
ms
20 + 0.1 Cb (4)
300
ns
20 + 0.1 Cb (4)
300
ns
400
pF
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Cb in picofarads (pF)
Figure 1. I2C/SMBus Timing Diagram
Start
Stop
TLOW:SEXT
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
PMB_Clk
Clk ACK
Clk ACK
PMB_Data
Figure 2. Bus Timing in Extended Mode
8
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2.500
1.3
2.498
1.0
2.496
0.8
2.494
0.5
DNL High
0.3
DNL Low
DNL (LSB)
ADC Reference Voltage (V)
6.7 Typical Characteristics
2.492
2.490
0.0
2.488
±0.3
2.486
±0.5
2.484
±0.8
2.482
±50
±30
±10
10
30
50
70
90
110
Temperature (Cƒ)
±1.0
130
±50
±30
10
±10
30
50
70
90
110
Temperature (ƒC)
C001
Figure 3. ADC Reference Voltage vs Temperature
130
C002
Figure 4. ADC Differential Nonlinearity vs Temperature
2.5
2.0
INL (LSB)
1.5
1.0
INL High
0.5
INL Low
0.0
±0.5
±1.0
±1.5
±50
±30
±10
10
30
50
70
Temperature (ƒC)
90
110
130
C003
Figure 5. ADC Integral Nonlinearity vs Temperature
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7 Detailed Description
7.1 Overview
Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, etc. can have multiple voltage rails and
require certain power on/off sequences in order to function correctly. The UCD90160A can control up to 16
voltage rails and ensure correct power sequences during normal condition and fault conditions.
In addition to sequencing, UCD90160A can continuously monitor rail voltages, fault conditions, and report the
system health information to a PMBus host, improving systems’ long term reliability.
Also, UCD90160A can protect electronic systems by responding to power system faults. The fault responses are
conveniently configured with Fusion Digital Power Designer software. Fault events are stored in on-chip
nonvolatile flash memory with time stamp in order to assist failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known
as margining. UCD90160A can perform closed-loop margining for up to 10 voltage rails. During normal
operation, UCD90160A can also actively trim DC output voltages using the same margining circuitry.
UCD90160A supports both PMBus- and pin-based control environments. UCD90160A functions as a PMBus
slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also,
UCD90160A can be controlled by up to 8 GPIO configured GPI pins. One GPI can be used as fault pin which
can shut down rails. The GPIs can be used as Boolean logic input to control up to 16 Logic GPO outputs. Each
Logic GPO has a flexible Boolean logic builder. Input signals of the Boolean logic builder can include GPIs, other
Logic GPO outputs, and selectable system flags such as POWER_GOOD, faults, warnings, etc. A simple state
machine is also available for each Logic GPO pin.
UCD90160A provides additional features such a scascading, pin-selected states, system watchdog, system
reset, runtime clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up
to 3 GPIs to define up to 8 rail states. These states can implement system low-power modes as set out in the
Advanced Configuration and Power Interface (ACPI) specification.
7.2 Functional Block Diagram
Comparators
JTAG
Or
GPIO
I2C/PMBus
General Purpose I/O
(GPIO)
Rail Enables (16 max)
6
Digital Outputs (16 max)
Monitor
Inputs
Digital Inputs (8 max)
16
12-bit
200ksps,
ADC
(0.5% Int. Ref)
22
SEQUENCING ENGINE
Multi-phase PWM (8 max)
FLASH Memory
User Data, Fault
and Peak Logging
BOOLEAN
Logic Builder
Margining Outputs (10 max)
64-pin QFN
7.3 Feature Description
7.3.1 Rail Configuration
A rail includes voltage, a power supply enable and a margining output. At least one must be included in a rail
definition. Once the user has defined how the power supply rails should operate in a particular system, analog
input pins and GPIOs can be selected to monitor and enable each supply (Figure 6).
10
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Feature Description (continued)
Figure 6. Fusion Digital Power Designer Software Pin-Assignment Tab
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 7):
• Nominal operating voltage (VOUT)
• Undervoltage (UV) and overvoltage (OV) warning and fault limits
• Margin-low and margin-high values
• Power-good on and power-good off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails, GPOs and GPIs for Sequence On dependencies
• Rails, GPOs and GPIs for Sequence Off dependencies
• Turn-on and turn-off delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
• Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
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Feature Description (continued)
Figure 7. Fusion Digital Power Designer Software VOUT-Config Tab
Use the Synchronize margins/limits/PG to Vout checkbox to change the nominal operating voltage of a rail and
also update all of the other limits associated with that rail according to the percentages shown to the right of each
entry.
The plot in the upper left section of Figure 7 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and powergood off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD90160A responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion
Digital Power Designer software. Once the configuration satisfies the user requirements, it can be written to
device SRAM if Fusion Digital Power Designer software is connected to a UCD90160A device using an I2C or
PMBus interface. SRAM contents are stored to data flash memory so that the configuration remains in the device
after a reset or power cycle.
The Fusion Digital Power Designer software Monitor page has a number of options, including a device
dashboard and a system dashboard, for viewing and controlling device and system status.
12
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Feature Description (continued)
Figure 8. Fusion Digital Power Designer Software Monitor Page
The UCD90160A also has rail state for each rail to debug the system.
Table 1. Rail State
RAIL STATE
VALUE
DESCRIPTION
IDLE
1
On condition is not met, or
rail is shut down due to fault, or
rail is waiting for the resequence
SEQ_ON
2
Wait the dependency to be met to assert ENABLE signal
START_DELAY
3
TON_DELAY to assert ENABLE signal
RAMP_UP
4
Enable is asserted and rail is on the way to reach power good threshold. If the
power good threshold is set to 0 V, the rail stays at this state even if the
monitored voltage is bigger than 0 V.
REGULATION
5
Once the monitoring voltage is over POWER_GOOD when enable signal is
asserted, rails stay at this state even if the voltage is below POWER_GOOD
late as long as there is no fault action taken.
SEQ_OFF
6
Wait the dependency to be met to de-assert ENABLE signal
STOP_DELAY
7
TOFF_DELAY to de-assert ENABLE signal
8
Enable signal is de-asserted and rail is ramping down. This state is only
available if TOFF_MAX_WARN_LIMIT is not set to unlimited; or If the turn off
is triggered by a fault action, rail must not be under fault retry to show RAMP
DOWN state. Otherwise, IDLE state is present.
RAMP_DOWN
The UCD90160A also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power supply or system failure. The status registers
(Figure 9) and the fault log (Figure 10) are available in the Fusion Digital Power Designer software. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference (SLVU352) and the PMBus
Specification for detailed descriptions of each status register and supported PMBus commands.
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Figure 9. Fusion GUI Rail-Status Register
14
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Figure 10. Fusion GUI Flash-Error Log (Logged Faults)
7.3.2 TI Fusion GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power
Designer is referenced throughout the data sheet as Fusion Digital Power Designer software and many sections
include screen shots. The Fusion Digital Power Designer software can be downloaded from www.ti.com.
7.3.3 PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD90160A supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD90160A, MFR_SPECIFIC commands are defined to configure or activate those
features. These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS
Command Reference (SLVU352). The most current UCD90xxx PMBus Command Reference can be found within
the TI Fusion Digital Power Designer software via the Help Menu (Help, Documentation & Help Center,
Sequencers tab, Documentation section).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007.
The specification is published by the Power Management Bus Implementers Forum and is available from
www.pmbus.org.
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The UCD90160A is PMBus compliant, in accordance with the Compliance section of the PMBus specification.
The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT
function. The hardware can support either 100-kHz or 400-kHz PMBus operation.
7.4 Device Functional Modes
7.4.1 Power Supply Sequencing
The UCD90160A can control the turn-on and turn-off sequencing of up to 16 voltage rails by using a GPIO to set
a power supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON (1))
limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the
case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either
by
OPERATION
command,
PMBUS
CNTRL
pin,
or
auto-enable)
and
(TON_DELAY
+
TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and
(TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes
7.4.1.1 Turn-on Sequencing
The following sequence-on options are supported for each rail:
• Monitor only – do not sequence-on
• Fixed delay time (TON_DELAY) after an OPERATION command to turn on
• Fixed delay time after assertion of the PMBUS_CNTRL pin
• Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)
• Fixed time after a designated GPI has reached a user-specified state
• Fixed time after a designated GPO has reached a user-specified state
• Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
7.4.1.2 Turn-off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only – do not sequence-off
• Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off
• Fixed delay time after deassertion of the PMBUS_CNTRL pin
• Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)
• Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
• Fixed delay time in response to a GPI reaching a user-specified state
• Fixed time after a designated GPO has reached a user-specified state
• Any combination of the previous options
The maximum TOFF_DELAY time is 3276 ms.
(1)
16
In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first
time the parameter appears.
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Device Functional Modes (continued)
Ÿ Rail 1 and Rail 2 are both sequenced “ON”
and “OFF” by the PMBUS_CNTRL pin
only
Ÿ Rail 2 has Rail 1 as an “ON” dependency
Ÿ Rail 1 has Rail 2 as an “OFF” dependency
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
POWER_GOOD_ON[1]
POWER_GOOD_OFF[1]
RAIL 1 VOLTAGE
TOFF_DELAY[2]
TON_DELAY[2]
RAIL 2 EN
RAIL 2 VOLTAGE
TON_MAX_FAULT_LIMIT[2]
TOFF_MAX_WARN_LIMIT[2]
Figure 11. Sequence-on and Sequence-off Timing
7.4.1.3 Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and
user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI
dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the
PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop
command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD90160As,
it is possible for each controller to be both a master and a slave to another controller.
7.4.2 Pin-Selected Rail States
This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing
system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used
for operating system directed power management in servers and PCs. In up to 8 system states, the power
system designer can define which rails are on and which rails are off. If a new state is presented on the input
pins, and a rail is required to change state, it does so with regard to its sequence-on or sequence-off
dependencies.
The OPERATION command is modified when this function causes a rail to change its state. This means that the
ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any
effect on the rail state. The first three pins configured with the GPI_CONFIG command are used to select 1 of 8
system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, are used
to update each rail state. When selecting a new system state, changes to the status of the GPIs must not take
longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.
Table 2. GPI Selection of System States
GPI 2 State
GPI 1 State
GPI 0 State
System
State
NOT Asserted
Not Asserted
Not Asserted
0
NOT Asserted
Not Asserted
Asserted
1
NOT Asserted
Asserted
Not Asserted
2
NOT Asserted
Asserted
Asserted
3
Asserted
Not Asserted
Not Asserted
4
Asserted
Not Asserted
Asserted
5
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Table 2. GPI Selection of System States (continued)
GPI 2 State
GPI 1 State
GPI 0 State
System
State
Asserted
Asserted
Not Asserted
6
Asserted
Asserted
Asserted
7
7.4.3 Voltage Monitoring
Up to 16 voltages can be monitored using the analog input pins. The input voltage range is 0 to 2.5 V for MON
pins 1-6, 55-59, 62, and 63. Pins 50, 52, and 54 can measure down to 0.2 V.
The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the
sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage
should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is
used to lower the voltage applied to the analog input pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the
ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware
comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
Digital Power Designer software and are used to report the actual voltage being monitored instead of the ADC
input voltage. The nominal voltage is used to set the range and precision of the reported voltage according to
Table 3.
MON1 – MON6
MON1
MON2
.
.
.
.
MON16
Analog
Inputs
(16)
M
U
X
Fast Digital
Comparators
12-bit
SAR ADC
200ksps
MON1 – MON16
Glitch
Filter
Internal
2.5Vref
0.5%
Figure 12. Voltage Monitoring Block Diagram
Table 3. Voltage Range and Resolution
18
VOLTAGE RANGE
(V)
RESOLUTION
(mV)
0 to 127.99609
3.90625
0 to 63.99805
1.95313
0 to 31.99902
0.97656
0 to 15.99951
0.48824
0 to 7.99976
0.24414
0 to 3.99988
0.12207
0 to 1.99994
0.06104
0 to 0.99997
0.03052
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Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of
610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
7.4.4 Fault Responses and Alert Processing
The UCD90160A monitors whether the rail stays within a window of normal operation. There are two
programmable warning levels (under and over) and two programmable fault levels (under and over). When any
monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately,
and the appropriate bits are set in the PMBus status registers (see Figure 9). Detailed descriptions of the status
registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference
and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 102 ms with 400-μs resolution. The glitch filter only applies to fault
responses; a fault condition that is filtered by the glitch filter will still be recorded in the fault log.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
TIME BETWEEN
RESTARTS
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT _LIMIT
RAIL 1 VOLTAGE
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
TON_DELAY[2]
RAIL 2 EN
TOFF_DELAY[1]
MAX_GLITCH_TIME
MAX_GLITCH_TIME
TOFF_DELAY[2]
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Figure 13. Sequencing and Fault-Response Timing
PMBUS_CNTRL PIN
TON_DELAY[1]
RAIL 1 EN
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
Time Between Restarts
Rail 2 has Rail 1 as an “ON” dependency
POWER_GOOD_ON[1]
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
TON_DELAY[2]
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
Figure 14. Maximum Turn-on Fault
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The configurable fault limits are:
• TON_MAX_FAULT – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the
configured time
• VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
• VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
• VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or
operation
• VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or
operation
• TOFF_MAX_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal
rail voltage within the configured time
Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault
occurs. If a warning occurs, the following takes place:
Warning Actions
— Immediately assert the PMBALERT# pin
— Status bit is flagged
— Assert a GPIO pin (optional)
— Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault Responses
— Continue Without Interruption: Flag the fault and take no action
— Shut Down Immediately: Shut down the faulted rail immediately
— Shut Down using TOFF_DELAY: If a fault occurs on a rail, schedule the shutdown of this rail and all
fault-shutdown slaves. All selected rails, including the faulty rail, are sequenced off according to their
sequence-off dependencies and T_OFF_DELAY times.
Restart
— Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.
— Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.
The time between restarts is measured between when the rail enable pin is deasserted (after any
glitch filtering and turn-off delay times, if configured to observe them) and then reasserted. It can be
set between 0 and 1275 ms in 5-ms increments. Under voltage faults only have a maximum of 1
restart as an option.
— Restart Continuously: Same as Restart Up To N Times except that the device continues to restart
until the fault goes away, it is commanded off by the specified combination of PMBus OPERATION
command and PMBUS_CNTRL pin status, the device is reset, or power is removed from the device.
This option is not available for under voltage faults.
— Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after
continue-operation time is reached and then sequence-on those rails using sequence-on
dependencies and T_ON_DELAY times.
One GPI pin can also trigger faults if the GPI Fault Enable checkbox in Figure 19 is checked and proper
responses are set in Figure 20. Refer to GPI Special Functions for more details.
20
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7.4.5 Shut Down All Rails and Sequence On (Resequence)
In response to a fault, or a RESEQUENCE command, the UCD90160A can be configured to turn off a set of rails
and then sequence them back on. To sequence all rails in the system, then all rails must be selected as faultshutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves initiate soft shutdowns
regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and
sequence-on are not performed until retries are exhausted for a given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and
fault-shutdown slaves sequence-off, the UCD90160A waits for a programmable delay time between 0 and 1275
ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the
start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully
achieve regulation or for a user-selected 1, 2, 3, or 4 times. If the resequence operation is successful, the
resequence counter is reset if all of the rails that were resequenced maintain normal operation for one second.
Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If there
are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is taken.
For example, if a set of rails is already on its second resequence and the device is configured to resequence
three times, and another set of rails enters the resequence state, that second set of rails is only resequenced
once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can resequence,
and another set of rails enters the resequence state, the device now waits for all rails from both sets to shut
down before resequencing.
If any rails at resequence state are caused by a GPI fault response, the whole resequence is suspended until the
GPI fault is clear.
7.4.6 GPIOs
The UCD90160A has 22 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.
There are an additional four pins that can be used as either inputs or PWM outputs but not as GPOs. Table 4
lists possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system-level functions such as
external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or
down by configuring a rail without a MON pin but with a GPIO set as an enable.
Table 4. GPIO Pin Configuration Options
PIN NAME
PIN
RAIL EN
(16 MAX)
GPI
(8 MAX)
GPO
(16 MAX)
PWM OUT
(12 MAX)
MARGIN PWM
(10 MAX)
FPWM1/GPIO5
17
X
X
X
X
X
FPWM2/GPIO6
18
X
X
X
X
X
FPWM3/GPIO7
19
X
X
X
X
X
FPWM4/GPIO8
20
X
X
X
X
X
FPWM5/GPIO9
21
X
X
X
X
X
FPWM6/GPIO10
22
X
X
X
X
X
FPWM7/GPIO11
23
X
X
X
X
X
FPWM8/GPIO12
24
X
X
X
X
X
GPI1/PWM1
31
X
X
GPI2/PWM2
32
X
X
GPI3/PWM3
42
X
X
X
GPI4/PWM4
41
X
X
X
GPIO1
11
X
X
X
GPIO2
12
X
X
X
GPIO3
13
X
X
X
GPIO4
14
X
X
X
GPIO13
25
X
X
X
GPIO14
29
X
X
X
GPIO15
30
X
X
X
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Table 4. GPIO Pin Configuration Options (continued)
PIN NAME
PIN
RAIL EN
(16 MAX)
GPI
(8 MAX)
GPO
(16 MAX)
GPIO16
33
X
X
X
GPIO17
34
X
X
X
GPIO18
35
X
X
X
TCK/GPIO19
36
X
X
X
TDO/GPIO20
37
X
X
X
TDI/GPIO21
38
X
X
X
TMS/GPIO22
39
X
X
X
PWM OUT
(12 MAX)
MARGIN PWM
(10 MAX)
7.4.7 GPO Control
The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in
internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)
can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a
GPO using PMBus commands.
7.4.8 GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs, all ORed
together (Figure 15). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags.
One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the
status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted
until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are
shown in Table 5. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for
complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or
deassertion. The first 8 GPOs can be chosen as Rail Sequence on/off Dependency. The logic state of the GPO
instead of actual pin output is used as dependency condition.
Sub block repeated for each of GPI(1:7)
GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
1
AND_INVERSE(0)
_GPI(0)
GPI(0)
_GPI(1:7)
_STATUS(0:14)
_STATUS(15)
_GPO(1:7)
There is one STATUS_TYPE_SELECT for each of the two AND
gates in a boolean block
STATUS_TYPE_SELECT
STATUS(0)
OR_INVERSE(x)
Status Type 1
STATUS(1)
Sub block repeated for each of STATUS(0:14)
GPOx
STATUS_INVERSE(15)
Status Type 33
STATUS_ENABLE(15)
STATUS(15)
ASSERT_DELAY(x)
1
AND_INVERSE(1)
DE-ASSERT_DELAY(x)
_GPI(0:7)
_STATUS(0:15)
_GPO(0:7)
Sub block repeated for each of GPO(1:7)
GPO_INVERSE(0)
GPO_ENABLE(0)
1
GPO(0)
_GPO(0)
Figure 15. Boolean Logic Combinations
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Figure 16. Fusion Boolean Logic Builder
Table 5. Rail-Status Types for Boolean Logic
Rail-Status Types
POWER_GOOD
TON_MAX_FAULT
VOUT_UV_WARN_LATCH
MARGIN_EN
TOFF_MAX_WARN
VOUT_UV_FAULT_LATCH
MRG_LOW_nHIGH
SEQ_ON_TIMEOUT
TON_MAX_FAULT_LATCH
VOUT_OV_FAULT
SEQ_OFF_TIMEOUT
TOFF_MAX_WARN_LATCH
VOUT_OV_WARN
SYSTEM_WATCHDOG_TIMEOUT
SEQ_ON_TIMEOUT_LATCH
VOUT_UV_WARN
VOUT_OV_FAULT_LATCH
SEQ_OFF_TIMEOUT_LATCH
VOUT_UV_FAULT
VOUT_OV_WARN_LATCH
SYSTEM_WATCHDOG_TIMEOUT_LATCH
When GPO is set to POWER_GOOD, this POWER_GOOD state is based on the actual voltage measurement on
the monitor pins assigned to those rails. For a rail that does not have a monitor pin, or have a monitor pin but
without voltage monitoring, its POWER_GOOD state is used by sequencing purpose only, and is not be used by
the GPO logic evaluation.
7.4.8.1 GPO Delays
The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both
or none. GPO behavior using delays have different effects depending if the logic change occurs at a faster rate
than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back to
previous state within the time of a delay then the GPO does not manifest the change of state on the pin. In
Figure 17 the GPO is set so that it follows the GPI with a 3-ms delay at assertion and also at de-assertion. When
the GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the
GPO to follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic
state. The second time that the GPI changes to a high logic state it returns to low logic state before the delay
time expires. In this case the GPO does not change state. A delay configured in this manner serves as a glitch
filter for the GPO.
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3ms
GPI
GPO
1ms
Figure 17. GPO Behavior When Not Ignoring Inputs During Delay
The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the
delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires.
Figure 18 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic
changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored.
Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when
having the Ignore Input During Delay bit set has a width of at least the time delay.
3ms
3ms
3ms
3ms
GPI
GPO
1ms
Figure 18. GPO Behavior When Ignoring Inputs During Delay
7.4.8.2 State Machine Mode Enable
When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time.
When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When
the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a
very simple state machine and allows for more complex logical combinations.
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7.4.9 GPI Special Functions
Special input functions for which GPIs can be used. There can be no more than one pin assigned to each of
these functions.
• GPI Fault Enable - When set, the de-assertion of the GPI is treated as a fault.
• Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), a correctly configured
GPI clears the latched status.
• Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a
margined state (low or high).
• Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin
Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin
High.
• Fault Shutdown Rails - See Fault Shutdown Rails.
• Configured as Sequencing Debug Pin - See Configured as Sequencing Debug Pin.
• Configured as Fault Pin - See Configured as Sequencing Debug Pin.
• Enable Cold Boot Mode - See Cold Boot Mode Enable.
The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are
defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.
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Figure 19. GPI Configurations
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7.4.9.1 Fault Shutdown Rails
GPI Fault Enable must be set to enable this feature. When set, the de-assert of the assigned GPI trigger a
number of fault response options (see Figure 20). Retry action is not supported.
Figure 20. GPI Fault Response
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7.4.9.2 Configured as Sequencing Debug Pin
When the pin is asserted, device does not alert PMBUS_Alert pin, not response for faults, log faults defined in
the Table 6. The rail sequence on/off dependency conditions are ignored, as soon as the sequence on/off
timeout is expired, the rails will be sequenced on or off accordingly regardless of the timeout action, if the
sequence on/off timeout value is set to 0, the rails is sequenced on or off immediately. The fault pins do not pull
the fault bus low. The LGPOs affected by these events should be back to it original states.
Table 6. List of Events Affected by Debug Mode
EVENTS
DESCRIPTION
VOUT_OV_FAULT
Voltage Rail is over OV fault threshold
VOUT_OV_WARNING
Voltage Rail is over OV warning threshold
VOUT_UV_FAULT
Voltage Rail is under UV fault threshold
VOUT_UV_WARNING
Voltage Rail is under UV warning threshold
TON_MAX
Voltage Rail fails to reach power good threshold in predefined period
TOFF_MAX Warning
Voltage rail fails to reach power not good threshold in predefined period
All GPI deasserted
No logging, no fault responses, but the function of the GPI is not ignored.
SYSTEM_WATCHDOG_TIMEOUT
System watch timeout
RESEQUENCE_ERROR
Rail fails to resequence
SEQ_ON_TIMEOUT
Rail fails to meeting sequence on dependency in predefined period
SEQ_OFF_TIMEOUT
Rail fails to meeting sequence on dependency in predefined period
SLAVE_FAULT
Rail is shut down due to that its master has fault
7.4.9.3 Configured as Fault Pin
GPI Fault Enable must be set to enable this feature. When set, if there is no fault on a Fault Bus, the Fault Pin is
digital input pin and listen to the Fault Bus. When one or multiple UCD90160A devices detect a rail fault (see
Table 7), the corresponding Fault Pin is turned into active driven low state, pulling down the Fault Bus and
informing all other UCD90160A devices of the corresponding fault. This way, a coordinated action can be taken
across multiple devices. After the fault is cleared, the state of the Fault Pin is turned back to an input pin.
Table 7. Events Affecting Fault Pin
EVENTS
DESCRIPTION
RESEQUENCE_ERROR
Rail fails to resequence
SEQ_ON_TIMEOUT
Rail fails to meeting sequence on dependency in predefined period
SEQ_OFF_TIMEOUT
Rail fails to meeting sequence on dependency in predefined period
VOUT_UV_FAULT
Voltage rail is under UV threshold
VOUT_OV_FAULT
Voltage rail is over OV threshold
TON_MAX_FAULT
Voltage rail fails to reach power good threshold in predefined period.
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7.4.9.4 Cold Boot Mode Enable
Cold boot mode is used to heat-up a system by turning on cold boot rails for certain amounts of time when it is
under an extreme code temperature. UCD device is communicated with the system via particular GPI (thermal
state GPI) which is output from a thermal device. Cold boot mode is only entering once per UCD reset. There is
no system watch dog Reset during the cold boot mode.
Device reads the thermal state GPI to determine whether it should start cold boot or not when it is out of reset.
When the input of thermal state GPI is DE-ASSERTED, device enters cold boot mode and log the GPI fault if the
GPI fault log enable bit is set, otherwise device enters normal mode. The following changes on the thermal state
GPI do not introduce any logging. Only one GPI can be assigned for this function and one it is assigned, it
cannot be used for any other GPI functions.
The rails used in the cold boot mode are configurable. For those rails with Sequence On Dependency on the
thermal state GPI, they (non-cold boot rails) are not powered-up during the cold boot because the dependency is
not met. But non-cold boot rails will be power-on under normal mode because thermal state GPI is treated as
ASSERTED when cold boot mode is over. For those rails without sequence on dependency on the thermal state
GPI, they (cold boot rails) are power-on under both cold boot and normal mode. It is application’s responsibility to
set the proper ON_OFF_CONFIG for those cold boot rails. Cold boot rails are not power-on if their
ON_OFF_CONFIG settings are not met under cold boot mode. Cold boot mode timeout is used to tell how long
the device shall stay at the cold boot before it stops monitoring the thermal state GPI and shutdown all cold boot
rails with EN control. Normal Boot Start Delay is used to tell how long device should wait to ramp up the powers
after all cold boot rails with EN are below POWER_GOOD_OFF.
spacer
- If system temperature is < threshold degree C (Thermal State GPI)
o
Yes(DE_ASSERTED):
§ Log GPI fault
§ Start Cold Boot Timeout
§ No System Watchdog output
§ Ramp up the power supplies based on ON_OFF_CONFIG
§ Wait for thermal state GPI ASSERTED OR “Cold Boot Mode Timeout expired”
§ Disable the thermostat input listening mode
§ Force to shutdown down all cold boot rails with EN control immediately
§ Wait all cold boot rails with EN control below POWER_GOOD_OFF
§ Start and Wait “Normal boot Start Delay expired”
- Disable the thermostat input listening mode
- Treated Thermal State GPI as ASSERTED
- Ramp up power supplies based on ON_OFF_CONFIG
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7.4.10 Power Supply Enables
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the
GPIO pins are high-impedance except for FPWM/GPIO pins 17 to 24, which are driven low. External pulldown or
pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD90160A can
support a maximum of 16 enable pins.
NOTE
GPIO pins that have FPWM capability (pins 17 to 24) should only be used as power
supply enable signals if the signal is active high.
7.4.11 Cascading Multiple Devices
A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device
and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master/slave relationship among
multiple devices. During startup, the slave controllers initiate their start sequences after the master has
completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the
master starts to sequence-off, it sends the shut-down signal to its slaves.
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
Another method to cascade multiple devices is to connect the power-good output of the first device to a MON pin
of the second device; connect the power-good output of the second device to a MON pin of the third device, and
so on. Optionally, connect the power-good output of the last device to a MON pin of the first device. The rails
controlled by a device have dependency on the previous device’s power-good output. This way, the rails
controlled by multiple devices can be sequenced. Also, the de-assertion of a power-good output can trigger a UV
fault of the next device. The UV fault response can be configured to shut down other rails controlled by the same
device. This way, when one rail has fault shutdown, other rails controlled by other devices can be shut down
accordingly.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD90160A allows GPIOs to be configured to respond to a desired
subset of power-good signals.
Multiple UCD90160A devices can also work together and coordinate when faults happen with fault pin
connection. One GPI pins can be configured as Fault Pins. Fault Pin is connected to a Fault Bus. Each Fault Bus
is pulled up to 3.3 V by a 10-kΩ resistor. All the UCD90160A devices on the same Fault Bus are informed of the
same fault condition. An example of Fault Pin connections is shown in Figure 21.
3.3V
UCD90160A
UCD90160A
Fault Pin
Fault Pin
Fault Bus
Figure 21. Fault Pin Connections
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7.4.12 PWM Outputs
7.4.12.1 FPWM1-8
Pins 17–24 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 – same frequency
• FPWM3 and FPWM4 – same frequency
• FPWM5 and FPWM6 – same frequency
• FPWM7 and FPWM8 – same frequency
If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to
configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the
system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for
any other functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as Equation 1.
Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16)
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1.
2.
3.
4.
Divide 250 MHz by 75 MHz to obtain 3.33.
Round off 3.33 to obtain an integer of 3.
Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.
Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
7.4.12.2 PWM1-4
Pins 31, 32, 41, and 42 can be used as GPIs or PWM outputs.
If configured as PWM outputs, then limitations apply:
• PWM1 has a fixed frequency of 10 kHz
• PWM2 has a fixed frequency of 1 kHz
• PWM3 and PWM4 frequencies can be 0.93 Hz to 7.8125 MHz.
The frequency for PWM3 and PWM4 is derived by dividing down a 15.625-MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625 MHz by any integer between 2 and (224 – 1).
The duty cycle resolution will be dependent on the set frequency for PWM3 and PWM4.
The PWM3 or PWM4 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as Equation 2.
Change per Step (%)PWM3/4 = frequency ÷ (15.625 × 106) × 100
(2)
To determine the closest frequency to 1 MHz that PWM3 can be set to calculate as the following:
1.
2.
3.
4.
Divide 15.625 MHz by 1 MHz to obtain 15.625.
Round off 15.625 to obtain an integer of 16.
Divide 15.625 MHz by 16 to obtain actual closest frequency of 976.563 kHz.
Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.
All frequencies below 238 Hz will have a duty cycle resolution of 0.0015%.
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7.4.13 Programmable Multiphase PWMs
The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to
360°. This provides flexibility in PWM-based applications such as power supply controller, digital clock
generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180°, and 270°
(Figure 22).
Figure 22. Multiphase PWMs
7.4.14 Margining
Margining is used in product validation testing to verify that the complete system works properly over all
conditions, including minimum and maximum power supply voltages, load range, ambient temperature range,
and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION
command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG
command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes
different available margining options, including ignoring faults while margining and using closed-loop margining to
trim the power supply output voltage one time at power up.
7.4.14.1 Open-Loop Margining
Open-loop margining is done by connecting a power supply feedback node to ground through one resistor and to
the margined power supply output (VOUT) through another resistor. The power supply regulation loop responds to
the change in feedback node voltage by increasing or decreasing the power supply output voltage to return the
feedback voltage to the original value. The voltage change is determined by the fixed resistor values and the
voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for connecting resistors
from the feedback node of each power supply to VOUT or ground.
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MON(1:16)
3.3 V
UCD901 60A
POWE R
SUPPL Y
10k
GPIO(1:16)
VOUT
EN
3.3 V
Vou t
VFB
Rmrg_HI
VFB
GPIO
GPIO
³0´ or ³1´
³0´ or ³1´
VOUT
Rmrg_LO
3.3 V
POWE R
SUPPL Y
10k
EN
Vou t
VOUT
VFB
VFB
Rmrg_HI
VOUT
Rmrg_LO
3.3 V
Ope n L oop Marginin g
Figure 23. Open-Loop Margining
7.4.14.2 Closed-Loop Margining
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power supply feedback node through a resistor. The power supply output voltage is monitored,
and the margining voltage is controlled by adjusting the PWM duty cycle until the power supply output voltage
reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the
same that applies to the voltage measurement resolution (Table 3). The closed loop margining can operate in
several modes (Table 8). Given that this closed-loop system has feed back through the ADC, the closed-loop
margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and
margined voltage is configurable so that voltage increases when duty cycle increases or decreases. For more
details on configuring the UCD90160A for margining, see the Voltage Margining Using the UCD9012x application
note (SLVA375).
Table 8. Closed Loop Margining Modes
MODE
DESCRIPTION
DISABLE
Margining is disabled.
ENABLE_TRI_STATE
When not margining, the PWM pin is set to high impedance state.
ENABLE_ACTIVE_TRIM
When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at
VOUT_COMMAND.
ENABLE_FIXED_DUTY_CYCLE
When not margining, the PWM duty-cycle is set to a fixed duty-cycle.
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MON(1:16)
3.3 V
UCD901 60A
POWE R
SUPPL Y
10k
GPIO
Vou t
VOUT
EN
VFB
250 kHz
to 1 MHz
GPIO
R3
R4
R1
VFB
Vmarg
Closed Loop
Margin ing
C1
R2
Figure 24. Closed-Loop Margining
7.4.15 System Reset Signal
The UCD90160A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration
can be programmed as shown in Table 9. See an example of two SYSTEM RESET signals Figure 25. The first
SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off
after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after
a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.
See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width
configuration details.
Power Good On
Power Good On
Power Good Off
POWER GOOD
Delay
Delay
Delay
SYSTEM RESET
configured without pulse
Pulse
Pulse
SYSTEM RESET
configured with pulse
Figure 25. System Reset with and without Pulse Setting
The system reset can react to watchdog timing. In Figure 26 The first delay on SYSTEM RESET is for the initial
reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is
configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is
expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either
using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
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Power Good On
POWER GOOD
WDI
Watchdog
Start Time
Watchdog
Reset Time
Watchdog
Start Time
Delay
Watchdog
Reset Time
SYSTEM RESET
Delay or
GPI Tracking Release Delay
Figure 26. System Reset with Watchdog
Table 9. System-Reset Delay
DELAY
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.19 s
16.38 s
32.8 s
7.4.16 Watch Dog Timer
A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power supply
sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a systemreset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to
SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer.
The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested
through the Boolean Logic defined GPOs or through the System Reset function.
The WDT can be active immediately at power up or set to wait while the system initializes. Table 10 lists the
programmable wait times before the initial timeout sequence begins.
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Table 10. WDT Initial Wait
Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
800 ms
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102 s
205 s
410 s
819 s
1638 s
The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System
Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times
out, the UCD90160A can assert a GPIO pin configured as WDO that is separate from a GPIO defined as
system-reset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the
WDI pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.
<tWDI
WDI
<tWDI
<tWDI
tWDI
<tWDI
WDO
Figure 27. Timing of GPIOs Configured for Watchdog Timer Operation
7.4.17 Run Time Clock
The Run-Time clock output reports in milliseconds and days. Both values are 32-bit numbers. The value is saved
in nonvolatile memory whenever a STORE_DEFAULT_ALL command is issued. It can also be saved when a
power-down condition is detected (See Brownout Function).
The Run-Time clock may also be written. This allows the clock to be periodically corrected by the host. It also
allows the clock to be initialized to the actual, absolute time in years (for example, March 23, 2010). The user
must translate the absolute time to days and milliseconds.
The three usage scenarios for the Run-Time Clock are:
• Time from restart (reset or power-on). Run-Time Clock starts from 0 each time a restart occurs
• Absolute run-time, or operating time. Run-Time Clock is preserved across restarts, recording the total time
that the device has been in operation “Boot time” is not included in this period. Only normal operation time is
captured here.)
• Local time. An external processor sets the Run-Time Clock to real-world time each time the device is
restarted.
The Run-Time clock value is used to timestamp any faults that are logged.
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7.4.18 Data and Error Logging to Flash Memory
The UCD90160A can log up to 18 faults and the number of device resets to flash memory. Peak voltage
measurements are also stored for each rail. To reduce stress on the flash memory, a 30-second timer is started
if a measured value exceeds the previously logged value. Only the highest value from the 30-second interval is
written from RAM to flash. Data and Error logging to flash memory can be disabled by user so that the data and
error are only stored in the SRAM.
Multiple faults can be stored in flash memory and can be accessed over PMBus to help debug power supply
bugs or failures. Each logged fault includes:
• Rail number
• Fault type
• Fault time since previous device reset
• Last measured rail voltage
The total number of device resets is also stored to flash memory. The value can be reset using PMBus.
There are three settings for handling the fault log once it reaches its maximum capacity. These settings allow to
keep the latest faults by using a First In, First Out (FIFO) mode.
• FIFO log disabled - The first 18 faults will be logged. No additional faults will be logged until the fault log is
cleared.
• FIFO log for all faults - The most recent 18 faults will be logged. Once 18 faults are logged, any additional
faults will cause the oldest fault log entry to be lost.
• FIFO log for last half of faults - The first 9 faults will be logged. The most recent 9 faults will also be logged. In
the FIFO portion of the log, once 9 faults are logged, any additional faults will cause the oldest fault entry to
be lost.
With the brownout function enabled, the run-time clock value, peak monitor values, and faults are only logged to
flash when a power-down is detected. The device run-time clock value is stored across resets or power cycles
unless the brownout function is disabled, in which case the run-time clock is returned to zero after each reset.
It is also possible to update and calibrate the UCD90160A internal run-time clock via a PMBus host. For
example, a host processor with a real-time clock could periodically update the UCD90160A run-time clock to a
value that corresponds to the actual date and time. The host must translate the UCD90160A timer value back
into the appropriate units, based on the usage scenario chosen. See the REAL_TIME_CLOCK command in the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for more details.
7.4.19 Brownout Function
The UCD90160A can be enabled to turn off all nonvolatile logging until a brownout event is detected. A brownout
event occurs if VCC drops below 2.9 V. In order to enable this feature, the user must provide enough local
capacitance to deliver up to 80 mA (consider additional load based on GPOs sourcing external circuits such as
LEDs) on for 5 ms while maintaining a minimum of 2.6 V at the device. If using the brownout circuit (Figure 28),
then a schottky diode should be placed so that it blocks the other circuits that are also powered from the 3.3-V
supply.
With this feature enabled, the UCD90160A saves faults, peaks, and other log data to SRAM during normal
operation of the device. Once a brownout event is detected, all data is copied from SRAM to Flash if the log is
not disabled. Use of this feature allows the UCD90160A to keep track of a single run-time clock that spans
device resets or system power down (rather than resetting the run time clock after device reset). It can also
improve the UCD90160A internal response time to events, because Flash writes are disabled during normal
system operation. This is an optional feature and can be enabled using the MISC_CONFIG command. For more
details, see the UCD90xxx Sequencer and System Health Controller PMBus Command Reference.
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UCD901 60A
3.3 V
AVS S1
AVS S2
AVS S3
DVSS1
DVSS2
DVSS3
V33A
V33D
V33DIO1
V33DIO2
C
Figure 28. Brownout Circuit
7.4.20 PMBus Address Selection
Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each
address-detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is
calculated as follows.
PMBus Address = 12 × bin(VAD01) + bin(VAD00)
Where bin(VAD0x) is the address bin for one of eight addresses as shown in Table 11. The address bins are
defined by the MIN and MAX VOLTAGE RANGE (V). Each bin is a constant ratio of 1.25 from the previous bin.
This method maintains the width of each bin relative to the tolerance of standard 1% resistors.
Table 11. PMBus Address Bins
ADDRESS BIN
RPMBus
PMBus RESISTANCE (kΩ)
open
—
11
200
10
154
9
118
8
90.9
7
69.8
6
53.6
5
41.2
4
31.6
short
—
A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the
PMBus address to default to address 126 (0x7E). A high impedance (open) on either address pin that produces
a voltage above the maximum voltage also causes the PMBus address to default to address 126 (0x7E).
Address 0 is not used because it is the PMBus general-call address. Addresses 11 and 127 can not be used by
this device or any other device that shares the PMBus with it, because those are reserved for manufacturing
programming and test. It is recommended that address 126 not be used for any devices on the PMBus, because
this is the address that the UCD90160A defaults to if the address lines are shorted to ground or left open.
Table 12 summarizes which PMBus addresses can be used. Other SMBus/PMBus addresses have been
assigned for specific devices. For a system with other types of devices connected to the same PMBus, see the
SMBus device address assignments table in Appendix C of the latest version of the System Management Bus
(SMBus) specification. The SMBus specification can be downloaded at System Management Bus (SMBus)
Specification.
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Table 12. PMBus Address Assignment Rules
ADDRESS
STATUS
0
Prohibited
1-10
Available
11
Avoid
12
Prohibited
13-125
Available
126
For JTAG Use
127
Prohibited
REASON
SMBus general address call
Causes conflicts with other devices during program flash updates.
PMBus alert response protocol
Default value; may cause conflicts with other devices.
Used by TI manufacturing for device tests.
VDD
10 µA
Ibias
PMBUS_ADDR0
UCD901 60A
On/Off
Control
To 12-bit A DC
PMBUS_ADDR1
Resistors to set
PMBus addre ss
Figure 29. PMBus Address-Detection Method
CAUTION
Address 126 (0x7E) is not recommended to be selected as a permanent PMBus
address for any given application design.
Leaving the address in default state as 126 (0x7E) will enable the JTAG and not allow
using the JTAG compatible pins (36-39) as GPIOs.
7.4.21 Device Reset
The UCD90160A has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up,
the POR detects the V33D rise. When V33D is less than VRESET, the device comes out of reset.
The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low
voltage on this pin for longer than tRESET holds the device in reset. it comes out of reset within 1 ms after RESET
is released, and can return to a logic-high level. To avoid an erroneous trigger caused by noise, connect RESET
to a 10-kΩ pullup resistor (from RESET to 3.3 V) and 1000-pF capacitor (from RESET to AVSS).
Any time the device comes out of reset, it begins an initialization routine that lasts about 20 ms. During the
Initialization routine, the FPWM pins are held low. and all other GPIO and GPI pins are open-circuit. At the end of
initialization, the device begins normal operation as defined by the device configuration.
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7.5 Programming
7.5.1 Device Configuration and Programming
From the factory, the device contains the sequencing and monitoring firmware. It is also configured so that all
GPOs are high-impedance (except for FPWM/GPIO pins 17 to 24, which are driven low), with no sequencing or
fault-response operation. See Configuration Programming of UCD Devices, available from the Documentation &
Help Center that can be selected from the Fusion Digital Power Designer software Help menu, for full
UCD90160A configuration details.
After the user has designed a configuration file using Fusion GUI, there are three general device-configuration
programming options:
1. Devices can be programmed in-circuit by a host microcontroller using PMBus commands over I2C (see the
UCD90xxx
Sequencer
and
System
Health
Controller
PMBus
Command
Reference).
Each parameter write replaces the data in the associated memory (RAM) location. After all the required
configuration data has been sent to the device, it is transferred to the associated nonvolatile memory (data
flash) by issuing a special command, STORE_DEFAULT_ALL. This method is how the Fusion Digital Power
Designer software normally reads and writes a device configuration. This method may cause unexpected
behaviors on GPIO pins which can disable rails that provide power to device. It is not recommended for
production programming.
2. The Fusion Digital Power Designer software (Figure 30) can create a PMBus or I2C command script file that
can be used by the I2C master to configure the device. This method may cause unexpected behaviors on
GPIO pins which can disable rails that provide power to device. It is not recommended for production
programming.
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Programming (continued)
Figure 30. Fusion GUI PMBus Configuration Script Export Tool
3. Another in-circuit programming option is for the Fusion Digital Power Designer software to create a data flash
image from the configuration file (Figure 31). The configuration files can be exported in Intel Hex, data flash
script, Serial Vector Format (SVF) and S-record. The image file can be downloaded into the device using I2C
or JTAG. The Fusion Digital Power Designer software tools can be used on-board if the Fusion Digital Power
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Programming (continued)
Designer software can gain ownership of the target board I2C bus. It is recommended to use Intel Hex file or
data flash script file for production programming because the GPIOs are under controlled states.
Figure 31. Fusion GUI Device Configuration Export Tool
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Programming (continued)
Devices can be programmed off-board using the Fusion GUI tools or a dedicated device programmer. For small
runs, a ZIF socketed board with an I2C header can be used with the standard Fusion GUI or manufacturing GUI.
Use the UCD90SEQ64EVM-650: 64-Pin Sequencer Development Board. The Fusion Digital Power Designer
software can also create a data flash file that can then be loaded into the UCD90160A device using a dedicated
device programmer.
The UCD90160A must be powered in order to configure it using an I2C or PMBus interface. The PMBus clock
and data pins must be accessible and must be pulled high to the same VDD supply that powers the device, with
pullup resistors between 1 kΩ and 2 kΩ. Do not introduce additional bus capacitance (< 100 pF). Write the user
configuration to data flash using a gang programmer via JTAG or I2C interface before the device is installed in a
circuit. To use the I2C interface, the clock and data lines must be multiplexed or the device addresses must be
assigned by socket. The Fusion Digital Power Designer software tools can be used for socket addressing. Preprogramming can also be done using a single device test fixture.
Table 13. Configuration Options
DATA FLASH VIA JTAG
DATA FLASH VIA I2C(Recommend)
PMBus COMMANDS VIA I2C
Data Flash Export (.svf type file)
Data Flash Export (.srec or hex, data
flash script type file)
System file/Project file
I2C/PMBus script
Dedicated programmer
Fusion tools (with exclusive bus access
via USB to I2C adapter)
Fusion tools (with exclusive bus
access via USB to I2C adapter)
Fusion tools (with exclusive bus access
via USB to I2C adapter)
Fusion tools (with exclusive bus
access via USB to I2C adapter)
Off-Board Configuration
On-Board Configuration
Data flash export
IC
The advantages of off-board configuration include:
• Does not require access to device I2C bus on board.
• Once soldered on board, full board power is available without further configuration.
• Can be partially reconfigured once the device is mounted.
7.5.1.1 Full Configuration Update While in Normal Mode
Although performing a full configuration of the UCD90160A in a controlled test setup is recommended, there may
be times in which it is required to update the configuration while the device is in an operating system. Updating
the full configuration based on methods listed in DEVICE CONFIGURATION AND PROGRAMMING section
while the device is in an operating system can be challenging because these methods do not permit the
UCD90160A to operate as required by application during the programming. During described methods the
GPIOs may not be in the desired states which can disable rails that provide power to the UCD90160A device.
The UCD90160A has the capability to allow full configuration update while still operating in normal mode.
Updating the full configuration while in normal mode will consist of disabling data flash write protection, erasing
the data flash, writing the data flash image and reset the device. It is not required to reset the device immediately
but make note that the UCD90160A will continue to operate based on previous configuration with fault logging
disabled until reset. See Configuration Programming of UCD Devices, available from the Documentation & Help
Center that can be selected from the Fusion Digital Power Designer software Help menu, for details. The data
flash script file generated from Fusion Digital Power Designer software has all the required PMBus commands.
This is the recommended method for production programming.
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7.5.2 JTAG Interface
The JTAG port can be used for production programming. Four of the six JTAG pins can also be used as GPIOs
during normal operation. See the Pin Functions table at the beginning of the document and Table 4 for a list of
the JTAG signals and which can be used as GPIOs. The JTAG port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is
not supported on this device.
The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in
order to enable the GPIO pins with which it is multiplexed. There are two conditions under which the JTAG
interface is enabled:
• On power-up if the data flash is blank, allowing JTAG to be used for writing the configuration parameters to a
programmed device with no PMBus interaction
• When address 126 (0x7E) is detected at power up. A short to ground or an open condition on either address
pin will cause an address 126 (0x7E) to be generated which enables JTAG mode.
The Fusion Digital Power Designer software can create SVF files (See Device Configuration and Programming
section) based on a given data flash configuration which can be used to program the desired configuration by
JTAG. For Boundary Scan Description Language (BSDL) file that supports the UCD90160A, see the product
folder in www.ti.com.
There are many JTAG programmers in the market and they all do not function the same. When using JTAG to
configure the device, confirm that the availability of JTAG tools before committing to a programming solution.
7.5.3 Internal Fault Management and Memory Error Correction (ECC)
The UCD90160A verifies the firmware checksum at each power up. If it does not match, then the device waits for
I2C commands but does not execute the firmware. A device configuration checksum verification is also
performed at power up. If it does not match, the factory default configuration is loaded. The PMBALERT# pin is
asserted and a flag is set in the status register. The error-log checksum validates the contents of the error log to
make sure that section of flash is not corrupted.
There is an internal firmware watchdog timer. If it times out, the device resets so that if the firmware program is
corrupted, the device goes back to a known state. This is a normal device reset, so all of the GPIO pins are
open-drain and the FPWM pins are driven low while the device is in reset. Checks are also done on each
parameter that is passed, to make sure it falls within the acceptable range.
Error-correcting code (ECC) is used to improve data integrity and provide high-reliability storage of Data Flash
contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the
Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These
extra check bits, along with the hardware ECC algorithm, allow for any single-bit error to be detected and
corrected when the Data Flash is read.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
UCD90160A can be used to sequence, monitor and margin up to 10 voltage rails. Typical applications include
automatic test equipment, telecommunication and networking equipment, servers and storage systems, and so
forth. Device configuration can be performed in Fusion Digital Power Designer software without coding effort.
8.2 Typical Application
WARN_OV_0.8V_OR
_12V
GPIO13
SYS TE M RESET
GPIO14
OTHER SE QUENCE R
DONE (CASCADE
INP UT)
GPIO17
FPWM1
2MHz
Vmarg
Closed Loop
Margin ing
I2C/PMBUS
JTA G
Figure 32. Typical Application Schematic
NOTE
Figure 32 is a simplified application schematic. Voltage dividers such as the ones placed
on VMON1 input have been omitted for simplifying the schematic. All VMONx pins which
are configured to measure a voltage that exceeds the 2.5V ADC reference are required to
have a voltage divider.
8.2.1 Design Requirements
The TRST pin must have a 10-kΩ pulldown resistor to ground and the RESET pin must have a 10-kΩ pullup
resistor to V33D and a 1-nF decoupling capacitor to ground. The components must be placed as close to the
RESET pin as possible.
Depending on application environment, the PMBus signal integrity may be compromised at times. This causes
the UCD90160A to receive incorrect PMBus commands. In a particular case, if (D9h) ROM_MODE command is
erroneously received by a UCD90160A device, it causes the device to enter ROM mode, in this mode the device
does not function unless Fusion Digital Power Designer software is connected to the device. To avoid such
occurrences in a running system, it is suggested to enable Packet Error Checking (PEC) in the PMBus host. The
UCD90160A automatically detects and works with PMBus hosts, both with and without PEC enabled.
The fault log in UCD90160A is checksum protected. After new log entries are written into the fault log, the
checksum is updated accordingly. After each device reset, UCD90160A re-calculates the fault log checksum and
compares it with the existing checksum. If the two checksums are not the same, the device determines the fault
log as corrupted and erases the fault log as a result.
In the event that the V33D power is dropped before the device finishes writing the fault log, the checksum is not
updated correctly, thus the fault log is erased at the next power-up. The result is that no new faults are logged.
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Typical Application (continued)
Such an event usually happens when the main power of the board drops and no standby power can stay alive
for V33D. If such a scenario can be anticipated in an application, it is strongly suggested to use the brown-out
function and circuit as described in the Brownout Function section.
When a pair of FPWM pin are configured as both Rail Enable and PWM(either margining or general purpose
PWM) functions, there would be glitches on the pin configured as rail enable when device is out of reset and
under initialization, which may impact the connected power rail. It is not recommended to have such
configuration.
PMBus commands(system file, project file, PMBus write script file) method is not recommended for the
production programming because GPIO pins may have unexpected behaviors which can disable rails that
provide power to device. Data flash hex file or data flash script file shall be used for production programming
because GPIO pins are under controlled state.
It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device
programming. Data flash may be corrupted if failed to follow these rules.
When a pair of FPWM pins are both used for margining, after device is out of reset, the even FPWM pin may
output some pulse which is up to the configured duty cycle and frequency. These pulses may cause unexpected
behaviors on the margining rail if that rail is regulated before UCD is out of reset. It is recommended to use the
even FPWM pin to margin rails that are directly controlled by the device.
WARNING
Do not use the RESET pin to power cycle the rails. Instead, use the
PMBus_CNTRL pin as described in the Power Supply Sequencing section; or,
use the Pin-Selected Rail States function described in the Pin-Selected Rail
States section.
8.2.2 Detailed Design Procedure
Fusion Digital Power Designer software can be used to design the device configuration online or offline (with or
without a UCD90160A device connected to the computer). In offline mode, Fusion Digital Power Designer
software prompts the user to create or open a Project file (.xml) at launch. In online mode, Fusion Digital Power
Designer software automatically detects the device via the PMBus interface and reads the configuration data
from the device. A USB-to-GPIO Adapter (HPA172) from Texas Instruments is required to connect Fusion Digital
Power Designer software using the PMBus interface.
These are the general design steps:
1. Rail setup
2. Rail monitoring configuration
3. GPI configuration
4. Rail sequence configuration
5. Fault response configuration
6. GPO configuration
7. Margining configuration
8. Other configurations such as Pin Selected Rail States, Watchdog Timer, and System Reset.
After configuration changes, click the Write to Hardware button to apply the changes. In online mode, then click
the Store RAM to Flash button to permanently store the new configuration into the device data flash.
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Typical Application (continued)
8.2.3 Application Curves
PMBus Control Pin Assertion
PMBus Control Pin De-Assertion
Rail 1 EN with 5-ms Turn-on Delay
Rail 1 EN with 5-ms Turn-off Delay
Rail 2 EN with 10-ms Turn-off Delay
Rail 2 EN with 10-ms Turn-on Delay
Rail 3 EN with 15-ms Turn-off Delay
Rail 3 EN with 15-ms Turn-on Delay
Figure 33. Example Power-On Sequence
Figure 34. Example Power-Off Sequence
8.2.4 Estimating ADC Reporting Accuracy
The UCD90160A uses a 12-bit ADC and an internal 2.5-V reference (VREF) to convert MON pin inputs into
digitally reported voltages. The least significant bit (LSB) value is VLSB = VREF / 2N where N = 12, resulting in a
VLSB = 610 μV. The error in the reported voltage is a function of the ADC linearity errors and any variations in
VREF. The total unadjusted error (ETUE) for the UCD90160A ADC is ±5 LSB, and the variation of VREF is ±0.5%
between 0°C and 125°C and ±1% between –40°C and 125°C. VTUE is calculated as VLSB × ETUE. The total
reported voltage error is the sum of the reference-voltage error and VTUE. At lower monitored voltages, VTUE
dominates reported error, whereas at higher monitored voltages, the tolerance of VREF dominates the reported
error. Reported error can be calculated using Equation 3, where REFTOL is the tolerance of VREF, VACT is the
actual voltage being monitored at the MON pin, and VREF is the nominal voltage of the ADC reference.
æ 1+ REFTOL ö æ VREF ´ ETUE
ö
RPTERR = ç
+ VACT ÷ - 1
÷´ç
V
4096
ø
ACT
è
ø è
(3)
From Equation 3, for temperatures between 0°C and 125°C, if VACT = 0.5 V, then RPTERR = 1.11%. If VACT = 2.2
V, then RPTERR = 0.64%. For the full operating temperature range of –40°C to 125°C, if VACT = 0.5 V, then
RPTERR = 1.62%. If VACT = 2.2 V, then RPTERR = 1.14%.
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UCD90160A
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9 Power Supply Recommendations
Use a 3.3-V power supply with the UCD90160A. At power-up, V33D must ascend from 2.3 V to 2.9 V
monotonically with a minimum slew rate of 0.25 V/ms.
10 Layout
10.1 Layout Guidelines
The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board
(PCB). Connect the exposed thermal pad of the PCB to the device VSS pins and provide at least a 4 × 4 pattern
of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers.
For supply-voltage decoupling, provide power supply pin bypass to the device as follows:
• 1-μF, X7R ceramic in parallel with 0.01-μF, X7R ceramic at pin 47 (BPCAP)
• 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pins 44 (V33DIO2) and 45 (V33D)
• 0.1-μF, X7R ceramic at pin 7 (V33DIO1)
• 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 46 (V33A)
• Connect V33D (pin 45), V33DIO1 (pin 7) and V33DIO2 (pin 44) to 3.3-V supply directly. Connect V33A (pin
46) to V33D through a 4.99-Ω resistor. This resistor and V33A decoupling capacitors form a low-pass filter to
reduce noise on V33A.
Depending on use and application of the various GPIO signals used as digital outputs, some impedance control
may be desired to quiet fast signal edges. For example, when using the FPWM pins for fan control or voltage
margining, the pin is configured as a digital clock signal. Route these signals away from sensitive analog signals.
It is also good design practice to provide a series impedance of 20 Ω to 33 Ω at the signal source to slow fast
digital edges.
48
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Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: UCD90160A
UCD90160A
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SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
10.2 Layout Example
BPCAP 10nF
Thermal pad vias to
GND plane layer
V33A 0.1µF
V33D 0.1µF
Figure 35. Top Layer
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SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
www.ti.com
Layout Example (continued)
Resistors to set
PMBus address
4.99O between
V33D and V33A
BPCAP 1µF
V33DIO1 0.1µF
V33A 4.7µF
V33D 4.7µF
nRESET 10kO pull-up
and 1nF decoupling
nTRST 10kO pull-down
3.3V supply
Figure 36. Bottom Layer
50
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Product Folder Links: UCD90160A
UCD90160A
www.ti.com
SLVSDD4B – SEPTEMBER 2016 – REVISED SEPTEMBER 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
UCD90xxx Sequencer and System Health Controller PMBus™ Command Reference (SLVU352)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on TI.com. In the upper
right corner, click Alert me to register and receive a weekly digest of any product information that has changed.
For change details, review the revision history included in any revised document
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
PMBus, Fusion Digital Power, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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51
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCD90160ARGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCD90160A
UCD90160ARGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCD90160A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCD90160ARGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
UCD90160ARGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCD90160ARGCR
VQFN
RGC
64
2000
367.0
367.0
38.0
UCD90160ARGCT
VQFN
RGC
64
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
A
9.15
8.85
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7.5
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
PIN 1 ID
48
49
64
64X
0.5
0.3
64X
0.30
0.18
0.1
0.05
C A B
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
( 0.2) TYP
VIA
33
16
17
32
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64X (0.24)
64
49
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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