Texas Instruments | TPS62088, 2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm Wafer Chip Scale Package and Suitable for Embedding (Rev. D) | Datasheet | Texas Instruments TPS62088, 2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm Wafer Chip Scale Package and Suitable for Embedding (Rev. D) Datasheet

Texas Instruments TPS62088, 2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm Wafer Chip Scale Package and Suitable for Embedding (Rev. D) Datasheet
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TPS62088
SLVSD94D – NOVEMBER 2017 – REVISED SEPTEMBER 2019
TPS62088, 2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm
Wafer Chip Scale Package and Suitable for Embedding
1 Features
2 Applications
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1
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DCS-Control topology
Up to 95% efficiency
26-mΩ and 26-mΩ internal power MOSFETs
2.4-V to 5.5-V input voltage range
4-μA operating quiescent current
1% output voltage accuracy
4-MHz switching frequency
Power save mode for light-load efficiency
100% duty cycle for lowest dropout
Active output discharge
Power good output
Thermal shutdown protection
Hiccup short-circuit protection
Available in 6-pin WCSP and PowerWCSP with
0.4-mm pitch
0.3-mm tall YWC package supports embedded
systems
Supports 12 mm2 solution size
Supports < 0.6 mm height solution
Create a custom design using the TPS62088 with
the WEBENCH® Power Designer
Solid-state drives
Wearable products
Smart phones
Camera modules
Optical modules
3 Description
The TPS62088 device is a high-frequency
synchronous step-down converter optimized for small
solution size and high efficiency. With an input
voltage range of 2.4 V to 5.5 V, common battery
technologies are supported. At medium to heavy
loads, the converter operates in PWM mode and
automatically enters Power Save Mode operation at
light load to maintain high efficiency over the entire
load current range. The 4-MHz switching frequency
allows TPS62088 to use small external components.
Together with its DCS-control architecture, excellent
load transient performance and output voltage
regulation accuracy are achieved. Other features like
over current protection, thermal shutdown protection,
active output discharge and power good are built-in.
The device is available in a 6-pin WCSP package.
Device Information(1)
PART NUMBER
TPS62088xx
PACKAGE
BODY SIZE (NOM)
YFP (6)
0.8mm x 1.2mm x 0.5mm
YWC (6)
0.8mm x 1.2mm x 0.3mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Spacer
Typical Application Schematic
TPS6208818
VIN
R3
100 k
C1
4.7 µF
EN
VPG
PG GND
Copyright Ú 2017, Texas Instruments Incorporated
3.3-V Input Voltage Efficiency
VOUT
1.8 V
L1
0.24 µH
100
SW
FB
95
C2
10 µF
C3
10 µF
90
85
Efficiency (%)
VIN
2.4 V to 5.5 V
80
75
70
65
60
55
50
45
40
100P
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
1m
10m
Load (A)
100m
1
3
D007
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62088
SLVSD94D – NOVEMBER 2017 – REVISED SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
4
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
ELECTRICAL CHARACTERISTICS ........................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
11.3 Thermal Considerations ........................................ 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2019) to Revision D
Page
•
Changed TPS62088YWC status to production ...................................................................................................................... 1
•
Added TPS62088YWCEVM-084 to the Thermal information table ....................................................................................... 4
Changes from Revision B (August 2018) to Revision C
Page
•
Added YWC package option .................................................................................................................................................. 1
•
Added YWC package drawing................................................................................................................................................ 3
•
Updated the device operation limitation ................................................................................................................................. 4
•
Changed Updated the thermal metric for YFP and YWC package ........................................................................................ 4
•
Added typical blanking time and deglitch delay of PG ........................................................................................................... 9
Changes from Revision A (March 2018) to Revision B
•
Page
Changed the Packaging Information pages ........................................................................................................................ 23
Changes from Original (November 2017) to Revision A
Page
•
Changed TPS6208812, TPS6208818, and TPS6208833 From: Preview To: Production in the Device Information table ... 1
•
Added TPS62088EVM-814 to the Thermal information table ................................................................................................ 4
•
Changed the symbol for the feed forward capacitor, from C3 to C4 and from 0.012 to 12 µ in Equation 4........................ 12
2
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5 Device Options
Device Options
PART NUMBER (1)
OUTPUT VOLTAGE
TPS62088YFP
Adjustable
TPS62088YWC
Adjustable
TPS6208812YFP
1.2 V
TPS6208818YFP
1.8 V
TPS6208833YFP
3.3 V
(1)
For detailed ordering information, please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
6 Pin Configuration and Functions
YFP Package
Top View
1
A
2
EN
B
1
2
A
EN
VIN
B
PG
SW
C
FB
GND
VIN
PG
C
YWC Package
Top View
SW
FB
GND
Pin Functions
PIN
I/O
DESCRIPTION
A1
I
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
PG
B1
O
Power good open drain output pin. The pull-up resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
FB
C1
I
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
output.
GND
C2
-
Ground pin.
SW
B2
O
Switch pin of the power stage.
VIN
A2
I
Input voltage pin.
NAME
NO.
EN
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Voltage at Pins (2)
Temperature
(1)
MIN
MAX
VIN, FB, EN, PG
–0.3
6
UNIT
SW (DC)
–0.3
VIN + 0.3
SW (DC, in current limit)
–1.0
VIN + 0.3
SW (AC, less than 10ns) (3)
–2.5
10
Operating Junction, TJ
–40
150
Storage, Tstg
–65
150
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
While switching
(2)
(3)
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.4
5.5
V
VOUT
Output voltage range
0.6
4
V
IOUT
Output current range (1)
0
3
A
ISINK_PG
Sink current at PG pin
1
mA
VPG
Pull-up resistor voltage
TJ
Operating junction temperature
(1)
–40
5.5
V
125
°C
For YFP package versions, lifetime is reduced when operating continuously at 3-A output current with the junction temperature higher
than 85 °C.
7.4 Thermal Information
TPS62088
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
UNIT
YFP (6-PINS)
YWC (6-PINS)
YFP EVM-814
YWC EVM-084
141.3
130.9
85.7
70.6
°C/W
(2)
(2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.7
1.1
n/a
RθJB
Junction-to-board thermal resistance
47.3
27.3
n/a (2)
n/a (2)
°C/W
ψJT
Junction-to-top characterization parameter
0.5
0.7
1.9
0.5
°C/W
ψJB
Junction-to-board characterization parameter
47.5
27.2
55.9
38.7
°C/W
(1)
(2)
7.5
n/a
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM.
ELECTRICAL CHARACTERISTICS
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
10
µA
0.05
0.5
µA
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching
ISD
Shutdown current
EN = Low, TJ = -40℃ to 85℃
4
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ELECTRICAL CHARACTERISTICS (continued)
TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted.
PARAMETER
VUVLO
TJSD
TEST CONDITIONS
MIN
2.1
TYP
MAX
2.2
2.3
UNIT
Under voltage lock out threshold
VIN falling
Under voltage lock out hysteresis
VIN rising
160
mV
V
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
LOGIC INTERFACE EN
VIH
High-level input threshold voltage
VIL
Low-level input threshold voltage
IEN,LKG
Input leakage current into EN pin
1.0
V
0.01
0.4
V
0.1
µA
SOFT START, POWER GOOD
tSS
Soft start time
Power good lower threshold
VPG
Power good upper threshold
Time from EN high to 95% of VOUT nominal
1.25
ms
VPG rising, VFB referenced to VFB nominal
94
96
98
%
VPG falling, VFB referenced to VFB nominal
90
92
94
%
VPG rising, VFB referenced to VFB nominal
103
105
107
%
VPG falling, VFB referenced to VFB nominal
108
110
112
%
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
0.4
V
0.01
0.1
µA
OUTPUT
VOUT
Output voltage accuracy
TPS6208812, PWM mode
1.188
1.2
1.212
TPS6208818, PWM mode
1.782
1.8
1.818
TPS6208833, PWM mode
3.267
3.3
3.333
VFB
Feedback regulation voltage
PWM mode
IFB,LKG
Feedback input leakage current
TPS62088, VFB = 0.6 V
RFB
Internal resistor divider connected to FB
pin
TPS6208812, TPS6208818, TPS6208833
IDIS
Output discharge current
VSW = 0.4V; EN = LOW
594
V
600
606
mV
0.01
0.05
µA
7.5
MΩ
400
mA
High-side FET on-resistance
26
mΩ
Low-side FET on-resistance
26
75
POWER SWITCH
RDS(on)
ILIM
High-side FET switch current limit
fSW
PWM switching frequency
3.6
IOUT = 1 A, VOUT = 1.8 V
4.3
mΩ
5.0
4
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MHz
5
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70.0
70.0
60.0
60.0
50.0
50.0
RDS(on) (mOhm)
RDS(on) (mOhm)
7.6 Typical Characteristics
40.0
30.0
20.0
10.0
0.0
2.5
40.0
30.0
20.0
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
3.0
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
10.0
3.5
4.0
4.5
Input Voltage (V)
5.0
0.0
2.5
5.5
3.0
$
6KXWGRZQ &XUUHQW
4XLHVFHQW &XUUHQW
$
0.4
5.5
D011
4.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
3.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
0.3
0.2
0.1
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
0.0
2.5
D001
Figure 3. Quiescent Current
6
5.0
0.5
6.0
0.0
2.5
4.0
4.5
Input Voltage (V)
Figure 2. Low-Side FET On-Resistance
Figure 1. High-Side FET On-Resistance
8.0
2.0
3.5
D010
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D000
Figure 4. Shutdown Current
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8 Detailed Description
8.1 Overview
The TPS62088 synchronous step-down converter adopts a new generation DCS-Control (Direct Control with
Seamless transition into Power Save Mode) topology without the output voltage sense (VOS) pin. This is an
advanced regulation topology that combines the advantages of hysteretic, voltage, and current mode control
schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. The devices offer both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
8.2 Functional Block Diagram
PG
VPG_H
EN
+
±
VFB
Control Logic
VREF
UVLO
Thermal Shutdown
Startup
VIN
VPG_L
+
±
GND
Peak Current Detect
VSW
TON
VIN
VSW
HICCUP
Direct Control
&
Compensation
VREF
Modulator
Comparator
FB
Zero Current Detect
Discharge
+
_EA
SW
Gate
Drive
GND
Fixed VOUT
GND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode operation. The power save mode occurs
when the inductor current becomes discontinuous. Power Save Mode is based on a fixed on-time architecture,
as related in Equation 1.
tON
250ns u
VOUT
VIN
(1)
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Feature Description (continued)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
When the device operates close to 100% duty cycle mode, the device can't enter Power Save Mode regardless
of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains
output regulation in PWM mode.
8.3.2 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )
where
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
(2)
8.3.3 Soft Start
After enabling the device, there is a 250-µs delay before switching starts. Then, an internal soft startup circuitry
ramps up the output voltage which reaches nominal output voltage during the startup time of 1 ms. This avoids
excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage
drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET remains off, while the inductor current flows through its body diode and
quickly ramps down.
When this switch current limits is triggered 32 times, the device stops switching. The device then automatically
starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit
protection. The device repeats this mode until the high load condition disappears.
8.3.5 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down
the device at voltages lower than VUVLO.
8.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops the power stage switching when the junction temperature
exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal
operation automatically by switching the power stage again.
8
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8.4 Device Functional Modes
8.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic High. Accordingly, shutdown mode is forced if the EN pin
is pulled Low with a shutdown current of typically 50 nA. In shutdown mode, the internal power switches as well
as the entire control circuitry are turned off. An internal switch smoothly discharges the output through the SW
pin in shutdown mode. Do not leave the EN pin floating.
The typical threshold value of the EN pin is 0.89 V for rising input signal, and 0.62 V for falling input signal.
8.4.2 Power Good
The device has a power good output. The PG pin goes high impedance once the FB pin voltage is above 96%
and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher
than 110% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG
falling edge has a deglitch delay of 20 µs.
Table 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH IMPEDANCE
EN = High, VFB ≥ 0.576 V
Enable
EN = High, VFB ≤ 0.552 V
EN = High, VFB ≤ 0.63 V
LOW
√
√
√
EN = High, VFB ≥ 0.66 V
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
0.7 V < VIN < VUVLO
Power Supply Removal
VIN < 0.7 V
√
undefined
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
VIN
2.4 V to 5.5 V
TPS62088
VIN
C1
4.7 µF
R3
100 k
L1
0.24 µH
VOUT
1.8 V
SW
C2
10 µF
EN
C3
10 µF
R1
200 k
C4
120 pF
VPG
PG GND FB
R2
100 k
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Figure 5. Typical Application of Adjustable Output
VIN
2.4 V to 5.5 V
TPS6208818
R3
100 k
C1
4.7 µF
VIN
SW
EN
FB
VOUT
1.8 V
L1
0.24 µH
C2
10 µF
C3
10 µF
VPG
PG GND
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Figure 6. Typical Application of Fixed Output
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
10
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
Output voltage
1.8 V
Maximum peak output current
3A
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Table 3 lists the components used for the example.
Table 3. List of Components of Figure 5
REFERENCE
C1
C2, C3
(1)
MANUFACTURER (1)
DESCRIPTION
4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475MA
Taiyo Yuden
10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106MA73D
Murata
C4
120 pF, Ceramic capacitor, 50 V, size 0603, GRM1885C1H121JA01D
Murata
L1
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
Murata
R1
Depending on the output voltage, 1%, size 0603
Std
R2
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
R3
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
See Third-party Products disclaimer.
Table 4. List of Components of Figure 6, Smallest Solution
REFERENCE
C1, C2, C3
(1)
MANUFACTURER (1)
DESCRIPTION
10 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J106ME47
Murata
L1
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
Murata
R3
100 kΩ, Chip resistor, 1/16 W, size 0402
Std
See Third-party Products disclaimer.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.6V to 4V, according to Equation 3. To
keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 kΩ to have at least 0.6 µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in the application note SLYT469.
§V
R1 R2 u ¨ OUT
© VFB
·
1¸
¹
§V
R2 u ¨ OUT
© 0.6V
·
1¸
¹
(3)
For devices with a fixed output voltage, the FB pin must be connected to VOUT. R1, R2 and C4 are not needed.
The fixed output voltage devices have an internal feed forward capacitor.
9.2.2.3 Feed Forward Capacitor
A feed forward capacitor (C4) is required in parallel with R1. Equation 4 calculates the capacitor value. For the
recommended 100k value for R2, a 120 pF feed forward capacitor is used.
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12 Ps
R2
C4
(4)
9.2.2.4 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 5 outlines
possible inductor and capacitor value combinations for most applications. Checked cells represent combinations
that are proven for stability by simulation and lab test. Further combinations should be checked for each
individual application.
Table 5. Matrix of Output Capacitor and Inductor Combinations
NOMINAL L [µH] (1)
NOMINAL COUT [µF] (2)
10
2 x 10 or 1 x 22
47
0.24
+
+ (3)
+
0.33
+
+
+
100
0.47
(1)
(2)
(3)
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
This LC combination is the standard value and recommended for most applications. Other '+' marks indicate recommended filter
combinations. Other values may be acceptable in some applications but should be fully tested by the user.
9.2.2.5 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 5 is given.
DI
IL,MAX = IOUT,MAX + L
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
(5)
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor. Table 6 lists recommended inductors.
Table 6. List of Recommended Inductors (1)
Inductance
[µH]
Current Rating [A]
Dimensions
[L x W x H mm]
DC Resistance [mΩ]
Part Number
0.24
4.9
1.6 x 0.8 x 1.0
30
Murata, DFE160810S-R24M
(DFE18SANR24MG0)
0.24
6.5
2.0 x 1.2 x 1.0
25
Murata, DFE201210U-R24M
0.24
4.9
1.6 x 0.8 x 0.8
22
Cyntec, HTEH16080H-R24MSR
0.25
9.7
4.0 x 4.0 x 1.2
7.64
Coilcraft, XFL4012-251ME
0.24
3.5
2.0 x 1.6 x 0.6
35
Wurth Electronics, 74479977124
0.24
3.5
2.0 x 1.6 x 0.6
35
Sunlord, MPM201606SR24M
(1)
See Third-party Products disclaimer.
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9.2.2.6 Capacitor Selection
The input capacitor is the low-impedance energy source for the converters which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those pins. For most applications, 4.7 μF is sufficient, though a larger value
reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 2 x 10 μF or 1 x 22 µF; this
capacitance can vary over a wide range as outline in the output filter selection table.
A feed forward capacitor is required for the adjustable version, as described in Setting The Output Voltage. This
capacitor is not required for the fixed output voltage versions.
9.2.3 Application Curves
VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted.
90
0.612
85
0.609
80
0.606
0.603
70
Vout (V)
Efficiency (%)
75
65
60
0.6
0.597
55
0.594
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
50
45
40
100P
1m
0.591
10m
Load (A)
100m
1
0.588
100P
3
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D002
VOUT = 0.6 V
10m
Load (A)
100m
1
3
D021
VOUT = 0.6 V
Figure 7. Efficiency
Figure 8. Load Regulation
0.909
90
85
0.906
80
0.903
70
Vout (V)
Efficiency (%)
75
65
60
0.9
0.897
55
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
50
45
40
100P
1m
0.894
10m
Load (A)
100m
VOUT = 0.9 V
1
3
0.891
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D003
10m
Load (A)
100m
1
3
D031
VOUT = 0.9 V
Figure 9. Efficiency
Figure 10. Load Regulation
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VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted.
100
1.212
95
1.209
90
1.206
1.203
80
Vout (V)
Efficiency (%)
85
75
70
1.2
1.197
65
60
55
50
100P
1.194
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
1m
1.191
10m
Load (A)
100m
1
1.188
100P
3
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D004
VOUT = 1.2 V
10m
Load (A)
100m
1
3
D041
VOUT = 1.2 V
Figure 11. Efficiency
Figure 12. Load Regulation
1.818
100
95
1.812
1.806
85
Vout (V)
Efficiency (%)
90
80
75
70
65
60
100P
1.8
1.794
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
1m
1.788
10m
Load (A)
100m
1
1.782
100P
3
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1m
D005
VOUT = 1.8 V
10m
Load (A)
100m
1
3
D051
VOUT = 1.8 V
Figure 13. Efficiency
Figure 14. Load Regulation
3.333
100
3.322
95
3.3
90
Vout (V)
Efficiency (%)
3.311
85
3.289
3.278
3.267
80
3.256
75
70
100P
VIN = 4.2V
VIN = 5.0V
1m
3.245
10m
Load (A)
100m
VOUT = 3.3 V
1
3
3.234
100P
1m
D006
10m
Load (A)
100m
1
3
D061
VOUT = 3.3 V
Figure 15. Efficiency
14
VIN = 4.2V
VIN = 5.0V
Figure 16. Load Regulation
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VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted.
5.0
4.0
Switching Frequency (MHz)
Switching Frequency (MHz)
5.0
3.0
2.0
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1.0
0.0
0.0
0.5
1.0
1.5
Load (A)
2.0
2.5
3.0
4.0
3.0
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
2.0
1.0
2.5
3.0
3.5
D008
VIN = 3.3 V
4.0
4.5
Input Voltage (V)
5.0
5.5
D009
IOUT = 1.0 A
Figure 17. Switching Frequency
Figure 18. Switching Frequency
ICOIL
1A/DIV
ICOIL
1A/DIV
VOUT
10mV/DIV
AC
VOUT
10mV/DIV
AC
VSW
5V/DIV
VSW
5V/DIV
Time - 200ns/DIV
7LPH
V ',9
D014
D013
IOUT = 3.0 A
IOUT = 0.1 A
Figure 19. PWM Operation
Figure 20. PSM Operation
VEN
5V/DIV
VEN
5V/DIV
VPG
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
ICOIL
0.5A/DIV
ICOIL
2A/DIV
7LPH
V ',9
7LPH
V ',9
D015
No Load
D016
IOUT = 3.0 A
Figure 21. Startup with No-Load
Figure 22. Startup with Load
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VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted.
VPG
5V/DIV
VPG
5V/DIV
ILOAD
2A/DIV
ICOIL
2A/DIV
VOUT
50mV/DIV
AC
VOUT
1V/DIV
7LPH
V ',9
7LPH
V ',9
D017
D018
IOUT = 0.1 A to 3 A
IOUT = 1 A
Figure 23. Load Transient
Figure 24. HICCUP Short Circuit Protection
VPG
5V/DIV
ICOIL
2A/DIV
VOUT
1V/DIV
7LPH
V ',9
D019
IOUT = 1 A
Figure 25. HICCUP Short Circuit Protection (Zoom In)
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See
Figure 26 and Figure 27 for the recommended PCB layout.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
• The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes. The connection of the output voltage trace for the FB
resistors should be made at the output capacitor.
• Refer to Figure 26 and Figure 27 for an example of component placement, routing and thermal design.
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11.2 Layout Example
Figure 27. PCB Layout of Fixed Output Voltage Application
Figure 26. PCB Layout of Adjustable Output Voltage
Application
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics Application Notes,
SZZA017 and SPRA953.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Development Support
12.2.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2.2 Related Documentation
For related documentation, see the following:
• Thermal Characteristics Application Note, SZZA017
• Thermal Characteristics Application Note, SPRA953
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
YWC0006A
PowerWCSP - 0.3 mm max height
SCALE 15.000
POWER CHIP SCALE PACKAGE
0.82
0.78
B
A
PIN A1 INDEX
AREA
1.22
1.18
0.20
0.16
0.3 MAX
C
SEATING PLANE
0.10
0.07
3X
PKG
0.16
0.14
3X
0.378
0.358
C
SYMM
B
0.86
2X
0.43
0.187
0.167
0.015
C A B
A
1
2
4X
0.165
0.439
0.247
0.227
0.015
C A B
4223997/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YWC0006A
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
PKG
PKG
3X (0.15)
3X (0.368)
1
3X (0.2)
2
A
2
A
4X (0.237)
(0.43) TYP
3X (0.368)
1
4X (0.237)
2X (0.2)
(0.43) TYP
2X (0.177)
SYMM
SYMM
B
B
(R0.05) TYP
SOLDER MASK
OPENING
TYP
C
(R0.05) TYP
SOLDER MASK
OPENING
TYP
C
METAL UNDER
SOLDER MASK
TYP
METAL EDGE
TYP
0.0375 MAX
ALL AROUND
TYP
(0.165)
0.0375 MIN
ALL AROUND
TYP
(0.165)
(0.464)
(0.439)
LAND PATTERN EXAMPLE
LAND PATTERN EXAMPLE
NON SOLDER MASK DEFINED
SCALE: 40X
SOLDER MASK DEFINED
SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
YWC0006A
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
PKG
3X (0.2)
3X (0.368)
3X (0.2)
3X (0.348)
1
A
4X (0.237)
(0.43) TYP
2
4X (0.237)
(0.43) TYP
PKG
SYMM
SYMM
2X (0.2)
2X (0.2)
B
(R0.05) TYP
(R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
C
SOLDER MASK
OPENING
TYP
EXPOSED
METAL
3X
(0.165)
(0.175)
TO PKG
(0.464)
(0.474)
SOLDER PASTE EXAMPLE
SOLDER PASTE EXAMPLE
SOLDER MASK DEFINED
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
NON SOLDER MASK DEFINED
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OUTLINE
YFP0006-C01
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.30
0.25
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
0.4
TYP
SYMM
C
D: Max = 1.22 mm, Min = 1.18 mm
0.8
TYP
SYMM
B
E: Max = 0.82 mm, Min = 0.78 mm
0.4 TYP
A
6X
0.015
0.25
0.21
C A B
1
2
4224455/B 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFP0006-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X (
0.23)
2
1
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224455/B 02/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFP0006-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
6X ( 0.25)
1
2
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4224455/B 02/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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19-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS6208812YFPR
ACTIVE
DSBGA
YFP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B5
TPS6208812YFPT
ACTIVE
DSBGA
YFP
6
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B5
TPS6208818YFPR
ACTIVE
DSBGA
YFP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B6
TPS6208818YFPT
ACTIVE
DSBGA
YFP
6
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B6
TPS6208833YFPR
ACTIVE
DSBGA
YFP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B7
TPS6208833YFPT
ACTIVE
DSBGA
YFP
6
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B7
TPS62088YFPR
ACTIVE
DSBGA
YFP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
15X
TPS62088YFPT
ACTIVE
DSBGA
YFP
6
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
15X
TPS62088YWCR
ACTIVE
DSBGA
YWC
6
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 125
1GB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
19-Nov-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPS6208812YFPR
DSBGA
YFP
6
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
0.97
1.37
0.6
4.0
8.0
Q1
TPS6208812YFPT
DSBGA
YFP
6
250
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS6208818YFPR
DSBGA
YFP
6
3000
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS6208818YFPT
DSBGA
YFP
6
250
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS6208833YFPR
DSBGA
YFP
6
3000
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS6208833YFPT
DSBGA
YFP
6
250
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS62088YFPR
DSBGA
YFP
6
3000
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS62088YFPT
DSBGA
YFP
6
250
180.0
8.4
0.97
1.37
0.6
4.0
8.0
Q1
TPS62088YWCR
DSBGA
YWC
6
3000
180.0
8.4
0.95
1.35
0.38
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS6208812YFPR
DSBGA
YFP
6
3000
182.0
182.0
20.0
TPS6208812YFPT
DSBGA
YFP
6
250
210.0
185.0
35.0
TPS6208818YFPR
DSBGA
YFP
6
3000
210.0
185.0
35.0
TPS6208818YFPT
DSBGA
YFP
6
250
210.0
185.0
35.0
TPS6208833YFPR
DSBGA
YFP
6
3000
182.0
182.0
20.0
TPS6208833YFPT
DSBGA
YFP
6
250
210.0
185.0
35.0
TPS62088YFPR
DSBGA
YFP
6
3000
182.0
182.0
20.0
TPS62088YFPT
DSBGA
YFP
6
250
182.0
182.0
20.0
TPS62088YWCR
DSBGA
YWC
6
3000
182.0
182.0
20.0
Pack Materials-Page 2
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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