Texas Instruments | TPS6521815 User-Programmable Power Management IC (PMIC) With 6 DC/DC Converters, 1 LDO, and 3 Load Switches | Datasheet | Texas Instruments TPS6521815 User-Programmable Power Management IC (PMIC) With 6 DC/DC Converters, 1 LDO, and 3 Load Switches Datasheet

Texas Instruments TPS6521815 User-Programmable Power Management IC (PMIC) With 6 DC/DC Converters, 1 LDO, and 3 Load Switches Datasheet
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TPS6521815
SLDS261 – NOVEMBER 2019
TPS6521815 User-Programmable Power Management IC (PMIC) With 6 DC/DC Converters,
1 LDO, and 3 Load Switches
1 Device Overview
1.1
Features
1
• Three Adjustable Step-Down Converters With
Integrated Switching FETs (DCDC1, DCDC2, and
DCDC3):
– Up to 1.8-A output current
– VIN Range From 2.7 V to 5.5 V
– Adjustable Output Voltage Range 0.85 V to
1.675 V (DCDC1 and DCDC2)
– Adjustable Output Voltage Range 0.9 V to 3.4 V
(DCDC3)
– Power Save Mode at Light Load Current
– 100% Duty Cycle for Lowest Dropout
– Active Output-Discharge When Disabled
• One Adjustable Buck-Boost Converter With
Integrated Switching FETs (DCDC4):
– Up to 1.6-A output current
– VIN Range From 2.7 V to 5.5 V
– Adjustable Output Voltage Range 1.175 V to 3.4
V
– Active Output-Discharge When Disabled
• Two Low-Quiescent Current, High Efficiency StepDown Converters for Battery Backup Domain
(DCDC5, DCDC6)
– DCDC5: 1-V Output
– DCDC6: 1.8-V Output
– VIN Range from 2.2 V to 5.5 V
– Supplied From System Power or Coin-Cell
Backup Battery
• Adjustable General-Purpose LDO (LDO1)
– LDO1: 1.8-V Default up to 400 mA
1.2
•
•
•
•
•
•
•
•
Applications
Grid Infrastructure
Medical Equipment
Appliances
Building Security Systems
1.3
•
– VIN Range From 1.8 V to 5.5 V
– Adjustable Output Voltage Range From 0.9 V to
3.4 V
– Active Output-Discharge When Disabled
Low-Voltage Load Switch (LS1) With 350-mA
Current Limit
– VIN Range From 1.2 V to 3.6 V
– 110-mΩ (Max) Switch Impedance at 1.35 V
5-V Load Switch (LS2) With 100-mA or 500-mA
Selectable Current Limit
– VIN Range From 3 V to 5.5 V
– 500-mΩ (Max) Switch Impedance at 5 V
High-Voltage Load Switch (LS3) With 100-mA or
500-mA Selectable Current Limit
– VIN Range From 1.8 V to 10 V
– 500-mΩ (Max) Switch Impedance
Supervisor With Built-in Supervisor Function
Monitors
– DCDC1, DCDC2 ±4% Tolerance
– DCDC3, DCDC4 ±5% Tolerance
– LDO1 ±5% Tolerance
Protection, Diagnostics, and Control:
– Undervoltage Lockout (UVLO)
– Always-on Push-Button Monitor
– Overtemperature Warning and Shutdown
– Separate Power-Good Output for Backup and
Main Supplies
– I2C Interface (Address 0x24) (See Timing
Requirements for I2C Operation at 400 kHz)
•
•
•
•
Human-Machine Interface (HMI)
Industrial Automation
Electronic Point of Sale (ePOS)
Test and Measurement
Description
The TPS6521815 is a single chip, power-management IC (PMIC) that is user-programmable to power a
variety of SoCs and FPGAs. The device is characterized across a –40°C to +105°C temperature range,
making it suitable for various industrial applications.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS6521815
SLDS261 – NOVEMBER 2019
www.ti.com
Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and
DDRx memory. The default output voltages for each converter can be adjusted through the I2C interface.
DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the
processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor
components. DCDC3 remains powered while the processor is in sleep mode to maintain power to DDRx
memory. Backup power provides two step-down converters for the tamper, RTC, or both domains of the
processor if system power fails or is disabled. If both system power and coin-cell battery are connected to
the PMIC, power is not drawn from the coin-cell battery. A separate power good signal monitors the
backup converters. A battery backup monitor determines the power level of the coin-cell battery.
Device Information (1)
PART NUMBER
TPS6521815
(1)
2
PACKAGE
VQFN (48)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Device Overview
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1.4
SLDS261 – NOVEMBER 2019
Simplified Schematic
+
10 …F
VIO
VIO
1 …F
4.7 …F
CC
GPIO3
IN_BU
NC
NC
LS1
IN_LS1
IN_LS2
LS2
GPO2
IN_BIAS
INT_LDO
100 k
100 k
4.7 …F
4.7 …F
1.5 µH
VDD_18
(DCDC6)
100 k
10 …F
1.5 µH
L3
L6
FB3
FB6
nWAKEUP
FB5
FB2
L5
L2
100 k
100 k
22 …F
DC34_SEL
nINT
PFI
PWR_EN
DCDC4
FB1
47 …F
1.5 µH
IN_DCDC4
GPIO1
L4A
VIO
100 k
100 k
nPFO
AC_DET
VIO
PGOOD
100 k
IN_BIAS
VIO
10 …F
10 …F
LS3
100 k
IN_LS3
IN_LDO1
SCL
SDA
100 k
VIO
VIO
4.7 …F
LDO1
L1
1.5 µH
100 nF
L4B
100 k
10 …F
1.5 µH
IN_nCC
IN_DCDC1
VIO
100 k
22 …F
TPS65218xx
PB
IN_BIAS
10 µH
PGOOD_BU
IN_DCDC2
4.7 …F
1 …F
SYS_BU
IN_DCDC3
10 …F
±
10
10 …F
4.7 …F
4.7 …F
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Figure 1-1. Simplified Schematic
Device Overview
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TPS6521815
SLDS261 – NOVEMBER 2019
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Table of Contents
1
Device Overview ......................................... 1
5.4
Device Functional Modes
1.1
Features .............................................. 1
5.5
Programming ........................................ 48
1.2
Applications ........................................... 1
5.6
Register Maps ....................................... 50
1.3
Description ............................................ 1
1.4
6
...........................
47
Application and Implementation .................... 92
Simplified Schematic ................................. 3
6.1
Application Information .............................. 92
2
3
Revision History ......................................... 4
Pin Configuration and Functions ..................... 5
6.2
Typical Application
4
Specifications
3.1
............................................
..................................
94
Power Supply Recommendations .................. 98
Layout .................................................... 98
8
8.1
Layout Guidelines ................................... 98
4.1
Absolute Maximum Ratings .......................... 8
8.2
Layout Example ..................................... 98
4.2
ESD Ratings .......................................... 8
4.3
Recommended Operating Conditions ................ 9
9.1
Device Support..................................... 100
4.4
Thermal Information .................................. 9
9.2
Documentation Support ............................ 100
4.5
Electrical Characteristics ............................ 10
9.3
Receiving Notification of Documentation Updates. 100
18
9.4
Support Resources
20
9.5
Trademarks ........................................ 100
21
9.6
Electrostatic Discharge Caution
21
9.7
Glossary............................................ 101
...............................
4.7
Typical Characteristics ..............................
Detailed Description ...................................
5.1
Overview ............................................
5.2
Functional Block Diagram ...........................
5.3
Feature Description .................................
4.6
5
Pin Functions ......................................... 5
7
8
Timing Requirements
22
23
9
Device and Documentation Support .............. 100
................................
...................
100
101
10 Mechanical, Packaging, and Orderable
Information ............................................. 101
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
4
DATE
REVISION
NOTES
November 2019
*
Initial Release
Revision History
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SLDS261 – NOVEMBER 2019
3 Pin Configuration and Functions
L1
FB1
PWR_EN
nINT
PB
IN_DCDC2
L2
FB2
nWAKEUP
FB3
L3
IN_DCDC3
48
47
46
45
44
43
42
41
40
39
38
37
Figure 3-1 shows the 48-pin RSL Plastic Quad Flatpack No-Lead.
IN_DCDC1
1
36
IN_BIAS
SDA
2
35
INT_LDO
SCL
3
34
GPO2
LDO1
4
33
LS2
IN_LDO1
5
32
IN_LS2
IN_LS3
6
31
IN_LS1
LS3
7
30
LS1
PGOOD
8
29
N/C
AC_DET
9
28
N/C
nPFO
10
27
IN_BU
GPIO1
11
26
GPIO3
IN_DCDC4
12
25
CC
Thermal
13
14
15
16
17
18
19
20
21
22
23
24
L4A
L4B
DCDC4
PFI
DC34_SEL
IN_nCC
PGOOD_BU
L5
FB5
FB6
L6
SYS_BU
Pad
Not to scale
Figure 3-1. 48-Pin RSL VQFN With Exposed Thermal Pad
(Top View, 6 mm × 6 mm × 1 mm With 0.4-mm Pitch)
3.1
Pin Functions
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
IN_DCDC1
P
2
SDA
I/O
Input supply pin for DCDC1.
3
SCL
I
Clock input for the I2C interface. Connect to pullup resistor.
4
LDO1
O
Output voltage pin for LDO1. Connect to capacitor.
5
IN_LDO1
P
Input supply pin for LDO1.
6
IN_LS3
P
Input supply pin for load switch 3.
7
LS3
O
Output voltage pin for load switch 3. Connect to capacitor.
8
PGOOD
O
Power-good output (configured as open drain). Pulled low when either DCDC1-4 or LDO1 are out of
regulation. Load switches and DCDC5-6 do not affect PGOOD pin.
9
AC_DET
I
AC monitor input and enable for DCDC1-4, LDO1 and load switches. See Section 5.4.1 for details. Tie pin to
IN_BIAS if not used.
10
nPFO
O
Power-fail comparator output, deglitched (open drain). Pin is pulled low when PFI input is below power-fail
threshold.
Data line for the I2C interface. Connect to pullup resistor.
Pin Configuration and Functions
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
11
GPIO1
I/O
12
IN_DCDC4
P
Input supply pin for DCDC4.
13
L4A
P
Switch pin for DCDC4. Connect to inductor.
14
L4B
P
Switch pin for DCDC4. Connect to inductor.
15
DCDC4
P
Output voltage pin for DCDC4. Connect to capacitor.
16
PFI
I
Power-fail comparator input. Connect to resistor divider.
17
DC34_SEL
I
Power-up default selection pin for DCDC3 or DCDC4. Power-up default is programmed by a resistor
connected to ground. See Section 5.3.1.13 for resistor options.
18
IN_nCC
O
Output pin indicates if DCDC5 and DCDC6 are powered from main supply (IN_BU) or coin-cell battery (CC).
Pin is push-pull output. Pulled low when PMIC is powered from coin cell battery. Pulled high when PMIC is
powered from main supply (IN_BU).
19
PGOOD_BU
O
Power-good, push-pull output for DCDC5 and DCDC6. Pulled low when either DCDC5 or DCDC6 is out of
regulation. Pulled high (to DCDC6 output voltage) when both rails are in regulation.
20
L5
P
Switch pin for DCDC5. Connect to inductor.
21
FB5
I
Feedback voltage pin for DCDC5. Connect to output capacitor.
22
FB6
I
Feedback voltage pin for DCDC6. Connect to output capacitor.
23
L6
P
Switch pin for DCDC6. Connect to inductor.
24
SYS_BU
P
System voltage pin for battery-backup supply power path. Connect to 1-µF capacitor. Connecting any
external load to this pin is not recommended.
25
CC
P
Coin cell battery input. Serves as the supply to DCDC5 and DCDC6 if no voltage is applied to IN_BU. Tie this
pin to ground if it is not in use.
26
GPIO3
I/O
Pin can be configured as warm reset (negative edge) for DCDC1 and DCDC2 or as a general-purpose, opendrain output. See Section 5.3.1.14 for more details.
27
IN_BU
P
Default input supply pin for battery backup supplies (DCDC5 and DCDC6).
28
N/C
29
N/C
—
No connect. Leave pin floating.
30
LS1
O
Output voltage pin for load switch 1. Connect to capacitor.
31
IN_LS1
P
Input supply pin for load switch 1.
32
IN_LS2
P
Input supply pin for load switch 2.
33
LS2
O
Output voltage pin for load switch 2. Connect to capacitor.
34
GPO2
O
Pin configured as DDR reset signal (controlled by GPIO1) or as general-purpose output. Buffer can be
configured as push-pull or open-drain.
35
INT_LDO
P
Internal bias voltage. Connect to a 1-μF capacitor. TI does not recommended connecting any external load to
this pin.
36
IN_BIAS
P
Input supply pin for reference system.
37
IN_DCDC3
P
Input supply pin for DCDC3.
38
L3
P
Switch pin for DCDC3. Connect to inductor.
Pin configured as DDR reset-input (driving GPO2) or as general-purpose, open-drain output. See
Section 5.3.1.14 for more information.
39
FB3
I
Feedback voltage pin for DCDC3. Connect to output capacitor.
40
nWAKEUP
O
Signal to SOC to indicate a power on event (active low, open-drain output).
41
FB2
I
Feedback voltage pin for DCDC2. Connect to output capacitor.
42
L2
P
Switch pin for DCDC2. Connect to inductor.
43
IN_DCDC2
P
Input supply pin for DCDC2.
44
PB
I
Push-button monitor input. Typically connected to a momentary switch to ground (active low). See
Section 5.4.1 for details.
45
nINT
O
Interrupt output (active low, open drain). Pin is pulled low if an interrupt bit is set. The pin returns to Hi-Z state
after the bit causing the interrupt has been read. Interrupts can be masked.
46
PWR_EN
I
Power enable input for DCDC1-4, LDO1 and load switches. See Section 5.4.1 for details.
47
FB1
I
Feedback voltage pin for DCDC1. Connect to output capacitor.
48
L1
P
Switch pin for DCDC1. Connect to inductor.
6
Pin Configuration and Functions
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Pin Functions (continued)
PIN
NO.
—
NAME
Thermal Pad
TYPE
P
DESCRIPTION
Power ground and thermal relief. Connect to ground plane.
Pin Configuration and Functions
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4 Specifications
4.1
Absolute Maximum Ratings
Operating under free-air temperature range (unless otherwise noted) (1)
MIN
MAX
IN_BIAS, IN_LDO1, IN_LS2, IN_DCDC1, IN_DCDC2,
IN_DCDC3, IN_DCDC4
–0.3
7
IN_LS1, CC
–0.3
3.6
IN_LS3
–0.3
11.2
IN_BU
–0.3
5.8
Output voltage
All pins unless specified separately
–0.3
7
Source or sink
current
GPO2
6
PGOOD_BU, IN_nCC
1
Sink current
PGOOD, nWAKEUP, nINT, nPFO, SDA, GPIO1, GPIO3
Supply voltage
UNIT
V
V
mA
6
mA
TA
Operating ambient temperature
–40
105
°C
TJ
Junction temperature
–40
125
°C
Storage temperature
–65
150
°C
Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
8
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Specifications
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4.3
SLDS261 – NOVEMBER 2019
Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage, IN_BIAS
2.7
5.5
V
Input voltage for DCDC1, DCDC2, DCDC3, and DCDC4
2.7
5.5
V
Supply voltage, IN_BU
2.2
5.5
V
Supply voltage, CC
2.2
3.3
V
Input voltage for LDO1
1.8
5.5
V
Input voltage for LS1
1.2
3.6
V
Input voltage for LS2
3
5.5
V
Input voltage for LS3
1.8
10
V
Output voltage for DCDC1
0.85
1.675
V
Output voltage for DCDC2
0.85
1.675
V
Output voltage for DCDC3
0.9
3.4
V
Output voltage for DCDC4
1.175
3.4
V
Output voltage for DCDC5
1
V
Output voltage for DCDC6
1.8
V
Output voltage for LDO1
Output current for DCDC1, DCDC2, and DCDC3
Output current for DCDC4
0.9
3.4
V
0
1.8
A
VIN_DCDC4 = 2.8 V
1
VIN_DCDC4 = 3.6 V
1.3
VIN_DCDC4 = 5 V
1.6
A
Output current for DCDC5 and DCDC6
0
25
mA
Output current for LDO1
0
400
mA
Output current for LS1
0
300
mA
Output current for LS2
0
920
mA
VIN_LS3 > 2.3 V
0
900
VIN_LS3 ≤ 2.3 V
0
475
Output current for LS3
4.4
mA
Thermal Information
TPS65218x5
THERMAL METRIC
(1)
RSL (VQFN)
UNIT
48 PINS
RθJC(top)
Junction-to-case (top)
17.2
°C/W
RθJB
Junction-to-board
5.8
°C/W
RθJA
Thermal resistance, junction to ambient. JEDEC 4-layer, high-K board.
30.6
°C/W
ΨJT
Junction-to-package top
0.2
°C/W
ΨJB
Junction-to-board
5.6
°C/W
Junction-to-case (bottom)
1.5
°C/W
RθJC(bot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Specifications
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Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE AND CURRENTS
VIN_BIAS
Input supply voltage range
Normal operation
2.7
5.5
EEPROM programming
4.5
5.5
Deglitch time
IOFF
OFF state current, total current
into IN_BIAS, IN_DCDCx,
IN_LDO1, IN_LS
VIN = 3.6 V; All rails disabled.
TJ = 0°C to 85°C
ISUSPEND
SUSPEND current, total current
into IN_BIAS, IN_DCDCx,
IN_LDO1, IN_LS
VIN = 3.6 V; DCDC3 enabled, low-power mode, no
load.
All other rails disabled.
TJ = 0°C to 105°C
VSYS_BU
SYS_BU voltage range
Powered from VIN_BU or VCC
CSYS_BU
Recommended SYS_BU
capacitor
Ceramic, X5R or X7R, see Table 6-3.
Tolerance
Ceramic, X5R or X7R, rated voltage ≥ 6.3 V
V
5
ms
5
µA
220
µA
SYS_BU
2.2
5.5
1
–20%
V
µF
20%
INT_LDO
VINT_LDO
Output voltage
2.5
DC accuracy
IOUT < 10 mA
IOUT
Output current range
Maximum allowable external load
ILIMIT
Short circuit current limit
Output shorted to GND
Hold-up time
Measured from VINT_LDO = to VINT_LDO = 1.8 V
All rails enabled before power off,
IN_BIAS tied to IN_DCDC1-4, IN_LDO1
VIN_BIAS = 2.8 V to 0 V in < 5 µs
No external load on INT_LDO
CINT_LDO = 1 µF, see Table 6-3.
Nominal output capacitor value
Ceramic, X5R or X7R, see Table 6-3.
Tolerance
Ceramic, X5R or X7R, rated voltage ≥ 6.3 V
tHOLD
COUT
–2%
V
2%
0
10
23
mA
150
0.1
mA
ms
1
22
–20%
20%
µF
DCDC1 (1.1-V BUCK)
VIN_DCDC1
VDCDC1
IOUT
IQ
RDS(ON)
ILIMIT
Input voltage range
VIN_BIAS > VUVLO
5.5
V
Output voltage range
Adjustable through I2C
0.85
1.675
V
DC accuracy
2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A
–2%
2%
Continuous output current
VIN_DCDC1 > 2.7 V
Quiescent current
Total current from IN_DCDC1 pin; Device not
switching, no load
High-side FET on resistance
Low-side FET on resistance
1.8
A
25
50
µA
VIN_DCDC1 = 3.6 V
230
355
VIN_DCDC1 = 3.6 V
90
145
High-side current limit
VIN_DCDC1 = 3.6 V
2.8
Low-side current limit
VIN_DCDC1 = 3.6 V
3.1
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
VPG
VOUT falling
Deglitch
VOUT rising
88.5%
90%
91.5%
STRICT = 1b
96%
96.5%
97%
STRICT = 0b
3.8%
4.1%
4.4%
0.25%
STRICT = 0b
1
ms
STRICT = 1b
50
µs
STRICT = 0b
10
µs
STRICT = 1b
10
µs
5
ms
Time-out
10
A
STRICT = 0b
STRICT = 1b
mΩ
Specifications
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
VOV
TEST CONDITIONS
Hysteresis
VOUT falling, STRICT = 1b
0.25%
50
Deglitch
VOUT rising, STRICT = 1b
Inrush current
VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF
RDIS
Discharge resistor
Nominal inductor value
See Table 6-2.
Tolerance
COUT
TYP
103.5%
VOUT rising, STRICT = 1b
IINRUSH
L
MIN
103%
Overvoltage detection threshold
Output capacitance value
150
250
1
1.5
–30%
Ceramic, X5R or X7R, see Table 6-3.
10
MAX UNIT
104%
µs
500
mA
350
Ω
2.2
µH
30%
22
100 (1)
µF
DCDC2 (1.1-V BUCK)
VIN_DCDC2
VDCDC2
IOUT
IQ
RDS(ON)
ILIMIT
Input voltage range
VIN_BIAS > VUVLO
2.7
5.5
V
Output voltage range
Adjustable through I2C
0.85
1.675
V
DC accuracy
2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A
–2%
2%
Continuous output current
VIN_DCDC2 > 2.7 V
Quiescent current
Total current from IN_DCDC2 pin; device not
switching, no load
High-side FET on resistance
Low-side FET on resistance
1.8
A
25
50
µA
VIN_DCDC2 = 3.6 V
230
355
VIN_DCDC2 = 3.6 V
90
145
High-side current limit
VIN_DCDC2 = 3.6 V
2.8
Low-side current limit
VIN_DCDC2 = 3.6 V
3.1
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
A
STRICT = 0b
88.5%
90%
STRICT = 1b
96%
96.5%
97%
STRICT = 0b
3.8%
4.1%
4.4%
STRICT = 1b
mΩ
91.5%
0.25%
STRICT = 0b
1
ms
STRICT = 1b
50
µs
STRICT = 0b
10
µs
STRICT = 1b
10
µs
Time-out
Occurs at enable of DCDC2 and after DCDC2
register write (register 0x17).
5
ms
Overvoltage detection threshold
VOUT rising, STRICT = 1b
Hysteresis
VOUT falling, STRICT = 1b
0.25%
Deglitch
VOUT rising, STRICT = 1b
50
IINRUSH
Inrush current
VIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF
RDIS
Discharge resistor
VPG
VOUT falling
Deglitch
VOUT rising
VOV
Nominal inductor value
L
See Table 6-2.
Tolerance
COUT
Output capacitance value
103%
103.5%
104%
µs
500
mA
150
250
350
Ω
1
1.5
2.2
µH
–30%
30%
100 (1)
µF
2.7
5.5
V
0.9
3.4
V
–2%
2%
Ceramic, X5R or X7R, see Table 6-3.
10
VIN_BIAS > VUVLO
22
DCDC3 (1.2-V BUCK)
VIN_DCDC3
VDCDC3
IOUT
IQ
RDS(ON)
(1)
Input voltage range
2
Output voltage range
Adjustable through I C
DC accuracy
2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A,
VIN_DCDC3 ≥ (VDCDC3 + 700 mV)
Continuous output current
VIN_DCDC3 > 2.7 V
Quiescent current
Total current from IN_DCDC3 pin;
Device not switching, no load
High-side FET on resistance
Low-side FET on resistance
1.8
A
25
50
µA
VIN_DCDC3 = 3.6 V
230
345
VIN_DCDC3 = 3.6 V
100
150
mΩ
500-µF of remote capacitance can be supported for DCDC1 and DCDC2.
Specifications
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
ILIMIT
TEST CONDITIONS
MIN
TYP
High-side current limit
VIN_DCDC3 = 3.6 V
2.8
Low-side current limit
VIN_DCDC3 = 3.6 V
3
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
MAX UNIT
A
STRICT = 0b
88.5%
90%
STRICT = 1b
95%
95.5%
96%
STRICT = 0b
3.8%
4.1%
4.4%
STRICT = 1b
91.5%
0.25%
STRICT = 0b
1
ms
STRICT = 1b
50
µs
STRICT = 0b
10
µs
STRICT = 1b
10
µs
Time-out
Occurs at enable of DCDC3 and after DCDC3
register write (register 0x18).
5
ms
Overvoltage detection threshold
VOUT rising, STRICT = 1b
Hysteresis
VOUT falling, STRICT = 1b
0.25%
Deglitch
VOUT rising, STRICT = 1b
50
IINRUSH
Inrush current
VIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF
RDIS
Discharge resistor
VPG
VOUT falling
Deglitch
VOUT rising
VOV
Nominal inductor value
L
104%
Output capacitance value
105%
µs
500
See Table 6-2.
Tolerance
COUT
104.5%
250
350
Ω
1.0
1.5
2.2
µH
–30%
Ceramic, X5R or X7R, see Table 6-3.
mA
150
10
30%
22
100
µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
Output voltage ripple
PFM mode enabled;
4.2 V ≤ VIN ≤ 5.5 V;
0 A ≤ IOUT ≤ 1.6 A
VOUT = 3.3 V
150 mVpp
Minimum duty cycle in stepdown mode
IOUT
Continuous output current
IQ
Quiescent current
fSW
Switching frequency
High-side FET on resistance
18%
VIN_DCDC4 = 2.8 V, VOUT = 3.3 V
1
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V
1.3
VIN_DCDC4 = 5 V, VOUT = 3.3 V
1.6
Total current from IN_DCDC4 pin; Device not
switching, no load
VIN_DCDC3 = 3.6 V
Low-side FET on resistance
VIN_DCDC3 = 3.6 V
Average switch current limit
VIN_DCDC4 = 3.6 V
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
VPG
166
L4B to DCDC4
149
L4A to GND
142
190
144
190
3000
mΩ
mA
STRICT = 0b
88.5%
90%
91.5%
STRICT = 1b
95%
95.5%
96%
STRICT = 0b
3.8%
4.1%
4.4%
0.25%
STRICT = 0b
1
ms
STRICT = 1b
50
µs
STRICT = 0b
10
µs
STRICT = 1b
10
µs
Occurs at enable of DCDC4 and after DCDC4
register write (register 0x19)
5
ms
Deglitch
VOUT rising
12
kHz
IN_DCDC4 to L4A
L4B to GND
µA
STRICT = 1b
VOUT falling
Time-out
50
2400
RDS(ON)
ILIMIT
25
A
Specifications
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SLDS261 – NOVEMBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
104%
104.5%
Overvoltage detection threshold
VOUT rising, STRICT = 1b
Hysteresis
VOUT falling, STRICT = 1b
0.25%
Deglitch
VOUT rising, STRICT = 1b
50
IINRUSH
Inrush current
VIN_DCDC4 = 3.3 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT
≤ 100 µF
RDIS
Discharge resistor
VOV
Nominal inductor value
L
See Table 6-2.
Tolerance
COUT
Output capacitance value
MAX UNIT
105%
µs
500
mA
150
250
350
Ω
1.2
1.5
2.2
µH
–30%
Ceramic, X5R or X7R, see Table 6-3.
40
VIN_BU = 0 V
30%
80
100
µF
2.2
3.3
V
2.2
5.5
V
DCDC5 and DCDC6 POWER PATH
VCC
DCDC5 and DCDC6 input
voltage range.
VIN_BU
DCDC5 and DCDC6 input
voltage range (2)
tRISE
VCC, VIN_BU rise time
VCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V
Power path switch impedance
CC to SYS_BU
VCC = 2.4 V, VIN_BU = 0 V
14.5
Power path switch impedance
IN_BU to SYS_BU
VIN_BU = 3.6 V
10.5
Forward leakage current
Into CC pin;
VCC = 3.3 V, VIN_BU = 0 V;
OFF state; FSEAL = 0b;
over full temperature range
Reverse leakage current
Out of CC pin;
VCC = 1.5 V; VIN_BU = 5.5 V;
over full temperature range
RCC
Acceptable CC source
impedance
IOUT,
IOUT,
IQ
Quiescent current
Average current into CC pin; RECOVERY or OFF
state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and
DCDC6 enabled, no load TJ = 25°C
350
nA
QINRUSH
Inrush charge
VIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF;
SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 Ω CCC =
4.7 µF
720
nC
RDS(ON)
ILEAK
DCDC5
DCDC6
30
µs
Ω
50
300
nA
500
< 10 µA;
< 10 µA
1000
Ω
DCDC5 (1-V BATTERY BACKUP SUPPLY)
Output voltage
VDCDC5
DC accuracy
1
–2.5%
2.5%
2.7 V ≤ VIN_BU ≤ 5.5 V
1.5 µA ≤ IOUT ≤ 25 mA
0°C ≤ TA < 105°C
–2%
2%
–2.5%
2.5%
2.2 V ≤ VCC ≤ 3.3 V; VIN_BU = 0;
1.5 µA ≤ IOUT ≤ 100 µA
Output voltage ripple
IOUT
Continuous output current
L = 10 µH; COUT = 22 µF; 100-µA load, occurs
during band-gap sampling
2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V
32 (3) mVpp
10
2.7 V ≤ VIN_BU ≤ 5.5 V
RDS(ON)
ILIMIT
(2)
(3)
V
2.7 V ≤ VIN_BU ≤ 5.5 V;
1.5 µA ≤ IOUT ≤ 25 mA
–40°C ≤ TA < 0°C
100
µA
25
mA
High-side FET on resistance
VIN_BU = 2.8 V
2.5
3.5
Low-side FET on resistance
VIN_BU = 2.8 V
2
3
High-side current limit
VIN_BU = 2.8 V
50
Ω
mA
IN_BU has priority over CC input.
For PHP package: 160 mVpp at -40°C, and 120 mVpp from 25°C to 105°C.
Specifications
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
VPG
L
TEST CONDITIONS
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
Nominal inductor value
Chip inductor, see Table 6-2.
Tolerance
Output capacitance value
COUT
Ceramic, X5R or X7R, see Table 6-3.
Tolerance
MIN
TYP
MAX UNIT
79%
85%
91%
6%
4.7
10
22
–30%
30%
20 (4)
47
–20%
20%
µH
µF
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
VDCDC6
Output voltage
VDCDC6
Output voltage ripple
L = 10 µH; COUT = 22 µF; 100-µA load
1.8
IOUT
Continuous output current
2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V
10
2.7 V ≤ VIN_BU ≤ 5.5 V
RDS(ON)
ILIMIT
VPG
L
(4)
14
100
µA
25
mA
High-side FET on resistance
VIN_BU = 3 V
2.5
3.5
Low-side FET on resistance
VIN_BU = 3 V
2
3
High-side current limit
VIN_BU = 3 V
50
Power-good threshold
VOUT falling
Hysteresis
VOUT rising
Nominal inductor value
Chip inductor, see Table 6-2
Tolerance
COUT
V
30 (3) mVpp
Output capacitance value
87%
Tolerance
mA
95%
3%
4.7
–30%
Ceramic, X5R or X7R, see Table 6-3
91%
Ω
10
22
µH
30%
20 (4)
47
–20%
20%
µF
For PHP package: 40 µF.
Specifications
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SLDS261 – NOVEMBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LDO1 (1.8-V LDO)
VIN_LDO1
Input voltage range
VIN_BIAS > VUVLO
IQ
Quiescent current
No load
Output voltage range
Adjustable through I2C
DC accuracy
VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA
VOUT
35
–2%
2%
VIN_LDO1 – VDO = VOUT
0
200
VIN_LDO1 > 2.7 V, VOUT = 1.8 V
0
400
ILIMIT
Short circuit current limit
Output shorted to GND
VDO
Dropout voltage
IOUT = 100 mA, VIN = 3.6 V
VOUT falling
Power-good threshold
Hysteresis, VOUT rising
VOUT falling
Deglitch
VOUT rising
445
550
STRICT = 0b
86%
90%
94%
STRICT = 1b
95%
95.5%
96%
STRICT = 0b
3%
4%
5%
1
ms
STRICT = 1b
50
µs
STRICT = 0b
10
µs
STRICT = 1b
10
µs
5
ms
Overvoltage detection threshold
VOUT rising, STRICT = 1b
Hysteresis
VOUT falling, STRICT = 1b
0.25%
VOUT rising, STRICT = 1b
50
Discharge resistor
COUT
Output capacitance value
mV
0.25%
Time-out
RDIS
mA
STRICT = 0b
Occurs at enable of LDO and after LDO register
write (register 0x1B)
Deglitch
V
mA
200
STRICT = 1b
V
µA
3.4
Output current range
VOV
5.5
0.9
IOUT
VPG
1.8
104%
VOUT falling, STRICT = 1b
104.5%
105%
µs
1
150
Ceramic, X5R or X7R
ms
250
380
Ω
22
100
µF
3.6
V
LOAD SWITCH 1 (LS1)
VIN_LS1
RDS(ON)
Input voltage range
VIN_BIAS > VUVLO
Static on resistance
110
VIN_LS1 = 1.8 V, IOUT = 300 mA,
DDR2, LPDDR, MDDR at 266 MHz over full
temperature range
110
VIN_LS1 = 1.5 V, IOUT = 300 mA,
DDR3 at 333 MHz over full temperature range
110
VIN_LS1 = 1.35 V, IOUT = 300 mA,
DDR3L at 333 MHz over full temperature range
110
VIN_LS1 = 1.2 V, IOUT = 200 mA,
LPDDR2 at 333 MHz over full temperature range
150
ILIMIT
Short circuit current limit
Output shorted to GND
tBLANK
Interrupt blanking time
Output shorted to GND until interrupt is triggered.
RDIS
Internal discharge resistor at
output (5)
TOTS
COUT
(5)
(6)
Overtemperature shutdown
1.2
VIN_LS1 = 3.3 V, IOUT = 300 mA, over full
temperature range
LS1DCHRG = 1
(6)
350
Nominal output capacitance
value
mA
15
ms
150
250
380
125
132
139
Hysteresis
10
Ceramic, X5R or X7R, see Table 6-3.
10
mΩ
100
Ω
°C
µF
Discharge function disabled by default.
Switch is temporarily turned OFF if temperature exceeds OTS threshold.
Specifications
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOAD SWITCH 2 (LS2)
VIN_LS2
Input voltage range
VUVLO
RDS(ON)
VIN_BIAS > VUVLO
3
(7)
Undervoltage lockout
Measured at IN_LS2. Supply falling
Hysteresis
Input voltage rising
2.48
Static on resistance
VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature
range
5.5
2.6
LS2ILIM[1:0] = 00b
94
126
LS2ILIM[1:0] = 01b
188
251
LS2ILIM[1:0] = 10b
465
631
LS2ILIM[1:0] = 11b
922
Short circuit current limit
Output shorted to GND;
VIN_LS2 ≥ 4 V
ILEAK
Reverse leakage current
VLS2 > VIN_LS2 + 1 V
12
tBLANK
Interrupt blanking time
Output shorted to GND until interrupt is triggered
15
RDIS
Internal discharge resistor at
output (5)
Overtemperature shutdown
LS2DCHRG = 1b
(7)
30
Ceramic, X5R or X7R, see Table 6-3.
mA
µA
ms
250
380
125
132
139
10
Nominal output capacitance
value
COUT
mΩ
1290
150
Hysteresis
V
mV
500
ILIMIT
TOTS
2.7
170
V
Ω
°C
1
100
µF
1.8
10
V
LOAD SWITCH 3 (LS3)
VIN_LS3
Input voltage range
RDS(ON)
VIN_BIAS > VUVLO
Static on resistance
VIN_LS3 = 9 V, IOUT= 500 mA, over full temperature
range
440
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature
range
526
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature
range
656
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature
range
910
VIN_LS3 > 2.3 V,
Output shorted to GND
ILIMIT
Short circuit current limit
VIN_LS3 ≤ 2.3 V,
Output shorted to GND
tBLANK
Interrupt blanking time
RDIS
Internal discharge resistor at
output (5)
TOTS
COUT
Overtemperature shutdown
mΩ
LS3ILIM[1:0] = 00b
98
126
LS3ILIM[1:0] = 01b
194
253
LS3ILIM[1:0] = 10b
475
738
LS3ILIM[1:0] = 11b
900
1234
LS3ILIM[1:0] = 00b
98
126
LS3ILIM[1:0] = 01b
194
253
LS3ILIM[1:0] = 10b
475
Output shorted to GND until interrupt is triggered.
LS3DCHRG = 1
(7)
738
15
ms
650
1000
1500
Ω
125
132
139
°C
Hysteresis
Nominal output capacitance
value
10
Ceramic, X5R or X7R, see Table 6-3.
mA
1
100
°C
220
µF
BACKUP BATTERY MONITOR
Comparator threshold
VTH
Ideal level
3
V
Good level
2.6
V
Low level
2.3
Accuracy
RLOAD
(7)
16
Load impedance
–3%
Applied from CC to GND during comparison.
70
V
3%
100
130
kΩ
Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
Specifications
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SLDS261 – NOVEMBER 2019
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
tDLY
Measurement delay
TEST CONDITIONS
MIN
RLOAD is connected during delay time. Measurement
is taken at the end of delay.
TYP
MAX UNIT
600
ms
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLY
PGOOD delay time
PGDLY[1:0] = 00b
10
PGDLY[1:0] = 01b
20
PGDLY[1:0] = 10b
50
PGDLY[1:0] = 11b
PB input
AC_DET input
tDG
Deglitch time
PWR_EN input
GPIO1
GPIO3
tRESET
Reset time
PB input held low
150
Rising edge
100
ms
Falling edge
50
ms
Rising edge
100
µs
Falling edge
10
ms
Rising edge
10
ms
Falling edge
100
µs
Rising edge
1
ms
Falling edge
1
ms
Rising edge
5
µs
Falling edge
5
µs
TRST = 0b
8
TRST = 1b
15
SCL, SDA, GPIO1, and GPIO3
VIH
High level input voltage
AC_DET, PB
PWR_EN
VIL
VOH
VOL
VPFI
Low level input voltage
VDC34_SEL
1.3
V
1.3
0
0.4
GPO2; ISOURCE = 5 mA; GPO2_BUF = 1
VIN_LS1 –
0.3
VIN_LS1
PGOOD_BU; ISOURCE = 100 µA
VDCDC6 –
10 mV
nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2,
and GPIO3; ISINK = 2 mA
0
0.3
nPFO; ISINK = 2 mA
0
0.35
PGOOD_BU; ISINK = 100 µA
0
0.3
Input falling
800
Input rising
40
Accuracy
DCDC3 and DCDC4 power-up
default selection thresholds
V
V
Hysteresis
DC34_SEL bias current
s
0.66 ×
IN_BIAS
Power-fail comparator threshold
Deglitch
IDC34_SEL
SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and
GPIO3
High level output voltage
Low level output voltage
ms
–4%
V
mV
mV
4%
Input falling
25
µs
Input rising
10
ms
Enabled only at power-up.
9.05
10
Threshold 1
100
Threshold 2
163
Threshold 3
275
Threshold 4
400
Threshold 5
575
Threshold 6
825
Threshold 7
1200
11.93
Specifications
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mV
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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
RDC34_SEL
IBIAS
ILEAK
DCDC3 and DCDC4 power-up
default selection resistor values
Input bias current
Pin leakage current
MIN
TYP
Setting 0
TEST CONDITIONS
0
0
7.7
Setting 1
11.8
12.1
12.4
Setting 2
19.5
20
20.5
Setting 3
30.9
31.6
32.3
Setting 4
44.4
45.3
46.3
Setting 5
64.8
66.1
67.3
Setting 6
93.6
95.3
97.2
Setting 7
146
150
SCL, SDA, GPIO1 (8), GPIO3 (8); VIN = 3.3 V
MAX UNIT
0.01
kΩ
1
µA
PB, AC_DET, PFI; VIN = 3.3 V
500
nA
nINT, nWAKEUP, nPFO, PGOOD, PWR_EN,
GPIO1 (9), GPO2 (10), GPIO3 (9)
VOUT = 3.3 V
500
nA
OSCILLATOR
ƒOSC
Oscillator frequency
Frequency accuracy
2400
TJ = –40°C to +105°C
–12%
kHz
12%
OVERTEMPERATURE SHUTDOWN
TOTS
TWARN
Overtemperature shutdown
Increasing junction temperature
Hysteresis
Decreasing junction temperature
High-temperature warning
Increasing junction temperature
Hysteresis
Decreasing junction temperature
135
145
155
20
90
100
110
15
°C
°C
(8) Configured as input.
(9) Configured as output.
(10) Configured as open-drain output.
4.6
Timing Requirements
MIN
Serial clock frequency
tHD;STA
Hold time (repeated) START condition. After this period, the
first clock pulse is generated.
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
tSU;DAT
Data set-up time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU;STO
Set-up time for STOP condition
(1)
18
UNIT
kHz
400
tLOW
Data hold time
MAX
100
fSCL
tHD;DAT
NOM
SCL = 100 kHz
4
µs
SCL = 400 kHz
600
ns
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
4
SCL = 400 kHz (1)
1
µs
µs
SCL = 100 kHz
4.7
µs
SCL = 400 kHz
600
SCL = 100 kHz
0
3.45
µs
SCL = 400 kHz
0
900
ns
SCL = 100 kHz
250
SCL = 400 kHz
100
ns
ns
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
ns
ns
SCL = 100 kHz
4
µs
SCL = 400 kHz
600
ns
The SCL duty cycle at 400 kHz must be > 40%.
Specifications
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Timing Requirements (continued)
MIN
SCL = 100 kHz
4.7
NOM
MAX
tBUF
Bus free time between STOP and START condition
SCL = 400 kHz
1.3
tSP
Pulse width of spikes which must be suppressed by the input SCL = 100 kHz
filter
SCL = 400 kHz
— (2)
— (2)
0
50
Cb
Capacitive load for each bus line
(2)
UNIT
µs
SCL = 100 kHz
400
SCL = 400 kHz
400
ns
pF
The inputs of I2C devices in Standard-mode do not require spike suppression.
Specifications
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Typical Characteristics
0.3%
0.25%
0.2%
0.15%
0.1%
0.05%
0
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
VIN = 3.6 V
VIN = 5 V
Accuracy
Accuracy
at TJ = 25°C unless otherwise noted
0
0.2
0.4
0.6
0.8
1
1.2
Output Current (A)
1.4
1.6
0.15%
0.1%
0.05%
0
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
-0.45%
-0.5%
-0.55%
VIN = 3.6 V
VIN = 5 V
0
1.8
0.2
0.4
0.6
0.8
1
1.2
Output Current (A)
D001
VOUT = 1.1 V
D002
0.75%
VIN = 3.6 V
VIN = 5 V
0.05%
VIN = 3.6 V
VIN = 5 V
0.5%
0.25%
Accuracy
0
Accuracy
1.8
Figure 4-2. DCDC2 Accuracy
0.1%
-0.05%
-0.1%
-0.15%
0
-0.25%
-0.5%
-0.75%
-0.2%
-1%
-0.25%
-1.25%
0
0.2
0.4
0.6
0.8
1
1.2
Output Current (A)
1.4
1.6
1.8
0
0.2
0.4
D003
VOUT = 1.2 V
VIN = 3.6 V
VIN = 5 V
1%
0.8%
Accuracy
0.6%
0.4%
0.2%
0
-0.2%
-0.4%
-0.6%
-0.8%
0
0.005
0.01
0.015
Output Current (A)
1.2
1.4
1.6
D004
Figure 4-4. DCDC4 Accuracy
1.4%
1.2%
0.6
0.8
1
Output Current (A)
VOUT = 3.3 V
Figure 4-3. DCDC3 Accuracy
Accuracy
1.6
VOUT = 1.1 V
Figure 4-1. DCDC1 Accuracy
0.02
0.025
0.05%
0
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
-0.45%
-0.5%
-0.55%
-0.6%
VIN = 3.6 V
VIN = 5 V
0
D005
VOUT = 1 V
0.005
0.01
0.015
Output Current (A)
0.02
0.025
D006
VOUT = 1.8 V
Figure 4-5. DCDC5 Accuracy
20
1.4
Figure 4-6. DCDC6 Accuracy
Specifications
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5 Detailed Description
5.1
Overview
The TPS6521815 provides three step-down converters, three load switches, three general-purpose I/Os,
two battery backup supplies, one buck-boost converter, and one LDO. The system can be supplied by a
regulated 5-V supply. A coin-cell battery can be added to supply the two always-on backup supplies. The
device is characterized across a –40°C to +105°C temperature range, which makes it suitable for various
industrial applications.
The I2C interface provides comprehensive features for using TPS6521815. All rails, load switches, and
GPIOs can be enabled and disabled. Voltage thresholds for the UVLO and supervisor can be customized.
Power-up and power-down sequences can also be programmed through I2C. Interrupts for
overtemperature, overcurrent, and undervoltage can be monitored for the load-switches (LSx).
The integrated voltage supervisor monitors DCDC 1-4 and LDO1. It has two settings; the standard
settings only monitor for undervoltage, while the strict settings implement tight tolerances on both
undervoltage and overvoltage. A power-good signal is provided to report the regulation state of the five
rails.
The three hysteretic step-down converters can each supply up to 1.8 A of current. The default output
voltages for each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 feature
dynamic voltage scaling with adjustable slew rate. The step-down converters operate in a low power mode
at light load, and can be forced into PWM operation for noise sensitive applications.
The battery backup supplies consist of two low power step-down converters optimized for very light loads
and are monitored with a separate power-good signal (PGOOD_BU). The converters can be configured to
operate as always-on supplies with the addition of a coin cell battery. The state of the battery can be
monitored over I2C.
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Functional Block Diagram
To SOC
VDD_10 (1 V)
Battery-backup
22 …F domain supply
L5 10 µH
DCDC6 (1.8 V)
PGOOD_BU
DCDC5_PG
DCDC6_PG
FB5
DCDC5
DCDC6 (1.8 V)
IN_nCC
To SOC
FB6
DCDC6
IN_BU
2.7-V to 5.5-V
system power
10
Coin
cell
CC
SYS_BU
+
1 …F
4.7 …F 4.7 …F
±
From 1.8-V to 5.5-V
supply
IN_LDO1
0.9-V to 3.3-V analog supply
(adjustable, default 1.8 V)
LDO1
Always-on coin-cell battery backup supplies
IN_LS2
100-mA / 500-mA
load switch
10 …F
IN_LS1
From 1.2-V to 3.3-V
supply
LS1
200-mA load switch
LS3
LS1
IN_LS3
From 1.8-V to 10-V
supply
LS3
500-mA load
switch
10 …F
10 …F
IN_DCDC3
From 2.7-V to 5.5-V
system power
IN_DCDC1
4.7 …F
From 2.7-V to 5.5-V
system power
4.7 …F
L1 10 µH
L3
1.5-V DDR3 supply
(adjustable)
FB3
10 …F
DCDC3
DCDC1
IN_DCDC4
From 2.7-V to 5.5-V
system power
4.7 …F
FB1
1.1-V core supply
(adjustable)
10 …F
IN_DCDC2
From 2.7-V to 5.5-V
system power
4.7 …F
L4A
L2 10 µH
L4B
DCDC4
DCDC2
FB2
1.1-V MPU supply
(adjustable)
10 …F
DCDC4
3.3-V I/O supply
(adjustable)
IN_BIAS
47 …F
VSELECT
Input Power
VIO
VREF
10
SDA
From SOC
PWR_EN
From SOC
1 …F
Supervisor
and up,
down
sequencer
VIO VDD_18
(1.8 V / (DCDC6)
3.3 V)
+
±
OD
I2C
OD
GPIO1
AC_DET
IN_BIAS
100 k
VIO
(1.8 V /
3.3 V)
VIO
(1.8 V /
3.3 V)
To SOC
To SOC
To SOC
To SOC
DIGITAL
IN_LS1
Momentary push-button
nWAKEUP
nINT
100 k
IN_BIAS
100 k
nPFO
PGOOD
OD
SCL
10
INT_LDO
BIAS
VDCDC1
VDCDC2
VDCDC3
VDCDC4
LDO1
OD
PFI
VIO
From 2.7-V to 5.5-V
system power
100 nF
DC34_SEL
From external
charger
From 3-V to 5.5-V
supply
LS2
LS2
LDO1
10 …F
From SOC
VDD_18 (1.8 V)
Battery-backup
domain supply
22 …F
L6 10 µH
OD
GPIO2
OD
GPIO3
PB
From SOC
To DDR3 memory
From SOC
OD
Thermal
Pad
22
Detailed Description
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5.3
SLDS261 – NOVEMBER 2019
Feature Description
5.3.1
Wake-Up and Power-Up and Power-Down Sequencing
The TPS6521815 has a predefined power-up and power-down sequence, which does not change in a
typical application. The user can define custom sequences with I2C. The power-up sequence is defined by
a series of ten strobes and nine delay times. Each output rail is assigned to a strobe to determine the
order of enabling rails. A single rail is assigned to only one strobe, but multiple rails can be assigned to
the same strobe. The delay times between strobes are between 2 ms and 5 ms.
5.3.1.1
Power-Up Sequencing
When the power-up sequence initiates, STROBE 1 occurs, and any rail assigned to this strobe is enabled.
After a delay time of DLY1, STROBE 2 occurs and the rail assigned to this strobe is powered up. The
sequence continues until all strobes occur and all DLYx times execute. Strobe assignments and delay
times are defined in the SEQx registers, and are changed under I2C control. The power-up sequence
executes if one of the following events occurs:
• From the OFF state:
– The push-button (PB) is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN is asserted (driven to high-level) or
– The main power is connected (IN_BIAS) and AC_DET is grounded and
– The device is not in undervoltage lockout (UVLO) or overtemperature shutdown (OTS).
• From the PRE_OFF state:
– The PB is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN is asserted (driven to high-level) and
– The device is not in UVLO or OTS.
• From the SUSPEND state:
– The PB is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN pin is pulled high (level sensitive) and
– The device is not in UVLO or OTS.
When a power-up event is detected, the device enters a WAIT_PWR_EN state and triggers the power-up
sequence. The device remains in WAIT_PWR_EN as long as the PWR_EN and either the PB or AC_DET
pin are held low. If both, the PB and AC_DET return to logic-high state and the PWR_EN pin has not been
asserted within 20 s of entering WAIT_PWR_EN state, the power-down sequence is triggered and the
device returns to OFF state. Once PWR_EN is asserted, the device advances to ACTIVE state, which is
functionally equivalent to WAIT_PWR_EN. However, the AC_DET pin is ignored and power-down is
controlled by the PWR_EN pin only.
Rails not assigned to a strobe (SEQ = 0000b) are not affected by power-up and power-down sequencing
and remain in their current ON or OFF state regardless of the sequencer. A rail can be enabled and
disabled at any time by setting the corresponding enable bit in the ENABLEx register, with the exception
that the ENABLEx register cannot be accessed while the sequencer is active. Enable bits always reflect
the current enable state of the rail. For example, the sequencer sets and resets the enable bits for the rails
under its control.
NOTE
The power-up sequence is defined by strobes and delay times, and can be triggered by the
PB, AC_DET (not shown, same as PB), or PWR_EN pin.
Detailed Description
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PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
STROBE 8
STROBE 9 STROBE 10
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
Push-button deglitch time is not shown.
Figure 5-1. Power-Up Sequences from OFF or SUSPEND State;
PB is Power-Up Event
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
STROBE 8
STROBE 9 STROBE 10
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
Figure 5-2. Power-Up Sequences from SUSPEND State;
PWR_EN is Power-Up Event
FAULT Recovery
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
STROBE 8
STROBE 9 STROBE 10
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
Figure 5-3. Power-Up Sequences from RECOVERY State
24
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5.3.1.2
SLDS261 – NOVEMBER 2019
Power-Down Sequencing
By default, the power-down sequence follows the reverse of the power-up sequence. When the powerdown sequence is triggered, STROBE 10 occurs and any rail assigned to STROBE 10 is shut down and
its discharge circuit is enabled. After a delay time of DLY9, STROBE 9 occurs and any rail assigned to it is
shut down and its discharge circuit is enabled. The sequence continues until all strobes occur and all
DLYx times execute. The DLYx times are extended by a factor of 10x to provide ample time for discharge,
and preventing output voltages from crossing during shut-down. The DLYFCTR bit is applied globally to all
power-down delay times. Regardless of the DLYx and DLYFCTR settings, the PMIC enters OFF,
SUSPEND, or RECOVERY state 500 ms after the power-down sequence initiates, to ensure that the
discharge circuits remain enabled for a minimum of 150 ms before the next power-up sequence starts.
A power-down sequence executes if one of the following events occurs:
• The device is in the WAIT_PWR_EN state, the PB and AC_DET pins are high, PWR_EN is low, and
the 20-s timer has expired.
• The device is in the ACTIVE state and the PWR_EN pin is pulled low.
• The device is in the WAIT_PWR_EN, ACTIVE, or SUSPEND state and the push-button is held low for
> 8 s (15 s if TRST = 1b).
• A fault occurs in the device (OTS, UVLO, PGOOD failure).
When transitioning from ACTIVE to SUSPEND state, rails not controlled by the power-down sequencer
maintains the same ON/OFF state in SUSPEND state that it had in ACTIVE state. This allows for the
selected power rails to remain powered up when in the SUSPEND state.
When transitioning to the OFF or RECOVERY state, rails not under sequencer control are shut-down as
follows:
• DCDC1, DCDC2, DCDC3, DCDC4, LDO1, and LS1 shut down at the beginning of the power-down
sequence, if not under sequencer control (SEQ = 0b).
• LS2 and LS3 shut down as the state machine enters an OFF or RECOVERY state; 500 ms after the
power-down sequence is triggered.
If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut
down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and
LDO1). The amount of time the discharge circuitry remains active is a function of the INT_LDO hold up
time (see Section 5.3.1.6 for more details).
5.3.1.3
Strobe 1 and Strobe 2
STROBE 1 and STROBE 2 are dedicated to DCDC5 and DCDC6 which are always-on; powered up as
soon as the device exits the OFF state, and ON in any other state. STROBE 1 and STROBE 2 options are
available only for DCDC5 and DCDC6, not for any other rails.
STROBE 1 and STROBE 2 occur in every power-up sequence, regardless if the rail is already powered
up. If the rail is not to be powered up, its respective strobe setting must be set to 0x00.
When a power-down sequence initiates, STROBE 1 and STROBE 2 occur only if the FSEAL bit is 0b.
Otherwise, both strobes are omitted and DCDC5 and DCDC6 maintain state.
NOTE
The power-down sequence follows the reverse of the power-up sequence. STROBE2 and
STROBE1 are executed only if FSEAL bit is 0b.
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PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
STROBE 4
STROBE 3
STROBE 2
STROBE 1
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b SEQ = 0010b SEQ = 0001b
Figure 5-4. Power-Down Sequences to OFF State;
PWR_EN is Power-Down Event; FSEAL = 0b
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
STROBE 4
STROBE 3
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE2 and STROBE1 are not shown.
Figure 5-5. Power-Down Sequences to SUSPEND State;
PWR_EN is Power-Down Event; FSEAL = 1b
PB (input)
PWR_EN
(input)
FAULT
nWAKEUP
(output)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
STROBE 4
STROBE 3
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE2 and STROBE1 are not shown.
Figure 5-6. Power-Down Sequences to RECOVERY State;
TSD or UV is Power-Down Event; FSEAL = 1b
26
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5.3.1.4
SLDS261 – NOVEMBER 2019
Supply Voltage Supervisor and Power-Good (PGOOD)
Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1,
DCDC2, DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and
driven low when one or more rails encounter a fault which brings the output voltage outside the specified
tolerance range. In a typical application PGOOD drives the reset signal of the SOC.
The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all
enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and
deglitch times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for
undervoltage and overvoltage with tight limits and short deglitch times. Table 5-1 summarizes these
details.
Table 5-1. Supervisor Characteristics Controlled by the STRICT Bit
PARAMETER
STRICT = 0b (TYP)
STRICT = 1b (TYP)
90%
96.5% (DCDC1 and DCDC2)
95.5% (DCDC3, DCDC4, and LDO1)
Deglitch (output falling)
1 ms
50 µs
Deglitch (output rising)
10 µs
10 µs
Threshold (output falling)
N/A
103.5% (DCDC1 and DCDC2)
104.5% (DCDC3, DCDC4, and
LDO1)
Deglitch (output falling)
N/A
1 ms
Deglitch (output rising)
N/A
50 µs
Threshold (output falling)
Undervoltage
monitoring
Overvoltage
monitoring
Overvoltage threshold
(output rising)
LDO1
Hysteresis
Undervoltage threshold
(output falling)
Hysteresis
Power-good comparator
output (internal signal)
Voltage droop has no effect on
PGOOD output if duration is
less than deglitch time.
Voltage droop has no effect on
PGOOD output if duration is
less than deglitch time.
PGOOD
Deglitch time
Figure 5-7. Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch Times
The following rules apply to the PGOOD output:
• The power-up default state for THE PGOOD is low. When all rails are disabled, the PGOOD output is
driven low.
• Only enabled rails are monitored. Disabled rails are ignored.
• Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously
monitored thereafter. This allows the rail to power-up.
• The PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
• If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, then
the PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY
does not apply.
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•
•
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Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If
all rails are disabled, the PGOOD is driven low as the last rail is disabled.
If the power-down sequencer is triggered, PGOOD is driven low.
The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.
Figure 5-8 shows a typical power-up sequence and PGOOD timing.
VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
LDO1
DLY1 + DLY2
5 ms
DLY4 + DLY3
PG LDO1
(internal)
DCDC3
FAULT
DLY3 + DLY4
5 ms
DLY6 + DLY5
PG DCDC3
(internal)
DLY5 + DLY6
DCDC4
5 ms
DLY7
PG DCDC4
(internal)
DLY7
DCDC1
5 ms
DLY8
PG DCDC1
(internal)
DLY8
DCDC2
5 ms
DLY9
PG DCDC2
(internal)
PG_DLY
PGOOD
(1)
Sequence shown for TPS65218D0 variant. For other TPS65218xx variants, refer to registers SEQ1-7 in Section 5.6.4 for factoryprogrammed sequence order and timing.
Figure 5-8. Typical Power-Up Sequence of the Main Output Rails for TPS65218D0
5.3.1.5
Backup Supply Power-Good (PGOOD_BU)
PGOOD_BU is a push-pull output indicating if DCDC5 and DCDC6 are in regulation. The output is driven
to high when both rails are in regulation, and driven low if at least one of the rails is below the power-good
threshold. The output-high level is equal to the output voltage of DCDC6.
PGOOD_BU is the logical and between PGOOD (DCDC5) and PGOOD (DCDC6), and has no delay time
built-in. Unlike the main power-good, a fault on DCDC5 or DCDC6 does not trigger the power-down
sequencer, does not disable any of the rails in the system, and has no effect on the PGOOD pin. DCDC5
and DCDC6 recover automatically once the fault is removed.
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NOTE
In this example, the power-down is triggered by a fault on DCDC3.
This timing diagram assumes each rail powers up within the strobe delay time. If a rail takes
longer than the strobe delay time to power up, the next rail will wait for the previous rail to
reach its PGOOD voltage, and then may wait an additional 1 ms until it is enabled.
VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
DCDC6
PG DCDC6
(internal)
DCDC5
DLY1
PG DCDC5
(internal)
PGOOD_BU
(1)
Sequence shown for TPS65218D0 and TPS6521825 variants. For TPS6521815 variant, order and timing of DCDC5 and DCDC6 can
be modified using registers SEQ1-2 and SEQ5 in Section 5.6.4.
Figure 5-9. Typical Power-Up Sequence of DCDC5 and DCDC6
5.3.1.6
Internal LDO (INT_LDO)
The internal LDO provides a regulated voltage to the internal digital core and analog circuitry. The internal
LDO has a nominal output voltage of 2.5 V and can support up to 10 mA of external load. During
EEPROM programming, the output voltage is elevated to 3.6 V as described in Section 5.5.1. Therefore,
any external circuitry connected to INT_LDO must be capable of supporting that voltage.
When system power fails, the UVLO comparator triggers the power-down sequence. If system power
drops below 2.3 V, the digital core is reset and all remaining power rails are shut down instantaneously
and are pulled low to ground by their internal discharge circuitry (DCDC1-4 and LDO1).
The internal LDO reverse blocks to prevent the discharging of the output capacitor (CINT_LDO) on the
INT_LDO pin. The remaining charge on the INT_LDO output capacitor provides a supply for the power rail
discharge circuitry to ensure the outputs are discharged to ground even if the system supply has failed.
The amount of hold-up time specified in Section 4.5 is a function of the output capacitor value (CINT_LDO)
and the amount of external load on the INT_LDO pin, if any. The design allows for enough hold-up time to
sufficiently discharge DCDC1-4, and LDO1 to ensure proper processor power-down sequencing.
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From
system
power
IN_BIAS
INT_LDO
1 …F
UVLO
RESET
Digital Core
Power-Rail
Discharge Circuitry
EEPROM
Figure 5-10. Internal LDO and UVLO Sensing
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Current Limited Load Switches
The TPS6521815 provides three current limited load switches with individual inputs, outputs, and enable
control. Each switch provides the following control and diagnostic features:
• The ON or OFF state of the switch is controlled by the corresponding LSx_EN bit in the ENABLE
register.
• LS1 can be controlled by the sequencer or through I2C communication.
• LS2 and LS3 can only be controlled through I2C communication. The sequencer has no control over
LS2 and LS3.
• Each switch has an active discharge function, disabled by default, and enabled through the
LSxDCHRG bit. When enabled, the switch output is discharged to ground whenever the switch is
disabled.
• When the PFI input drops below the power-fail threshold (the power-fail comparator trips), the load
switches are automatically disabled to shed system load. This function must be individually enabled for
each switch through the corresponding LSxnPFO bit. The switches do not turn back on automatically
as the system voltage recovers, and must be manually re-enabled.
• An interrupt (LSx_I) issues whenever a load switch actively limits the output current, such as when the
output load exceeds the current limit value. The switch remains ON and provides current to the load
according to the current-limit setting.
• All three load switches have local overtemperature sensors which disable the corresponding switch if
the power dissipation and junction temperature exceeds the safe operating value. The switch
automatically recovers once the temperature drops below the OTS threshold value minus hysteresis.
The LSx_F (fault) interrupt bit is set while the switch is held OFF by the OTS function.
5.3.1.7.1 Load Switch 1 (LS1)
LS1 is a non-reverse blocking, low-voltage (< 3.6 V), low-impedance switch intended to support DDRx
self-refresh mode by cutting off the DDRx supply to the SOC DDRx interface during SUSPEND mode. In a
typical application, the input of LS1 is tied to the output of DCDC3 while the output of LS1 is connected to
the memory-interface supply pin of the SOC. LS1 can be controlled by the internal sequencer, just as any
power rail.
LS1_EN
LS1DIS
LS1nPFO
SOC
IN_LS1
LS1
From DCDC3
250
10 …F
DDR Memory
Interface
LS1_I
LS1_F
Figure 5-11. Typical Application of Load Switch 1
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5.3.1.7.2 Load Switch 2 (LS2)
LS2 is a reverse-blocking, 5 V, low-impedance switch. Load switch 2 provides four different current limit
values (100/200/500/1000 mA) that are selectable through LS2ILIM[1:0] bits. Overcurrent is reported
through the LS2_I interrupt.
LS2 has its own input-undervoltage protection which forces the switch OFF if the switch input voltage
(VIN_LS2) is <2.7 V. Similar to OTS, the LS2_F interrupt is set when the switch is held OFF by the local
UVLO function, and the switch recovers automatically when the input voltage rises above the UVLO
threshold.
LS2_EN
LS2DIS
LS2nPFO
LS2ILIM[1:0]
IN_LS2
LS2
+5 V
5-V boost
0.1 …F
250
120 …F
GND
5-V
Port
LS2_I
LS2_F
Figure 5-12. Typical Application of Load Switch 2
5.3.1.7.3 Load Switch 3 (LS3)
LS3 is a non-reverse blocking, medium-voltage (< 10 V), low-impedance switch that can be used to
provide 1.8-V to 10-V power to an auxiliary port. LS3 has four selectable current limit values that are
selectable through LS3ILIM[1:0].
LS3_EN
LS3DIS
LS3nPFO
LS3ILIM[1:0]
IN_LS3
LS3
From any
1.8-V to 10-V supply
250
VPORT
0.1 …F
120 …F
GND
AUX
Port
LS3_I
LS3_F
Figure 5-13. Typical Application of Load Switch 3
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LDO1
LDO1 is a general-purpose LDO intended to provide power to analog circuitry on the SOC. LDO1 has an
input voltage range from 1.8 V to 5.5 V, and can be connected either directly to the system power or the
output of a DCDC converter. The output voltage is programmable in the range of 0.9 V to 3.4 V with a
default of 1.8 V. LDO1 supports up to 200 mA at the minimum specified headroom voltage, and up to 400
mA at the typical operating condition of VOUT = 1.8 V, VIN_LDO1 > 2.7 V.
5.3.1.9
Coin Cell Battery Voltage Acquisition
CC
10
LOW (2.3 V)
+
DISABLED
+
±
CC_AQ = 1
Coin Cell
VREF
±
GOOD (2.6 V)
+
Enable 100-k
load resistor on CC
input.
Enable comparators.
VREF
±
CC_STAT[1:0]
IDEAL (3 V)
+
VREF
LOGIC CORE
±
Wait 600 ms
LOAD ENABLE
Latch comparator outputs;
Store result in CC_STAT[1:0]
Disable 100-k load resistor.
Disable comparators
Restore CC_AQ bit to 0 (CC_AQ = 0)
Issue interrupt (CC_AQC = 1)
CC_STAT[1:0] = 00b ± VCC < VLOW; Coin cell is not present or at end-of-life (EOL).
CC_STAT[1:0] = 01b ± VLOW < VCC < VGOOD; Coin cell is LOW.
CC_STAT[1:0] = 10b ± VGOOD < VCC < VIDEAL; Coin cell is GOOD.
CC_STAT[1:0] = 11b ± VIDEAL < VCC; Coin cell voltage is IDEAL.
Figure 5-14. Left: Flow Chart for Acquiring Coin Cell Battery Voltage
Right: Comparator Circuit
5.3.1.10 UVLO
Depending on the slew rate of the input voltage into the IN_BIAS pin, the power rails of TPS6521815 will
be enabled at either VULVO or VULVO + VHYS.
If the slew rate of the IN_BIAS voltage is greater than 30 V/s, then TPS6521815 will power up at VULVO.
Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the
PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.55 V, the input
voltage would have to recover above VUVLO in less than 5 ms for the device to remain active.
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If the slew rate of the IN_BIAS voltage is less than 30 V/s, then TPS6521815 will power up at VULVO +
VHYS. Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before
the PMIC shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.5 V, the
input voltage would have to recover above VUVLO + VHYS in less than 5 ms for the device to remain active.
In either slew rate scenario, if the input voltage were to fall below 2.5 V, the digital core is reset and all
remaining power rails are shut down instantaneously and are pulled low to ground by their internal
discharge circuitry (DCDC1-4 and LDO1).
UVLO hysteresis
UVLO threshold, supply falling
< 5 ms
VIN_BIAS
UVLO active
UVLO (internal signal)
UVLO inactive
> 5-ms
deglitch
Figure 5-15. Definition of UVLO and Hysteresis
After the UVLO triggers, the internal LDO blocks current flow from its output capacitor back to the IN_BIAS
pin, allowing the digital core and the discharge circuits to remain powered for a limited amount of time to
properly shut-down and discharge the output rails. The hold-up time is determined by the value of the
capacitor connected to INT_LDO. See Section 5.3.1.6 for more details.
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5.3.1.11 Power-Fail Comparator
The power-fail comparator notifies the system host if the system supply voltage drops and the system is at
risk of shutting down. The comparator has an internal 800-mV threshold and the trip-point is adjusted by
an external resistor divider.
By default, the power-fail comparator has no impact on any of the power rails or load switches. Load
switches are configured individually, to be disabled when the PFI comparator trips to shed system load
and extend hold-up time as described in Section 5.3.1.7. The power-fail comparator also triggers the
power-down sequencer, such that all or selective rails power-down when the system voltage fails. To tie
the power-fail comparator into the power-down sequence, the OFFnPFO bit in the CONTROL register
must be set to 1.
The power-fail comparator cannot be monitored by software, such that no interrupt or status bit is
associated to this function.
System supply voltage
nPFO
PFI
+
VREF
(800 mV)
Deglitch
±
PFI hysteresis
PFI threshold, supply falling
<25 µs
VPFI
nPFO inactive
nPFO (pin)
nPFO active
10-ms deglitch
25-µs deglitch
Figure 5-16. Power-Fail Comparator Simplified Circuit and Timing Diagram
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5.3.1.12 Battery-Backup Supply Power-Path
VSYS_BU
DCDC5 and DCDC6 are supplied from either the CC (coin-cell battery) input or IN_BU (main system
supply). The power-path is designed to prioritize IN_BU to maximize coin-cell battery life. Whenever the
PMIC is powered-up (WAIT_PWR_EN, ACTIVE, SUSPEND, and RECOVERY state), the power-path is
forced to select the IN_BU input. In OFF mode the power-path selects the higher of the two inputs with a
built-in hysteresis of 150 mV as shown in Figure 5-17.
VIN_BU
VSYS_BU
VINT_LDO
VIN_BU,
VSYS_BU
VCC
VCC
150 mV
VINT_LDO = 2.5 V
VnPUC = 2.3 V
0V
VCC
VIN_BU
ACTIVE STATE OFF STATE, FSEAL = 1b
Rapid decay of VIN_BIAS (preregulator)
Figure 5-17. Switching Behavior of the BatteryBackup-Supply Power-Path;
Power-Path Hysteresis
Figure 5-18. Switching Behavior of the BatteryBackup-Supply Power-Path;
Main Power Supply Removal
VIN_BU
VSYS_BU
VINT_LDO
VIN_BU
VSYS_BU
VINT_LDO
VUVLO + VHYST
VUVLO + VHYST
VINT_LDO = 2.5 V
VnPUC = 2.3 V
VCC
VINT_LDO = 2.5 V
VnPUC = 2.3 V
VCC = 2.2 V
VIN_BU = 2.05 V
ACTIVE STATE OFF STATE, FSEAL = 1b
ACTIVE STATE OFF STATE, FSEAL = 1b
(VIN_BIAS slow decay)
VIN_BIAS slow decay
Figure 5-19. Switching Behavior of the BatteryBackup-Supply Power-Path;
Weakening Main Battery, Strong Coin-Cell
Figure 5-20. Switching Behavior of the BatteryBackup-Supply Power-Path;
Weakening Main Battery, Weak Coin-Cell
When VIN_BIAS drops below the UVLO threshold, the PMIC shuts down all rails and enters OFF mode. At
this point the power-path selects the higher of the two input supplies. If the coin-cell battery is less than
150 mV above the UVLO threshold, SYS_BU remains connected to IN_BU (see Figure 5-19). If the coincell is >150 mV above the UVLO threshold, the power-path switches to the CC input as shown in
Figure 5-20. With no load on the main supply, the input voltage may recover over time to a value greater
than the coin-cell voltage and the power-path switches back to IN_BU. This is a typical behavior in a Li-Ion
battery powered system.
Depending on the system load, VIN_BIAS may drop below VINT_LDO before the power-down sequence is
completed. In that case, INT_LDO is turned OFF and the digital core is reset forcing the unit into OFF
mode and the power-path switches to IN_BU as shown in Figure 5-18.
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5.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
INT_LDO
DC34_SEL current source disabled.
All comparators disabled.
10 µA
SOURCE ENABLE
DC34_SEL
+
Sequence is triggered by any
event forcing register reset.
1200 mV
RSEL
+
Enable 10 µA DC34_SEL current source.
Enable comparators.
825 mV
575 mV
400 mV
Disable comparators
Disable DC34_SEL current source.
100 mV
V3
DCDC4[5:0]
V2
V1
±
+
Start power-up sequencer
DCDC3[5:0]
±
+
163 mV
LOGIC CORE
±
+
275 mV
V4
±
+
Latch comparator outputs;
Depending on result, over-write
DCDC3[5:0] and / or DCDC4[5:0]
power-up default.
V5
±
+
Wait 100 µs
V6
±
V0
±
Figure 5-21. Left: Flow Chart for Selecting DCDC Power-Up Default Voltage
Right: Comparator Circuit
Table 5-2. Power-Up Default Values of DCDC3 and DCDC4
RSEL [KΩ]
MIN
TYP
POWER-UP DEFAULT
MAX
DCDC3[5:0]
DCDC4[5:0]
0
0
7.7
Programmed default (1.2 V)
Programmed default (3.3 V)
11.8
12.1
12.4
0x12 (1.35 V)
Programmed default (3.3 V)
19.5
20
20.5
0x18 (1.5 V)
Programmed default (3.3 V)
30.9
31.6
32.3
0x1F (1.8 V)
Programmed default (3.3 V)
44.4
45.3
46.3
0x3D (3.3 V)
0x01 (1.2 V)
64.8
66.1
67.3
Programmed default (1.2 V)
0x07 (1.35 V)
93.6
95.3
97.2
Programmed default (1.2 V)
0x0D (1.5 V)
146
150
Tied to
INT_LDO
Programmed default (1.2 V)
0x14 (1.8 V)
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5.3.1.14 I/O Configuration
The device has two GPIOs and one GPO pin, which are configured as follows:
• GPIO1:
– General-purpose, open-drain output is controlled by the GPO1 user bit or sequencer.
– DDR3 reset input signal from SOC. The signal is either latched or passed-through to the GPO2 pin.
See Table 5-3 for details.
• GPO2:
– General-purpose output is controlled by the GPO2 user bit.
– DDR3 reset output signal. Signal is controlled by GPIO1 and PGOOD. See Table 5-4 for details.
– Output buffer is configured as open-drain or push-pull.
• GPIO3:
– General-purpose, open-drain output id controlled by the GPO3 user bit or sequencer.
– Reset input-signal for DCDC1 and DCDC2.
Table 5-3. GPIO1 Configuration
IO1_SEL
(EEPROM)
GPO1
(USER BIT)
PGOOD
(PMIC SIGNAL)
GPIO1
(I/O PIN)
0
0
X
0
0
1
X
HiZ
COMMENTS
Open-drain output, driving low
Open-drain output, HiZ
Table 5-4. GPO2 Configuration
IO1_SEL
(EEPROM)
GPO2_BUF
(EEPROM)
GPO2
(USER BIT)
0
0
0
GPO2 is open drain output controlled by GPO2 user bit (driving low).
0
0
1
GPO2 is open drain output controlled by GPO2 user bit (HiZ).
0
1
0
GPO2 is push-pull output controlled by GPO2 user bit (driving low).
0
1
1
GPO2 is push-pull output controlled by GPO2 user bit (driving high).
1
0
X
GPO2 is open drain output controlled by GPIO1 and PGOOD.
1
1
X
GPO2 is push-pull output controlled by GPIO1 and PGOOD.
COMMENTS
Table 5-5. GPIO3 Configuration
DC12_RST
(EEPROM)
GPO3
(USER BIT)
GPIO3
(I/O PIN)
0
0
0
0
1
HiZ
1
X
Active low
COMMENTS
Open-drain output, driving low
Open-drain output, HiZ
GPIO3 is DCDC1 and DCDC2 reset input signal to PMIC (active low). See
Section 5.3.1.14.2 for details.
5.3.1.14.1 Configuring GPO2 as Open-Drain Output
GPO2 may be configured as open-drain or push-pull output. The supply for the push-pull driver is
internally connected to the IN_LS1 input pin, whereas an external pull-up resistor and supply are required
in the open-drain configuration. Because of the internal connection to IN_LS1, the external pull-up supply
must not exceed the voltage on the IN_LS1 pin, otherwise leakage current may be observed from GPO2
to IN_LS1 as shown in Figure 5-22.
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IN_LS1
External
pullup supply
Leakage path if external
pullup supply is > IN_LS1
GPO2
Push-Pull
Driver
Open-Drain
Driver
Figure 5-22. GPO2 as Open-Drain Output
NOTE
When configured as open-drain output, the external pull-up supply must not exceed the
voltage level on IN_LS1 pin.
5.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
The GPIO3 is an edge-sensitive reset input to the PMIC, when the DC12_RST bit set to 1. The reset
signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default
whenever GPIO3 input transitions from high to low, while all other registers maintain their current values.
DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power
cycled. This function recovers the processor from reset events while in low-power mode.
PGOOD (1 ms delayed)
GPIO1
Latch,
Gating
IO1_SEL (EEPROM: 0b = output, 1b = input)
GPO1 (user register bit, sequencer control enabled)
GPO2_BUF (EEPROM: 0b = open drain, 1b = push-pull)
IN_LS1
GPO2
EN
1
0
GPO2 (user register bit)
DC12_RST (EEPROM: 0b = disabled, 1b = enabled)
GPIO3
DCDC 1 and DCDC 2 reset
GPO3 (user register bit, sequencer control enabled)
Figure 5-23. I/O Pin Logic
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PMIC power-up
PGOOD
GPIO1 (DDR_RESET_IN)
(coming from SOC)
1 ms
GPO2 (DDR_RESET_OUT)
(going to DDR memory)
1 ms
RESET_OUT follows RESET_IN
RESET_IN is latched
RESET_OUT follows RESET_IN
Figure 5-24. DDR3 Reset Timing Diagram
NOTE
GPIO must be configured as input (IO1_SEL = 1b). GPO2 is automatically configured as
output.
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5.3.1.15 Push Button Input (PB)
The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a
momentary switch to ground and an external pullup resistor. The power-up sequence is triggered if the PB
input is held low for 600 ms.
<100 ms
PB pin (input)
System Power
(5.5 V)
Push
Button
100 ms
50 ms
100 k
PB
PB deglitched
(internal signal)
550 ms
Power-up event
(internal signal)
Figure 5-25. Left: Typical PB Input Circuit
Right: Push-Button Input (PB) Deglitch and Power-Up Timing
In ACTIVE mode, the TPS6521815 monitors the PB input and issues an interrupt when the pin status
changes, such as when it drops below or rises above the PB input-low or input-high thresholds. The
interrupt is masked by the PBM bit in the INT_MASK1 register.
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PB is pressed, INT
pin is pulled low,
PB._STATE bit is
set.
PB is released.
INT pin is pulled
low, PB_STATE bit
is reset.
PB is pressed, INT
pin is pulled low,
PB_STATE bit is
set.
PB is released before
INT register is read
through I2C. INT pin
remains low,
PB_STATE bit is reset.
PB pin
(50-ms deglitched input)
nWAKEUP
150 µs
PB interrupt bit
INT pin (output)
PB_STATE bit
I2C access to INT register
INT register is read
through I2C while PB
remains pressed. INT
pin is released,
PB_STATE bit remains
set.
INT register is read
through I2C.
INT register is read
through I2C. INT pin is
released.
Figure 5-26. PB Input-Low or Input-High Thresholds
NOTE
Interrupts are issued whenever the PB pin status changes. The PB_STATE bit reflects the
current status of the PB input. nWAKEUP is pulled low for 150 µs on every falling edge of
PB.
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5.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
In ACTIVE state, the nWAKEUP pin is pulled low for five 32-kHz clock cycles (approximately 150 µs)
whenever a falling edge on the PB input is detected. This allows the host processor to wakeup from DEEP
SLEEP mode of operation. It is recommended to pull-up the nWAKEUP pin to DCDC6 output through a 1MΩ resistor.
5.3.1.15.2 Push Button Reset
If the PB input is pulled low for 8 s (15 s if TRST = 1b) or longer, then all rails except for DCDC5 and
DCDC6 are disabled, and the device enters the RECOVERY state. The device powers up automatically
after the 500 ms power-down sequence is complete, regardless of the state of the PB input. Holding the
PB pin low for 8 s (15 s if TRST = 1b), only turns off the device temporarily and forces a system restart,
and is not a power-down function. If the PB is held low continuously, the device power-cycles in 8-s and
15-s intervals.
5.3.1.16 AC_DET Input (AC_DET)
The AC_DET pin is a CMOS-type input used in three different ways to control the power-up of the PMIC:
• In a battery operated system, AC_DET is typically connected to an external battery charger with an
open-drain power-good output pulled low when a valid charger supply is connected to the system. A
falling edge on the AC_DET pin causes the PMIC to power up.
• In a non-portable system, the AC_DET pin may be shorted to ground and the device powers up
whenever system power is applied to the chip.
• If none of the above behaviors are desired, AC_DET may be tied to system power (IN_BIAS). Powerup is then controlled through the push-button input or PWR_EN input.
System Power
(5.5 V)
System Power
(5.5 V)
100 k
AC_DET
AC_DET
(A)
A.
B.
C.
AC_DET
(B)
(C)
Portable Systems
Non-portable Systems
Disabled
Figure 5-27. AC_DET Pin Configurations
<100 ms
AC_DET pin
(input)
AC_DET
deglitched
(internal signal)
10 ms
100 ms
Power-up event
(internal signal)
Figure 5-28. AC_DET Input Deglitch and Power-Up Timing (Portable Systems)
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In ACTIVE state, the TPS6521815 monitors the AC_DET input and issues an interrupt when the pin status
changes, such as when it drops below or rises above the AC_DET input-low or input-high thresholds. The
interrupt is masked by the ACM bit in the INT_MASK1 register.
AC goes low, INT
pin is pulled low,
PC_STATE bit is
set.
AC goes high. INT
pin is pulled low,
AC_STATE bit is
reset.
AC goes low, INT
pin is pulled low,
AC_STATE bit is
set.
AC goes high before
INT register is read
through I2C. INT pin
remains low,
AC_STATE bit is reset.
AC_DET pin
(10-ms deglitched input)
AC interrupt bit
INT pin (output)
AC_STATE bit
I2C access to INT register
INT register is read
through I2C while AC
remains low. INT pin is
released, AC_STATE bit
remains set.
INT register is read
through I2C. INT pin is
released.
INT register is read
through I2C.
Figure 5-29. AC_STATE Pin
NOTE
Interrupts are issued whenever the AC_DET pin status changes. The AC_STATE bit reflects
the current status of the AC_DET input.
5.3.1.17 Interrupt Pin (INT)
The interrupt pin signals any event or fault condition to the host processor. Whenever a fault or event
occurs in the device, the corresponding interrupt bit is set in the INT register, and the open-drain output is
pulled low. The INT pin is released (returns to Hi-Z state) and fault bits are cleared when the host reads
the INT register. If a failure persists, the corresponding INT bit remains set and the INT pin is pulled low
again after a maximum of 32 µs.
The MASK register masks events from generating interrupts. The MASK settings affect the INT pin only,
and have no impact on the protection and monitor circuits.
44
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5.3.1.18 I2C Bus Operation
The TPS6521815 hosts a slave I2C interface (address 0x24) that supports data rates up to 400 kbps,
auto-increment addressing. (1)
Slave Address + R/nW
A4
A3
A2
A1
A0 R/nW A
S7
S6
S5
S4
S3
S2
Data
S
A6
S
Start Condition
A
Acknowledge
A6
...
A0
Device Address
Read, Not Write
P
Stop Condition
S7
...
S0
Subaddress
R/nW
A5
Register Address
S1
S0
A
D7
D6
D5
D4
D7
D3
...
D2
D0
D1
D0
A
P
Data
Figure 5-30. Subaddress in I2C Transmission
The I2C bus is a communications link between a controller and a series of slave terminals. The link is
established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA).
The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for
data communication between the controller and the slave terminals. Each device has an open drain output
to transmit data on the serial data line. An external pullup resistor must be placed on the serial data line to
pull the drain output high during data transmission.
Data transmission initiates with a start bit from the controller as shown in Figure 5-32. The start condition
is recognized when the SDA line transitions from high to low during the high portion of the SCL signal.
Upon reception of a start bit, the device receives serial data on the SDA input and checks for valid
address and control information. If the appropriate slave address is set for the device, the device issues
an acknowledge pulse and prepares to receive register address and data. Data transmission is completed
by either the reception of a stop condition or the reception of the data word sent to the device. A stop
condition is recognized as a low to high transition of the SDA input during the high portion of the SCL
signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An
acknowledge issues after the reception of valid slave address, register-address, and data words. The I2C
interfaces an auto-sequence through the register addresses, so that multiple data words can be sent for a
given I2C transmission. Reference Figure 5-31 and Figure 5-32 for details.
S
SLAVE ADDRESS
W A
REGISTER ADDRESS
A
DATAREGADDR
A
DATASUBADDR+n
A
DATASUBADDR+n+1
A
P
n bytes + ACK
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
S
SLAVE ADDRESS
DATAREGADDR+n
R
A
A
DATAREGADDR
DATAREGADDR+n+1
A
A
P
n bytes + ACK
From master to slave
R Read (high)
S Start
A Not Acknowledge
From slave to master
W Write (low)
P Stop
A Acknowledge
Top: Master Writes Data to Slave
Bottom: Master Reads Data from Slave
Figure 5-31. I2C Data Protocol
(1)
Note: The SCL duty cycle at 400 kHz must be >40%.
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SDA
1-7
SCL
8
9
1-7
8
9
1-7
8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/nACK
STOP
2
Figure 5-32. I C Protocol and Transmission Timing
I2C Start Stop and Acknowledge Protocol
SDA
tf
tLOW
tSU;DAT
tr
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
tSU;STA
tHD;DAT
tSU;STO
tf
tHIGH
S
Sr
P
S
2
Figure 5-33. I C Protocol and Transmission Timing
I2C Data Transmission Timing
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5.4
SLDS261 – NOVEMBER 2019
Device Functional Modes
5.4.1
Modes of Operation
ANY STATE
NO POWER
External power and
Coin Cell removed
FSEAL
:0
PB low for > 8 s ||
OTS ||
PGOOD fault
VIN_BIAS < VUVLO ||
(OFFnPFO = 1 & VPFI < power-fail threshold)
SEQ DOWN
(500 ms)
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I2C
PGOOD
PGOOD_BU
nWAKEUP
Registers
= OFF
= FSEAL dependent
= OFF
= ON
= NO
= low
= rail dependent
= low
: GHIDXOW
ANY STATE
SEQ DOWN
(500 ms)
VIN_BIAS > (VUVLO + hysteresis)
VIN_BIAS > (VUVLO + hysteresis) &
PB = high &
AC_DET = high &
PWR_EN = low
PRE_OFF
OFF
VIN_BIAS > (VUVLO + hysteresis) &
(PB (;) || AC_DET (;) ||
PWR_EN = high)
VIN_BIAS > (VUVLO + hysteresis) &
(PB (;) ||
AC_DET (;) ||
PWR_EN = high)
WAIT_PWR_EN
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I 2C
PGOOD
PGOOD_BU
nWAKEUP
Registers
= OFF
= FSEAL dependent
= OFF
= OFF
OTS
= NO
= low
= rail dependent
RECOVERY
= low
: GHIDXOW
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I2C
PGOOD
PGOOD_BU
FSEAL
nWAKEUP
= ON
= ON
= ON
= ON
= YES
= high (rail dependent)
= high (rail dependent)
= can be set to 1 but not to 0
= low
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I2C
PGOOD
PGOOD_BU
FSEAL
nWAKEUP
= ON
= ON
= ON
= ON
= YES
= high (rail dependent)
= high (rail dependent)
= can be set to 1 but not to 0
= HiZ
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I2C
PGOOD
PGOOD_BU
nWAKEUP
DCDC1 reg.
DCDC2 reg.
= seq. dependent
= seq. / FSEAL dependent
= seq. dependent
= ON
= YES
= low
= high (rail dependent)
= HiZ
: GHIDXOW
: GHIDXOW
DCDC1...4
DCDC5...6
LDO1
INT_LDO
I 2C
PGOOD
PGOOD_BU
nWAKEUP
FSEAL
Registers
= OFF
= FSEAL dependent
= OFF
= ON
= NO
= low
= high
= HiZ
= maintains state
: GHIDXOW
PWR_EN = high
20 s time-out &
PB = high &
PWR_EN = low
ACTIVE
PWR_EN = low
DCDC1...4 = OFF &
LDO1 = OFF
SEQ DOWN
(500 ms)
DCDC1 = ON || DCDC2 = ON ||
DCDC3 = ON || DCDC4 = ON ||
LDO1 = ON
SUSPEND
PWR_EN = high ||
AC_DET (;) ||
PB (;)
PB (↓) has 50 ms debounce.
AC_DET (↓) has 10 ms debounce.
(↓) = denotes falling edge of signal.
Figure 5-34. Modes of Operation Diagram
5.4.2
OFF
In OFF mode, the PMIC is completely shut down with the exception of a few circuits to monitor the
AC_DET, PWR_EN, and PB input. All power rails are turned off and the registers are reset to their default
values. The I2C communication interface is turned off. This is the lowest-power mode of operation. To exit
OFF mode VIN_BIAS must exceed the UVLO threshold and one of the following wake-up events must occur:
• The PB input is pulled low.
• THE AC_DET input is pulled low.
• The PWR_EN input is pulled high.
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To enter OFF state, ensure that all power rails are assigned to the sequencer, then pull the PWR_EN pin
low. Additionally, if the OFFnPFO bit is set to 1b and the PFI input falls below the power fail threshold the
device transitions to the OFF state. If the freshness seal is broken, DCDC5 and DCDC6 remains on in the
OFF state. If a PGOOD or OTS fault occurs while in the ACTIVE state, TPS6521815 will transition to the
RESET state.
5.4.3
ACTIVE
This is the typical mode of operation when the system is up and running. All DCDC converters, LDOs, and
load switch are operational and can be controlled through the I2C interface. After a wake-up event, the
PMIC enables all rails controlled by the sequencer and pulls the nWAKEUP pin low to signal the event to
the host processor. The device only enters ACTIVE state if the host asserts the PWR_EN pin within 20 s
after the wake-up event. Otherwise it will enter OFF state. The nWAKEUP pin returns to HiZ mode after
the PWR_EN pin is asserted. ACTIVE state can also be directly entered from SUSPEND state by pulling
the PWR_EN pin high. See SUSPEND state description for details. To exit ACTIVE mode, the PWR_EN
pin must be pulled low.
5.4.4
SUSPEND
SUSPEND state is a low-power mode of operation intended to support system standby. Typically all
power rails are turned off with the exception of any rail with an SEQ register set to 0h. DCDC5 and
DCDC6 also remain enabled if the freshness seal is broken. To enter SUSPEND state, pull the PWR_EN
pin low. All power rails controlled by the power-down sequencer are shut down, and after 500 ms the
device enters SUSPEND state. All rails not controlled by the power-down sequencer will maintain state.
Note that all register values are reset as the device enters the SUSPEND state. The device enters
ACTIVE state after it detects a wake-up event as described in the previous sections.
5.4.5
RESET
The TPS6521815 can be reset by holding the PB pin low for more than 8 or 15 s, depending on the value
of the TRST bit. All rails are shut down by the sequencer and all register values reset to their default
values. Rails not controlled by the sequencer are shut down additionally. Note that the RESET function
power-cycles the device and only temporarily shuts down the output rails. Resetting the device does not
lead to OFF state. If the PB_IN pin is kept low for an extended amount of time, the device continues to
cycle between ACTIVE and RESET state, entering RESET every 8 or 15 s.
The device is also reset if a PGOOD or OTS fault occurs. The TPS6521815 remains in the recovery state
until the fault is removed, at which time it transitions back to the ACTIVE state.
5.5
5.5.1
Programming
Programming Power-Up Default Values
A consecutive write of 0x50, 0x1A, or 0xCE to the password register commits the current register settings
to EEPROM memory so they become the new power-up default values.
NOTE
Only bits marked with (E2) in the register map have EEPROM programmable power-up
default settings. All other bits keep the factory settings listed in the register map. Changing
the power-up default values is not recommended in production but for prototyping only.
The EEPROM of a device can only be programmed up to 1000 times. The number of programming cycles
should never exceed this amount. Contact TI for changing production settings.
48
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EEPROM values can only be changed if the input voltage (VIN_BIAS) is greater than 4.5 V. If the input
voltage is less than 4.5 V, EEPROM values remain unchanged and the VPROG interrupt is issued.
EEPROM programming requires less than 100 ms. During this time the supply voltage must be held
constant and all I2C write commands are ignored. Completion of EEPROM programming is signaled by
the EE_CMPL interrupt.
Program EEPROM Registers
IDLE
0x50, 0x1A, and 0xCE written to the PASSWORD register
Check supply voltage
(VIN_BIAS)
VIN_BIAS ” 4.5 V
VIN_BIAS > 4.5 V
Lock I2C Interface for write
access
< 100 ms
INT_LDO output
adjusted to 3.6 V
Program EEPROM
EE bit permanently set to 1b
INT_LDO output
adjusted to 2.5 V
Unlock I2C Interface
Issue PRGC Interrupt
Issue PRGC Interrupt
Figure 5-35. Flow Chart for Programming New Power-Up Default Values
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5.6
5.6.1
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Register Maps
Password Protection
Registers 0x11h through 0x26h are protected against accidental write by a 8-bit password. The password
must be written prior to writing to a protected register and automatically resets to 0x00h after the next I2C
transaction, regardless of the register accessed or transaction type (read or write). The password is
required for write access only and is not required for read access.
To write to a protected register:
1. Write the address of the destination register, XORed with the protection password (0x7Dh), to the
PASSWORD register (0x10h).
2. Write the data to the password protected register.
3. If the content of the PASSWORD register is XORed, with an address send that matches 0x7Dh, then
the data transfers to the protected register. Otherwise, the transaction is ignored. In either case the
PASSWORD register resets to 0x00 after the transaction.
The cycle must be repeated for any other register that is Level1 write protected.
5.6.2
Freshness Seal (FSEAL) Bit
The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and
DCDC6. The FSEAL bit exists in a default state of 0b, and can be set to 1b and reset to 0b once for
factory testing. The second time the bit is set to 1b, it remains 1b and cannot reset again under software
control. Coin-cell battery and main supply must be disconnected from the device to reset the FSEAL bit
again. With the FSEAL bit set to 1b, DCDC5 and DCDC6 are forced ON regardless of the state of the
DC5_EN and DC6_EN bit, and the rails do not turn off when the device enters the OFF state.
A consecutive write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b. The
three bytes must be written consecutively for the sequence to be valid. No other read or write transactions
are allowed between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in
the STATUS register reflects the new setting.
After setting the FSEAL bit, the device can enter the OFF state or any other mode of operation without
affecting the state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.
A second write of [0xB1, 0xFE, and 0xA3] to the password register resets the FSEAL bit to 0b. The three
bytes must be written consecutively for the sequence to be valid.
A third write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b and locks it into
this state for as long as the coin-cell supply (CC) remains connected to the device.
5.6.3
FLAG Register
The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails
while the system is suspended. The following rules apply to the FLAG register:
• The power-up default value for any flag bit is 0.
• Flag bits are read-only and cannot be written to.
• Upon entering a SUSPEND state, the flag bits are set to same value as their corresponding ENABLE
bits. Rails and GPOs enabled in a SUSPEND state have flag bits set to 1, while all other flag bits are
set to 0. Flag bits are not updated while in the SUSPEND state or when exiting the SUSPEND state.
• The FLAG register is static in WAIT_PWR_EN and ACTIVE state. The FLAG register reflects the
enable state of DCDC1, DCDC2, DCDC3, DCDC4, and LDO1; and, reflects the enable state of GPO1,
GPO2, and GPO3 during the last SUSPEND state.
The host processor reads the FLAG register to determine if the system powered up from the OFF or
SUSPEND state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and
therefore the DC3_FLG or DC4_FLG bits are set.
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5.6.4
SLDS261 – NOVEMBER 2019
TPS6521815 Registers
Table 5-6 lists the memory-mapped registers for the TPS6521815. All register offset addresses not listed
in Table 5-6 should be considered as reserved locations and the register contents should not be modified.
Table 5-6. TPS6521815 Registers
SUBADDRESS
ACRONYM
REGISTER NAME
R/W
PASSWORD
PROTECTED
SECTION
0x00
CHIPID
CHIP ID
R
No
Go
0x01
INT1
INTERRUPT 1
R
No
Go
0x02
INT2
INTERRUPT 2
R
No
Go
0x03
INT_MASK1
INTERRUPT MASK 1
R/W
No
Go
0x04
INT_MASK2
INTERRUPT MASK 2
R/W
No
Go
0x05
STATUS
STATUS
R
No
Go
0x06
CONTROL
CONTROL
R/W
No
Go
0x07
FLAG
FLAG
R
No
Go
0x10
PASSWORD
PASSWORD
R/W
No
Go
0x11
ENABLE1
ENABLE 1
R/W
Yes
Go
0x12
ENABLE2
ENABLE 2
R/W
Yes
Go
0x13
CONFIG1
CONFIGURATION 1
R/W
Yes
Go
0x14
CONFIG2
CONFIGURATION 2
R/W
Yes
Go
0x15
CONFIG3
CONFIGURATION 3
R/W
Yes
Go
0x16
DCDC1
DCDC1 CONTROL
R/W
Yes
Go
0x17
DCDC2
DCDC2 CONTROL
R/W
Yes
Go
0x18
DCDC3
DCDC3 CONTROL
R/W
Yes
Go
0x19
DCDC4
DCDC4 CONTROL
R/W
Yes
Go
0x1A
SLEW
SLEW RATE CONTROL
R/W
Yes
Go
0x1B
LDO1
LDO1 CONTROL
R/W
Yes
Go
0x20
SEQ1
SEQUENCER 1
R/W
Yes
Go
0x21
SEQ2
SEQUENCER 2
R/W
Yes
Go
0x22
SEQ3
SEQUENCER 3
R/W
Yes
Go
0x23
SEQ4
SEQUENCER 4
R/W
Yes
Go
0x24
SEQ5
SEQUENCER 5
R/W
Yes
Go
0x25
SEQ6
SEQUENCER 6
R/W
Yes
Go
0x26
SEQ7
SEQUENCER 7
R/W
Yes
Go
Table 5-7 explains the common abbreviations used in this section.
Table 5-7. Common Abbreviations
Abbreviation
Description
R
Read
W
Write
R/W
Read and write capable
E2
Backed by EEPROM
h
Hexadecimal notation of a group of bits
b
Hexadecimal notation of a bit or group of bits
X
Do not care reset value
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CHIPID Register (subaddress = 0x00) [reset = 0x15]
CHIPID is shown in Figure 5-36 and described in Table 5-8.
Return to Summary Table.
Figure 5-36. CHIPID Register
7
6
5
CHIP
R-2h
4
3
2
1
REV
R-5h
0
Table 5-8. CHIPID Register Field Descriptions
Bit
Field
Type
7-3
CHIP
R
Reset
Description
2h
Chip ID:
0h = TPS65218D0
1h = Future use
2h = TPS6521815
3h = Future use
4h = TPS6521825
5h = Future use
...
1Fh = Future use
2-0
REV
R
5h
Revision code:
0h = Revision 1.0
1h = Revision 1.1
2h = Revision 2.0
3h = Revision 2.1
4h = Revision 3.0
5h = Revision 4.0 (D0)
6h = Future use
7h = Future use
52
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5.6.4.2
SLDS261 – NOVEMBER 2019
INT1 Register (subaddress = 0x01) [reset = 0x00]
INT1 is shown in Figure 5-37 and described in Table 5-9.
Return to Summary Table.
Figure 5-37. INT1 Register
7
6
RESERVED
R-00b
5
VPRG
R-0b
4
AC
R-0b
3
PB
R-0b
2
HOT
R-0b
1
CC_AQC
R-0b
0
PRGC
R-0b
Table 5-9. INT1 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
VPRG
R
0b
5
Description
Programming voltage interrupt:
0b = No significance.
1b = Input voltage is too low for programming power-up default
values.
4
AC
R
0b
AC_DET pin status change interrupt. Note: Status information is
available in STATUS register.
0b = No change in status.
1b = AC_DET status change (AC_DET pin changed high to low or
low to high).
3
PB
R
0b
Push-button status change interrupt. Note: Status information is
available in STATUS register
0b = No change in status.
1b = Push-button status change (PB changed high to low or low to
high).
2
HOT
R
0b
Thermal shutdown early warning:
0b = Chip temperature is below HOT threshold.
1b = Chip temperature exceeds HOT threshold.
1
CC_AQC
R
0b
Coin cell battery voltage acquisition complete interrupt:
0b = No significance.
1b = Backup battery status comparators have settled and results are
available in STATUS register.
0
PRGC
R
0b
EEPROM programming complete interrupt:
0b = No significance.
1b = Programming of power-up default settings has completed
successfully.
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INT2 Register (subaddress = 0x02) [reset = 0x00]
INT2 is shown in Figure 5-38 and described in Table 5-10.
Return to Summary Table.
Figure 5-38. INT2 Register
7
6
RESERVED
R-00b
5
LS3_F
R-0b
4
LS2_F
R-0b
3
LS1_F
R-0b
2
LS3_I
R-0b
1
LS2_I
R-0b
0
LS1_I
R-0b
Table 5-10. INT2 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
LS3_F
R
0b
5
Description
Load switch 3 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
4
LS2_F
R
0b
Load switch 2 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit or input
voltage dropped below minimum value. Switch is temporarily
disabled.
3
LS1_F
R
0b
Load switch 1 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
2
LS3_I
R
0b
Load switch 3 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
1
LS2_I
R
0b
Load switch 2 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
0
LS1_I
R
0b
Load switch 1 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
54
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5.6.4.4
SLDS261 – NOVEMBER 2019
INT_MASK1 Register (subaddress = 0x03) [reset = 0x00]
INT_MASK1 is shown in Figure 5-39 and described in Table 5-11.
Return to Summary Table.
Figure 5-39. INT_MASK1 Register
7
6
RESERVED
R-00b
5
VPRGM
R/W-0b
4
ACM
R/W-0b
3
PBM
R/W-0b
2
HOTM
R/W-0b
1
CC_AQCM
R/W-0b
0
PRGCM
R/W-0b
Table 5-11. INT_MASK1 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
VPRGM
R/W
0b
5
Description
Programming voltage interrupt mask bit. Note: mask bit has no effect
on monitoring function:
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
4
ACM
R/W
0b
AC_DET interrupt masking bit:
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
Note: mask bit has no effect on monitoring function.
3
PBM
R/W
0b
PB interrupt masking bit. Note: mask bit has no effect on monitoring
function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
2
HOTM
R/W
0b
HOT interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
1
CC_AQCM
R/W
0b
C_AQC interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
0
PRGCM
R/W
0b
PRGC interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
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INT_MASK2 Register (subaddress = 0x04) [reset = 0x00]
INT_MASK2 is shown in Figure 5-40 and described in Table 5-12.
Return to Summary Table.
Figure 5-40. INT_MASK2 Register
7
6
RESERVED
R-00b
5
LS3_FM
R/W-0b
4
LS2_FM
R/W-0b
3
LS1_FM
R/W-0b
2
LS3_IM
R/W-0b
1
LS2_IM
R/W-0b
0
LS1_IM
R/W-0b
Table 5-12. INT_MASK2 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
LS3_FM
R/W
0b
5
Description
LS3 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
4
LS2_FM
R/W
0b
LS2 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
3
LS1_FM
R/W
0b
LS1 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
2
LS3_IM
R/W
0b
LS3 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
1
LS2_IM
R/W
0b
LS2 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
0
LS1_IM
R/W
0b
LS1 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
56
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5.6.4.6
SLDS261 – NOVEMBER 2019
STATUS Register (subaddress = 0x05) [reset = 00XXXXXXb]
Register mask: C0h
STATUS is shown in Figure 5-41 and is described in Table 5-13.
Return to Summary Table.
Figure 5-41. STATUS Register
7
FSEAL
R-0b
6
EE
R-0b
5
AC_STATE
R-X
4
PB_STATE
R-X
3
2
1
STATE
R-X
0
CC_STAT
R-X
Table 5-13. STATUS Register Field Descriptions
Bit
7
Field
Type
Reset
FSEAL
R
0b
Description
Freshness seal (FSEAL) status. Note: See Section 5.6.2 for details.
0b = FSEAL is in native state (fresh).
1b = FSEAL is broken.
6
EE
R
0b
EEPROM status:
0b = EEPROM values have not been changed from factory default
setting.
1b = EEPROM values have been changed from factory default
settings.
5
AC_STATE
R
X
AC_DET input status bit:
0b = AC_DET input is inactive (AC_DET input pin is high).
1b = AC_DET input is active (AC_DET input is low).
4
PB_STATE
R
X
PB input status bit:
0b = Push Button input is inactive (PB input pin is high).
1b = Push Button input is active (PB input pin is low).
3-2
STATE
R
X
State machine STATE indication:
0h = PMIC is in transitional state.
1h = PMIC is in WAIT_PWR_EN state.
2h = PMIC is in ACTIVE state.
3h = PMIC is in SUSPEND state.
1-0
CC_STAT
R
X
Coin cell state of charge. Note: Coin-cell voltage acquisition must be
triggered first before status bits are valid. See CC_AQ bit in
Section 5.6.4.7.
0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching endof-life (EOL).
1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW.
2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD.
3h = VIDEAL < VCC; Coin cell voltage is IDEAL.
Detailed Description
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CONTROL Register (subaddress = 0x06) [reset = 0x00]
CONTROL is shown in Figure 5-42 and described in Table 5-14.
Return to Summary Table.
Figure 5-42. CONTROL Register
7
6
5
4
3
2
RESERVED
R-0000 00b
1
OFFnPFO
R/W-0b
0
CC_AQ
R/W-0b
Table 5-14. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
7-2
RESERVED
R
0000 00b
OFFnPFO
R/W
0b
1
Description
Power-fail shutdown bit:
0b = nPFO has no effect on PMIC state.
1b = All rails are shut down and PMIC enters OFF state when PFI
comparator trips (nPFO is low).
0
CC_AQ
R/W
0b
Coin Cell battery voltage acquisition start bit:
0b = No significance
1b = Triggers voltage acquisition. Bit is automatically reset to 0.
58
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5.6.4.8
SLDS261 – NOVEMBER 2019
FLAG Register (subaddress = 0x07) [reset = 0x00]
FLAG is shown in Figure 5-43 and described in Table 5-15.
Return to Summary Table.
Figure 5-43. FLAG Register
7
GPO3_FLG
R-0b
6
GPO2_FLG
R-0b
5
GPO1_FLG
R-0b
4
LDO1_FLG
R-0b
3
DC4_FLG
R-0b
2
DC3_FLG
R-0b
1
DC2_FLG
R-0b
0
DC1_FLG
R-0b
Table 5-15. FLAG Register Field Descriptions
Bit
7
Field
Type
Reset
GPO3_FLG
R
0b
Description
GPO3 Flag bit:
0b = Device powered up from OFF or SUSPEND state and GPO3
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO3 was
enabled while in SUSPEND.
6
GPO2_FLG
R
0b
GPO2 Flag bit
0b = Device powered up from OFF or SUSPEND state and GPO2
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO2 was
enabled while in SUSPEND.
5
GPO1_FLG
R
0b
GPO1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and GPO1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO1 was
enabled while in SUSPEND.
4
LDO1_FLG
R
0b
LDO1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and LDO1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and LDO1 was
enabled while in SUSPEND.
3
DC4_FLG
R
0b
DCDC4 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC4
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC4 was
enabled while in SUSPEND.
2
DC3_FLG
R
0b
DCDC3 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC3
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC3 was
enabled while in SUSPEND.
1
DC2_FLG
R
0b
DCDC2 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC2
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC2 was
enabled while in SUSPEND.
Detailed Description
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Table 5-15. FLAG Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
DC1_FLG
R
0b
Description
DCDC1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GDCDC1PO3
was enabled while in SUSPEND.
5.6.4.9
PASSWORD Register (subaddress = 0x10) [reset = 0x00]
PASSWORD is shown in Figure 5-44 and described in Table 5-16.
Return to Summary Table.
Figure 5-44. PASSWORD Register
7
6
5
4
3
2
1
0
PWRD
R/W-00h
Table 5-16. PASSWORD Register Field Descriptions
60
Bit
Field
Type
Reset
7-0
PWRD
R/W
00h
Description
Register is used for accessing password protected registers (see
Section 5.6.1 for details). Breaking the freshness seal (see
Section 5.6.2 for details).Programming power-up default values (see
Section 5.5.1 for details). Read-back always yields 0x00.
Detailed Description
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5.6.4.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]
ENABLE1 is shown in Figure 5-45 and described in Table 5-17.
Return to Summary Table.
Password protected.
Figure 5-45. ENABLE1 Register
7
6
RESERVED
R-00b
5
DC6_EN
R/W-0b
4
DC5_EN
R/W-0b
3
DC4_EN
R/W-0b
2
DC3_EN
R/W-0b
1
DC2_EN
R/W-0b
0
DC1_EN
R/W-0b
Table 5-17. ENABLE1 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
DC6_EN
R/W
0b
5
Description
DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See
Section 5.6.2 for details.
0b = Disabled
1b = Enabled
4
DC5_EN
R/W
0b
DCDC5 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer. DCDC5 can
only be disabled if FSEAL = 0. See Section 5.6.2 for details.
0b = Disabled
1b = Enabled
3
DC4_EN
R/W
0b
DCDC4 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
2
DC3_EN
R/W
0b
DCDC3 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
1
DC2_EN
R/W
0b
DCDC2 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
0
DC1_EN
R/W
0b
DCDC1 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
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5.6.4.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x00]
ENABLE2 is shown in Figure 5-46 and described in Table 5-18.
Return to Summary Table.
Password protected.
Figure 5-46. ENABLE2 Register
7
RESERVED
R-0b
6
GPIO3
R/W-0b
5
GPIO2
R/W-0b
4
GPIO1
R/W-0b
3
LS3_EN
R/W-0b
2
LS2_EN
R/W-0b
1
LS1_EN
R/W-0b
0
LDO1_EN
R/W-0b
Table 5-18. ENABLE2 Register Field Descriptions
Bit
Field
Type
Reset
7
RESERVED
R
0b
6
GPIO3
R/W
0b
Description
General purpose output 3 / reset polarity. Note: If DC12_RST bit
(register 0x14) is set to 1 this bit has no function.
0b = GPIO3 output is driven low.
1b = GPIO3 output is HiZ.
5
GPIO2
R/W
0b
General purpose output 2. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO2 output is driven low.
1b = GPO2 output is HiZ.
4
GPIO1
R/W
0b
General purpose output 1. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO1 output is driven low.
1b = GPO1 output is HiZ.
3
LS3_EN
R/W
0b
Load switch 3 (LS3) enable bit.
0b = Disabled
1b = Enabled
2
LS2_EN
R/W
0b
Load switch 2 (LS2) enable bit.
0b = Disabled
1b = Enabled
1
LS1_EN
R/W
0b
Load switch 1 (LS1) enable bit.
0b = Disabled
1b = Enabled
Note: At power-up and down this bit is automatically updated by the
internal power sequencer.
0
LDO1_EN
R/W
0b
LDO1 enable bit.
0b = Disabled
1b = Enabled
Note: At power-up and down this bit is automatically updated by the
internal power sequencer.
62
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5.6.4.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x08]
CONFIG1 is shown in Figure 5-47 and described in Table 5-19.
Return to Summary Table.
Password protected.
Figure 5-47. CONFIG1 Register
7
TRST
R/W-0b
6
GPO2_BUF
R/W-0b
5
IO1_SEL
R/W-0b
4
3
PGDLY
R/W-01b
2
STRICT
R/W-0b
1
0
UVLO
R/W-00b
Table 5-19. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
7
TRST
R/W, E2
0b
Description
Push-button reset time constant:
0b = 8 s
1b = 15 s
6
GPO2_BUF
R/W, E2
0b
GPO2 output buffer configuration:
0b = GPO2 buffer is configured as open-drain.
1b = GPO2 buffer is configured as push-pull (high-level is driven to
IN_LS1).
5
IO1_SEL
R/W, E2
0b
GPIO1 / GPO2 configuration bit. See Section 5.3.1.14 for details.
0b = GPIO1 is configured as general-purpose, open-drain output.
GPO2 is independent output.
1b = GPIO1 is configured as input, controlling GPO2. Intended for
DDR3 reset signal control.
4-3
PGDLY
R/W, E2
01b
Power-Good delay. Note: Power-good delay applies to rising-edge
only (power-up), not falling edge (power-down or fault).
00b = 10 ms
01b = 20 ms
10b = 50 ms
11b = 150 ms
2
STRICT
R/W, E2
0b
Supply Voltage Supervisor Sensitivity selection. See Section 4.5 for
details.
0b = Power-good threshold (VOUT falling) has wider limits. Overvoltage is not monitored.
1b = Power-good threshold (VOUT falling) has tight limits. Overvoltage is monitored.
1-0
UVLO
R/W, E2
00b
UVLO setting
00b = 2.75 V
01b = 2.95 V
10b = 3.25 V
11b = 3.35 V
Detailed Description
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5.6.4.13 CONFIG2 Register (subaddress = 0x14) [reset = 0x40]
CONFIG2 is shown in Figure 5-48 and described in Table 5-20.
Return to Summary Table.
Password protected.
Figure 5-48. CONFIG2 Register
7
DC12_RST
R/W-0b
6
UVLOHYS
R/W-1b
5
4
3
RESERVED
R-00b
2
LS3ILIM
R/W-00b
1
0
LS2ILIM
R/W-00b
Table 5-20. CONFIG2 Register Field Descriptions
Bit
7
Field
Type
DC12_RST
R/W, E2
Reset
Description
DCDC1 and DCDC2 reset-pin enable:
0b = GPIO3 is configured as general-purpose output.
1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2.
6
UVLOHYS
R/W, E2
1b
UVLO hysteresis:
0b = 200 mV
1b = 400 mV
5-4
RESERVED
R
00b
3-2
LS3ILIM
R/W
00b
Load switch 3 (LS3) current limit selection:
00b = 100 mA, (MIN = 98 mA)
01b = 200 mA, (MIN = 194 mA)
10b = 500 mA, (MIN = 475 mA)
11b = 1000 mA, (MIN = 900 mA)
See the LS3 current limit specification in Section 4.5 for more details.
1-0
LS2ILIM
R/W
00b
Load switch 2 (LS2) current limit selection:
00b = 100 mA, (MIN = 94 mA)
01b = 200 mA, (MIN = 188 mA)
10b = 500 mA, (MIN = 465 mA)
11b = 1000 mA, (MIN = 922 mA)
See the LS2 current limit specification in Section 4.5 for more details.
64
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5.6.4.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
CONFIG3 is shown in Figure 5-49 and described in Table 5-21.
Return to Summary Table.
Password protected.
Figure 5-49. CONFIG3 Register
7
6
RESERVED
R-00b
5
LS3nPFO
R/W-0b
4
LS2nPFO
R/W-0b
3
LS1nPFO
R/W-0b
2
LS3DCHRG
R/W-0b
1
LS2DCHRG
R/W-0b
0
LS1DCHRG
R/W-0b
Table 5-21. CONFIG3 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
LS3nPFO
R/W
0b
5
Description
Load switch 3 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
4
LS2nPFO
R/W
0b
Load switch 2 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
3
LS1nPFO
R/W
0b
Load switch 1 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
2
LS3DCHRG
R/W
0b
Load switch 3 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
1
LS2DCHRG
R/W
0b
Load switch 2 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
0
LS1DCHRG
R/W
0b
Load switch 1 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
Detailed Description
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5.6.4.15 DCDC1 Register (offset = 0x16) [reset = 0x80]
DCDC1 is shown in Figure 5-50 and described in Table 5-22.
Return to Summary Table.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is
performed on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or the GODSBL bit must be set to 1b in
register 0x1A.
Figure 5-50. DCDC1 Register
7
PFM
R/W-1b
6
RESERVED
R-0b
5
4
3
2
1
0
DCDC1
R/W-00h
Table 5-22. DCDC1 Register Field Descriptions
Bit
Field
Type
Reset
7
PFM
R/W
1b
Description
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
66
RESERVED
R
0b
Detailed Description
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Table 5-22. DCDC1 Register Field Descriptions (continued)
Bit
Field
Type
5-0
DCDC1
R/W, E2
Reset
Description
00h
DCDC1 output voltage setting:
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200
Detailed Description
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Table 5-22. DCDC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675
68
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5.6.4.16 DCDC2 Register (subaddress = 0x17) [reset = 0x80]
DCDC2 is shown in Figure 5-51 and described in Table 5-23.
Return to Summary Table.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is
performed on the DCDC2 register.
Note 3: To change the output voltage of DCDC2, the GO bit or the GODSBL bit must be set to 1b in
register 0x1A.
Figure 5-51. DCDC2 Register
7
PFM
R/W-1b
6
RESERVED
R-0b
5
4
3
2
1
0
DCDC2
R/W-00h
Table 5-23. DCDC2 Register Field Descriptions
Bit
Field
Type
Reset
7
PFM
R/W
1b
Description
Pulse frequency modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
R
0b
Detailed Description
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Table 5-23. DCDC2 Register Field Descriptions (continued)
Bit
Field
Type
5-0
DCDC2
R/W, E2
Reset
Description
00h
DCDC2 output voltage setting:
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200
70
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Table 5-23. DCDC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675
Detailed Description
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5.6.4.17 DCDC3 Register (subaddress = 0x18) [reset = 0x80]
DCDC3 is shown in Figure 5-52 and described in Table 5-24.
Return to Summary Table.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is
performed on the DCDC3 register.
NOTE
Power-up default may differ depending on RSEL value. See Section 5.3.1.13 for details.
Figure 5-52. DCDC3 Register
7
PFM
R/W-1b
6
RESERVED
R-0b
5
4
3
2
1
0
DCDC3
R/W-00h
Table 5-24. DCDC3 Register Field Descriptions
Bit
Field
Type
Reset
7
PFM
R/W
1b
Description
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
72
RESERVED
R
0b
Detailed Description
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Table 5-24. DCDC3 Register Field Descriptions (continued)
Bit
Field
Type
5-0
DCDC3
R/W, E2
Reset
Description
00h
DCDC3 output voltage setting:
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525
1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000
Detailed Description
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Table 5-24. DCDC3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400
74
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5.6.4.18 DCDC4 Register (subaddress = 0x19) [reset = 0x80]
DCDC4 is shown in Figure 5-53 and described in Table 5-25.
Return to Summary Table.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is
performed on the DCDC4 register.
NOTE
Power-up default may differ depending on RSEL value. See Section 5.3.1.13 for details. The
Reserved setting should not be selected and the output voltage settings should not be
modified while the converter is operating.
Figure 5-53. DCDC4 Register
7
PFM
R/W-1b
6
RESERVED
R-0b
5
4
3
2
1
0
DCDC4
R/W-00h
Table 5-25. DCDC4 Register Field Descriptions
Bit
Field
Type
Reset
7
PFM
R/W
1b
Description
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
R
0b
Detailed Description
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Table 5-25. DCDC4 Register Field Descriptions (continued)
Bit
Field
Type
5-0
DCDC4
R/W, E2
Reset
Description
00h
DCDC4 output voltage setting:
0h = 1.175
1h = 1.200
2h = 1.225
3h = 1.250
4h = 1.275
5h = 1.300
6h = 1.325
7h = 1.350
8h = 1.375
9h = 1.400
Ah = 1.425
Bh = 1.450
Ch = 1.475
Dh = 1.500
Eh = 1.525
Fh = 1.550
10h = 1.600
11h = 1.650
12h = 1.700
13h = 1.750
14h = 1.800
15h = 1.850
16h = 1.900
17h = 1.950
18h = 2.000
19h = 2.050
1Ah = 2.100
1Bh = 2.150
1Ch = 2.200
1Dh = 2.250
1Eh = 2.300
1Fh = 2.3500
20h = 2.400
21h = 2.450
22h = 2.500
23h = 2.550
76
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Table 5-25. DCDC4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 2.600
25h = 2.650
26h = 2.700
27h = 2.750
28h = 2.800
29h = 2.850
2Ah = 2.900
2Bh = 2.950
2Ch = 3.000
2Dh = 3.050
2Eh = 3.100
2Fh = 3.150
30h = 3.200
31h = 3.250
32h = 3.300
33h = 3.350
34h = 3.400
35h = reserved
36h = reserved
37h = reserved
38h = reserved
39h = reserved
3Ah = reserved
3Bh = reserved
3Ch = reserved
3Dh = reserved
3Eh = reserved
3Fh = reserved
Detailed Description
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5.6.4.19 SLEW Register (subaddress = 0x1A) [reset = 0x06]
SLEW is shown in Figure 5-54 and described in Table 5-26.
Return to Summary Table.
NOTE
Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to
lower voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1
and DCDC2 must be set to 0.
Figure 5-54. SLEW Register
7
GO
R/W-0b
6
GODSBL
R/W-0b
5
4
RESERVED
R-000b
3
2
1
SLEW
R/W-6h
0
Table 5-26. SLEW Register Field Descriptions
Bit
7
Field
Type
Reset
GO
R/W
0b
Description
Go bit. Note: Bit is automatically reset at the end of the voltage
transition.
0b = No change
1b = Initiates the transition from present state to the output voltage
setting currently stored in DCDC1 and DCDC2 register. SLEW
setting does apply.
6
GODSBL
R/W
0b
Go disable bit
0b = Enabled
1b = Disabled; DCDC1 and DCDC2 output voltage changes
whenever set-point is updated in DCDC1 and DCDC2 register
without having to write to the GO bit. SLEW setting does apply.
5-3
RESERVED
R
000b
2-0
SLEW
R/W
6h
Output slew rate setting:
0h = 160 µs/step (0.0625 mV/µs at 10 mV per step)
1h = 80 µs/step (0.125 mV/µs at 10 mV per step)
2h = 40 µs/step (0.250 mV/µs at 10 mV per step)
3h = 20 µs/step (0.500 mV/µs at 10 mV per step)
4h = 10 µs/step (1.0 mV/µs at 10 mV per step)
5h = 5 µs/step (2.0 mV/µs at 10 mV per step)
6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step)
7h = Immediate; slew rate is only limited by control loop response
time. Note: The actual slew rate depends on the voltage step per
code. Refer to DCDCx registers for details.
78
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5.6.4.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
LDO1 is shown in Figure 5-55 and described in Table 5-27.
Return to Summary Table.
Note 1: This register is password protected. For more information, see Section 5.6.1.
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is
performed on the LDO1 register.
Figure 5-55. LDO1 Register
7
6
5
4
3
RESERVED
R-00b
2
1
0
LDO1
R/W-1Fh
Table 5-27. LDO1 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
00b
5-0
LDO1
R/W, E2
1Fh
Description
LDO1 output voltage setting:
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525
Detailed Description
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Table 5-27. LDO1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000
24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400
80
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5.6.4.21 SEQ1 Register (subaddress = 0x20) [reset = 0x00]
SEQ1 is shown in Figure 5-56 and described in Table 5-28.
Return to Summary Table.
Password protected.
Figure 5-56. SEQ1 Register
7
DLY8
R/W-0b
6
DLY7
R/W-0b
5
DLY6
R/W-0b
4
DLY5
R/W-0b
3
DLY4
R/W-0b
2
DLY3
R/W-0b
1
DLY2
R/W-0b
0
DLY1
R/W-0b
Table 5-28. SEQ1 Register Field Descriptions
Bit
Field
Type
Reset
7
DLY8
R/W, E2
0b
Description
Delay8 (occurs after Strobe 8 and before Strobe 9.)
0b = 2 ms
1b = 5 ms
6
DLY7
R/W, E2
0b
Delay7 (occurs after Strobe 7 and before Strobe 8.)
0b = 2 ms
1b = 5 ms
5
DLY6
R/W, E2
0b
Delay6 (occurs after Strobe 6 and before Strobe 7.)
0b = 2 ms
1b = 5 ms
4
DLY5
R/W, E2
0b
Delay5 (occurs after Strobe 5 and before Strobe 6.)
0b = 2 ms
1b = 5 ms
3
DLY4
R/W, E2
0b
Delay4 (occurs after Strobe 4 and before Strobe 5.)
0b = 2 ms
1b = 5 ms
2
DLY3
R/W, E2
0b
Delay3 (occurs after Strobe 3 and before Strobe 4.)
0b = 2 ms
1b = 5 ms
1
DLY2
R/W, E2
0b
Delay2 (occurs after Strobe 2 and before Strobe 3.)
0b = 2 ms
1b = 5 ms
0
DLY1
R/W, E2
0b
Delay1 (occurs after Strobe 1 and before Strobe 2.)
0b = 2 ms
1b = 5 ms
Detailed Description
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5.6.4.22 SEQ2 Register (subaddress = 0x21) [reset = 0x00]
SEQ2 is shown in Figure 5-57 and described in Table 5-29.
Return to Summary Table.
Password protected.
Figure 5-57. SEQ2 Register
7
DLYFCTR
R/W -0b
6
5
4
3
2
1
RESERVED
R-000 000b
0
DLY9
R/W -0b
Table 5-29. SEQ2 Register Field Descriptions
Bit
7
Field
Type
Reset
DLYFCTR
R/W, E2
0b
Description
Power-down delay factor:
0b = 1x
1b = 10x (delay times are multiplied by 10x during power-down.)
Note: DLYFCTR has no effect on power-up timing.
6-1
0
RESERVED
R
000 000b
DLY9
R/W, E2
0b
Delay9 (occurs after Strobe 9 and before Strobe 10.)
0b = 2 ms
1b = 5 ms
82
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5.6.4.23 SEQ3 Register (subaddress = 0x22) [reset = 0x00]
SEQ3 is shown in Figure 5-58 and described in Table 5-30.
Return to Summary Table.
Password protected.
Figure 5-58. SEQ3 Register
7
6
5
4
3
2
DC2_SEQ
R/W-0h
1
0
DC1_SEQ
R/W-0h
Table 5-30. SEQ3 Register Field Descriptions
Bit
Field
Type
7-4
DC2_SEQ
R/W, E2
Reset
Description
0h
DCDC2 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
Detailed Description
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Table 5-30. SEQ3 Register Field Descriptions (continued)
Bit
Field
Type
3-0
DC1_SEQ
R/W, E2
Reset
Description
0h
DCDC1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
84
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5.6.4.24 SEQ4 Register (subaddress = 0x23) [reset = 0x00]
SEQ4 is shown in Figure 5-59 and described in Table 5-31.
Return to Summary Table.
Password protected.
Figure 5-59. SEQ4 Register
7
6
5
4
3
2
DC4_SEQ
R/W-0h
1
0
DC3_SEQ
R/W-0h
Table 5-31. SEQ4 Register Field Descriptions
Bit
Field
Type
7-4
DC4_SEQ
R/W, E2
Reset
Description
0h
DCDC4 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
Detailed Description
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Table 5-31. SEQ4 Register Field Descriptions (continued)
Bit
Field
Type
3-0
DC3_SEQ
R/W, E2
Reset
Description
0h
DCDC3 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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5.6.4.25 SEQ5 Register (subaddress = 0x24) [reset = 0x00]
SEQ5 is shown in Figure 5-60 and described in Table 5-32.
Return to Summary Table.
Password protected.
Figure 5-60. SEQ5 Register
7
6
5
4
RESERVED
R-0h
DC6_SEQ
R/W-0h
3
2
RESERVED
R-0h
1
0
DC5_SEQ
R/W-0h
Table 5-32. SEQ5 Register Field Descriptions
Bit
Field
Type
Reset
7-6
RESERVED
R
0h
5-4
DC6_SEQ
R/W, E2
0h
Description
DCDC6 enable STROBE. Note: STROBE 1 and STROBE 2 are
executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by
sequencer once freshness seal is broken.
0h = Rail is not controlled by sequencer.
1h = Enable at STROBE 1.
2h = Enable at STROBE 2.
3h = Rail is not controlled by sequencer.
3-2
RESERVED
R
1-0
DC5_SEQ
R/W, E2
0h
0h
DCDC5 enable STROBE. Note: STROBE 1 and STROBE 2 are
executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by
sequencer once freshness seal is broken.
0h = Rail is not controlled by sequencer.
1h = Enable at STROBE 1.
2h = Enable at STROBE 2.
3h = Rail is not controlled by sequencer.
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5.6.4.26 SEQ6 Register (subaddress = 0x25) [reset = 0x00]
SEQ6 is shown in Figure 5-61 and described in Table 5-33.
Return to Summary Table.
Password protected.
Figure 5-61. SEQ6 Register
7
6
5
4
3
2
LS1_SEQ
R/W-0h
1
0
LDO1_SEQ
R/W-0h
Table 5-33. SEQ6 Register Field Descriptions
Bit
Field
Type
7-4
LS1_SEQ
R/W, E2
Reset
Description
0h
LS1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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Table 5-33. SEQ6 Register Field Descriptions (continued)
Bit
Field
Type
3-0
LDO1_SEQ
R/W, E2
Reset
Description
0h
LDO1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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5.6.4.27 SEQ7 Register (subaddress = 0x26) [reset = 0x00]
SEQ7 is shown in Figure 5-62 and described in Table 5-34.
Return to Summary Table.
Password protected.
Figure 5-62. SEQ7 Register
7
6
5
4
3
2
GPO3_SEQ
R/W-0h
1
0
GPO1_SEQ
R/W-0h
Table 5-34. SEQ7 Register Field Descriptions
Bit
Field
Type
7-4
GPO3_SEQ
R/W, E2
Reset
Description
0h
GPO3 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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Table 5-34. SEQ7 Register Field Descriptions (continued)
Bit
Field
Type
3-0
GPO1_SEQ
R/W, E2
Reset
Description
0h
GPO1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Application Information
The TPS6521815 is designed to pair with various application processors. The typical application in
Section 6.2 is based on and uses terminology consistent with the Sitara™ family of processors.
6.1.1
Applications Without Backup Battery
In applications that require always-on supplies but no battery backup, the CC input to the power path must
be connected to ground.
DCDC6 (1.8 V)
To SOC
L5
PGOOD_BU
DCDC5_PG
DCDC6_PG
DCDC5
DCDC6 (1.8 V)
To SOC
2.7-V to 5.5-V
system power
IN_nCC
22 …F
VDD_10 (1 V)
Battery backup
domain supply
22 …F
VDD_18 (1.8 V)
Battery backup
domain supply
10 µH
FB5
L6 10 µH
DCDC6
FB6
IN_BU
4.7 …F
CC
SYS_BU
1 …F
Always-on coin-cell battery backup supplies
IN_BIAS
BIAS
From 2.7-V to 6.5-V
system power
INT_LDO
100 nF
Figure 6-1. CC Input to Power Path
NOTE
In applications without backup battery, CC input must be tied to ground.
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Applications Without Battery Backup Supplies
In applications that do not require always-on supplies, both inputs and the output of the power-path can
simply be grounded. All pins related to DCDC5 and DCDC6 are also tied to ground, and PGOOD_BU and
IN_nCC are kept floating. With the backup supplies completely disabled, the FSEAL bit in the STATUS
register is undefined and should be ignored.
DCDC6 (1.8 V)
PGOOD_BU
L5
DCDC5_PG
DCDC6_PG
No connect
DCDC5
FB5
DCDC6 (1.8 V)
L6
IN_nCC
DCDC6
No connect
FB6
IN_BU
CC
SYS_BU
Always-on coin-cell battery backup supplies
Figure 6-2. DCDC5 and DCDC6 Pins
NOTE
In applications that do not require always-on supplies, PGOOD_BU and IN_nCC can be kept
floating. All other pins are tied to ground.
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Typical Application
System Power (5.5 V)
DCDC6
VDDSHVx
for GPIOx
VDDSHV3
Push
Button
nWAKEUP
PB
RTC_WAKEUP
nINT
GPIOx
PGOOD
Digital
AC_DET
PWRONRSTn
PWR_EN
RTC_PMIC_EN
SCL and SDA
I2C0_SCL/SDA
GPIO3
10
Coin
Cell
Battery Backup
Supplies
+
±
IN_BU
2.7-V to 5.5-V
system power
PGOOD_BU
CC
IN_LDO1
DCDC5
DCDC6
LDO1
IN_DCDC1
DCDC1 (buck)
IN_DCDC2
IN_DCDC3
IN_DCDC4
IN_BIAS
From DCDC3
IN_LS1
DCDC2 (buck)
DCDC3 (buck)
DCDC4 (buck-boost)
1.0 V (DCDC5)
CAP_VDD_RTC
1.8 V (DCDC6)
VDDS_RTC
1.8 V
1.8V Analog & I/O
0.95 / 1.1 V
VDD_CORE
0.95 / 1.1 / 1.2 / 1.26 /1.325 V
VDD_MPU
1.35 / 1.5 V
3.3 V
3.3V Analog & I/O
DDR_RESETn
BIAS
LS1
RTC_PWRONRSTn
IN_nCC
LS1
VDDS_DDR
TPS65218
DDR3/L Memory
(1)
Block diagram shows TPS65218D0 powering AM437x processor. For TPS6521825, refer to this Tech Note. For TPS6521815, the
wiring is not pre-defined and is programmed for the specific processor in the application.
Figure 6-3. Typical Application Schematic for TPS65218D0
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Design Requirements
Table 6-1 lists the design requirements.
Table 6-1. Design Parameters for TPS65218D0 (1)
(1)
6.2.2
VOLTAGE
SEQUENCE
DCDC1
1.1 V
8
DCDC2
1.1 V
9
DCDC3
1.2 V
5
DCDC4
3.3 V
7
DCDC5
1.0 V
2
DCDC6
1.8 V
1
LDO1
1.8 V
3
Default output voltages shown for TPS65218D0. For other
TPS65218xx variants, refer to DCDC1-4 and LDO1 registers in
Section 5.6.4.
Detailed Design Procedure
6.2.2.1
Output Filter Design
The step down converters (DCDC1, DCDC2, and DCDC3) on TPS6521815 are designed to operate with
effective inductance values in the range of 1 to 2.2 µH and with effective output capacitance in the range
of 10 to 100 µF. The internal compensation is optimized to operate with an output filter of L = 1.5 µH and
COUT = 10 µF.
The buck boost converter (DCDC4) on TPS6521815 is designed to operate with effective inductance
values in the range of 1.2 to 2.2 µH. The internal compensation is optimized to operate with an output filter
of L = 1.5 µH and COUT = 47 µF.
The two battery backup converters (DCDC5 and DCDC6) are designed to operate with effective
inductance values in the range of 4.7 to 22 µH. The internal compensation is optimized with an output filter
of L = 10 µH and COUT = 20 µF.
Larger or smaller inductor/capacitance values can be used to optimize performance of the device for
specific operation conditions.
6.2.2.2
Inductor Selection for Buck Converters
The inductor value affects its peak to peak ripple current, the PWM to PFM transition point, the output
voltage ripple, and the efficiency. The selected inductor must be rated for its DC resistance and saturation
current. The inductor ripple current (∆L) decreases with higher inductance and increases with higher VIN or
VOUT. Equation 1 calculates the maximum inductor current ripple under static load conditions. The
saturation current of the inductor should be rated higher than the maximum inductor current as calculated
with Equation 2. This is recommended as during heavy load transient the inductor current will rise above
the calculated value.
V
± OUT
VIN
'I L VOUT u
/u¦
(1)
I L max
I OUT max
'I L
2
where
•
•
F = Switching frequency
L = Inductor value
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•
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∆IL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(2)
The following inductors have been used with the TPS6521815 (see Table 6-2).
Table 6-2. List of Recommended Inductors
PART NUMBER
VALUE
SIZE (mm) [L × W × H]
MANUFACTURER
INDUCTORS FOR DCDC1, DCDC2, DCDC3, DCDC4
SPM3012T-1R5M
1.5 µH, 2.8 A, 77 mΩ
3.2 × 3.0 × 1.2
TDK
IHLP1212BZER1R5M11
1.5 µH, 4.0 A, 28.5 mΩ
3.6 × 3.0 × 2.0
Vishay
MLZ2012N100L
10 µH, 110 mA, 300 mΩ
2012 / 0805 (2.00 × 1.25 ×
1.25)
TDK
LQM21FN100M80
10 µH, 100 mA, 300 mΩ
2012 / 0805 (2.00 × 1.25 ×
1.25)
Murata
INDUCTORS FOR DCDC5, DCDC6
6.2.2.3
Output Capacitor Selection
The hysteretic PWM control scheme of the TPS6521815 switching converters allows the use of tiny
ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric.
At light load currents the converter operates in power save mode, and the output voltage ripple is
dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor
values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM mode.
The two battery backup converters (DCDC5 and DCDC6) always operate in PFM mode. For these
converters, a capacitor of at least 20 µF is recommended on the output to help minimize voltage ripple.
The buck-boost converter requires additional output capacitance to help maintain converter stability during
high load conditions. At least 40 µF of output capacitance is recommended and an additional 100-nF
capacitor can be added to further filter output ripple at higher frequencies.
Table 6-2 lists the recommended capacitors.
Table 6-3. List of Recommended Capacitors
PART NUMBER
VALUE
SIZE (mm) [L × W × H]
MANUFACTURER
CAPACITORS FOR VOLTAGES UP TO 5.5 V (1)
GRM188R60J105K
1 µF
1608 / 0603 (1.6 × 0.8 × 0.8)
Murata
GRM21BR60J475K
4.7 µF
2012 / 0805 (2.0 × 1.25 × 1.25)
Murata
GRM31MR60J106K
10 µF
3216 / 1206 (3.2 × 1.6 × 1.6)
Murata
GRM31CR60J226K
22 µF
3216 / 1206 (3.2 × 1.6 × 1.6)
Murata
GRM21BR60J106K
10 µF
2012 / 0805 (2.0 × 1.25 × 1.25)
Murata
GRM31CR60J476M
47 µF
3216 / 1206 (3.2 × 1.6 × 1.6)
Murata
CAPACITORS FOR VOLTAGES UP TO 3.3 V
(1)
96
(1)
The DC bias effect of ceramic capacitors must be considered when selecting a capacitor.
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Application Curves
at TJ = 25°C unless otherwise noted
100%
90
80
70
Efficiency (%)
Efficiency
80%
60%
40%
60
50
40
30
20%
20
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
10
0
0
0
400.001
800.001
1200.001
Output Current (mA)
0
1600.001
0.2
0.4
D007
0.6
0.8
1
1.2
Output Current (A)
VOUT = 1.1 V
1.4
1.6
1.8
VOUT = 1.2 V
Figure 6-4. DCDC1/DCDC2 Efficiency
Figure 6-5. DCDC3 Efficiency
90%
100%
80%
80%
70%
Efficiency
Efficiency
60%
50%
40%
60%
40%
30%
20%
20%
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
10%
0
VIN = 2.7 V
VIN = 3.6 V
VIN = 5 V
0
0
0.2
0.4
0.6
0.8
1
1.2
Output Current (A)
1.4
1.6
1.8
0
0.2
0.4
0.6
0.8
1
Output Current (A)
D009
VOUT = 1.5 V
1.2
1.4
1.6
D010
VOUT = 3.3 V
Figure 6-6. DCDC3 Efficiency
Figure 6-7. DCDC4 Efficiency
90%
85%
80%
Efficiency
75%
70%
65%
60%
55%
50%
DCDC5 (1 V)
DCDC6 (1.8 V)
45%
40%
0
IN_BU = 0 V
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Output Current (mA)
0.1
D011
CC = 3 V
Figure 6-8. DCDC5/DCDC6 Efficiency
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7 Power Supply Recommendations
The device is designed to operate with an input voltage supply range between 2.7 V and 5.5 V. This input
supply can be from a single cell Li-Ion battery or other externally regulated supply. If the input supply is
located more than a few inches from the TPS6521815 additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 47 µF is a typical
choice.
The coin cell back up input is designed to operate with a input voltage supply between 2.2 V and 3.3 V
This input should be supplied by a coin cell battery with 3-V nominal voltage.
8 Layout
8.1
Layout Guidelines
Follow these layout guidelines:
• The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.
• The optimum placement is closest to the IN_X pins of the device. Take care to minimize the loop area
formed by the bypass capacitor connection, the IN_X pin, and the thermal pad of the device.
• The thermal pad should be tied to the PCB ground plane with a minimum of 25 vias. See Figure 8-2 for
an example.
• The LX trace should be kept on the PCB top layer and free of any vias.
• The FBX traces should be routed away from any potential noise source to avoid coupling.
• DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive distance
between the capacitance and DCDC4 pin may cause poor converter performance.
8.2
Layout Example
VOUT
Output Filter
Capacitor
L1
Via to Ground Plane
Via to Internal Plane
FB1
Input Bypass
Capacitor
IN
Thermal
Pad
Figure 8-1. Layout Recommendation
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s
Recommended Thermal Pad by size
Hole size (s) = 8 mil
Diameter (d) = 16 mil
d
Figure 8-2. Thermal Pad Layout Recommendation
Layout
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9 Device and Documentation Support
9.1
9.1.1
Device Support
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.2
9.2.1
Documentation Support
Related Documentation
For related documentation see the following:
• Texas Instruments, Basic Calculation of a Buck Converter's Power Stage application report
• Texas Instruments, Design Calculations for Buck-Boost Converters application report
• Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor
Applications application report
• Texas Instruments, TPS65218EVM user's guide
• Texas Instruments, TPS65218 Power Management Integrated Circuit (PMIC) for Industrial Applications
application report
9.3
Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
9.4
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
9.5
Trademarks
Sitara, E2E are trademarks of Texas Instruments.
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9.6
SLDS261 – NOVEMBER 2019
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.7
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2019, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS6521815RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
T6521815
TPS6521815RSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
T6521815
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS6521815RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS6521815RSLT
VQFN
RSL
48
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS6521815RSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS6521815RSLT
VQFN
RSL
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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Copyright © 2019, Texas Instruments Incorporated
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