Texas Instruments | UCC21540, UCC21540A, UCC21541 Reinforced Isolation Dual-Channel Gate Driver With 3.3-mm Channel-to-Channel Spacing Option (Rev. C) | Datasheet | Texas Instruments UCC21540, UCC21540A, UCC21541 Reinforced Isolation Dual-Channel Gate Driver With 3.3-mm Channel-to-Channel Spacing Option (Rev. C) Datasheet

Texas Instruments UCC21540, UCC21540A, UCC21541 Reinforced Isolation Dual-Channel Gate Driver With 3.3-mm Channel-to-Channel Spacing Option (Rev. C) Datasheet
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UCC21540, UCC21540A, UCC21541
SLUSDE1C – NOVEMBER 2018 – REVISED SEPTEMBER 2019
UCC21540, UCC21540A, UCC21541 Reinforced Isolation Dual-Channel Gate Driver
With 3.3-mm Channel-to-Channel Spacing Option
1 Features
3 Description
•
The UCC2154x is an isolated dual channel gate
driver family designed with up to 4-A/6-A peak
source/sink current to drive power MOSFET, IGBT,
and GaN transistors. UCC21540 in DWK package
also offers 3.3-mm minimum channel-to-channel
spacing which facilitates higher bus voltage.
1
•
•
•
•
•
•
•
Wide body package options
– DW SOIC-16: pin-2-pin to UCC21520
– DWK SOIC-14: 3.3 mm Ch-2-Ch spacing
CMTI greater than 100 V/ns
Up to 4-A peak source and 6-A peak sink output
Up to 18-V VDD output drive supply
– 5-V and 8-V VDD UVLO Options
Switching parameters:
– 40-ns maximum propagation delay
– 5-ns maximum delay matching
– 5.5-ns maximum pulse-width distortion
– 35-µs maximum VDD power-up delay
Resistor-programmable dead time
TTL and CMOS compatible inputs
Safety-related certifications:
– 8000-VPK reinforced isolation per DIN V VDE V
0884-11:2017-01
– 5700-VRMS isolation for 1 minute per UL 1577
– CQC certification per GB4943.1-2011
(Planned)
The UCC2154x family can be configured as two lowside drivers, two high-side drivers, or a half-bridge
driver. The input side is isolated from the two output
drivers by a 5.7-kVRMS isolation barrier, with a
minimum of 100-V/ns common-mode transient
immunity (CMTI).
Protection features include: resistor programmable
dead time, disable feature to shut down both outputs
simultaneously, integrated de-glitch filter that rejects
input transients shorter than 5ns, and negative
voltage handling for up to –2V spikes for 200ns on
input and output pins. All supplies have UVLO
protection.
Device Information(1)
2 Applications
•
•
•
•
•
IPK
Rec. VDD
Supply
Min.
PACKAGE
UCC21540DW
4.0-A/6.0-A
9.2-V
SOIC (16)
UCC21540DWK
4.0-A/6.0-A
9.2-V
SOIC (14)
UCC21540ADWK
4.0-A/6.0-A
6.0-V
SOIC (14)
UCC21541DW
1.5-A/2.5-A
9.2-V
SOIC (16)
PART NUMBER
Isolated AC-to-DC and DC-to-DC power supplies
Server, telecom, IT and industrial infrastructures
Motor drives and solar inverters
HEV and EV battery chargers
Industrial transportation
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VDD
VCC
RBOOT
HV DC-Link
VCC
INB
VCCI
CIN
PC
CVCC
GND
I/O
DIS
DIS
RDIS
16
2
15
4
5
RON
OUTA
CIN
RGS
CBOOT
SW
Functional
Isolation
VDD
11
10
8
ROFF
14
CDIS
VCCI
VDDA
VSSA
3
Isolation Barrier
RIN
PWM-B
1
Input Logic
INA
PWM-A
VDDB
ROFF
RON
OUTB
VSSB
CVDD
RGS
9
VSS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
UCC21540, UCC21540A, UCC21541
SLUSDE1C – NOVEMBER 2018 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
2
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety-Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 16
8.1
8.2
8.3
8.4
8.5
Minimum Pulses......................................................
Propagation Delay and Pulse Width Distortion.......
Rising and Falling Time .........................................
Input and Disable Response Time..........................
Programmable Dead Time ......................................
16
16
16
17
17
8.6 Power-up UVLO Delay to OUTPUT........................ 18
8.7 CMTI Testing........................................................... 19
9
Detailed Description ............................................ 20
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
21
24
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Application ................................................ 26
11 Power Supply Recommendations ..................... 36
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Example .................................................... 38
13 Device and Documentation Support ................. 40
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
40
40
14 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2019) to Revision C
Page
•
Changed Features, Applications, and Description sections .................................................................................................. 1
•
Added initial release of the UCC21540A device. .................................................................................................................. 1
•
Added VDE and UL numbers in Safety-Related Certifications Table ................................................................................... 7
•
Added UCC21540A UVLO thresholds ................................................................................................................................... 8
Changes from Revision A (December 2018) to Revision B
•
Page
Added the initial release of the SOIC (14) orderable. ............................................................................................................ 1
Changes from Original (November 2018) to Revision A
•
Page
Changed marketing status from Advance Information to Initial release. ............................................................................... 1
5 Device Comparison Table
2
DEVICE OPTIONS
UVLO
PEAK CURRENT
PACKAGE
UCC21540DW
8.0-V
4-A Source, 6-A Sink
SOIC-16
UCC21540DWK
8.0-V
4-A Source, 6-A Sink
SOIC-14
UCC21540ADWK
5.0-V
4-A Source, 6-A Sink
SOIC-14
UCC21541DW
8.0-V
1.5-A Source, 2.5-A Sink
SOIC-16
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SLUSDE1C – NOVEMBER 2018 – REVISED SEPTEMBER 2019
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
DWK Package
14-Pin SOIC
Top View
16
VDDA
INA
1
16
VDDA
INB
2
15
OUTA
INB
2
15
OUTA
VCCI
3
14
VSSA
VCCI
3
14
VSSA
GND
4
13
NC
GND
4
DIS
5
12
NC
DIS
5
DT
6
11
VDDB
DT
6
11
VDDB
NC
7
10
OUTB
NC
7
10
OUTB
VCCI
8
9
VSSB
VCCI
8
9
VSSB
Not to scale
ISOLATION
1
ISOLATION
INA
Not to scale
Pin Functions
PIN
NAME
DIS
NO.
5
I/O
(1)
Description
I
Disables both driver outputs if asserted high, enables if set low. It is recommended to tie this pin to
ground if not used to achieve better noise immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close
to DIS pin when connecting to a µC with distance.
DT
6
I
DT pin configuration:
•
Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
•
Placing a resistor (RDT) between DT and GND adjusts dead time according to the equation: DT (in
ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a ceramic capacitor, 2.2 nF or
greater, close to DT pin to achieve better noise immunity.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
-
No internal connection.
For SOIC-14 DWK Package, pin 12 and pin 13 are removed.
7
NC
12
13
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close
to the device as possible.
VCCI
8
P
This pin is internally shorted to pin 3.
Preference should be given to bypassing pin 3-4 instead of pins 8-4.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located
as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located
as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P = power, I = input, O = output
Copyright © 2018–2019, Texas Instruments Incorporated
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.5
6
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.5
20
V
–0.5
VVDDA+0.5,
VVDDB+0.5
V
–2
VVDDA+0.5,
VVDDB+0.5
V
–0.5
VVCCI+0.5
V
–2
VVCCI+0.5
V
OUTA to VSSA, OUTB to VSSB
Output signal voltage
OUTA to VSSA, OUTB to VSSB, Transient for 200
ns
INA, INB, DIS and DT to GND
Input signal voltage
INA, INB Transient to GND for 200ns
Channel to channel isolation voltage
Junction temperature, TJ
|VSSA-VSSB| in DW Package
1500
|VSSA-VSSB| in DWK Package
1850
(2)
Storage temperature, Tstg
(1)
(2)
V
–40
150
°C
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3
5.5
UCC21540A – 5V UVLO Option
6.0
18
UCC21540, UCC21541 – 8V UVLO Option
9.2
18
Junction Temperature
–40
130
°C
Ambient Temperature
–40
125
°C
VCCI
VCCI Input supply voltage
VDDA,
VDDB
Driver output bias supply
TJ
TA
4
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UNIT
V
Copyright © 2018–2019, Texas Instruments Incorporated
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SLUSDE1C – NOVEMBER 2018 – REVISED SEPTEMBER 2019
7.4 Thermal Information
UCC21540,
UCC21541
THERMAL METRIC (1)
UNIT
DW/K (SOIC)
RθJA
Junction-to-ambient thermal resistance
69.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.1
°C/W
RθJB
Junction-to-board thermal resistance
29.0
°C/W
ψJT
Junction-to-top characterization parameter
20.0
°C/W
ψJB
Junction-to-board characterization parameter
28.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Power Ratings
PD
Power dissipation
PDI
Power dissipation by transmitter side
PDA, PDB
Power dissipation by each driver side
Copyright © 2018–2019, Texas Instruments Incorporated
VCCI = 5.5 V, VDDA/B = 12 V, INA/B = 3.3
V, 5.1 MHz 50% duty cycle square wave 1.0nF load
VALUE
UNIT
1775
mW
15
mW
880
mW
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7.6 Insulation Specifications
VALUE
UNIT
CLR
PARAMETER
External clearance (1)
Shortest pin-to-pin distance through air
TEST CONDITIONS
>8
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 8.5 µm)
>17
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage (3)
AC voltage (bipolar)
1414
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 1)
1000
VRMS
DC voltage
1414
VDC
VTEST = VIOTM, t = 60 s (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After I/O safety test subgroup 2/3.
Vini = VIOTM, tini = 60 s;
<5
Vpd(m) = 1.2 X VIORM = 1697 VPK, tm = 10 s
Method a, After environmental tests subgroup 1.
Vini = VIOTM, tini = 60 s;
Apparent charge (4)
qpd
<5
pC
Vpd(m) = 1.6 X VIORM = 2262 VPK, tm = 10 s
Method b1; At routine
preconditioning (type test)
test
(100%
production)
and
<5
Vini = 1.2 × VIOTM; tini = 1 s;
Vpd(m) = 1.875 * VIORM = 2651 VPK , tm = 1 s
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output (5)
VIO = 0.4 sin (2πft), f =1 MHz
1.2
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS =150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications..
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
CQC
Certified according to DIN V VDE V 088411:2017-01
Recognized under UL 1577 Component
Recognition Program
Certified according to GB 4943.1-2011
Reinforced Insulation Maximum Transient
Isolation Voltage, 8000 VPK;
Maximum Repetitive Peak Voltage, 1414
VPK;
Maximum Surge Isolation Voltage, 8000
VPK
Single protection, 5700 VRMS
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate
Certification number: 40040142
File number: E181974
Planned
7.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
Safety output supply
current
θJA = 69.7ºC/W, VVDDA/B = 12 V, TJ =
150°C, TA = 25°C
See Figure 2
PS
Safety supply power
θJA = 69.7ºC/W, VVCCI = 5.5 V, TJ = 150°C,
TA = 25°C
See Figure 3
TS
Safety temperature (1)
IS
(1)
SIDE
MIN
DRIVER A,
DRIVER B
TYP
MAX
73
INPUT
15
DRIVER A
880
DRIVER B
880
TOTAL
1775
150
UNIT
mA
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C unless
otherwise noted (1) (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA, IVDDB
VDDA and VDDB quiescent
current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI operating current
current per channel (f = 500-kHz,
50% duty cycle)
2.5
mA
IVDDA, IVDDB
VDDA and VDDB operating
current
current per channel (f = 500 kHz,
50% duty cycle), CL = 100 pF
2.5
mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON
UVLO Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
UVLO Falling threshold
2.35
2.5
2.65
V
VVCCI_HYS
UVLO Threshold hysteresis
0.2
V
UCC21540A VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (5-V UVLO)
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
5.0
5.5
5.9
V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
4.7
5.2
5.6
V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
0.3
V
UCC21540, UCC21541 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (8-V UVLO)
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
8
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
7.5
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
8.5
9
V
8
8.5
V
0.5
V
INA, INB AND DISABLE
VINAH, VINBH,
VDISH
Input high threshold voltage
1.6
1.8
2
V
VINAL, VINBL,
VDISL
Input low threshold voltage
0.8
1
1.25
V
VINA_HYS,
VINB_HYS,
VDIS_HYS
Input threshold hysteresis
0.8
V
OUTPUT
IOA+, IOB+
IOA-, IOB-
ROHA, ROHB
(1)
(2)
8
UCC21540, UCC21540A
Peak output source current
2
4
UCC21541
Peak output source current
1
1.5
3
6
1.5
2.5
UCC21540, UCC21540A
Peak output sink current
A
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
A
UCC21541
Peak output sink current
UCC21540, UCC21541
Output resistance at high state
IOUT = –10 mA, ROHA, ROHB do not
represent drive pull-up
performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
10
Ω
Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted).
Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C unless
otherwise noted(1)(2).
PARAMETER
TEST CONDITIONS
UCC21540 Output resistance at
low state
ROLA, ROLB
UCC21541 Output resistance at
low state
MAX
0.55
1.1
1.3
2.6
UNIT
Ω
VVDDA, VVDDB = 12 V, IOUT = –10
mA
Output voltage at high state
VOLA, VOLB
UCC21540 Output voltage at low
state
VVDDA, VVDDB = 12 V, IOUT = 10
UCC21541 Output voltage at low mA
state
Driver output (VOUTA, VOUTB)
active pull down
TYP
IOUT = 10 mA
VOHA, VOHB
VOAPDA, VOAPDB
MIN
11.9
11.95
V
5.5
11
13
26
1.75
2.1
mV
VVDDA and VVDDB unpowered,
IOUTA, IOUTB = 200 mA
V
DEAD TIME AND OVERLAP PROGRAMMING
DT pin tied to VCCI
Dead time, DT
Dead time matching, |DTAB-DTBA|
Overlap determined by INA, INB
-
RDT = 10 kΩ
80
100
120
RDT = 20 kΩ
160
200
240
RDT = 50 kΩ
400
500
600
RDT = 10 kΩ
-
0
10
RDT = 20 kΩ
-
0
20
RDT = 50 kΩ
-
0
65
ns
ns
7.10 Switching Characteristics
VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, load capacitance COUT = 0 pF, TA = –40°C to +125°C unless otherwise noted (1).
PARAMETER
tRISE
tFALL
TEST CONDITIONS
UCC21540 Output rise time, see
Figure 27
UCC21541 Output rise time, see
Figure 27
UCC21540 Output fall time, see
Figure 27
UCC21541 Output fall time, see
Figure 27
MIN
CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz
CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz
TYP
MAX
5
16
UNIT
8
20
6
12
9
15
10
20
ns
ns
ns
tPWmin
Minimum input pulse width that
passes to output,
see Figure 24 and Figure 25
Output does not change the state if
input signal less than tPWmin
tPDHL
Propagation delay at falling edge,
see Figure 26
INx high threshold, VINH, to 10% of
the output
28
40
ns
tPDLH
Propagation delay at rising edge,
see Figure 26
INx low threshold, VINL, to 90% of
the output
28
40
ns
UCC21540 Pulse width distortion
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB|
see Figure 26
5.5
ns
6.5
ns
5
ns
tPWD
tDM
(1)
UCC21541 Pulse width distortion
Propagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|,
see Figure 26
f = 250kHz
Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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Switching Characteristics (continued)
VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, load capacitance COUT = 0 pF, TA = –40°C to +125°C unless otherwise noted(1).
PARAMETER
tVCCI+ to
OUT
tVDD+ to
TEST CONDITIONS
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See Figure 30
MIN
TYP
MAX
40
59
23
35
UNIT
INA or INB tied to VCCI
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
INA or INB tied to VCCI
See Figure 31
|CMH|
High-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to VCCI;
VCM=1000 V;
100
|CML|
Low-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND;
VCM=1000 V;
100
µs
V/ns
7.11 Insulation Characteristics Curves
1.E+12
1.E+11
1.E+10
87.5%
1268 Yrs
676 Yrs
1.E+09
TDDB Line (< 1 ppm Fail Rate)
Time to Fail (sec)
1.E+08
VDE Safety Margin Zone
1.E+07
1.E+06
Operating Zone
1.E+05
1.E+04
1.E+03
20%
1.E+02
1.E+01
200
1200
2200
3200
4200
5200
6200
7200
Applied Voltage (VRMS)
Working Isolation Voltage = 1000 VRMS
TA upto 150 oC
Projected Insulation Lifetime = 676 Years
Applied Voltage Frequency = 60 Hz
Figure 1. Reinforced Isolation Capacitor Life Time Projection
10
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100
2000
IVDDA/B for VDD=12V
IVDDA/B for VDD=18V
80
Safety Limiting Power (mW)
Safety Limiting Current per Channel (mA)
Insulation Characteristics Curves (continued)
60
40
20
0
1600
1200
800
400
0
0
50
100
150
Ambient Temperature (°C)
200
UCC2
D001
0
50
100
150
Ambient Temperature (°C)
200
UCC2
D001
Current in Each Channel with Both Channels Running
Simultaneously
Figure 2. Thermal Derating Curve for Limiting Current Per
VDE
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Figure 3. Thermal Derating Curve for Limiting Power Per
VDE
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7.12 Typical Characteristics
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
2.68
1.6
VCCI Operating Current (mA)
VCCI = 3.3V
VCCI = 5.0V
Current (mA)
1.5
1.4
1.3
1.2
-40
-20
0
20
No Load
40
60
80
Temperature (°C)
100
120
2.64
2.6
2.56
2.52
2.48
2.44
2.4
-40
140
VCCI = 3.3V, fS=50kHz
VCCI = 3.3V, fS=1.0MHz
VCCI = 5.0V, fS=50kHz
VCCI = 5.0V, fS=1.0MHz
-20
0
20
D001
40
60
80
Temperature (°C)
Figure 4. VCCI Quiescent Current
D001
Figure 5. VCCI Operating Current - IVCCI
VDD = 12V
VDD = 18V
2.58
1.4
Current (mA)
VCCI Operating Current (mA)
140
1.6
VCCI = 3.3V
VCCI = 5.0V
2.56
2.54
1.2
1
2.52
2.5
0
100
200
300
400 500 600 700
Frequency (kHz)
800
0.8
-40
900 1000
-20
40
60
80
Temperature (°C)
100
120
140
D001
Figure 7. VDD Per Channel Quiescent Current (IVDDA, IVDDB)
3
3
2.8
VDD Operating Current (mA)
2.7
2.4
2.1
VDD = 12V, fS=50kHz
VDD = 12V, fS=1.0MHz
VDD = 15V, fS=50kHz
VDD = 15V, fS=1.0MHz
1.8
1.5
1.2
No Load
20
INA = INB = GND No Load
Figure 6. VCCI Operating Current vs. Frequency
0.9
-40
0
D001
Both ChA and ChB are switching at 50% duty cycle
VDD Operating Current (mA)
120
Both ChA and ChB are switching at 50% duty cycle
INA = INB = GND
2.6
2.6
2.4
2.2
2
1.8
1.6
1.4
VDD = 12V
VDD = 15V
1.2
1
-20
0
20
40
60
80
Temperature (°C)
100
120
140
At 50% duty cycle
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0
100
200
300
D001
Figure 8. VDD Per Channel Operating Current - IVDDA/B
12
100
400 500 600 700
Frequency (kHz)
800
900 1000
D001
INA and INB both switching No Load with 50% duty cycle
Figure 9. Per Channel Operating Current (IVDDA/B) vs.
Frequency
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
212
2.9
VVCCI_ON
VVCCI_OFF
208
UVLO Hysteresis (mV)
UVLO Thresholds (V)
2.8
2.7
2.6
2.5
2.4
-40
204
200
196
192
-20
0
20
40
60
80
Temperature (°C)
100
120
188
-40
140
-20
0
20
D001
Figure 10. VCCI UVLO Threshold Voltage
40
60
80
Temperature (°C)
100
120
140
D001
Figure 11. VCCI UVLO Threshold Hysteresis Voltage
540
9
VVDD_ON
VVDD_OFF
UVLO Hysteresis (mV)
UVLO Thresholds (V)
8.7
8.4
8.1
530
520
510
7.8
7.5
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
500
-40
140
Figure 12. VDD UVLO Threshold Voltage
20
40
60
80
Temperature (°C)
100
120
140
D001
Figure 13. VDD UVLO Threshold Hysteresis Voltage
IN/DIS Threshold Hysteresis (mV)
IN/DIS High
IN/DIS Low
IN/DIS Thresholds (V)
0
875
2.5
2
1.5
1
0.5
-40
-20
D001
-20
0
20
40
60
80
Temperature (°C)
100
120
140
825
800
775
750
-40
-20
0
20
D001
Figure 14. INA/INB/DIS High and Low Threshold Voltage
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850
40
60
80
Temperature (°C)
100
120
140
D001
Figure 15. INA/INB/DIS High and Low Threshold Hysteresis
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
3
37.5
Propagation Delay (ns)
35
Propagation Delay Matching (ns)
Rising Edge (tPDLH)
Falling Edge (tPDHL)
32.5
30
27.5
25
22.5
20
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
2
1
0
-1
-2
-40
140
-20
0
D001
Figure 16. Propagation Delay, Rising and Falling Edge
3
60
2
56
1
0
-1
20
40
60
80
Temperature (°C)
100
120
140
D001
Figure 17. Propagation Delay Matching, Rising and Falling
Edge
DIS Response Time (ns)
Pulse Width Distortion (ns)
Rising Edge
Falling Edge
-2
DIS Low to High
DIS High to Low
52
48
44
40
36
-3
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
32
-40
140
-20
0
20
D001
40
60
80
Temperature (°C)
100
120
140
D001
tPDLH – tPDHL
Figure 18. Pulse Width Distortion
Figure 19. DISABLE Response Time
10
VDD Open
VDD = 0V
1.5
1
0.5
0
-40
8
7
6
5
-20
0
20
40
60
80
Temperature (°C)
100
120
Figure 20. OUTPUT Active Pulldown Voltage
14
9
2
Minimum Input Pulse (ns)
Output Active Pull Down Voltage (V)
2.5
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140
4
-40
-20
0
20
D001
40
60
80
Temperature (°C)
100
120
140
D001
Figure 21. Minimum Pulse that Changes Output
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Typical Characteristics (continued)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
700
6
RDT = 10k:
RDT = 20k:
RDT = 50k:
Dead Time (ns)
500
400
300
200
100
0
-40
RDT = 10k:
RDT = 20k:
RDT = 50k:
5
Dead Time Matching (ns)
600
4
3
2
1
0
-1
-20
0
20
40
60
80
Temperature (°C)
100
120
Figure 22. Dead Time Temperature Drift
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140
D024
-2
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D025
Figure 23. Dead Time Matching
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8 Parameter Measurement Information
8.1 Minimum Pulses
A typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. An
input pulse with duration longer than tPWmin, typically 10 ns, must be asserted on INA or INB to guarantee an
output state change at OUTA or OUTB. See Figure 24 and Figure 25 for detailed information of the operation of
deglitch filter.
INx
VINH
VINL
VINL
VINH
INx
tPWM < tPWmin
tPWM < tPWmin
OUTx
OUTx
Figure 24. Deglitch Filter – Turn ON
Figure 25. Deglitch Filter – Turn OFF
8.2 Propagation Delay and Pulse Width Distortion
Figure 26 shows calculation of pulse width distortion (tPWD) and delay matching (tDM) from the propagation delays
of channels A and B. To measure delay matching, both inputs must be in phase, and the DT pin must be shorted
to VCCI to enable output overlap.
INA/B
tPDHLA
tPDLHA
tDM
OUTA
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB
Figure 26. Delay Matching and Pulse Width Distortion
8.3 Rising and Falling Time
Figure 27 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Output Stage.
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Rising and Falling Time (continued)
80%
tRISE
90%
tFALL
20%
10%
Figure 27. Rising and Falling Time Criteria
8.4 Input and Disable Response Time
Figure 28 shows the response time of the disable function. For more information, see Disable Pin.
INx
DIS High
Response Time
DIS
DIS Low
Response Time
OUTx
90%
90%
tPDLH
tPDHL
10%
10%
10%
Figure 28. Disable Pin Timing
8.5 Programmable Dead Time
Tying DT to VCCI disables DT feature and allows the outputs to overlap. Placing a resistor (RDT) between DT
and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing
this pin with a ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity. For more
details on dead time, refer to Programmable Dead Time (DT) Pin.
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Programmable Dead Time (continued)
INA
INB
90%
10%
OUTA
tPDHL
tPDLH
90%
10%
OUTB
tPDHL
Dead Time
(Set by RDT)
Dead Time
(Determined by Input signals if
longer than DT set by RDT)
Figure 29. Dead Time Switching Parameters
8.6 Power-up UVLO Delay to OUTPUT
Whenever the supply voltage VCCI crosses from below the falling threshold VVCCI_OFF to above the rising
threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold VVDDx_OFF to
above the rising threshold VVDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI
UVLO this delay is defined as tVCCI+ to OUT, and is typically 40 µs. For VDDx UVLO this delay is defined as tVDD+ to
OUT, and is typically 23 µs. TI recommends allowing some margin before driving input signals, to ensure the
driver VCCI and VDD bias supplies are fully activated. Figure 30 and Figure 31 show the power-up UVLO delay
timing diagram for VCCI and VDD.
Whenever the supply voltage VCCI crosses below the falling threshold VVCCI_OFF, or VDDx crosses below the
falling threshold VVDDx_OFF, the outputs stop responding to the inputs and are held low within 1 µs. This
asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.
When VCCI goes away but VDDx is present, outputs are held low; when VDDx is gone, outputs are CLAMPED
low through the active pull down feature. For more detailed UVLO feature description, please check session
VDD, VCCI, and Under Voltage Lock Out (UVLO).
VCCI,
INx
VDDx
VVCCI_ON
VVCCI_OFF
VDDx
tVCCI+ to OUT
OUTx
VVDD_ON
tVDD+ to OUT
VVDD_OFF
OUTx
Figure 30. VCCI Power-up UVLO Delay
18
VCCI,
INx
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Figure 31. VDDA/B Power-up UVLO Delay
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8.7 CMTI Testing
Figure 32 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VCC
VCCI
GND
DIS
GND
DT
VCCI
16
2
15
3
14
4
5
Isolation Barrier
INB
1
Input Logic
INA
VDDA
OUTA
OUTA
VSSA
Functional
Isolation
11
6
10
8
9
VDDB
OUTB
OUTB
VSSB
VSS
Common Mode Surge
Generator
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Figure 32. Simplified CMTI Testing Setup
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9 Detailed Description
9.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC2154x is a flexible dual gate driver which can be configured to fit a variety of power supply and motor
drive topologies, as well as drive several types of transistors. The UCC2154x has many features that allow it to
integrate well with control circuitry and protect the gates it drives such as: resistor-programmable dead time (DT)
control, disable pin, and under voltage lock out (UVLO) for both input and output supplies. The UCC2154x also
holds its outputs low when the inputs are left open or when the input pulse duration is too short. The driver inputs
are CMOS and TTL compatible for interfacing with digital and analog power controllers alike. Each channel is
controlled by its respective input pins (INA and INB), allowing full and independent control of each of the outputs.
9.2 Functional Block Diagram
INA
1
16 VDDA
200 k:
VCCI
3
GND
4
DT
6
DIS
5
UVLO
Deadtime
Control
Driver
DEMOD
UVLO
Isolation Barrier
MOD
VCCI
Deglitch
Filter
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
50 k:
MOD
INB
UVLO
2
NC
7
VCCI
8
Driver
DEMOD
Deglitch
Filter
10 OUTB
9
VSSB
200 k:
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9.3 Feature Description
9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC2154x has an internal under voltage lock out (UVLO) protection feature on each supply voltage
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the channel output low, regardless of
the status of the input pins.
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (illustrated in Figure 33). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.75V, regardless of whether bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
Figure 33. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which
commonly occurs when the device starts switching and operating current consumption increases suddenly.
The inputs of the UCC2154x also has an internal under voltage lock out (UVLO) protection feature. The inputs
cannot affect the outputs unless the supply voltage VCCI exceeds VVCCI_ON on start-up. The outputs are held low
and cannot respond to inputs when the supply voltage VCCI drops below VVCCI_OFF after start-up. Like the UVLO
for VDD, there is hystersis (VVCCI_HYS) to ensure stable operation.
Table 1. VCCI UVLO Feature Logic (1)
CONDITION
(1)
INPUTS
OUTPUTS
INA
INB
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
H
L
L
L
VCCI-GND < VVCCI_ON during device start up
L
H
L
L
VCCI-GND < VVCCI_ON during device start up
H
H
L
L
VCCI-GND < VVCCI_ON during device start up
L
L
L
L
VCCI-GND < VVCCI_OFF after device start up
H
L
L
L
VCCI-GND < VVCCI_OFF after device start up
L
H
L
L
VCCI-GND < VVCCI_OFF after device start up
H
H
L
L
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
VDDx > VDD_ON.
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Table 2. VDD UVLO Feature Logic (1)
CONDITION
INPUTS
INA
(1)
OUTPUTS
INB
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
H
L
L
L
VDD-VSS < VVDD_ON during device start up
L
H
L
L
VDD-VSS < VVDD_ON during device start up
H
H
L
L
VDD-VSS < VVDD_ON during device start up
L
L
L
L
VDD-VSS < VVDD_OFF after device start up
H
L
L
L
VDD-VSS < VVDD_OFF after device start up
L
H
L
L
VDD-VSS < VVDD_OFF after device start up
H
H
L
L
VDD-VSS < VVDD_OFF after device start up
L
L
L
L
VCCI > VCCI_ON.
9.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up (see VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes). Table 3 shows the operation with INA, INB and DIS and the corresponding output state.
Table 3. INPUT/OUTPUT Logic Table (1) (2)
INPUTS
INA
INB
OUTPUTS
DIS
OUTA
NOTE
OUTB
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
H
L
L
L
DT is programmed with RDT.
H
H
L
H
H
DT pin pulled high to VCCI.
Left Open
Left Open
L
L
L
X
X
H
L
L
(1)
(2)
If the dead time function is used, output transitions occur after the dead
time expires. See Programmable Dead Time (DT) Pin.
Bypass using a ≥1-nF low ESR/ESL capacitor close to DIS pin when
connecting to a micro-controller with distance.
"X" means L, H or left open.
For improved noise immunity, TI recommends connecting INA, INB, and DIS to GND, and DT to VCCI, when these pins are not used.
9.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC2154x is based on a TTL and CMOS compatible input-threshold
logic that is totally isolated from the VDD supply voltage of the output channels. The input pins are easy to drive
with logic-level control signals (such as those from 3.3-V microcontrollers), since the UCC2154x has a typical
high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see
Figure 14 and Figure 15). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable
operation. If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors
are typically 200 kΩ for INA/B and 50 kΩ for DIS (see Functional Block Diagram). TI recommends grounding any
unused inputs.
The amplitude of any signal applied to the inputs should not exceed the voltage at the VCCI pin. The UCC2154x
cannot be driven from an analog controller with an output voltage greater than the VCCI voltage.
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9.3.4 Output Stage
The UCC2154x output stage features a pull-up structure which delivers the highest peak-source current when it
is most needed: during the Miller plateau region of the power-switch turn on transition (when the power switch
drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET
and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a
boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the Nchannel MOSFET during a narrow instant when the output is changing states from low to high. The on-resistance
of this N-channel MOSFET (RNMOS) for UCC21540 is approximately 1.47-Ω when activated, and RNMOS is
approximately 3.2-Ω for UCC21541.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the pull-up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC2154x pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter.
The pull-down structure of the UCC2154x is composed of an N-channel MOSFET. The ROL parameter, which is
also a DC measurement, is representative of the impedance of the pull-down state in the device. The output
voltage swings between VDD and VSS for rail-to-rail operation.
VDD
ROH
Input
Signal
ShootThrough
Prevention
Circuitry
RNMOS
OUT
Pull Up
ROL
VSS
Figure 34. Output Stage
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9.3.5 Diode Structure in the UCC2154x
Figure 35 illustrates the multiple diodes involved in the ESD protection components. This provides a pictorial
representation of the absolute maximum rating for the device.
VCCI
VDDA
3,8
16
20 V
6V
15 OUTA
6V
14 VSSA
INA
1
INB
2
DIS
5
DT
6
11 VDDB
20 V
10 OUTB
4
9
GND
VSSB
Figure 35. ESD Structure
9.4 Device Functional Modes
9.4.1 Disable Pin
When the DIS pin is set high, both outputs are shut down simultaneously. When the DIS pin is set low, the
UCC2154x operates normally. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting
to a micro-controller with distance. The DIS circuit logic structure is similar compared to INA or INB, and the
propagation delay typical performance can be found in Figure 19. The DIS pin is only functional (and necessary)
when VCCI stays above the UVLO threshold. It is recommended to tie this pin to GND if the DIS pin is not used
to achieve better noise immunity.
9.4.2 Programmable Dead Time (DT) Pin
The UCC2154x allows the user to adjust dead time (DT) in the following ways:
9.4.2.1 DT Pin Tied to VCCI
Outputs completely match inputs, so no minimum dead time is asserted. This allows the outputs to overlap. TI
recommends connecting this pin directly to VCCI if it is not used to achieve better noise immunity.
9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
Program tDT by placing a resistor, RDT, between the DT pin and GND. TI recommends bypassing this pin with a
ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity. The appropriate RDT value
can be determined from:
tDT | 10 u RDT
where
•
•
24
tDT is the programmed dead time, in nanoseconds.
RDT is the value of resistance between DT pin and GND, in kilo-ohms.
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Device Functional Modes (continued)
The steady state voltage at the DT pin is about 0.8 V. RDT programs a small current at this pin, which sets the
dead time. As the value of RDT increases, the current sourced by the DT pin decreases. The DT pin current will
be less than 10 µA when RDT = 100 kΩ. For larger values of RDT, TI recommends placing RDT and a ceramic
capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better
dead time matching between both channels.
The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed
dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may
also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a
dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs
will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does
not affect the programmed dead time setting for normal operation. Various driver dead time logic operating
conditions are illustrated and explained in Figure 36.
INA
INB
DT
OUTA
OUTB
A
B
C
D
E
F
Figure 36. Input and Output Logic Relationship with Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal dead time is longer than the programmed dead time. When INA
goes high after the duration of the input signal dead time, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. In this case, the input signal dead time is longer than the programmed dead time. When INB goes
high after the duration of the input signal dead time, it immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, OUTB is immediately pulled
low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low.
After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, OUTA is immediately pulled
low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low.
After the programmed dead time, OUTB is allowed to go high.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCC2154x effectively combines both isolation and buffer-drive functions. The flexible, universal capability of
the UCC2154x (with up to 5.5-V VCCI and 18-V VDDA/VDDB) allows the device to be used as a low-side, highside, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or GaN transistor. With integrated
components, advanced protection features (UVLO, dead time, and disable) and optimized switching
performance, the UCC2154x enables designers to build smaller, more robust designs for enterprise, telecom,
automotive, and industrial applications with a faster time to market.
10.2 Typical Application
The circuit in Figure 37 shows a reference design with the UCC2154x driving a typical half-bridge configuration
which could be used in several popular power converter topologies such as synchronous buck, synchronous
boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VCC
VDD
RBOOT
HV DC-Link
VCC
RIN
INB
PWM-B
CIN
PC
VCCI
CVCC
GND
I/O
DIS
DIS
RDIS
16
2
15
3
14
4
5
6
CDT
VCCI
VDDA
ROFF
RON
OUTA
VSSA
8
CIN
RGS
CBOOT
SW
Functional
Isolation
VDD
11
DT
CDIS
RDT
1
Isolation Barrier
PWM-A
Input Logic
INA
10
VDDB
ROFF
RON
OUTB
VSSB
CBOOT
RGS
9
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Figure 37. Typical Application Schematic
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Typical Application (continued)
10.2.1 Design Requirements
Table 4 lists reference design parameters for the example application: UCC2154x driving 650-V MOSFETs in a
high side-low side configuration.
Table 4. UCC2154x Design Requirements
PARAMETER
VALUE
UNITS
Power transistor
650-V, 150-mΩ RDS_ON with 12-V VGS
-
VCC
5.0
V
VDD
12
V
Input signal amplitude
3.3
V
Switching frequency (fs)
100
kHz
Dead Time
200
ns
DC link voltage
400
V
10.2.2 Detailed Design Procedure
10.2.2.1 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to 100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
10.2.2.2 Select Dead Time Resistor and Capacitor
From Equation 1, a 20-kΩ resistor is selected to set the dead time to 200 ns. A 2.2-nF capacitor is placed in
parallel close to the DT pin to improve noise immunity.
10.2.2.3 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
When selecting external bootstrap diodes, TI recommends choosing high voltage, fast recovery diodes or SiC
Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 400
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.7 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
IDBoot
pk
VDD VBDF
RBoot
12V 1.5V
| 4A
2.7:
where
•
VBDF is the estimated bootstrap diode forward voltage drop around 4 A.
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10.2.2.4 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
• Limit ringing caused by parasitic inductances/capacitances.
• Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
• Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
• Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC2154x has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
IOA
IOB
§
VDD VBDF
min ¨ 4A,
¨
RNMOS || ROH RON RGFET _ Int
©
·
¸
¸
¹
§
VDD
min ¨ 4A,
¨
RNMOS || ROH RON RGFET _ Int
©
·
¸
¸
¹
(3)
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(4)
In this example:
IOA
IOB
VDD VBDF
RNMOS || ROH RON RGFET _ Int
12V 0.8V
| 2.3A
1.47: || 5: 2.2: 1.5:
VDD
RON RGFET _ Int
12V
| 2.5A
1.47: || 5: 2.2: 1.5:
RNMOS || ROH
(5)
(6)
Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
IOA
IOB
§
VDD VBDF VGDF
min ¨ 6A,
¨
ROL ROFF || RON RGFET _ Int
©
·
¸
¸
¹
§
min ¨ 6A,
¨
ROL
©
·
¸
¸
¹
VDD VGDF
ROFF || RON RGFET _ Int
(7)
where
•
•
•
28
ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(8)
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In this example,
VDD VBDF VGDF
ROL ROFF || RON RGFET _ Int
IOA
IOB
ROL
VDD VGDF
ROFF || RON RGFET _ Int
12V 0.8V 0.85V
| 5.0A
0.55: 0: 1.5:
(9)
12V 0.85V
| 5.4A
0.55: 0: 1.5:
(10)
Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
10.2.2.5 Estimating Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC2154x (PGD) and the power
losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in
PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC2154x , and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 6 and Figure 9 show the operating current consumption vs. operating frequency
with no load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore,
the PGDQ can be calculated with
PGDQ
VVCCI u IVCCI
VVDDA u IDDA
VVDDB u IDDB
50mW
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW
2 u VDD u QG u fSW
where
•
QG is the gate charge of the power transistor.
(12)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW
2 u 12V u 100nC u 100kHz
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240mW
(13)
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QG represents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet,
and is subject to change with different testing conditions. The UCC2154x gate driver loss on the output stage,
PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate
driver loss is dissipated inside the UCC2154x . If there are external turn-on and turn-off resistances, the total loss
will be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly,
the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,
however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two
scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
PGSW §
ROH || RNMOS
u¨
¨ ROH || RNMOS RON RGFET _ Int
2
©
PGDO
ROL
ROL
ROFF || RON RGFET _ Int
·
¸
¸
¹
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC2154x
gate driver loss can be estimated with:
240mW §
5: || 1.47:
u¨
2
© 5: || 1.47: 2.2: 1.5:
PGDO
·
0.55:
¸ | 60mW
0.55: 0: 1.5: ¹
(15)
Case 2 - Nonlinear Pull-Up/Down Resistor:
2 u fSW
PGDO
TR _ Sys
ª
«
u 4A u
VDD
«
0
¬«
³
TF _ Sys
VOUTA /B t dt 6A u
³
0
º
VOUTA /B t dt »
»
»¼
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pulldown based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC2154x
PGD, is:
PGD
PGDQ
PGDO
(17)
which is equal to 127 mW in the design example.
10.2.2.6 Estimating Junction Temperature
The junction temperature of the UCC21540UCC2154x can be estimated with:
TJ
TC
< JT u PGD
where
•
•
•
TJ is the junction temperature.
TC is the UCC2154x case-top temperature measured with a thermocouple or some other instrument.
ψJT is the junction-to-top characterization parameter from the Thermal Information table.
(18)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
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estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor
and IC Package Thermal Metrics application report.
10.2.2.7 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. TI recommends
choosing low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with sufficient voltage
ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC will impact the
actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500 nF when a DC
bias of 15 VDC is applied.
10.2.2.7.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 4-A, the source peak current, and needs to maintain a stable gate drive
voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
QTotal
QG
IVDD @100kHz No Load
fSW
100nC
1.5mA
100kHz
115nC
where
•
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
(19)
Therefore, the absolute minimum CBoot requirement is:
QTotal
'VVDDA
CBoot
115nC
0.5V
230nF
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
(20)
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a margin in the CBoot value and place it as close to the VDD and VSS
pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot =1 F
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
NOTE
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
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10.2.2.7.3 Select a VDDB Capacitor
Channel B has the same current requirements as channel A, therefore, a VDDB capacitor (shown as CVDD in
Figure 37) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor
with a value over 10 µF, should be used in parallel with CVDD.
10.2.2.8 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 38 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 17 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 17 V – 5.1 V ≈ 12 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
16
1
15
2
VDDA
ROFF
CA1
RZ
OUTA
+
VA
±
RON
CIN
CA2
4
5
Input Logic
3
Isolation Barrier
VSSA
VZ
14
SW
Functional
Isolation
11
6
10
VDDB
OUTB
VSSB
8
Copyright © 2018, Texas Instruments Incorporated
9
Figure 38. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
32
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Figure 39 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
16
1
15
2
VDDA
CA1
OUTA
CA2
4
5
Input Logic
3
Isolation Barrier
VSSA
14
HV DC-Link
ROFF
+
VA+
±
RON
CIN
+
VA±
SW
Functional
Isolation
11
6
10
8
9
VDDB
OUTB
VSSB
Copyright © 2018, Texas Instruments Incorporated
Figure 39. Negative Bias with Two Iso-Bias Power Supplies
Copyright © 2018–2019, Texas Instruments Incorporated
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The last example, shown in Figure 40, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and
the bootstrap power supply can be used for the high side drive. This design requires the least cost and design
effort among the three solutions. However, this solution has limitations:
1.
The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias
voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency
resonant convertors or phase shift convertors will favor this solution.
2.
The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side
switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to
refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply
for the high side, like in the other two example circuits.
VDD
RBOOT
HV DC-Link
1
16
2
15
VDDA
ROFF
RON
CBOOT
CIN
RGS
Input Logic
Isolation Barrier
14
3
5
VZ
OUTA
VSSA
4
CZ
SW
Functional
Isolation
VDD
11
6
10
VDDB
CZ
VZ
OUTB
CVDD
VSSB
8
ROFF
RON
RGS
9
VSS
Copyright © 2018, Texas Instruments Incorporated
Figure 40. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
34
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10.2.3 Application Curves
Figure 41 and Figure 42 shows the bench test waveforms for the design example shown in Figure 37 under
these conditions: VCC = 5.0 V, VDD = 12 V, fSW = 100 kHz, VDC-Link = 400 V.
Channel 1 (Blue): Gate-source signal on the high side power transistor.
Channel 2 (Cyan): Gate-source signal on the low side power transistor.
Channel 3 (Pink): INA pin signal.
Channel 4 (Green): INB pin signal.
In Figure 41, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on
the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement
section of Figure 41. Note that with high voltage present, lower bandwidth differential probes are required, which
limits the achievable accuracy of the measurement.
Figure 42 shows a zoomed-in version of the waveform of Figure 41, with measurements for propagation delay
and dead time. Importantly, the output waveform is measured between the power transistors’ gate and source
pins, and is not measured directly from the driver OUTA and OUTB pins.
Figure 41. Bench Test Waveform for INA/B and OUTA/B
Copyright © 2018–2019, Texas Instruments Incorporated
Figure 42. Zoomed-In bench-test waveform
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11 Power Supply Recommendations
The recommended input supply voltage (VCCI) for the UCC2154x is between 3 V and 5.5 V. The output bias
supply voltage (VDDA/VDDB) ranges from 9.2 V to 18 V. The lower end of this bias supply range is governed by
the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below
their respective UVLO thresholds during normal operation. (For more information on UVLO see VDD, VCCI, and
Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate
voltage of the power device being driven by the UCC2154x . The recommended maximum VDDA/VDDB is 18 V.
A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output
goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to
minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass
capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC
pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can
be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary
bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 pF.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of the UCC2154x , this bypass capacitor has a minimum
recommended value of 100 nF.
36
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12 Layout
12.1 Layout Guidelines
Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC2154x .
12.1.1 Component Placement Considerations
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• To improve noise immunity when driving the DIS pin from a distant micro-controller or high impedance
source, TI recommends adding a small bypass capacitor, ≥ 1000 pF, between the DIS pin and GND.
• If the dead time feature is used, TI recommends placing the programming resistor RDT and bypassing
capacitor close to the DT pin of the UCC2154x to prevent noise from unintentionally coupling to the internal
dead time circuit. The capacitor should be ≥ 2.2 nF.
12.1.2 Grounding Considerations
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical loop area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
12.1.3 High-Voltage Considerations
• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may
compromise the isolation performance.
• For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout
between the high and low-side PCB traces. UCC21540DWK package has pin12 and pin13 removed and has
a minimum 3.3mm creepage distance which allows higher bus voltage.
12.1.4 Thermal Considerations
• A large amount of power may be dissipated by the UCC2154x if the driving voltage is high, the load is heavy,
or the switching frequency is high (refer to Estimating Gate Driver Power Loss for more details). Proper PCB
layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance
(θJB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 44 and Figure 45). However, high voltage PCB
considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces
or copper from different high-voltage planes overlap.
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12.2 Layout Example
Figure 43 shows a 2-layer PCB layout example with the signals and key components labeled for SOIC-16 DW
package. SOIC-14 DW package has Pin 12 and Pin 13 removed. For more detailed information, please refer to
the UCC21540EVM design - "Using the UCC21540EVM - TI"
Figure 43. Layout Example
Figure 44 and Figure 45 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 44. Top Layer Traces and Copper
38
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Figure 45. Bottom Layer Traces and Copper (Flipped)
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21540 UCC21540A UCC21541
UCC21540, UCC21540A, UCC21541
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SLUSDE1C – NOVEMBER 2018 – REVISED SEPTEMBER 2019
Layout Example (continued)
Figure 46 and Figure 47 are 3-D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
Figure 46. 3-D PCB Top View
Copyright © 2018–2019, Texas Instruments Incorporated
Figure 47. 3-D PCB Bottom View
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC21540
Click here
Click here
Click here
Click here
Click here
UCC21541
Click here
Click here
Click here
Click here
Click here
13.5 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC21540ADWK
ACTIVE
SOIC
DWK
14
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540A
UCC21540ADWKR
ACTIVE
SOIC
DWK
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540A
UCC21540DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540
UCC21540DWK
ACTIVE
SOIC
DWK
14
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540
UCC21540DWKR
ACTIVE
SOIC
DWK
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540
UCC21540DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21540
UCC21541DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21541
UCC21541DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
UCC21541
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC21540ADWKR
SOIC
DWK
14
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
UCC21540DWKR
SOIC
DWK
14
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
UCC21540DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
UCC21541DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC21540ADWKR
SOIC
DWK
14
2000
350.0
350.0
43.0
UCC21540DWKR
SOIC
DWK
14
2000
350.0
350.0
43.0
UCC21540DWR
SOIC
DW
16
2000
350.0
350.0
43.0
UCC21541DWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DWK0014A
SOIC - 2.65 mm max height
SCALE 1.500
SMALL OUTLINE INTEGRATED CIRCUIT
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
11X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
B
7.6
7.4
NOTE 4
14X 0.51
0.31
0.25
C A
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4224374/A 06/2018
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DWK0014A
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
14X (2)
SYMM
14X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
14X (0.6)
14X (0.6)
SYMM
SYMM
11X (1.27)
11X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224374/A 06/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWK0014A
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
SYMM
14X (1.65)
14X (2)
1
1
16
16
14X (0.6)
14X (0.6)
SYMM
SYMM
11X (1.27)
11X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4224374/A 06/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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