Texas Instruments | TPS56C230 4.5-V to 18-V, 12-A Synchronous Step-Down Converter (Rev. A) | Datasheet | Texas Instruments TPS56C230 4.5-V to 18-V, 12-A Synchronous Step-Down Converter (Rev. A) Datasheet

Texas Instruments TPS56C230 4.5-V to 18-V, 12-A Synchronous Step-Down Converter (Rev. A) Datasheet
Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
TPS56C230 4.5-V to 18-V, 12-A Synchronous Step-Down Converter
1 Features
3 Description
•
•
•
•
The TPS56C230 is a high efficiency synchronous
buck converter with integrated FETs. System
designers can use the device in a wide variety of
applications since it draws low standby current and
requires few external components.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Input voltage range: 4.5 V to 18 V
Output voltage range: 0.6 V to 5.5 V
Supports 12-A continuous output current
D-CAP3™ architecture control for fast transient
response
±1% feedback voltage accuracy (25°C)
Integrated 17-mΩ and 5.9-mΩ FETs
Selectable Eco-mode™ and Forced Continuous
Conductive Mode (FCCM) by MODE pin
500-kHz switching frequency
Adjustable soft-start time with default 1.2 ms
Integrated Power Good indicator
Built-in output discharge function
Cycle-by-cycle over current protection
Non-latched over-voltage, under-voltage, overtemperature and under voltage lock-out
protections
-40°C to 125°C Operating Junction Temperature
20-pin 3.0-mm × 3.0-mm HotRod™ VQFN
package
Pin to pin compatible with 8-A TPS568230
Create a Custom Design Using the TPS56C230
With the WEBENCH® Power Designer
The TPS56C230 employs D-CAP3 control that
provides fast transient response and excellent line
and load regulation with internal compensation. It also
has a proprietary circuit that enables the device to
support low equivalent series resistance (ESR) output
capacitors such as specialty polymer and ultra-low
ESR ceramic capacitors.
TPS56C230‘s MODE pin can be used to set Ecomode or FCCM mode for light-load operation. Ecomode maintains high efficiency during light load
operation, and FCCM mode operations keeps output
ripple small at light load. The device supports both
internal and external soft-start time option. It has an
internal fixed soft-start time 1.2 ms, but if the
application needs a longer soft-start time, the external
SS pin can be used to achieve it by connecting a
external capacitor.
The TPS56C230 integrates power good indicator and
provides output discharge function. It provides
complete protection including OVP, UVP, OCP, OTP
and UVLO. The device is available in a 20-pin 3.0mm x 3.0-mm HotRod package and the junction
temperature is specified from –40°C to 125°C.
2 Applications
•
•
•
•
Device Information(1)
DTV and Set-top box
PC and Industrial PC
Wired networking
Distributed power systems
PART NUMBER
TPS56C230
Efficiency vs Output Current Eco-mode
L
100
VIN
VOUT
VCC
90
TPS56C230
EN
BST
CBST
COUT
R1
MODE
FB
PGOOD
R2
PGOOD
SS
VCC
AGND
PGND
85
Efficiency (%)
CIN
95
SW
VIN
RM_L
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
RM_H
PACKAGE
VQFN (20)
80
75
70
65
Css
60
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
55
50
0.01
0.1
1
I-Load (A)
10 15
D013
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2019) to Revision A
•
2
Page
Changed marketing status from Advance Information to production data.. .......................................................................... 1
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
5 Pin Configuration and Functions
RJE Package
20-Pin VQFN
Top View
PGND
VCC
NC
20
19
7
18
176
16
3
SW
4
SW
15
6
6
1
BST
FB
13
AGND
7
4
3
7
VIN
14
4
3
2
3
VIN
MODE
PGND
VIN
4
12
EN
VIN
5
11
SS
7
SW
PGND
6
9
3
7
8
4
6
10
PGND PGOOD
NC
Pin Functions
PIN
I/O
DESCRIPTION
1
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 uF is recommended.
VIN
2,3,4,5
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
SW
6,19,20
O
Switching node connection to the inductor and bootstrap capacitor for buck. This pin voltage swings from a
diode voltage below the ground up to input voltage of buck.
PGND
7,8,18,Pad
G
Power GND terminal for the controller circuit and the internal circuitry.
PGOOD
9
O
Open drain power good indicator. It is asserted low if output voltage is out of PG threshold, over voltage or
if the device is under thermal shutdown, EN shutdown or during soft start.
SS
11
I
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.2ms.
NC
10,16
EN
12
I
Enable input of buck converter
AGND
13
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB
14
I
Feedback sensing pin for Buck output voltage. Connect this pin to the resistor divider between output
voltage and AGND.
MODE
15
I
Light load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND for
different MODE options shown in Table 1
VCC
17
O
The driver and control circuits are powered from this voltage. Decouple with a minimum 1 μF ceramic
capacitor as close to VCC as possible.
NAME
NO.
BST
Not connect. Can be connected to GND plane for better thermal achieved.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
3
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
(1)
MIN
MAX
UNIT
VIN
–0.3
20
V
BST
–0.3
25
V
BST-SW
–0.3
6
V
EN, MODE, FB, SS
–0.3
6
V
PGND, AGND,
–0.3
0.3
V
SW
–1
20
V
SW (10-ns transient)
–3
22
V
–0.3
6
V
TJ
Operating junction temperature
PGOOD
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Electrostatic
discharge
V(ESD)
(1)
(2)
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22- V C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
MAX
VIN
4.5
18
V
BST
–0.3
23.5
V
BST-SW
–0.3
5.5
V
EN, MODE, FB, SS
–0.3
5.5
V
PGND, AGND
–0.3
0.3
V
–1
18
V
–0.3
5.5
V
SW
Output voltage
PGOOD
IOUT
Output current
TJ
Operating junction temperature
–40
UNIT
12
A
125
°C
6.4 Thermal Information
TPS56C230
THERMAL METRIC (1)
RJE (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance (standard board)
42.3
°C/W
RθJA_effective
Junction-to-ambient thermal resistance (4-layer custom board) (2)
28.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.2
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
70 mm x 70 mm, 4 layers, thickness: 1.5 mm. 2 oz. copper traces located on the top and bottom of the PCB. 4 thermal vias in the
PowerPAD area under the device package.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
Thermal Information (continued)
TPS56C230
THERMAL METRIC (1)
RJE (VQFN)
UNIT
20 PINS
ψJB
Junction-to-board characterization parameter
12.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.1
°C/W
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
IVIN
Non-switching supply current
No load, VEN=5V
4.5
400
18
μA
V
IVINSDN
Shutdown supply current
No load, VEN=0V
2
μA
VCC OUTPUT
VCC
VCC output voltage
ICC
VCC current limit
VVIN>5.0V
4.85
VVIN=4.5V
5
5.15
V
4.5
20
mA
FEEDBACK VOLTAGE
VFB
FB voltage
TJ = 25°C
594
600
606
mV
TJ = -40°C to 125°C
591
600
609
mV
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
TJ = 25°C
500
tON(MIN)
SW minumum on time
TJ = 25°C
60
tOFF(MIN)
SW minimum off time
TJ = 25°C, VFB = 0.5 V
kHz
ns
180
ns
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
17
mΩ
RDS(ON)L
Low side switch resistance
TJ = 25°C
5.9
mΩ
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
TJ=25°C, VEN=0V
350
Ω
tSS
Soft start time
Internal soft-start time,SS floating
1.2
ms
ISS
Soft start charge current
5
μA
PGOOD from low to high
1
ms
VFB falling (fault)
85
%
VFB rising (good)
90
%
VFB rising (fault)
115
%
VFB falling (good)
110
POWER GOOD
tPGDLY
VPGTH
PGOOD start-up delay
PGOOD threshold
VPG_L
PGOOD sink current capability
IOL =4mA
IPGLK
PGOOD leak current
VPGOOD =5.5V
%
0.4
V
1
μA
CURRENT LIMIT
IOCL
Over current threshold (valley)
INOCL
Negative over current threshold
TJ = 25°C
14
15
16
A
TJ = -40°C to 125°C
13
15
17.5
A
4
A
LOGIC THRESHOLD
VENH
EN high-level input voltage
VENL
EN low-level input voltage
IEN
Enable internal pull down current
VEN=0.8V
1.2
1.3
1.4
0.9
1.1
1.2
2
V
V
µA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
5
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
Electrical Characteristics (continued)
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VOVP
OVP trip threshold
125
%
tOVPDLY
OVP prop deglitch
120
us
VUVP
UVP trip threshold
60
%
tUVPDLY
UVP prop deglitch
256
us
tUVPDEL
Output Hiccup delay relative to SS time
1.5
cycle
tUVPEN
Output Hiccup enable delay relative to SS
time
10.5
cycle
UVLO
Wake up VIN voltage
VUVLOVIN
VIN UVLO threshold
Shutdown VIN voltage
4.2
3.6
4.4
V
3.7
Hysteresis VIN voltage
0.5
V
OVER TEMPERATURE PROTECTION
TOTP
OTP trip threshold (1)
Shutdown temperature
150
°C
TOTPHSY
OTP hysteresis (1)
Hysteresis
20
°C
(1)
6
Not production tested
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
480
3
460
2.8
Shutdown Current (PA)
Supply Current (PA)
6.6 Typical Characteristics
440
420
400
380
2.6
2.4
2.2
2
360
-50
-20
10
40
70
Junction Temperature (qC)
100
1.8
-50
130
VEN = 5 V
100
130
D002
Figure 2. Shutdown Current vs Temperature
615
1.45
610
1.4
EN On Voltage (V)
VFB Feedback Voltage (mV)
10
40
70
Junction Temperature (qC)
VEN = 0 V
Figure 1. Supply Current vs Junction Temperature
605
600
595
590
1.35
1.3
1.25
1.2
585
-50
-20
10
40
70
Junction Temperature (qC)
100
1.15
-50
130
1.2
28
High-Side RDS(on) (m:)
32
1.16
1.12
1.08
1.04
10
40
70
Junction Temperature (qC)
100
130
D004
Figure 4. Enable On Voltage vs Junction Temperature
1.24
1
-50
-20
D003
Figure 3. Feedback Voltage vs Junction Temperature
EN Off Voltage (V)
-20
D001
24
20
16
12
-20
10
40
70
Junction Temperature (qC)
100
130
8
-50
D005
Figure 5. Enable Off Voltage vs Junction Temperature
-20
10
40
70
Junction Temperature (qC)
100
130
D006
Figure 6. High-Side RDS(on) vs Junction Temperature
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
7
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
12
128
10
127
OVP Threshold (%)
Low-Side RDS(on) (m:)
Typical Characteristics (continued)
8
6
4
2
126
125
124
123
0
-50
-20
10
40
70
Junction Temperature (qC)
100
122
-50
130
380
63
370
62
61
60
59
100
130
D008
360
350
340
330
58
-50
-20
10
40
70
Junction Temperature (qC)
100
320
-50
130
20
1.4
Soft-Start Time (ms)
1.5
18
16
14
12
10
40
70
Junction Temperature (qC)
100
130
D010
Figure 10. Discharge Resistor vs Junction Temperature
22
10
-50
-20
D009
Figure 9. UVP Threshold vs Junction Temperature
Valley Current Limit (A)
10
40
70
Junction Temperature (qC)
Figure 8. OVP Threshold vs Junction Temperature
64
Discharge Resistor (:)
UVP Threshold (%)
Figure 7. Low-Side RDS(on) vs Junction Temperature
1.3
1.2
1.1
1
-20
10
40
70
Junction Temperature (qC)
100
130
0.9
-50
D011
Figure 11. Valley Current Limit vs Junction Temperature
8
-20
D007
-20
10
40
70
Junction Temperature (qC)
100
130
D012
Figure 12. Soft-Start Time vs Junction Temperature
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
100
100
95
90
90
80
85
70
Efficiency (%)
Efficiency (%)
Typical Characteristics (continued)
80
75
70
65
60
50
40
30
60
20
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
55
50
0.01
0.1
1
0
0.01
10 15
I-Load (A)
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
10
600
600
500
400
300
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
0
1
2
3
4
5
6
7
I-Load (A)
8
9
10
11
10 15
D014
Figure 14. Efficiency vs Load Current, FCCM
700
Switching Frequency (kHz)
Switching Frequency (kHz)
Figure 13. Efficiency vs Load Current, Eco-mode
0
1
I-Load (A)
700
100
0.1
D013
500
400
300
200
VIN=12V, VOUT=1.2V
VIN=12V, VOUT=2.5V
VIN=12V, VOUT=5V
100
0
12
0
1
D017
Figure 15. Switching Frequency vs Load Current, Eco-mode
2
3
4
5
6
7
I-Load (A)
8
9
10
11
12
D018
Figure 16. Switching Frequency vs Load Current, FCCM
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
9
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
7 Detailed Description
7.1 Overview
The TPS56C230 is high density synchronous buck converter which operates from 4.5-V to 18-V input voltage
(VIN), and the output voltage range is from 0.6 V to 5.5 V. It has 17-mΩ and 5.9-mΩ integrated MOSFETs that
enable high efficiency up to 12 A. The device employs D-CAP3 mode control that enables low external
component count, ease of design, optimization of the power design for cost, size and efficiency, and provides
fast transient response with no external compensation components and an accurate feedback voltage. The
control topology supports seamless transition between CCM mode at heavy load conditions and DCM operation
at light load conditions. Eco-mode allows the TPS56C230 to maintain high efficiency at light load and FCCM
mode keeps the output ripple small at light load. The TPS56C230 is able to adapt to both low equivalent series
resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
7.2 Functional Block Diagram
PG high
threshold
UV threshold
+
PGOOD
+
UV
Delay
+
+
PG low
threshold
OV
OV threshold
VIN
FB
+
0.6 V
+
VREGOK
LDO
VCC
4.2 V /
3.7 V
+
+PWM
+
Control Logic
BST
SS
VIN
Ripple injection
SW
Internal SS
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
Eco-mode/FCCM
Soft-Start
PGOOD
SW
XCON
SS
PGND
One shot
+
OCL
EN threshold
EN
+
ZC
+
+
NOCL
150°C /20°C
+
THOK
AGND
Light load operation set
Discharge control
MODE
10
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both lowESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56C230 also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the converter output voltage, VOUT, and is
inversely proportional to the input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS56C230 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in Equation 1.
1
¦P =
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the internal output set-point resistor divider network and the
internal gain of the TPS56C230. The low-frequency L-C double pole has a 180 degree drop in phase. At the
output filter frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal
ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB
per decade and increases the phase to 90 degree one decade above the zero frequency. The inductor and
capacitor selected for the output filter must be such that the double pole is placed close enough to the highfrequency zero so that the phase boost provided by this high-frequency zero provides adequate phase margin for
the stability requirement. The crossover frequency of the overall system should usually be targeted to be less
than one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS56C230 has an internal 1.2-ms soft-start time, and also an external SS pin is provided for setting longer
soft start time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a longer soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 2:
6OO (IO) =
%OO (J() × 84'( (8)
+OO :Q#;
(2)
where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS56C230 can support large duty operation by its internal TON extension function. When VIN/VOUT < 1.6,
and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and also
improve the performance of the load transient performance.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A pullup resistor of 100 kΩ is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
11
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
Feature Description (continued)
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
in an OVP, UVP, or thermal shutdown event
during the soft-start period.
7.3.5 Overcurrent Protection and Undervoltage Protection
The TPS56C230 has the overcurrent protection and undervoltage protection. The output overcurrent limit (OCL)
is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the
OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch
current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will shut off after a wait time of 256us and then re-start after the hiccup time (typically
10.5*Tss). When the over current condition is removed, the output voltage is recovered.
7.3.6 Overvoltage Protection
The TPS56C230 has the overvoltage protection feature and have the same implementation. When the output
voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, the output will
be discharged after a wait time of 120 µs. When the over voltage condition is removed, the output voltage will be
recovered.
7.3.7 Out-of-Bounds Operation
The TPS56C230 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much
lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault,
OOB protection operates as an early protection mechanism. During the OOB operation, the device operates in
force PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor
current quickly discharges the output capacitor thus causing the output voltage to fall quickly towards the
setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe
operation of the internal FETs.
7.3.8 UVLO Protection
The undervoltage lockout (UVLO) protection monitors the VCC pin voltage to protect the internal circuitry from
low input voltages. When the voltage is lower than UVLO threshold voltage, the device shuts off and outputs are
discharged to prevent mis-operation of the device. The converter begins operation again when the input voltage
exceeds the threshold by a hysteresis of 500 mV (typical). This is a non-latch protection.
7.3.9 Output Voltage Discharge
The TPS56C230 has the discharge function by using internal MOSFET about 350Ω, which is connected to the
output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.10 Thermal Shutdown
The TPS56C230 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device shuts off and the output will be discharged. This is a non-latch protection, the device restarts
switching when the temperature goes below the thermal shutdown threshold.
12
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS56C230 has a MODE pin that can setup two different states of operation for light load operation. The light
load running includes Eco-mode and FCCM mode.
7.4.2
Eco-mode™ Control
The Eco-mode control schemes to maintain high light load efficiency. As the output current decreases from
heavy load conditions, the inductor current is also reduced and eventually comes to a point where the rippled
valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction
modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current
further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the same
as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with
smaller load current to the level of the reference voltage. This makes the switching frequency lower, proportional
to the load current, and keeps the light load efficiency high. The light load current where the transition to Ecomode operation happens ( IOUT(LL) ) can be calculated from Equation 3.
(V -V
) × VOUT
1
IOUT(LL) =
× IN OUT
2 × LOUT × FSW
VIN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to select the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Force CCM
Force CCM(FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant value over the full load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
7.4.4 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in Table 1 . The voltage on the MODE pin recommended to be set by connecting this pin to the center tap
of a resistor divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom
resistor (RM_L) as 1% resistors is shown in Table 1. It is recommended to choose the resistor to set the voltage at
around 5%*VCC for Eco-mode or 15%*VCC for FCCM. It is important that the voltage for the MODE pin is
derived from the VCC rail only since internally this voltage is referenced to detect the MODE option, and not to
leave the mode pin floating. The MODE pin setting can be reset only by a VIN power cycling or EN toggle.
Table 1. MODE Pin Resistor Settings
Voltage on MODE
Recommended Resistor
LIGHT LOAD OPERATION
RM_H(kΩ)
RM_L (kΩ)
(0~10%)*VCC
330
15
Eco-mode
(10%~20%)*VCC
180
33
FCCM
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
13
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
Figure 17 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
EN threshold
1.3V
EN
VCC UVLO
4.2V
VCC
MODE2
MODE1
MODE
500us
100us
tss
VOUT
1.5*tss
1ms
PGOOD
Figure 17. Power-Up Sequence
7.4.5 Standby Operation
The TPS56C230 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when floating, the part is disabled by
default.
14
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
8 Application and Implementation
NOTE
Information in the following application sections are not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 18 shows a typical application for TPS56C230 with 1.2-V output. This design converts
an input voltage range of 4.5 V to 18 V down to 1.2 V with a maximum output current of 12 A.
8.2 Typical Application
C1
U1
C2
0.1uF
1uF
VIN = 4.5 - 18V
VIN
17
VCC
GND
C3
22uF
C4
22uF
2
3
4
5
C5
0.1uF
VCC
BST
VIN
VIN
VIN
VIN
SW
SW
SW
SS
NC
NC
FB
C10
GND
18nF
11
MODE
15
12
EN
GND
R3
VCC
9
EN
AGND
PGND
PGND
PGND
PGND
MODE
PGOOD
100k
R4
330k
1
L1
6 SW
19
20
VOUT = 1.2V/12A
VOUT
680nH
14
R1
10
16
10.0k
13
7
8
18
21
C6
C7
C8
C9
47uF
47uF
47uF
47uF
GND
R2
10.0k
TPS56C230RJER
GND
R5
GND
15k
GND
Figure 18. 1.2-V, 12-A Reference Design
8.2.1 Design Requirements
Table 2 lists the design parameters for this example.
Table 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
Output voltage
1.2
V
IOUT
Output current
12
A
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
FSW
Switching frequency
1.2A - 10.8A load step, 2.5A/us
12A load
12
18
V
2% x VOUT
500
Light load operating mode
TA
±5% x VOUT
4.5
kHz
Eco-mode
Ambient temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS56C230 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
15
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See Equation 4
8176 = 0.6 × (1 +
4722'4
)
4.19'4
(4)
8.2.2.3 MODE Selection
The light load running mode (Eco-mode or FCCM ) are set by a voltage divider from VCC to GND connected to
the MODE pin. See Table 1 for possible MODE pin configurations. For this design example ,the switching
frequency is about 500kHz, the light load running mode is Eco-mode and the output current is 12 A.
8.2.2.4 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 3 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 5 and Equation 6. It is
important that the inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
÷
IL(rms)= ç I OUT + × ç
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø ø
è
IOUT(ripple)
IL(peak) = IOUT +
2
(5)
(6)
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device, so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.5 Output Capacitor Selection
After selecting the inductor, the output capacitor needs to be optimized. In D-CAP3, the regulator reacts within
one cycle to the change in the duty cycle, so the good transient performance can be achieved without large
amounts of output capacitance. The recommended output capacitance range is given in Table 3. Ceramic
capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple).
Table 3. Recommended Component Values
16
RUPPER
(kΩ)
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (PF)
10
0
500
0.47
66
330
-
10
10
500
0.68
66
330
-
2.5
20
63
500
1.2
66
330
3.3
20
90
500
1.5
66
330
22-110
5.0
15
110
500
1.8
66
330
22-110
VOUT (V)
RLOWER (kΩ)
0.6
1.2
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
8.2.2.6 Input Capacitor Selection
The TPS56C230 requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in Equation 7.
IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW
(7)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by Equation 8:
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
ICIN(rms) = IOUT ×
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
8.2.3 Application Curves
Figure 19 through Figure 34 apply to the circuit of Figure 18. VIN = 12 V. TA = 25°C unless otherwise specified.
1
100
90
0.6
Load Regulation (%)
80
Efficiency (%)
70
60
50
40
30
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
20
10
0
0.01
0.1
1
-0.2
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
-0.6
-1
0.001
10 15
I-Load (A)
0.2
0.01
Figure 19. Efficiency Curve
1
1015
D032
Figure 20. Load Regulation
800
700
700
600
Switching Frequency (kHz)
Swtiching Frequency (kHz)
0.1
I-Load (A)
D000
600
500
400
300
500
400
300
200
VIN=4.5V, VOUT=1.2V
VIN=7.4V, VOUT=1.2V
VIN=12V, VOUT=1.2V
VIN=18V, VOUT=1.2V
100
200
0
4
6
8
10
12
VIN (V)
14
16
18
0
1
D033
2
3
4
5
6
7
I-Load (A)
8
9
10
11
12
D034
IOUT = 12 A
Figure 21. Switching Frequency vs Input Voltage
Figure 22. Switching Frequency vs Output Load
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
17
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
1
1
0.8
0.6
Line Regulation (%)
Line Regulation (%)
0.6
0.2
-0.2
-0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1
4
6
8
10
12
VIN (V)
14
16
18
4
6
D035
IOUT=0.1A
10
12
VIN (V)
14
16
18
D036
IOUT=12A
Figure 23. Line Regulation
Figure 24. Line Regulation
EN=5V/div
EN=5V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
800us/div
800us/div
IOUT = 6A
IOUT = 6A
Figure 25. Start-Up Through EN
Figure 26. Shut-down Through EN
Vin=10V/div
Vin=10V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
800us/div
800us/div
IOUT = 6 A
IOUT = 6 A
Figure 27. Start Up Relative to VIN Rising
18
8
Figure 28. Shut Down Relative to VIN Falling
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
Vout=20mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=10V/div
SW=10V/div
20us/div
2us/div
IOUT = 0.1 A
IOUT = 12 A
Figure 29. Output Voltage Ripple
Figure 30. Output Voltage Ripple
Vout=100mV/div (AC coupled)
Vout=100mV/div (AC coupled)
Iout=10A/div
Iout=10A/div
1.2 A to 10.8 A
200us/div
Slew Rate=2.5A/us
0 A to 12 A
Figure 31. Transient Response
200us/div
Slew Rate=2.5A/us
Figure 32. Transient Response
Vout=1V/div
Vout=1V/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
100us/div
10ms/div
Figure 33. Normal Operation to Output Hard Short
Figure 34. Output Hard Short Hiccup Protection
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
19
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
9 Power Supply Recommendations
The TPS56C230 is intended to be powered by a well regulated DC voltage. The input voltage range is 4.5 V to
18 V. TPS56C230 is a buck converter. The input supply voltage must be greater than the desired output voltage
for proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS56C230 circuit, some additional input bulk capacitance is recommended.
Typical values are 100 μF to 470 μF.
20
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 2.75inch, two-layer PCB with 2-oz copper used as example.
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitors and also as close to the output pin as possible.
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
Feedback could be 20mil and must be routed away from the switching node, BST node or other high
efficiency signal.
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
Figure 35 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 18.
Trace on the top layer
C
Trace on the bottom layer
VIN
C
R
4
VIN
BST
3
6
VIN
SW
VIN
VIN
Additional Vias to
the GND plane
7
C
SW
Trace on the bottom layer
SW
SW
PGND
GND
4
4
VCC3
6
PGOOD
3
6
L
Vias to the GND plane
NC
NC
3
VOUT
FB
MODE
AGND
EN
SS
6
4
R
PGND
PGND
7
7
PGND
R
R
R
Additional Vias to
the GND plane
R
Additional Vias to
the GND plane
C
C
0Ÿ
AGND
PGND
Additional Vias to
the GND plane
Figure 35. PCB Layout Recommendation Diagram
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
21
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS56C230 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
D-CAP3, Eco-mode, HotRod, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
23
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
B
A
(45°X0.08) TYP
(0.25)
DETAIL A
3.1
2.9
PIN 1 INDEX AREA
CHAMFERS ARE OPTIONAL
TYPICAL
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 1.8
PKG
SEE TERMINAL
DETAIL A
10
6
(0.1) TYP
16X 0.45
11
5
(0.007)
2X
1.8
PKG
0.975±0.1
21
20X 0.25
0.15
1
PIN 1 ID
DETAIL B
0.1
0.05
15
20
16
(0.123)
C B A
C
20X 0.5
0.3
0.926±0.1
4224338 / B 10/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
24
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
TPS56C230
www.ti.com
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
(0.926)
(0.123)
16
20
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(2.8)
(0.975)
11
5
(R0.05) TYP
6
PKG
10
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224338 / B 07/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271) .
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
25
TPS56C230
SLUSDE4A – AUGUST 2019 – REVISED AUGUST 2019
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0020B
PLASTIC QUAD FLATPACK- NO LEAD
(0.926)
(0.123)
16
20
20X (0.6)
20X (0.2)
1
15
(0.007)
16X (0.45)
21
PKG
(0.975) (2.8)
5
11
(R0.05) TYP
6
PKG
10
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4224338 / B 07/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
26
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS56C230
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS56C230RJER
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN-HR
RJE
20
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
56C230
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS56C230RJER
Package Package Pins
Type Drawing
VQFNHR
RJE
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS56C230RJER
VQFN-HR
RJE
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising