Texas Instruments | UCC28056 6-Pin Single-Phase Transition-Mode PFC Controller (Rev. E) | Datasheet | Texas Instruments UCC28056 6-Pin Single-Phase Transition-Mode PFC Controller (Rev. E) Datasheet

Texas Instruments UCC28056 6-Pin Single-Phase Transition-Mode PFC Controller (Rev. E) Datasheet
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UCC28056
SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019
UCC28056 6-Pin Single-Phase Transition-Mode PFC Controller
1 Features
3 Description
•
The UCC28056 device drives PFC boost stages
based on an innovative mixed mode method that
operates in transition mode (TM) at full load and
transitions seamlessly into discontinuous conduction
mode (DCM) at reduced load, automatically reducing
switching frequency. This device incorporates burst
mode operation to further improve light load
performance, enabling systems to meet challenging
energy standards while eliminating the need to switch
off the PFC. UCC28056 can drive a PFC power stage
up to 300 W, ensuring sinusoidal line input current
with low distortion, close to unity power factor. When
used with the LLC controller UCC256403/4, and dual
synchronous rectifier controller UCC24624 less than
80 mW system standby power can be achieved,
enabling PFC always on architecture and eliminating
the need for an auxiliary converter. This with FET
Drain valley turn-on with simple boost inductor allows
fewest component count and reduced system cost.
•
•
•
•
•
•
•
•
•
•
•
•
Ultra-low no-load input power enables < 80-mW
standby power at 230 VAC in PFC+LLC system
Excellent light load efficiency and high efficiency
over wide range of load due to multi-mode TM
and DCM control
Enables low system cost through FET drain valley
synchronized turn-on which eliminates need for
second winding on the boost inductor
Enables compliance to green power standards
without disabling PFC
– EuP Lot 6 Tier 2, CoC Ver. 5 Tier 2, Energy
Star Ver. 6.1, DoE Level VI
Burst mode with soft-entry and soft-exit periods
enables ultra-low audible noise output
Enhanced error amplifier, responds rapidly to load
steps without degrading input current distortion
User adjustable valley delay ensures valley
switching
Low start-up current consumption (<46 µA)
Wide VCC range 8.5 V to 34 V
Cycle-by-cycle current limit
Second independent output over-voltage
protection
Integrated over-temperature protection
Create a custom design using the UCC28056
device with the WEBENCH® Power Designer
Device Information(1)
PACKAGE
BODY SIZE (NOM)
UCC28056
SOT-23(6)
2.90 mm x 1.6 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
No Load Power
50
45
2 Applications
•
•
•
•
PART NUMBER
Input Power (mW)
1
Desktop computing and digital TV
Gaming, set top box and AC adapter front end
LED drivers and luminaries
Industrial and medical power supplies, e-bike
chargers, power tools chargers
40
35
30
25
20
80
120
160
200
240
280
Line Voltage (VRMS)
Simplified Application
LBST
DBST
ROS1
CIn
CC0
RC0
UCC28056
RZC1
VCC
VOSNS
COMP
ZDC/CS
DRV
VCC
GND
VOUT
Bus
CC01
COut
ROS2
RDG
RCS
CCC
RZC2
Bus
GND
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28056
SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Tables...................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
4
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Controller Functional Modes ................................... 25
9
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application ................................................. 27
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 44
12 Device and Documentation Support ................. 47
12.1
12.2
12.3
12.4
12.5
12.6
Custom Design With WEBENCH® Tools .............
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
47
47
47
47
47
47
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April, 2019) to Revision E
Page
•
Added target market applications. ......................................................................................................................................... 4
•
Added explanation for ZCD noise immunity. ......................................................................................................................... 4
•
Changed new variant of LLC controller. ............................................................................................................................... 14
•
Added burst mode modified.................................................................................................................................................. 14
•
Added burst mode levels for versions. ................................................................................................................................ 25
•
Added burst modes for different versions............................................................................................................................. 25
•
Changed boost inductance calculation. ............................................................................................................................... 30
•
Changed inductor requirements. ......................................................................................................................................... 31
Changes from Revision C (February 2018) to Revision D
Page
•
Added Link to UCC256403/4 LLC controller .......................................................................................................................... 1
•
Added Link to UCC24624 synchronous rectifier controller..................................................................................................... 1
•
Updated Description section................................................................................................................................................... 1
•
Updated Description section................................................................................................................................................... 1
•
Added Device Comparison Table........................................................................................................................................... 4
•
Changed VBSTFall graph into normalized graph. .................................................................................................................... 12
•
Changed VBSTRise graph into normalized graph. ................................................................................................................... 12
•
Changed VOSNSOVP1Rise graph into normalized graph............................................................................................................ 13
•
Changed VOSNSOVP1Fall graph into normalized graph............................................................................................................. 13
Changes from Revision B (January 2018) to Revision C
•
2
Page
Updated Description section .................................................................................................................................................. 1
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SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019
Changes from Revision A (November 2017) to Revision B
Page
•
Updated Simplified Application............................................................................................................................................... 1
•
Changed document status from Advance Information to Production Data ............................................................................ 1
Changes from Original (October 2017) to Revision A
•
Page
Added WEBENCH links to data sheet ................................................................................................................................... 1
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UCC28056
SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019
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5 Device Comparison Tables
DEVICE
UCC28056
UCC28056A
UCC28056B
UCC28056C
Target Applications
Not recommended
for new design
PFC Bus output
>400VDC
Improved audible
noise performance
Drop in replacement
for UCC28056
OVP2 FEATURE INCLUDED
YES
NO
YES
YES
OVP1 THRESHOLD
110% Vout
108% Vout
110% Vout
110% Vout
BURST MODE THRESHOLD
< 10% Load
< 15% Load
< 15% Load
< 10% Load
Basic noise immunity
Improved noise
immunity
Improved noise
immunity
Improved noise
immunity
ZCD NOISE IMMUNITY
The enhanced noise immunity of UCC28056A, UCC28056B, and UCC28056C provides system robustness
advantages and less sensitivity to PCB layout than the UCC28056. For more information on the system level
benefits that UCC28056A, UCC28056B and UCC28056C provide, please see UCC28056X Selection Guide
SLUA974.
PARAMETER
DEVICE
MIN
TYP
MAX
UCC28056A
2.64
2.7
2.76
2.69
2.75
2.81
2.55
2.625
2.68
2.60
2.675
2.73
UNIT
Output Over Voltage Protection
VOSOvp1Rise
UCC28056
VOSNS over-voltage threshold, rising,
VCC = 12 V
UCC28056B
V
UCC28056C
UCC28056A
VOSOvp1Fall
VOSNS over-voltage threshold, falling,
VCC = 12 V
VOSOvp1Hyst
VOSOovp1Rise - VOSOovp1Fall
UCC28056
UCC28056B
V
UCC28056C
TOvp2Blk
Ovp2 Comparator output is blanked for
this period after falling edge of DRV
All
0.072
V
UCC28056A
Not Applicable
UCC28056
UCC28056B
520
620
720
ns
720
820
ns
1.125
1.148
ns
UCC28056C
UCC28056A
TOvp2bEn
Ovp2b fault is detected if ZCD is detected
during this period after falling edge of
Ovp2 Comparator output
Not Applicable
UCC28056
UCC28056B
620
UCC28056C
UCC28056A
VOvp2Th
Second level output over-voltage fault
Threshold
Not Applicable
UCC28056
UCC28056B
1.102
UCC28056C
Burst Mode Operation
UCC28056
VBSTFall
VCOMP Burst Threshold Falling
UCC28056C
UCC28056A
UCC28056B
UCC28056
VBSTRise
VCOMP Burst Threshold Rising
UCC28056C
UCC28056A
UCC28056B
4
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0.5
0.75
V
0.625
0.875
Copyright © 2017–2019, Texas Instruments Incorporated
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SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VOSNS
1
6
COMP
ZCD/CS
2
5
DRV
VCC
3
4
GND
Pin Functions
PIN
NAME
COMP
NO.
6
I/O
DESCRIPTION
I/O
Output of the internal transconductance error amplifier and power demand input. To achieve
compensation of the voltage loop, connect a suitable RC network from this pin to GND. The error
amplifier output is internally limited to VCOClmp. An internal resistor, RCODisch, discharges the external
compensation network when the controller is in its Stopb state or when the Ovp2 comparator is tripped.
Switching stops, and the controller enters a low-power state (BstOffb), when the voltage on the COMP
pin drops below VBSTFall. Switching resumes when the COMP pin voltage exceeds VBSTRise.
DRV
5
I/O
GATE connection to drive the main power MOSFET. This output is internally limited to VDRHigh. This is
done to reduce power dissipation in the internal driver and allow controller operation from high VCC
voltages. An external resistor connected from DRV to GND adjusts the delay between the Drain
waveform falling below VIn and the DRV rising edge, allowing the turn on transition to be aligned to the
valley minimum accurately over a wide range of idle ring oscillating frequency.
GND
4
G
Controller Ground reference pin. Connect to the power stage at the lower terminal of the current sense
resistor, RCS, only.
VCC
3
P
Positive supply voltage. Switching operation can start once VCC exceeds VCCStart. Switching operation
ceases if VCC drops below VCCStop for longer than TUVLOBlk.
I
This pin is fed by a potential divider connected across the Drain & Source pins of the power MOSFET
switch. While the DRV pin is high this pin monitors the voltage across the current sense resistor, RCS.
This pin implement over-current protection functions. While the DRV pin in low this pin monitors the Drain
voltage waveform. Input voltage applied to the power stage can be obtained by filtering the Drain
waveform. Input voltage provides Line voltage feed - forward and Line Brown - In features. Drain voltage
waveform is also used to provide ZCD detection, valley synchronization and second level output over voltage protection features.
I
Voltage error amplifier inverting input. The error amplifier non - inverting input connects to internal
reference voltage VOSReg. Error amplifier gain increases with error magnitude to improve transient
response without compromising Line current distortion. Output over-voltage protection is implemented on
this pin. Switching operation halts if the voltage on this pin exceeds VOvp1Rise and resumes when it drops
below VOvp1Fall.
ZCD/CS
VOSNS
2
1
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
-0.5
36
ZCD/CS
-0.5
7
VOSNS
-0.5
7
COMP
-0.5
7
DRV
-0.3
20
Junction
temperature
range
TJ
-40
150
Storage
temperature
range, Tstg
Tstg
-65
150
Input voltage
Output voltage
Lead temperature
(1)
Soldering, 10 second
300
Reflow
260
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Input voltage
TA
Operating ambient temperature
NOM
MAX
12
UNIT
V
-40
125
°C
7.4 Thermal Information
UCC28056
THERMAL METRIC (1)
SOT23-6
UNIT
6 PINS
RΘJA
Junction-to-ambient thermal resistance
116.4
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
74.9
°C/W
RΘJB
Junction-to-board thermal resistance
36.1
°C/W
ΨJT
Junction-to-top characterization parameter
18.8
°C/W
ΨJB
Junction-to-board characterization parameter
36.0
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VCCStart
Turn-on threshold
VCC Rising
VCCStop
Turn-off threshold
VCC Falling
VCCHyst
UVLO Hysteresis (VCCStart - VCCStop)
TUVLOBlk
Turn-OFF Blanking Time
(1)
8.5
10.65
11
V
8.85
9.2
V
1.5
27
V
35
42
µs
46
µA
SUPPLY CURRENT
ICC_Startup
Current consumption before startup
VCC = VCCStart-200mV, TA < 110℃
ICC_FAULT
Current consumption during fault
condition
VCC = 12V
130
µA
ICC_BSTOFF
Current consumption during Burst OFF
VCC = 12V
period
132
µA
ICC_RUN
Operating current with DRV pin
unloaded
VCC = 12V
2.2
mA
VDRLow
DRV output low voltage
IDR = 100mA
0.9
V
VDRHigh
DRV output voltage high level, limited
VCC = 25V, IDR = -10mA
15
V
VDRHighMin
DRV minimum high voltage level
VCC = VCCStop + 200 mV, IDR = -8mA
RDRH
DRV, Pull-up resistance
TA = -40°C to 125°C, IDR = -8mA,
VCC=12V
RDRL
DRV, Pull-down resistance
TA = -40°C to 125°C, IDR = 100mA
tR
Rise Time
CLOAD=1nF, DRV=1V to 6V,
VCC=12V
tF
Fall Time
CLOAD=1nF, DRV=6V to 1V,
VCC=12V
Isource
Source peak current on DRV Pin
1.8
GATE DRIVE
10
13.7
8
V
9.7
16
Ω
2.0
4.6
9
Ω
10
34
61
ns
4
15
40
ns
(1)
(1)
-0.7
A
1
A
kΩ
Isink
Sink peak current on DRV Pin
RDG0
DRV to GND resistance value to
select TZCDR0 (1)
130
200
RDG1
DRV to GND resistance value to
select TZCDR1 (1)
81.18
82
82.82
kΩ
RDG2
DRV to GND resistance value to
select TZCDR2 (1)
61.38
62
62.62
kΩ
RDG3
DRV to GND resistance value to
select TZCDR3 (1)
42.57
43
43.43
kΩ
RDG4
DRV to GND resistance value to
select TZCDR4 (1)
26.73
27
27.27
kΩ
RDG5
DRV to GND resistance value to
select TZCDR5 (1)
17.82
18
18.18
kΩ
RDG6
DRV to GND resistance value to
select TZCDR6 (1)
12.87
13
13.13
kΩ
RDG7
DRV to GND resistance value to
select TZCDR7 (1)
9
9.1
9.2
kΩ
TDGSmpl
Time needed to detect RDG value.
3.95
4.4
4.95
ms
VDGClmp
Maximum voltage that will be applied
on DRV pin while detecting RDG value.
1
1.05
1.1
V
2.45
2.5
2.55
V
100
nA
TA < 85℃
Error Amplifier
VOSReg
Feedback voltage reference
IOSBias
ISNS pin bias current
VOS = VOSReg
gM
Error Amplifier Transconductance
Gain
|VOS-VOSReg| < DSuThs
(1)
-100
50
µS
Not tested in production. Ensured by design.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
gMNL
Error Amplifier Transconductance
Gain for large error
DSuThs
Non-Linear Gain Threshold
67
RCODisch
Internal COMP to GND resistance
when in STOPb state.
4.3
5
5.7
kΩ
VCOClmp
COMP pin internal high clamp voltage
5.5
5.6
5.71
V
|VOS-VOSReg| > DSuThs
300
COMP pin internal low clamp voltage
VCOSat
(1)
ICOMin
COMP Maximum Source Current
ICOMax
COMP Maximum Sink Current
µS
mV
0
V
-120
µA
120
µA
Line Voltage Feed-Forward
(1)
THLinMax
Line peak sampling window
VFF0Rise
Comparator rising threshold switching
from GFF0 to GFF1 (1)
While switching
11
12.3
13.6
ms
0.348
V
VFF1Rise
Comparator rising threshold switching
from GFF1 to GFF2 (1)
0.406
V
VFF2Rise
Comparator rising threshold switching
from GFF2 to GFF3 (1)
0.473
V
VFF3Rise
Comparator rising threshold switching
from GFF3 to GFF4 (1)
0.552
V
VFF4Rise
Comparator rising threshold switching
from GFF4 to GFF5 (1)
0.644
V
VFF5Rise
Comparator rising threshold switching
from GFF5 to GFF6 (1)
0.751
V
VFF6Rise
Comparator rising threshold switching
from GFF6 to GFF7 (1)
0.875
V
VFF0Fall
Comparator falling threshold switching
from GFF1 to GFF0 (1)
Peak value of VInSynth within THLinMax
Window
0.331
V
VFF1Fall
Comparator falling threshold switching
from GFF2 to GFF1 (1)
Peak value of VInSynth within THLinMax
Window
0.386
V
VFF2Fall
Comparator falling threshold switching
from GFF3 to GFF2 (1)
Peak value of VInSynth within THLinMax
Window
0.45
V
VFF3Fall
Comparator falling threshold switching
from GFF4 to GFF3 (1)
Peak value of VInSynth within THLinMax
Window
0.524
V
VFF4Fall
Comparator falling threshold switching
from GFF5 to GFF4 (1)
Peak value of VInSynth within THLinMax
Window
0.612
V
VFF5Fall
Comparator falling threshold switching
from GFF6 to GFF5 (1)
Peak value of VInSynth within THLinMax
Window
0.713
V
VFF6Fall
Comparator falling threshold switching
from GFF7 to GFF6 (1)
Peak value of VInSynth within THLinMax
Window
0.832
V
GFF0
Line Feed-Forward gain level 0
(1)
1
GFF1
Line Feed-Forward gain level 1
(1)
0.735
GFF2
Line Feed-Forward gain level 2
(1)
0.541
GFF3
Line Feed-Forward gain level 3
(1)
0.398
GFF4
Line Feed-Forward gain level 4
(1)
0.292
GFF5
Line Feed-Forward gain level 5
(1)
0.215
GFF6
Line Feed-Forward gain level 6
(1)
0.158
GFF7
Line Feed-Forward gain level 7
(1)
0.116
Maximum ON Time
TONMAX0
Maximum ON time when GFF = GFF0
12.1
12.8
13.2
µs
TONMAX1
Maximum ON time when GFF = GFF1
10.42
10.98
11.28
µs
8
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TONMAX2
Maximum ON time when GFF = GFF2
8.85
9.41
9.64
µs
TONMAX3
Maximum ON time when GFF = GFF3
7.59
8.07
8.32
µs
TONMAX4
Maximum ON time when GFF = GFF4
6.52
6.92
7.18
µs
TONMAX5
Maximum ON time when GFF = GFF5
5.56
5.93
6.16
µs
TONMAX6
Maximum ON time when GFF = GFF6
4.73
5.09
5.28
µs
TONMAX7
Maximum ON time when GFF = GFF7
4.07
4.36
4.57
µs
Burst Mode Operation See Device Comparison Table
Zero Current Detection and Valley Synch
VZcdVinHyst
ZcdVin Comparator hysteresis
(1)
12
19
26
mV
TDCHVinMin
ZcdVin Comparator blanking from
DRV falling edge (1)
250
358
467
ns
TZCDTo
If no negative transitions on Vin
comparator for this period then do not
wait for valleys
2.035
2.4
3.0
µs
TZCDR0
Minimum ZCD to DRV delay.
170
235
ns
ΔTZCDR1
TZCDR1 = TZCDR0 + ΔTZCDR1
(1)
RDG = RDG1
45.5
58.5
ns
ΔTZCDR2
TZCDR2 = TZCDR0 + ΔTZCDR2
(1)
RDG = RDG2
76
90
107
ns
ΔTZCDR3
TZCDR3 = TZCDR0 + ΔTZCDR3
(1)
RDG = RDG3
114
130
147
ns
ΔTZCDR4
TZCDR4 = TZCDR0 + ΔTZCDR4
(1)
RDG = RDG4
157
175
193
ns
ΔTZCDR5
TZCDR5 = TZCDR0 + ΔTZCDR5
(1)
RDG = RDG5
229
255
281
ns
ΔTZCDR6
TZCDR6 = TZCDR0 + ΔTZCDR6
(1)
RDG = RDG6
301
335
369
ns
ΔTZCDR7
TZCDR7 = TZCDR0 + ΔTZCDR7
(1)
RDG = RDG7
373
415
457
ns
VDDAmpl
Amplitude of 500 kHz sinewave signal
on ZCD/CS pin needed to trigger knee
detector
TDCHDDMin
Knee point detector blanking period
From VZC < VInSynth to DRV =
6V, CDR = 1nF, Fres = 1.2MHz, RDG =
RDG0
(1)
34.6
25
Measured from falling edge of DRV
pulse
mV
1.5
µs
1
s
Fault Protection
TLongFlt
Long Fault Duration
(1)
Line Brown-In Protection
VZCBoRise
Brown-out Protection Threshold when
in Stopb state
IZCBias
ZCD/CS Pin Bias Current
Peak cycle average voltage on
ZCD/CS Pin.
(1)
VZC = VZCBoFall
0.282
0.3
-100
0.318
V
100
nA
Over-Current Protection
VZCOcp1
ZCD/CS First Level over-current
protection threshold
450
500
550
mV
VZCOcp2
ZCD/CS Second Level over-current
protection threshold
670
750
825
mV
TOcp1Blk
ZCD/CS blanking time from DRV rising
edge to Enable Ocp1 Comparator
Output (1)
450
ns
TOcp2Blk
ZCD/CS blanking time from DRV rising
edge to Enable Ocp2 Comparator
Output (1)
250
ns
TOcpDrvDel
ZCD/CS crossing VOcpxTh to DRV
falling edge.
TDCHMax0
Max duration of TDCHb state if no ZCD
signal detected. After no OCPx Events
56
(1)
250
120
ns
µS
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TDCHMax1
Max duration of TDCHb state if no ZCD
signal detected. After one OCPx
Events (1)
500
µS
TDCHMax2
Max duration of TDCHb state if no ZCD
signal detected. After two consecutive
OCPx Events (1)
1000
µS
Output Over-Voltage Protection
See Device Comparison Table
Thermal Protection
TTSDRise
(1)
Thermal Shutdown Falling Threshold
TTSDFall
(1)
TTSDHyst
10
Thermal Shutdown Rising Threshold
TTSDRise - TTSDFall
While switching
While not switching
(1)
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135
145
155
°C
95
105
115
°C
38
40
42
°C
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7.6 Typical Characteristics
11
10.9
10.8
VCCStop (V)
VCCStart (V)
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
9.2
9.15
9.1
9.05
9
8.95
8.9
8.85
8.8
8.75
8.7
8.65
8.6
8.55
8.5
-40
-20
0
20
d000
Figure 1. VCCStart Threshold vs Temperature
40
60
80
Temperature (°C)
100
120
140
d000
Figure 2. VCCStop Threshold vs Temperature
2
0.033
1.98
0.032
1.96
0.031
ICC_Startup (mA)
VCCHYST (V)
1.94
1.92
1.9
1.88
1.86
0.03
0.029
0.028
0.027
1.84
0.026
1.82
1.8
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0.025
-40
140
0.132
0.128
0.11
0.124
0.105
ICC_BSTOFF (mA)
ICC_FAULT (mA)
0.12
0.115
0.1
0.095
0.09
0.075
-40
-20
0
20
40
60
80
Temperature (°C)
20
100
120
100
120
140
d000
0.12
0.116
0.112
0.108
0.104
0.096
140
0.092
-40
d000
Figure 5. VCC Fault Current vs Temperature
40
60
80
Temperature (°C)
0.1
VCC = 12V
VCC = 25V
VCC = 33V
0.08
0
Figure 4. VCC Startup Current vs Temperature
Figure 3. VCC Hysteresis vs Temperature
0.085
-20
d000
-20
0
20
40
60
80
Temperature (°C)
100
120
140
d000
Figure 6. VCC Burst Off Current vs Temperature
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Typical Characteristics (continued)
2.55
1.82
2.54
1.8
2.53
2.52
VOSNSReg (V)
ICC_RUN (mA)
1.78
1.76
1.74
2.51
2.5
2.49
2.48
1.72
2.47
VCC = 12V
VCC = 25V
VCC = 33V
1.7
1.68
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
2.46
2.45
-40
140
-20
0
20
d000
Figure 7. VCC Curent Run Mode vs Temperature
40
60
80
Temperature (°C)
100
120
140
d000
Figure 8. VOSNSReg vs Temperature
51
0.316
50.7
0.312
50.4
0.308
VZCBoRise (V)
gM (µS)
50.1
49.8
49.5
49.2
0.304
0.3
0.296
0.292
48.9
48.6
0.288
48.3
0.284
48
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0.28
-40
140
-20
1.15
1.05
1.145
1.04
1.14
1.03
1.135
1.02
VBSTFall Norm.
VOVP2Th (V)
40
60
80
Temperature (°C)
100
120
140
d001
Figure 10. VBoRise vs Temperature
1.13
1.125
1.12
1.01
1
0.99
0.98
1.115
0.97
1.11
0.96
1.105
-20
0
20
40
60
80
Temperature (°C)
100
120
140
d001
Figure 11. VOVP2 Threshold vs Temperature
12
20
d000
Figure 9. gM vs Temperature
1.1
-40
0
0.95
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
D001
It is Normalized respect its value at 25°C
Figure 12. Burst Mode Falling Threshold vs Temperature
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Typical Characteristics (continued)
1.05
3
1.04
2.9
2.8
1.02
2.7
1.01
TZCDTo (µs)
VBSTRise Norm.
1.03
1
0.99
2.6
2.5
0.98
2.4
0.97
2.3
0.96
0.95
-50
2.2
-25
0
25
50
75
Temperature (qC)
100
125
2.1
-40
150
-20
0
20
D002
It is Normalized respect its value at 25°C
1.05
1.04
1.04
1.03
1.03
1.02
1.01
1
0.99
0.98
0.97
140
d001
1.01
1
0.99
0.98
0.97
0.96
0.96
0.95
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
-25
0
D003
It is Normalized respect its value at 25°C
25
50
75
Temperature (qC)
100
125
150
D004
It is Normalized respect its value at 25°C
Figure 15. VOSNS OVP1 Rising Threshold vs Temperature
Figure 16. VOSNS OVP1 Falling Threshold vs Temperature
13.2
55
13.1
50
13
45
12.9
40
12.8
TDCM (µS)
TONMAX0 (µs)
120
1.02
0.95
-50
12.7
12.6
12.5
12.4
TDCM(GFF0)
TDCM(GFF1)
TDCM(GFF2)
TDCM(GFF3)
TDCM(GFF4)
TDCM(GFF5)
TDCM(GFF6)
TDCM(GFF7)
35
30
25
20
12.3
15
12.2
10
12.1
5
12
-40
100
Figure 14. ZCD Timeout vs Temperature
1.05
VOSNSOVP1Fall Norm
VOSNSOVP1Rise Norm.
Figure 13. Burst Mode Rising Threshold vs Temperature
40
60
80
Temperature (°C)
0
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
0.5
d001
Figure 17. TON Max vs Temperature
1
1.5
2
2.5
3
COMP (V)
3.5
4
4.5
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d001
Figure 18. TDCM vs COMP Voltage
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8 Detailed Description
8.1 Overview
The UCC28056 controller followed with the UCC256403/4 LLC controller device to provide a complete PFC and
LLC isolated off-Line power supply system. The combined power supply is designed to meet tough efficiency and
standby power requirements without the need for an Auxiliary Flyback converter and with no need to switch off
the PFC under light load conditions. It allows designers to meet modern green power standards with a simpler
and lower system cost of power supply.
The controller contains a number of features designed to maximize operating efficiency across the entire range
of Line and Load. A versatile CrM/DCM control algorithm allows UCC28056 to operate in transition mode at full
power and then transition seamlessly into DCM at reduced load without compromising Line current harmonics or
power factor. The controller operates at maximum frequency (Transition mode) when delivering full load and then
automatically reduce switching frequency, moving to DCM operation, when delivering reduced load for maximum
efficiency.
Light-load efficiency and standby power are further enhanced by transitioning automatically to a burst mode of
operation when delivering less than 10% load for UCC28056C variants and 15% load for UCC28056A/B. During
the burst OFF periods, the controller powers down most of its internal circuits to minimize controller power
consumption.
The UCC28056 controller includes a comprehensive list of fault protection features such as cycle-by-cycle
current limit, over-current protection, dual independent output over-voltage protection, Line Brown-In, Overtemperature protection and supply undervoltage lockout (UVLO).
Quantised 7-level line voltage feed-forward ensures that the loop gain is almost independent of line voltage, to
ease design of the output voltage control loop. A non-linear error amplifier greatly improves the response to large
steps in load without compromising steady state Line current harmonics.
14
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8.2 Functional Block Diagram
+
VOSReg
VOSNS
1
Error
Amplifier
VCOClmp
X
+
SSCnt/4
+
Ovp1Fltb
TONb
VOvp2Th
Stopb
PDem
+
BoFltb
GFF
VZCBoRise
TON
CrM / DCM
Control
Law
TDCM
+
VDRHigh
Zcdb
Zcdb
Ocpb
VInSyn(.)
2
TONb
Waveform
Generator
Gate
Driver
RDGRdb
SSCntb
Input
Voltage
Synthesiser
Digital
Peak
Detector
Pauseb
TDCHMax
Ocp1Fltb
Latch
MUX
TZCDR
+
Ocp2Fltb
VZCOcp2
Ocpb
OcpCnt
RDGRdb
TDCHMax
TZCDR0
TZCDR1
TZCDR2
TZCDR3
TZCDR4
TZCDR5
TZCDR6
TZCDR7
VCC
IDG
+
Ocp1Fltb
VZCOcp1
VCCStop, VCCStart
DRV
R
D Q
>CLK
+
ZCD/CS
5
Ovp2Fltb
VBstRise,VBstFall
Ovp2Fltb
COMP
RCODisch
BstRunb
VOSOvp1Rise, VOSOvp1Fall
6
VDGClmp
ADC
+
TUVLOBlk
UVLOFltb
TONb
VCC
3
Voltage VOSReg
Reference
Ocp2Fltb
TsdFltb
VREG
VDRHigh
Ovp2Fltb
Ovp1Fltb
ThrCycFlt
TLongFlt
UVLOFltb
BoFltb
Faultb
BstRunb
Fault and
Burst
Mode
State
Machine
RDGRdb
4
GND
Pauseb
Stopb
SSCnt
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8.3 Feature Description
8.3.1 CrM/DCM Control Principle
ILPkS( )
IL( , t)
ILPkS( )
IL( , t)
ILAvS( )
TON( )
ILAvS( )
TDCH( )
TON( )
TDCH( )
TPER( )
TPER( )
CrM Operation
DCM Operation
TDCM
Figure 19. PFC Inductor Current Waveform for CrM and DCM Operation
Consider a single switching cycle that occurs at angle (θ) during the Line Cycle. Assuming ideal CrM operation
the average inductor current (ILAvS(θ)) that flows during the switching cycle is given by:
ILAvS T
ILPkS T
2
VIn D u
TON T
VIn T
2 u LBST
RInEq
(1)
A fixed circuit has constant inductance (LBST), so if the switch ON duration (TON(θ)) holds constant (TON) , across
the Line Cycle, then the average input current remains proportional to the input voltage. In other words, when
controlled in this way, the Boost converter behaves as a resistive load (RInEq) connected across the Line.
2 u LBST
RInEq
TON
(2)
the next step is to consider DCM operation. Equation 3 describes the average inductor current that flows during
the switching cycle.
ILPkS T
T
T TDCH T
T
T u GONDCH T
VIn T
ILAvS T
u ON
VIn T u ON
2
TPER T
2 u LBST
RInEq
(3)
To ensure average input current proportional to input voltage it is necessary for the on-time product TON(θ) x
δONDCH(θ) is kept constant across the Line Cycle. Equation 4 shows the equivalent input resistance.
2 u LBST
RInEq
TON u GONDCH
(4)
The minimum effective input resistance (RInEqMin) is needed to draw maximum power (PInMax) from minimum Line
voltage (VInMinPkL):
VInMinPkL
PInMax
2 u RInEqMin
(5)
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Feature Description (continued)
Assume that full power operation at minimum Line operation is in CrM mode. Use Equation 6 to calculate the
PFC inductor value required to deliver maximum power from minimum Line.
2 u LBST
RInEqMin
TONMAX0
where
•
TONMAX0 is the maximum switch ON time
(6)
Input power demand is an expression of the ratio of input power over maximum input power.
RInEqMin
T
T u GONDCH T
PIn
VInPkL 2
VInPkL 2
PDem
u
u ON
2
PInMax VInMinPkL 2
RInEq
TONMAX0
VInMinPkL
(7)
Equation 8 rearranges Equation 7 to express TON(θ) time as a function of power demand.
TON T
PDem u
VInMinPkL2
VInPkL
2
u TONMAX0 u
1
VCO
GONDCH T
VCOMax
u GFF u
TONMAX0
GONDCH T
(8)
Equation 8 represents the CrM/DCM TON control principle implemented by UCC28056. This equation is quadratic
in nature but UCC28056 employs the value of δONDCH(θ) from previous cycles as the basis for computing TON(θ)
for the current cycle. The process is similar to solving an equation numerically by iteration.
A range of operating frequency options are available for CrM/DCM light-load operation. At one extreme, it can
operate at high frequency with low current pulses in CrM mode (TDCM = 0). At the other extreme it can operate, in
DCM mode, at minimum frequency (TDCM = TDCMMax) with current pulses of maximum amplitude. The controller
can select a TDCM value anywhere between these two extremes. Conduction loss normally dominates when
operating at minimum operating frequency leading to reduced efficiency. Switching loss normally dominates
when operating at maximum operating frequency (CrM) also leading to reduced efficiency. Typically the most
efficient operating frequency occurs when the pulse current amplitude is approximately one third of the maximum
value.
ILPkSOpt
1
2 u ILMaxPkL 3.5
(9)
ILMaxPkL
VInMinPkL u TONMAX0
2 u LBST
(10)
The UCC28056 transitions from CrM to DCM operation when the peak inductor current across a Line Cycle
drops below ILPkSOpt. While in DCM operation it adjusts the switching frequency to ensure that the peak inductor
current across a Line Cycle remains close to ILPkSOpt for all Line and Load conditions. In this way, UCC28056
attempts to maximize efficiency for all loads and for all Line voltages.
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Feature Description (continued)
8.3.2 Line Voltage Feed-Forward
The controller applies Line Voltage Feed-Forward to the COMP pin voltage (VCO) before it computes the TON and
TDCM durations. This sequence ensures that COMP voltage represents input power regardless of Line voltage
and ensures that Burst operation occurs at the same level of output power for all Line voltages. It also ensures
fixed gain between the COMP pin voltage and input power simplifying compensation of the voltage control loop.
GFF
§ VInMinPkL ·
¨
¸
© VInPkL ¹
2
(11)
For ease of computation, UCC28056
selected by a series of comparators
comparator to avoid repetitive changes
result. The comparator thresholds and
(PIn/VCO) does not vary by more than
VRMS).
employs seven discrete GFF levels, the most appropriate value being
monitoring the peak input voltage level. Hysteresis is built into each
in the selected GFF value and the step change in Line current that would
GFF levels are selected to ensure that the demand to input power gain
±20% over the full Universal Line voltage range (between 90 and 264
8.3.2.1 Peak Line Voltage Detection
UCC28056 internally reconstructs the input voltage waveform for the purpose of Peak Line voltage sensing and
Zero Current Detection (ZCD). In DCM or CrM mode the cycle average voltage across the Boost inductor must
be zero. UCC28056 generates an internal representation of input voltage by extracting the Drain waveform from
the ZCD/CS pin waveform and filtering it to extract the average Drain voltage across a switching cycle (VInSyn(θ))
The digital peak detector selects the value of GFF based upon the highest comparator threshold crossed over the
period THLinMax . The switch to a higher GFF value is implemented as soon as the corresponding threshold is
crossed. The switch to a lower GFF value is only implemented once the period THLinMax expires and the peak
detector has captured the Line voltage peak. The THLinMax timer is not synchronized to the Line operating
frequency.
Prior to the start of switching operation, at power - up or after a Burst - OFF period, the ZCD/CS pin voltage is
sampled and used to select the appropriate starting GFF level. This method assumes that the input rectifier and
capacitor after the rectifier bridge have captured the peak Line voltage during the period of no switching.
1.5
Line Voltage Rising
Line Voltage Falling
1.4
1.3
Normalized Gain
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
80
90
100
110
120
130
140
150
160
170
180
190
200
210
Line Voltage (RMS)
220
230
240
250
260
270
280
D001
Figure 20. Normalized Gain vs Line Voltage
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Feature Description (continued)
8.3.3 Valley Switching and CrM/DCM Hysteresis
The UCC28056 controller achieves maximum efficiency enabling power switching operation when the drain
voltage of the MOSFET is at a minimum (sometimes referred to as valley), of the resonance that occurs during
the TDCM period . Any energy stored in the Drain node capacitance (CDE ) dissipates in the power switch during
its turnon transition time. Valley switching ensures minimum energy is stored in CDE prior to the turnon period
and hence minimum switching loss. After the TDCM period, the controller waits for the next available valley on the
drain voltage before initiating a new switching cycle. The actual TDCM duration is therefore always an integer
multiple of the drain resonance period. If the calculated TDCM period extends over a valley boundary the actual
TDCM duration steps up in value by one resonant period. This step change in TDCM duration causes a step
change in Line current that rapidly decays as the TON(θ) computation iterates to a new solution to reflect the step
change in TDCM duration. Line current distortion, resulting from valley transitions, is kept to a minimum by
computing the TDCM duration from the COMP voltage. The COMP voltage varies little over the period of a Line
cycle and hence the calculated TDCM duration changes very little over the period of a Line cycle.
Line current distortion is particularly severe during the transition from the first valley (CrM) to the second valley
(DCM) operation while the input voltage is low. In this region, the first valley duration is extended by the clamping
action of the power switch body diode. In this region Line current is reduced when switching on the first valley,
(CrM) , because the inductor current is negative at the start of the on period. The reduction in Line current is not
observed for second or subsequent valley (DCM) operation because the inductor current starts the on period
from zero. UCC28056 implements hysteresis in the TDCM computation to virtually eliminate the possibility of
repeated CrM/DCM transitions across a Line cycle. Such transitions can only occur if the twice Line frequency
ripple on the COMP voltage is greater than 12% at the CrM/DCM boundary.
First Valley Ipk Err
IL(t)
VDS(t)
VIn
First Valley Ipk Err
0
DRV
TON
TZCDR
TON
TZCDR
Figure 21. Drain Voltage and Inductor Current Transitioning from DCM to CrM
8.3.3.1 Valley Delay Adjustment
The UCC28056 delivers maximum efficiency when controlling power stages that have widely differing natural
resonant frequencies. The application achieves this efficiency because the designer externally programs the
delay between the ZcdVIn comparator crossing and the rising edge of DRV (TZCDR). Ideal valley switching for
different power stage designs that may have very different natural resonant frequencies.
The TZCDR delay can be set to one of eight different values (TZCDR0 – TZCDR7) by setting the value of a resistor
(RDG) connected externally between the DRV and GND pins. During the startup period or when recovering from a
long fault, the controller transitions from the Stopb state to the RDGRdb state and then to the BstOffb state.
While in the RDGRdb state, an internal current source (IDG) transitions to the DRV pin. The the voltage that
results from this current determines the appropriate TZCDR delay. The controller uses this delay period for all
valley switching operation until a long fault causes the controller to return to the Stopb state.
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Feature Description (continued)
After entering its RDGRdb state, the controller waits for TDGSmpl before reading the pin voltage. To ensure that
the controller consistently detects the external resistance value correctly, do not allow the total external
capacitance connected between the DRV and GND pins to exceed 12 nF.
8.3.4 Transconductance Amplifier with Transient Speed-up Function
The voltage error amplifier is a transconductance amplifier. Voltage loop compensation connects from the error
amplifier output, COMP, to ground. The recommended type-2 compensation network is shown in . For loopstability purposes, the controller calculates the compensation network values based on small-signal perturbations
of the output voltage using the nominal transconductance gain gM.
VOSNS
+
1
6
VOSReg
COMP
VCOClmp
CCO
RCODisch
D
TONb
Stopb
CCO1
GND
Ovp2Fltb
R
RCO
Q
>CLK
GND
GND
Figure 22. Transconductance Error Amplifier with Typical Compensation Network
To improve the transient response to large perturbations, the error amplifier gain increases by a factor of six
times (6×) when the error amplifier input deviates more than ±3% from the nominal regulation voltage, VOSReg.
This increase allows faster charging and discharging of the compensation components to recover from step
changes in load current.
8.3.5 Faults and Protections
The UCC28056 includes a comprehensive set of protection features to ensure safer and more robust operation
during all operating conditions.
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Feature Description (continued)
8.3.5.1 Supply Undervoltage Lockout
Supply undervoltage lockout (UVLO) protection ensures that the controller operates only while the supply voltage
is in a range that ensures correct operation and adequate Gate drive amplitude for the power switch.
The controller remains in a dormant state, consuming little ICC current (ICC_Startup), until the VCC pin voltage
exceeds VCCStart. Once VCCStart is exceeded, the controller wakes into its Stopb state. After waking, the controller
proceeds with its normal start-up process.
The controller stops switching if the VCC pin voltage falls below VCCStop for a longer period than TUVLOBlk. The
controller then returns to a dormant condition. During this dormant period, the controller consumes a relatively
small amount of supply current (ICC) until it exceeds the VCCStart threshold again.
8.3.5.2 Two Level Over-Current Protection
The UCC28056 controller includes two overcurrent protection mechanisms to deliver safe robust protection
without danger of false tripping during operating transients. During the ON period of the switch, a current sense
resistor (RCS) connected in the source lead of the power switch senses the inductor current. The ZCD/CS pin
detects the voltage across the current sense resistor. Equation 12 dscribes the current sense voltage signal
applied to the ZCD/CS pin. Typically the second term in the bracket is much smaller than current sense resitance
value (RCS ) and can be neglected.
§
·
RZC2
VZC t IL t u ¨ RCS RDSON u
¸ | IL t u RCS
RZC1 RZC2 ¹
©
(12)
IL(t)
RZC1
2
RDSON x IL(t)
ZCD/CS
RZC2
VZC(t)
RCS x IL(t)
GND
GND
Figure 23. Equivalent Circuit of External Current Sense Network
8.3.5.2.1 Cycle-by-Cycle Current Limit Ocp1
Cycle-by-cycle peak current protection (Ocp1) terminates the on-time (TON) duration early if the current sense
voltage rises above 0.5 V. This current protection method limits the peak inductor current, thus avoiding inductor
saturation or damage to the power stage. When cycle-by-cycle current limit is active, it impacts Line current
distortion, but in all other respects normal switching operation continues and the controller maintains output
regulation.
The controller applies leading edge blanking to the current sense voltage signal. This application ensures that the
leading edge current spike caused by discharging CDE does not cause the Ocp1 comparator to terminate the
DRV pulse too early.
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Feature Description (continued)
8.3.5.2.2 Ocp2 Gross Over-Current or CCM Protection
A second comparator (Ocp2) with a higher threshold, and shorter blanking time, also monitors the current sense
voltage signal. If triggered, this second Ocp2 comparator also terminates the current on-time (TON) duration early.
In addition, if the controller triggers the Ocp2 comparator on three consecutive switching cycles, it also triggers a
long fault. The long fault halts switching operation and prevents restart for a period TLongFlt. After this delay, the
controller proceeds with its normal start-up process. In all transient or mild fault conditions the Ocp1 comparator,
with its lower threshold, triggers first and prevents the Ocp2 comparator from acting. The Ocp2 comparator acts
only if there is a gross fault such as a shorted output capacitor or bypass diode.
Under some fault conditions, including output overload, inductor current may become continuous because the
reset voltage is low. In this case even the relatively short Ocp1 blanking time may allow the inductor current to
continue ramping up. The UCC28056 controller addresses this condition by reducing the switching frequency to
allow a longer period for the inductor current to ramp down between on-time pulses.
The maximum allowed diode conduction period (TDCHMax) is doubled in the sequence (250 µs, 500 µs, 1000 µs)
each time the on-time duration terminates early by either one of the OCP comparators. If there is no ZCD signal
to indicate that the inductor current has fallen to zero, then the TDCHMax interval must expire before the next
switching cycle so the switching frequency is halved. The TDCHMax period is halved to reverse the sequence each
time the on-time period does not terminate early by one of the OCP comparators to restore the switching
frequency. If the ZCD signal indicates that inductor current has reached zero, then TDCHMax has no effect and
normal operation resumes automatically.
8.3.5.3 Output Over-Voltage Protection
The UCC28056 controller provides two independent forms of output over-voltage protections. This is done to
ensure that no single fault can result in excessive output voltage.
8.3.5.3.1 First Level Output Over-Voltage Protection (Ovp1)
The VOSNS pin monitors output capacitor voltage via an external resistor divider comprising ROS1 and ROS2. An
internal comparator (Ovp1) monitors the VOSNS pin voltage (VOS). If the voltage on this pin rises above
VOvp1Rise, indicating excessive output capacitor voltage, then the controller transitions to its BstOffb state. In this
state switching halts to prevent further increase in the output capacitor voltage. The controller returns to the Runb
state, and resumes switching operation, only after VOS falls below VOvp1Fall, indicating that the output voltage has
returned to normal range. To limit audible noise, the on-time pulse duration ramps during the transition between
Runb and BstOffb states. This ramp method is identical to that for Burst Mode operation.
8.3.5.3.2 Second Level Over-Voltage Protection (Ovp2)
During the TDCH period when the Boost diode is conducting, (and neglecting impedance in series with the Boost
diode) the voltage across the MOSFET approximates to the output voltage. The controller monitors the voltage
across the MOSFET via an external divider network connected to the ZCD/CS pin. This monitoring provides a
second independent method to detect excessive output voltage in case the VOSNS pin divider becomes
damaged. An Ovp2 comparator with a fixed threshold (VOvp2Th) monitors the ZCD/CS pin voltage during the TDCH
period. A fixed blanking period (TOvp2Blk) is applied after the falling edge of the DRV waveform to ensure that the
Ovp2 comparator is not tripped by inductive spikes on the leading edge of the Drain waveform.
The UCC28056 controller can operate with an in-rush limiting NTC resistor located on the load side of the Boost
MOSFET. Placing the NTC resistor in this location allows the use of a smaller controller with reduced current
rating and delivers better efficiency. The voltage drop across the series resistance introduced by the NTC,
particularly when cold, causes a voltage drop across the Boost MOSFET that is higher than the output voltage,
for example during the early part of the TDCH period when the current flowing through the Boost diode and NTC
resistor is highest. The excess voltage across the Boost MOSFET caused by the a cold NTC has two important
consequences:
• It may cause the Ovp2 comparator to be tripped when the output voltage is not excessive.
• Excessive voltage stress applied to the Boost MOSFET, during a cold start, may cause it to be damaged.
22
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Feature Description (continued)
The UCC28056 triggers an Ovp2 fault if the time between the falling edge of the Ovp2 comparator output and the
Zcdb signal is less than TOvp2En for three consecutive switching cycles. The series impedance required to trigger
a false Ovp2 fault is greatly increased because the Ovp2 comparator must be tripped close to the Zcdb point
when the current flowing through the NTC resistor is small.
An internal discharge resistor (RCODisch) between the COMP and GND pins connected for each switching cycle
causes the Ovp2 comparator to trip. This internal resistance discharges the external compensation network
reducing power demand and therefore the peak current flowing through the NTC resistor. The internal COMP
discharge resistor remains connected for any switching cycle that triggers the Ovp2 comparator. The internal
COMP discharge resistor becomes disconnected after the first switching cycle that does not trigger the Ovp2
comparator. By limiting the peak current flowing through the cold NTC resistor, the effect of this circuit is to limit
the peak voltage stress applied to the Boost MOSFET during a cold start.
VZC(t) ± Cold NTC
VOvp2Th
VZC(t) ± Hot NTC
IL(t)
DRV
Ovp2Fltb
TOvp2Blk
TOvp2En
Zcdb
Figure 24. Waveforms to Illustrate Ovp2 Operation
8.3.5.4 Thermal Shutdown Protection
The controller includes an internal temperature sensor. During the switching period, the controller triggers a
Thermal ShutDown (TSD) fault if the internal silicon temperature exceeds TTSDRise for three consecutive switching
cycles. The TSD fault halts switching operation and causes the controller to transition to its Stopb state for a
period TLongFlt. After this delay the controller continues the normal start-up process.
The controller does not exit the Stopb state to begin switching operation while the internal silicon temperature is
above TTSDFall.
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Feature Description (continued)
8.3.5.5 Line Under-Voltage or Brown-In
The input rectifier and capacitor form an analog peak detector that accumulates the peak Line voltage applied to
the input. This peak Line voltage appears across the Boost MOSFET. The controller observes peak Line voltage
via the external divider network attached to the ZCD/CS pin. The Line voltage start comparator does not allow
the controller to exit the Stopb state until the ZCD/CS pin voltage rises above the VZCBoRise threshold. This
behavior ensures that switching operation does not start until the Line voltage is high enough (85 VRMS) to deliver
full output power. During switching operation, the controller continues to operate regardless of the Line voltage,
until a fault causes it to enter a Stopb state.
8.3.6 High-Current Driver
An integrated, high-current driver allows the UCC28056 controller to drive the power MOSFET switch directly.
The controller limits the voltage applied to the DRV pin to VDRHigh. This limit enables a high VCC supply rail to
drive the controller without exceeding the VGS voltage rating of the power MOSFET. This limit also reduces
power dissipation in the internal gate driver when the controller operates from a VCC rail that is higher than
VDRHigh.
The integrated driver is protected against temporary short circuit of the DRV and GND pins.
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8.4 Controller Functional Modes
8.4.1 Burst Mode Operation
The UCC28056 controller provides leading light-load efficiency and standby power by implementing Burst mode
of operation with the following key features:
1. Power during burst is controlled to be approximately 11% of maximum output power for UCC28056/C and
16% of maximum power for UCC28056A/B for all Line voltage levels.
2. During the Burst OFF period, the current consumption of UCC28056 drops to less than 132 μA.
3. The TON pulse width is ramped up over the first four cycles, and ramped down over the last four cycles of
each Burst-on period. This Soft-ON/OFF scheme ramps the Line current at the edge of each Burst ON
period to limit audible noise and disturbance of the EMI filter.
Two comparator thresholds applied to the COMP pin voltage provide Burst Mode Operation. Switching halts after
four soft-OFF cycles when the COMP pin voltage falls below the VBstFall threshold. Switching resumes with four
Soft-ON cycles, when the COMP pin voltage rises above the VBstRise threshold. The average voltage of these two
thresholds represents approximately 11% VCOMaxfor UCC28056/C and 16% VCOMax for UCC28056A/B. The
power delivered during Burst ON is approximately 11% of maximum input power for UCC28056/C.
Faultbn
Stopb
RDGRdb
Fstopb
SoftOFFb
IinitTOb
SSCntb=1
BstRunbn +Ovp1Fltb
Runb
BstOffb
BstRunb & Ovp1Fltbn
SSCntb = 4
SoftONb
Figure 25. Fault and Burst Mode State Diagram
8.4.2 Soft Start
During Stopb state operation, an internal resistor (RCODisch) is connected between the COMP and GND pins to
discharge the external compensation network. Start-up transitions through the BstOffb state and switching
commence only after the COMP pin voltage rises above the VBstRise threshold. Switching therefore always starts
with the power demand at 12.5% of its maximum value. The Soft-ON feature ensures that the on-time period
ramps up over the first four switching cycles to the demanded value. These features limit audible noise at startup.
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Controller Functional Modes (continued)
Because the controller enables the error amplifier fast transient gain a startup, the input power ramps to
maximum at a rate limited only by the time constant of the external compensation network. This condition
ensures that the output capacitance charges rapidly to limit start-up delay.
26
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC28056 controller can be used in a wide range of applications in which a PFC stage is needed. This
design example demonstrates the features of the controller.
• EVM hardware
• Excel design calculator
9.2 Typical Application
Figure 26 shows a typical application of the UCC28056 as a preregulator with high power factor and efficiency.
The assembly consists of two distinct parts
• the control circuit centering on the UCC28056
• the power section
The power section is a Boost converter, with the inductor operating in Transition Mode (TM/CrM) or
Discontinuous Mode (DCM) according to Line and Load.
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Figure 26. Typical Application Circuit for 165-W Pre-Regulator
28
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9.2.1 Design Requirements
For this design example, use the parameters listed in the table below as the input parameters.
Table 1. System Design Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
AC Voltage range
85
265
VAC
AC Voltage frequency
47
63
Hz
165
W
OUTPUT CHARACTERISTICS
Output Power, POutMax
85 VAC to 265 VAC
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28056 controller with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters (efficiency, footprint,cost) using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Power Stage Design
The first step in the power stage design is to calculate the PFC inductor value needed to achieve the
specification, then the ratings for all other power components can be computed.
9.2.2.2.1 Boost Inductor Design
The minimum equivalent resistance presented, to the Line, by the input of the Boost PFC stage changes
according to the current Line Feed-Forward setting. RInEqMin0 and RInEqMin1 present the minimum equivalent input
resistance for the first two Line Feed-Forward levels.
2 u LBST
RInEqMin0
TONMAX0
(13)
RInEqMin1
2 u LBST
TONMAX0 u GFF1
(14)
Equation 15 calculates the maximum input power that can be drawn from a given Line voltage. The maximum
input power is set to 110% of POutMax to account for power stage efficiency.
PInMax
VInRMSMin2
RInEqMin
110% u POutMax
(15)
Equation 16 calculates the Boost inductance value required to ensure that maximum load can be delivered from
minimum Line voltage.
LBST0
VInRMSMin2
T
u ONMAX0
110% u POutMax
2
255 PH
(16)
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Ensure that POutMax can be delivered from the lowest Line voltage for GFF1. Use Equation 17 to calculate the
required Boost inductor value .
LBST1
K ZC u VFF0Fall
2
110% u 2 u POutMax
u
TONMAX0 u G FF1
2
235 PH
(17)
Choose the lower of the two values calculated in Equation 16 and Equation 17 (LBST0 and LBST1). Using a smaller
inductance value compromises light load efficiency. A larger inductance value cannot deliver the required
maximum load power (POutMax) across the required range of Line voltage.
Choose a Boost inductor value of 200 µH, considering a tolerance of 10%. In order to deliver maximum load
power the inductor must be able to operate with a peak current that is greater than both ILPk0 and ILPk1
LBST 200 PH
(18)
ILPk0
VInRMSMin u 2 u TONMAX0
LBST
ILPk1
K ZC u VFF0Fall u TONMAX0 u GFF1
LBST
ILPk
ILPk0
7.69 A
(19)
6.24 A
(20)
7.69 A
(21)
Use Equation 22 to calculate a current sense resistance that ensures the required peak inductor current (ILPk)
does not cause early termination of the TON period.
VZCOcp1Min
RCS
0.06 :
ILPk
(22)
Achieve this amount of resistance by connecting three resistors in parallel.
1
RCS
0.062 :
2
1
0.125 : 3 :
(23)
Use Equation 24 to calculate an inductance value that allows a saturation current above the maximum Ocp1
current limit value.
VZCOcp1Max
ILSat
8.8 A
RCS
(24)
Maximum current in the power components flows while delivering maximum load when supplied from minimum
Line voltage. In this condition, the UCC28056 controller always operates in transition mode (CrM). shows the
inductor current waveforms for ideal CrM operation.
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ILPkS( )
ILRMS( )
ILAvS( )
0
Œ
ILPkS( )
IL(t, )
ILRMS( )
ILAvS( )
TON
0
TDCH( )
t
Figure 27. Ideal Transition Mode (CrM) Inductor Current
Equation 25 describes the he Boost inductor RMS current over a single switching cycle, at angle θ through the
Line half-cycle.
ILPkS T
2 u ILAvS T
V
2
u InPkL u sin T
ILRMS T
3
3
3 RInEqMin
(25)
Equation 26 describes the Boost inductor RMS current over a complete Line cycle.
S
ILRMS
1
u ILRMS T
S
³
2
dT
0
2
3
u
VInRMS
RInEq
(26)
Maximum Boost inductor RMS current occurs at minimum Line voltage and maximum input power.
2 110% u POutMax
u
ILRMSMax
2.5 A
VInRMSMin
3
(27)
Based upon the inductor requirements, a custom magnetic can be designed, or a suitable catalogue controller
selected.
Table 2. Inductor Requirements
Description
Value
Unit
Inductance
200
µH
RMS Current
2.5
A
Saturation Current
8.8
A
9.2.2.2.2 Boost Switch Selection
The power switch carries the Boost inductor current during its ON period (TON). It carries no current during its
OFF period (TDCH). Equation 28 describes the switch RMS current, over a single switching cycle, at angle θ in the
Line half-cycle.
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IMosRMS T
ILPkS T u
GMos T
3
www.ti.com
2u
G
T
VInPkL
u sin T u Mos
RInEq
3
(28)
Equation 29 describes the duty cycle of switch conduction for ideal transition mode (CrM) operation.
TON
GMos T
TON TDCH (T)
(29)
The switch ON time is constant across the Line cycle but the OFF time varies according to the position in the
Line cycle. Volt-second balance across the Boost inductor, within each switching cycle, requires that.
TDCH T
TON
VIn T
VOut
VIn T
(30)
Equation 31 calculates the duty cycle of switch conduction.
V
GMos T 1
2 u InRMS u sin T
VOut
(31)
Equation 32 describes the RMS switch current across a complete Line half-cycle.
S
IMosRMS
1
u IMosRMS T
S
³
2
dT
0
VInRMS
4
u
RInEq
3
32 u 2 u VInRMS
9 u S u VOut
(32)
Maximum RMS current in the switch occurs at maximum load and minimum Line.
IMosRMSMax
110% u POutMax
4
u
VInRMSMin
3
32 u 2 u VInRMSMin
9 u S u VOut
2.1 A
(33)
Use the following guidelines for MOSFET selection for the Boost switch.
• The voltage rating must be greater than the maximum output voltage. Under transient or Line surge testing
the output voltage may exceed the normal regulation level. For this design example, the MOSFET voltage
rating is 650 V supports a regulated output voltage of 390 V.
• Based upon an acceptable level of conduction loss in the MOSFET, the required on-resistance (rDS(on)) value
can be calculated from the maximum RMS current. For this example design an STF24N60DM2 MOSFET,
from STMicrolelectronics was selected with an on-resistance of 0.37 Ω, when TJ = 125°C which allows
maximum conduction power loss (less than 1.7 W) in the MOSFET.
• For best efficiency, use a MOSFET that incorporates a fast body diode. Operation using discontinuous
inductor current (DCM) from a low input voltage incurs additional switching power loss if a MOSFET with slow
body diode is used.
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9.2.2.2.3 Boost Diode Selection
The Boost diode carries the Boost inductor current while the switch is OFF (TDCH), and carries zero current while
the switch is ON (TON). Equation 34 calculates The RMS diode current over a single switching cycle, at angle θ in
the Line half-cycle .
IDioRMS T
ILPkS T u
GDio T
3
2u
G
T
VInPkL
u sin T u Dio
RInEq
3
(34)
Equation 35 describes the duty cycle of Boost diode conduction for ideal transition mode operation .
V
GDio T 1 GMos T
2 u InRMS u sin T
VOut
(35)
Equation 36 describes the RMS Boost diode current across a complete Line half-cycle .
S
IDioRMS
1
2
u IDioRMS T dT
S
³
0
4 VInRMS
2 u 2 VInRMS
u
u
u
3 RInEq
VOut
S
(36)
The maximum RMS current in the Boost diode occurs at maximum load and minimum Line.
IDioRMSMax
4 110% u POutMax
2 u 2 VInRMSMin
u
u
u
3
VInRMSMin
VOut
S
1.3 A
(37)
Conduction power loss in the Boost diode is primarily a function of the average output current.
POutMax
IDioAVGMax
0.42 A
VOut
(38)
Use the previous calculations and these guidelines to select the Boost diode:
• Ensure that the Boost diode voltage rating exceeds the maximum output voltage. Under transient or Line
surge testing the output voltage may rise far above its normal regulation level.
• The Boost diode must have average and RMS current ratings that are higher than the numbers calculated by
Equation 37 and Equation 38.
• Diodes are available with a range of different speed/recovery charge. Fast diodes, with low reverse recovery
charge, typically have higher forward voltage drop. Fast diodes have higher conduction loss but lower
switching loss. Slow diodes, with high reverse recovery charge, typically have lower forward voltage drop.
Slow diodes have lower conduction loss but higher switching loss. Ensure maximum efficiency by matching
the diode speed rating to the application.
• When Line voltage is first applied, to the Boost converter input, an uncontrolled current flows through the
Boost diode while the output capacitor charges to the Line voltage peak level. The charging current is limited
only by the impedance of the Line and EMI filter stage, and may reach a very high magnitude during the
output capacitor charging period. Any diode carrying this current must be rated to carry this non-repetative
surge current. It is normal practice to add a bypass diode to divert most of this charging current away from
the Boost diode. The bypass diode can be a slow type with lower forward voltage drop. It is therefore cheaper
and more robust than the faster Boost diode.
• For this example design the STTH5L06 diode from STMicroelectronics® was selected. This diode has a
voltage rating of 600 V and an average current rating of 5 A. It has a forward voltage drop of approximately
0.85 V giving a conduction loss in the Boost diode, of less than 0.5 W.
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9.2.2.2.4 Output Capacitor Selection
Power drawn by the PFC stage from the Line supply may be represented by the following expression.
PIn T
2 u VInRMS u IInRMS u sin T
2
(39)
Assuming a typical application, with constant load power, for some parts of the Line cycle excess power is drawn
from the supply and stored in the output capacitor. In other parts of the Line cycle load power exceeds input
power and this deficit must be supplied from the output capacitor. This process of energy transfer to an from the
output capacitor necessarily results in twice Line frequency output voltage ripple. The amplitude of this twice Line
frequency ripple depends only upon the ratio POut/COut and the Line frequency.
POut
1
'VOutpp
u
COut 2 u S u fLine u VOut Re g
(40)
Choose an output capacitor value by prioritizing one of a number of application requirements:
• Twice Line frequency output ripple voltage at maximum load.
• Output voltage hold-up time after the Line supply has been disconnected.
• Output voltage deviation as a result of a transient load step.
For this design example assume that the twice Line frequency output ripple voltage amplitude is less than 3% of
its regulation level. The POutMax/COut ratio required to achieve this can be calculated using Equation 41
POutMax
W
t 2 u S u fLine u VOut Re g2 u 3% 1.43
PF
COut
(41)
Use Equation 42 to calculate the required capacitance value for this 165-W example design.
165W
COut t
115 PF
W
1.43
PF
(42)
For best Line current total harmonic distortion (THD), the maximum output voltage ripple amplitude must satisfy
the condition presented in Equation 43. Satisfying this condition ensures that the error amplifier non-linear gain
does not activate due to extremes of the output voltage ripple.
'VOutpp 2 u DSuThs
5.4%
VOut Re g
VOSRe g
(43)
Use Equation 44 to calculate the maximum RMS ripple current flowing in the output capacitor.
ICOutRMSMax
IDioRMSMax
2
§ POutMax ·
¨
¸
¨ VOut Re g ¸
©
¹
2
1.19 A
(44)
This current flowing into the output capacitor includes a switching frequency component (ICOutRMSHF) and a twice
Line frequency ripple component (ICOutRMSLF).
P
1
u OutMax 0.3 A
ICOutRMSLF
2 VOut Re g
(45)
ICOutRMSHF
34
IDioRMSMax
2
3 § POutMax ·
u¨
¸
2 ¨© VOut Re g ¸¹
2
1.15 A
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Electrolytic capacitors typically have a ripple current rating at twice Line frequency (120 Hz) and a different ripple
current rating at switching frequency (100 kHz). These ratings reflect the fact that the capacitor ESR is higher at
twice Line frequency and hence ripple current at this frequency leads to higher power loss than the same
amplitude of switching frequency ripple. Consider the equivalent high-frequency ripple current flowing in the
capacitor in order to select the correct capacitor.
ICEquRMSHF
ICOutRMSLF2 u KHLF2
ICOutRMSHF2
(47)
The parameter KHLF is the ratio of high frequency to low frequency RMS ripple current rating for the particular
capacitor series to be used.
100kHz _ ripple _ current _ rating
KHLF
120Hz _ ripple _ current _ rating
(48)
In this example design, for reasons of size and rating, two 68-µF, 450 V capacitors are selected from Rubycon
BXW series (450BXW68MEFC12.5X45), connected in parallel. In this way, both the capacitance value
requirement and ripple current rating are met with some additional margin.
COut 2 u 68 PF 136 PF
(49)
ICEquRMSHF
0.3 A
2
§ 1.525 ·
u¨
¸
© 0.610 ¹
2
1.15 A
2
1.37 A
(50)
9.2.2.3 ZCD/CS Pin
An external divider network attached to the ZCD/CS pin transfers both the attenuated Drain voltage waveform
(VDS) and the current sense signal (VCS) into the controller. This transfer is possible because the current sense
signal requires observation only when the switch is ON and the VDS signal is close to zero. While the Drain
voltage waveform requires sensing only when the switch is OFF and the current sense signal is close to zero.
ZZC2
VZC t
VCS t
VDS t u
ZZC1 ZZC2
(51)
Equation 52 describes the attenuated Drain voltage during the on-time period when the MOSFET is switched
ON.
VZC t
§
IL t u ¨ RCS
©
RDSON u
·
Z ZC2
¸
Z ZC1 Z ZC2 ¹
(52)
The ON state resistance of the MOSFET (RDSON) typically has a similar value to the current sense resistor (RCS).
The attenuation of the divider (ZZC1, ZZC2) is 1/401 and hence the second term of Equation 52 may be neglected.
VZC t
IL t u RCS
(53)
Hence the required current sense resistor value can be calculated from the maximum peak inductor current
obtained in section 9.2.2.2.1
Outside the TON period, when the MOSFET is switched OFF, the current flowing through the current sense
resistor is close to zero. In this case Equation 51 may be expressed as follows.
Z ZC2
VZC t
VDS t u
Z ZC1 Z ZC2
(54)
UCC28056 prevents the start of a new switching cycle until increasing negative slope is detected on the ZCD/CS
pin voltage waveform. The increasing negative slope indicates that the inductor current has fallen to zero so the
output diode is already OFF. Turn-ON switching loss is further reduced by synchronizing the start of each new
switching cycle with a minimum, or valley, on the Drain waveform.
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In theory, a simple resistor divider can be used to attenuate the Drain voltage waveform fed into the ZCD/CS pin.
In practice, the parasitic capacitance associated with the PCB traces and the ZCD/CS pin filter the attenuated
signal and introduce phase shift. The resulting distortion and phase shift negatively impact the ability of the part
to synchronize to the zero inductor current transitions. The problem is compounded by the need to limit power
dissipation in the resistive divider, which dictates the use of high resistance values, and increased filtering of the
attenuated signal.
Add a capacitor divider in parallel with the resistor divider in order to use of high value resistors without
introducing filtering and associated phase shift. In this case, ensure that the reactive divider ratio is equal to the
resistor divider ratio.
R ZC2
X ZC2
R ZC1 R ZC2 X ZC1 X ZC2
(55)
Hence:
R ZC1
R ZC2
CZC2
CZC1
(56)
There are number of internal voltage thresholds driven by the attenuated Drain voltage signal supplied to the
ZCD/CS pin. These include Brown-Out (VZCBoRise), Line feed-forward (VFFxRise, VFFxFall) and second output overvoltage (VOvp2Th). The same external divider ratio (KZC) drives all of these thresholds. Scope to vary the
attenuation ratio specified is limited because it impacts all of these thresholds in unison.
R ZC1
K ZC
1 401
R ZC2
(57)
VInRMSBoRise
VZCBoRise u
K ZC
85.1 V
2
(58)
The controller infers Line voltage from the switching cycle average voltage on the Drain node. Neglecting any
resistive voltage drop in the Boost inductor this must be equal to the voltage supplied from the input rectifier,
provided the Boost inductor current returns to zero at the end of each cycle (TM/CrM/DCM). Voltage drops in the
input rectifier bridge and EMI filter stage cause an error between predicted and measured threshold values. An
internal peak detector determines the peak input voltage across a Line half-cycle. Equation 58 above converts
this peak value to an RMS quantity, but assumes an ideal sinusoidal Line supply
Equation 59 calculates the output voltage required to trigger the second output overvoltage comparator (Ovp2).
VOutOvp2 VOvp2Th u K ZC 451 V
(59)
This parameter is observed via the Drain waveform, voltage drops in the Boost Diode and series NTC resistor,
causes the Ovp2 comparator to trip at a lower output voltage level.
Power dissipation in the Drain sensing resistor divider chain reaches its highest value during the Burst OFF
condition. During the Burst OFF condition, the Drain voltage approximates a DC voltage equal to the Line voltage
peak. This approximation assumes the time constant CIN × (RZC1+ RZC2) is long compared with a Line halfperiod. Under no-load conditions, the Burst OFF duty cycle is high therefore maximum power dissipation in the
Drain sensing resistor divider chain, occurs at high Line and no-load, as described in Equation 60.
PZCMax
36
VInRMSMax 2 u 2
R ZC1 R ZC2
(60)
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Equation 61 calculates the maximum value of RZC1 c, allowing a budget of 1% error due to input bias current
(IZCBias), on the lowest voltage threshold (VZCBoRise).
RZC1 d
Err% u K ZC u VZCBoRise
IZCBias
1% u 2 u 85V
100nA
12.0 M:
(61)
The upper resistor in the divider chain (RZC1) must withstand the peak output voltage under a surge test. For a
rugged solution, the resistor(s) in this location must have a voltage rating above the avalanche rating of the
Boost MOSFET. This design uses a series chain of three 1206, SMT, 3.24 MΩ resistors for this location, which
yields DC voltage withstand capability above 600 V.
R ZC1 3 u 3.24 M: 9.72 M:
(62)
R ZC2
R ZC1
K ZC 1
24.3 k:
(63)
Use Equation 60 to calculate the power dissipation in the ZCD/CS pin divider resistors.
PZCMax
VInRMSMax 2 u 2
R ZC1 RZC2
14 mW
(64)
Once arranged on the PCB, the resistor divider circuit has some parasitic capacitance across both the upper
(RZC1) and lower (RZC2) resistors. Experience suggests a parasitic capacitance (CZC1) of approximately 0.1 pF
across resistor RZC1, when it is made up of three 1206 SMT components, assuming a compact PCB layout. In
theory this parasitic capacitance could be used to form the entire value of CZC1 and an appropriate value of CZC2
added to achieve the ratio required by Equation 56. In practice most designers choose to add an explicit
capacitor in this location to improve tolerance to small changes in layout, such as may occur when connecting
oscilloscope probes. Ensure the time constant for the divider does not extend over many switching cycles. This
limitation ensures that Line surge or system ESD transient events may disturb the ZCD/CS pin DC level but does
not persist over an excessive number of switching cycles.
Select a single 10-pF, 1000-V, 0805 SMT capacitor with 5% tolerance.
CZC1 10 pF
(65)
Use Equation 66 calculate the lower divider capacitor value.
CZC2 K ZC u CZC1 4.01nF
(66)
In practice, once the final PCB layout is complete, adjust the lower capacitor value to account for parasitic
capacitances present on the PCB. Consider both the Drain and ZCD/CS pin waveforms and adjust the lower
capacitance value (CZC2) until the value allows the required ratio in signal amplitude. Use a low capacitance
probe for the ZCD/CS pin connection. Figure 28, Figure 29 and Figure 30 present the type of waveforms that
occur during this tuning process.
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CH1 = VDS
CH3 = VCO
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CH2 = VDR
CH3 = VZC
CH1 = VDS
CH3 = VCO
Figure 28. Amplitude VZC < (VDS/401). Reduce CZC2
Capacitance
CH1 = VDS
CH3 = VCO
CH2 = VDR
CH3 = VZC
Figure 29. Amplitude VZC = (VDS/401). Correct CZC2
Capacitance
CH2 = VDR
CH3 = VZC
Figure 30. Amplitude VZC > (VDS/401). Increase CZC2 Capacitance
9.2.2.3.1 Voltage Spikes on the ZCD/CS pin Waveform
Voltage offset on the ZCD/CS pin is likely to result from high-amplitude switching edge spikes on the waveform
applied to this pin. These switching edge spikes are clamped by any non-linear controller, such as the internal
ESD structures, and upset the DC operating point of the divider. This can be observed as a voltage offset on the
ZCD/CS pin signal, particularly at times when rate of change of current is highest (high load around the Line
voltage peaks). When designing the ZCD/CS pin divider, prevent it from picking up switching edge spikes. Use of
a low inductance type current sense resistor is also important for the same reason. If necessary an RC filter, with
a time constant of approximately 30 ns, may be added between the voltage divider and the ZCD/CS pin to
attenuate switching edge spikes. Ensure the capacitance (CZC3) of this filter is small relative to the value of CZC2.
Limit the error introduced by the R-C filter to less than 1%, by ensuring that the series resistance is below the
value calculated in Equation 67.
VZCBoRise
RZC3
u 1% 30 k:
IZCBias
(67)
38
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For this example design, the following values were selected for the RC filter to attenuate switching edge spikes.
R ZC3 3 k:
(68)
CZC3
10pF
(69)
9.2.2.4 VOSNS Pin
The VOSNS pin voltage is applied to the inverting input of an internal trasnconductance error amplifier. A fixed
reference voltage (VOSReg) being applied to the non-inverting input. The error amplifier has high gain hence in
steady-state, assuming VCOMP < 5-V, average voltage on the VOSNS pin must be approximately equal to the
reference voltage (VOSReg). Output voltage regulation set point (VOutReg) is therefore determined by the external
resistor divider network connecting the output voltage to the VOSNS pin according to the following expression.
VOut Re g
§R
VOSRe g u ¨ OS1
© ROS2
·
1¸
¹
(70)
The resistive divider that feeds the VOSNS pin makes a significant contribution to the unloaded input power.
Higher resistor values reduce power consumption of the divider.
VOut Re g2
POSDiv
ROS1
ROS2
(71)
Regulation accuracy degrades with increased resistor values due to the effect of VOSNS pin bias current
(IOSBias).
'VOSRe g IOSBias u ROS1
VOSRe g
VOut Re g
(72)
To ensure that VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage
divider resistor value must be constrained as show in Equation 73.
'VOSRe g VOut Re g
390 V
u
ROS1
1% u
39 M:
VOSRe g
IOSBias
100 nA
(73)
Equation 73 confirms that reduction of the VOSNS divider dissipation to below 4 mW does not negatively
affecting the regulation accuracy.
The PFC stage, of this design example, is to be followed by an LLC stage, that is controlled by UCC256301
device. The UCC28056 controller and the UCC256301 device operate together to form a complete off-Line
power supply system with excellent light-load efficiency and standby power. To limit no-load input power a single
resistor divider feeds both the VOSNS pin (UCC28056) and the BLK pin (UCC256301). A resistor divider with
two taps is required because the UCC28056 requires a different divide ratio (KOS) to that required for the
UCC256301 device (KBLK). The upper divider resistor (ROS1) is divided into two parts (ROS11, ROS12) to achieve
the additional tap.
VOut Re g ROS11 ROS12 ROS2
KOS
156
VOSRe g
ROS2
(74)
KBLK
ROS11 ROS12 ROS2
ROS12 ROS2
108
(75)
For this design example select an upper divider resistor made up of three series-connected, 3.24-MΩ, 1206 SMT
resistors. This compact and cost-effective design produces a suitable high-voltage resistor. If a single resistor is
preferred, use a high voltage type, rated for the maximum voltage that can appear across the output capacitor
during a Line surge test.
ROS11 3 u 3.24 M: 9.72 M:
(76)
Solving Equation 74 and Equation 75 simultaneously results in:
ROS12
·
ROS11 § KOS 1
1¸
u¨
KOS
K
1
© BLK
¹
27.95 k:
(77)
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ROS11 ROS12
K OS 1
ROS2
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62.89 k:
(78)
These two divider resistor values can be implemented using easily obtainable values as follows:
ROS2 75 k: / / 390 k: 62.9 k:
ROS12
36.5 k: / / 120 k:
28.0 k:
(79)
(80)
Actual regulation set point is therefore:
ROS11 ROS12 ROS2
VOut Re g
u VOSRe g
ROS2
390 V
(81)
Power dissipated in the VOSNS resistor divider is:
POSDiv
VOut Re g2
ROS11
ROS12
ROS2
15.5 mW
(82)
9.2.2.5 Voltage Loop Compensation
The design of the voltage control loop of a PFC stage is requires compromise. The voltage control loop must be
fast to achieve a good transient response to steps in load current, but tTo minimize distortion of the Line current
it must be slow. This section describes the selection of compensation components that deliver a target Line
current distortion and phase margin.
9.2.2.5.1 Plant Model
The first step is to produce a small signal model of the PFC Boost converter. A constant power load is assumed
to be connected across the output capacitor. This provides the most accurate representation of a switched mode
regulator delivering constant output voltage. The plant gain is assumed to be independent of Line voltage due to
the action of the internal Line voltage feed-forward circuit. Across the Universal Line voltage range (90 VRMS-264
VRMS), plant gain actually varies by ±-20% due to the quantized nature of the Line voltage feed-forward circuit.
vOut jZ
vCO jZ
GPlant jZ
1
u GPlant0
jZ
POutMax
1
u
jZ VCOMax u VOut Re g u COut
(83)
9.2.2.5.2 Compensator Design
The integrator response of the plant provides a gain roll off of –20dB/decade and introduces a phase lag of 90°.
A simple integrating compensation network provides unacceptable phase margin because it introduces a second
90° of phase lag into the voltage loop. To ensure adequate phase margin, use a type 2 compensation network to
provide the desired phase boost a the gain cross-over frequency. Equation 84 describes the mall-signal gain of
the error amplifier and type 2 compensation network.
§
·
1
1
¨ RCO
¸u
VOSRe g
j
C
j
CCO1
Z
u
Z
u
v CO jZ
CO ¹
GCtrl jZ
u gM u ©
1
1
v Out jZ
VOut Re g
RCO
jZ u CCO jZ u CCO1
(84)
Equation (84) may also be expressed as follows:
jZ
1
GCtrl0
2 u S u fZ
u
GCtrl jZ
jZ
jZ
1
2 u S u fP
where
fZ
40
1
2 u S u CCO u RCO
(86)
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fP
CCO CCO1
2 u S u CCO u CCO1 u RCO
GCtrl0
VOSRe g
VOut Re g
u gM u
(87)
1
CCO
CCO1
(88)
Rearranging Equation 86, Equation 87 and Equation 88 yields:
§ VOut Re g
·
f
1
u¨
u gM ¸
CCO1 Z u
¸
fP GCtrl0 ¨© VOSRe g
¹
fP fZ
CCO
u CCO1
fZ
RCO
(88)
(89)
(90)
1
1
u
2 u S u fZ CCO
(91)
For maximum phase Boost at the gain cross-over frequency, compensator design proceeds by placing the pole
and zero an equal distance above and below the gain cross-over frequency (fB) on the Bode plot. Because the
frequency axis is logarithmic this yields the following pole (fP) and zero (fZ) frequencies:
f
fZ B
K
(92)
fP fB u K
(93)
Phase margin of the loop is equal to the phase boost provided by the type 2 compensator, because the
underlying integrator characteristics of the plant and compensator combine to provide 180° of phase lag. To
achieve the desired phase margin (ΦPM) at fB the separation between the pole and zero frequencies may be
found by substituting Equation 92 and Equation 93 into Equation 85, and solving for K in terms of the phase
boost angle.
S·
§)
K tan ¨ PM
4 ¸¹
© 2
(94)
The next step is to select the desired phase margin. A typical phase margin range 45° to 75°. For this example
design a target phase margin of 65° is selected.
S
)PM 65q u
180q
(95)
S·
§)
K tan ¨ PM
4.51
4 ¸¹
© 2
(96)
The next step is to determine the loop gain cross-over frequency (fB). A faster loop, results in more twice Line
frequency ripple on the COMP pin voltage, leading to increased Line current distortion.
Begin by setting a target of 1% third harmonic distortion due to twice Line frequency COMP voltage ripple. To
achieve this target, the twice Line frequency COMP pin ripple must be less than 2% of the DC value during
steady-state full power operation. The design proceeds by selecting the loop gain cross-over frequency (fB) that
ensures twice Line frequency COMP pin ripple amplitude does not exceed 2% of its DC level.
Use Equation 97 to calculate twice Line frequency voltage ripple amplitude across the output capacitor.
POutMax
1
4.95 V
'VOut
u
VOut Re g 2 u 2 u S u fLine u COut
(97)
The output voltage ripple amplitude must be attenuated by the feedback network to meet our target of 2% ripple
amplitude on the COMP pin voltage.
VCOMax u 2%
GCtrl j2 u S u 2 u fLine
'VOut
(98)
Equation 99 simplifies Equation 98.
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0.0202
GCtrl0
K2
u 4 u S u fLine
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0.624 Hz
where
•
•
2 x fLine >> fP
2 x fLine >> fZ
(99)
Equation 100 describes unity at the gain cross-over frequency.
GPlant j2 u S u fB u GCtrl j2 u S u fB
1
(100)
Equation 100 can also be expressed as shown in Equation 101.
1
fB
u GPlant0 u GCtrl0 u K 6.66 Hz
2uS
(101)
Calculate the pole and zero frequencies using Equation 92 and Equation 93. Then determine the compensation
component values using Equation 89, Equation 90 and Equation 91.
f
fZ B 1.48 Hz
(102)
K
fP fB u K 30.0 Hz
(103)
CCO1
CCO
RCO
VOSRe g
fZ
1
u
u
u gM
fP GCtrl0 VOut Re g
fP
fZ
fP
u CCO1
25 nF
(104)
0.49 PF
(105)
1
1
u
2 u S u fZ CCO
220 k:
(106)
0
75
Gain_Plant
Gain_Ctrl
Gain_Loop
50
-30
-60
Phase (°)
Gain (dB)
25
0
-90
-25
-120
-50
-150
-75
0.1 0.2
0.5
1
2 3 4 5 7 10 2030 50 100 200
Frequency (Hz)
500 1000
-180
0.1 0.2
d001
Figure 31. Gain vs Frequency
42
Phase_Plant
Phase_Ctrl
Phase_Loop
0.5
1
2 3 4 5 7 10 2030 50 100 200
Frequency (Hz)
500 1000
d002
Figure 32. Phase vs Frequency
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98%
97.5%
97%
96.5%
96%
95.5%
95%
94.5%
94%
93.5%
93%
92.5%
92%
91.5%
91%
1
0.95
0.9
0.85
Power Factor
Efficiency (%)
9.2.3 Application Curves
0.8
0.75
0.7
0.65
0.6
0.55
85Vac
115Vac
230Vac
265Vac
85Vac
115Vac
230Vac
265Vac
0.5
0.45
0.4
0
20
40
60
80
100 120
Output Power (W)
140
160
180
0
20
40
d000
Figure 33. Efficiency vs Output Power
60
80
100 120
Output Power (W)
140
160
180
d000
Figure 34. Power Factor vs Output Power
20%
85Vac
115Vac
230Vac
265Vac
18%
THD (%)
16%
14%
12%
10%
8%
40
60
80
100
120
Output Power (W)
140
160
180
d000
Figure 35. THD vs Output Power
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10 Power Supply Recommendations
To operate UCC28056 must be powered from an external VCC supply voltage of 11 V to 34 V. To limit package
dissipation ensure that the supply voltage is not higher than 12 V. Locally decouple the VCC supply with a
capacitor of at least 1 µF connected between the VCC and GND pins using short PCB traces. The controller may
consume current from the VCC rail for a significant period of time; the exact duration depends upon Line and
load, before the output voltage (VOut) reaches regulation. The supply used to power the UCC28056 must be able
to source this energy during the period that output voltage attains regulation.
11 Layout
11.1 Layout Guidelines
11.1.1 VOSNS Pin
Locate the ROS2 and COS2 components adjacent to the VOSNS pin along with the lowest resistor(s) that comprise
ROS1. High voltage drops across the resistor(s) that comprise ROS1. Allow adequate spacing around the highvoltage nodes that connect to and within ROS1 to avoid air discharge across the PCB surface.
11.1.2 ZCD/CS Pin
Switching edge spikes imposed on the signal feeding this pin may cause the internal ESD structures to conduct,
causing a voltage offset to appear on the capacitive divider feeding this pin. To limit this risk, place the voltage
divider close to the ZCD/CS pin and far from the region of fast changing magnetic field. See the shaded area
show in Figure 37. Maintain a small number of nets between the resistors and capacitors in the divider to limit
capacitive pickup within the divider chain. Maintain the loop identified in Figure 36 small and contain the
minimum area to limit magnetic pickup. Run the connections between the current sense resistor and UCC28056
directly to the terminals of resistor and not be shared with power circuit traces.
When laying out the PCB start with the ZCD/CS pin divider placement and routing to ensure that the needs of
this pin come first.
11.1.3 VCC Pin
A local decoupling capacitor should be connected directly between the VCC and GND pins via short, dedicated,
PCB traces. This capacitor supplies the high current pulses needed to charge the gate capacitance of the power
MOSFET.
11.1.4 GND Pin
Be sure to separate the PCB traces for the GND net of the UCC28056 far from the power circuit GND net.
Connect the GND pin of the UCC28056 device to the power circuit GND at only one terminal of the current
sense resistor. This connection method ensures that the voltage between the UCC28056 device GND pin and
the ZCD/CS pins remains equal to the voltage across the current sense resistor during the MOSFET conduction
period.
11.1.5 DRV Pin
Avoid placing the DRV pin traces close to other high-impedance nets such as ZCD/CS or VOSNS. The fast rising
and falling edges associated with the waveform on this pin may capacitively couple onto these high impedance
nets causing disturbance near the switching edges.
11.1.6 COMP Pin
Locate the RC network attached to this pin close to the pin. Return to the GND pin should be via a short PCB
trace.
11.2 Layout Example
44
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Figure 36. Schematic with Layout Guidelines
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www.ti.com
RVCC
VEE
RCO
CCO
CCO1
ROS2b
ROS2a
COS2
COuta
ROS12a ROS11c ROS11b
COutb
ROS11a
CCC
ROS12b
RZC3
GND
CZC2a
CZC3
RZC1a
RDG
CZC2b
DDR
VCC
RDR1
RDR
Q1
RZC2
U1
RCSa
RCSb
JP4
CZC1
ZCD/CS
RZC1c
VOSNS
DRV
VOut+
RZC1b
COMP
JP5
VOut-
RCSc
CIn
NTC
DBST
LBST
D1
Top view. Copper pattern and SMT viewed through
board
Figure 37. Recommended PCB Layout
(Single-Sided Assembly)
46
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12 Device and Documentation Support
12.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28056 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
STMicroelectronics is a registered trademark of STMicroelectronics.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: UCC28056
47
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC28056ADBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805A
UCC28056ADBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805A
UCC28056BDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805B
UCC28056BDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805B
UCC28056CDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805C
UCC28056CDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
805C
UCC28056DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8056
UCC28056DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8056
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
UCC28056ADBVR
SOT-23
DBV
6
3000
178.0
9.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056ADBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056BDBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056BDBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056CDBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056CDBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
UCC28056DBVT
SOT-23
DBV
6
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28056ADBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
UCC28056ADBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
UCC28056BDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
UCC28056BDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
UCC28056CDBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
UCC28056CDBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
UCC28056DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
UCC28056DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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