Texas Instruments | TPS568230 4.5-V to 18-V Input, 8-A Synchronous Step-Down Voltage Regulator (Rev. C) | Datasheet | Texas Instruments TPS568230 4.5-V to 18-V Input, 8-A Synchronous Step-Down Voltage Regulator (Rev. C) Datasheet

Texas Instruments TPS568230 4.5-V to 18-V Input, 8-A Synchronous Step-Down Voltage Regulator (Rev. C) Datasheet
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TPS568230
SLVSEY5C – MARCH 2019 – REVISED AUGUST 2019
TPS568230 4.5-V to 18-V Input, 8-A Synchronous Step-Down Voltage Regulator
1 Features
3 Description
•
•
The TPS568230 is a cost effective, high-voltage
input, high efficiency synchronous buck converter
with integrated MOSFETs.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input voltage range: 4.5 V to 18 V
D-CAP3™ architecture control for fast transient
response
Output voltage range: 0.6 V to 7 V
0.6-V±1% reference voltage (25°C)
Supports 8-A continuous output current
Integrated 19.5-mΩ and 9.5-mΩ RDS(on) internal
power MOSFET
ULQ™(Ultra Low Quiescent current) feature to
enable long battery life
Selectable operation modes:
– Forced continuous conduction mode (FCCM)
– Out-of-Audio™(OOA) Mode
– Advanced Eco-Mode™
Selectable 600-kHz, 800-kHz and 1-MHz
switching frequency
Supports up to 90% duty operation
Adjustable soft start time by SS pin
Power good output
Built-in output discharge function
Cycle-by-cycle over current protection
Non-latched for fault protection
Small 3.0-mm × 3.0-mm HotRod™ QFN package
2 Applications
•
•
•
•
Digital TV, set-top box, gaming consoles
Server, storage and networking point-of-load
Industrial PC and factory automation applications
Distributed power systems with typical 5-V, 12-V,
15-V input
The TPS568230 has the ULQ™ (Ultra Low Quiescent
current) feature to enable low-bias current. It operates
with supply input voltage from 4.5 V to 18 V. It uses
DCAP3™ control mode to provide fast transient
response, good line, load regulation, no requirement
for external compensation, and support low
equivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors.
The TPS568230 provides complete Over-voltage,
Under-voltage, Over-current, Over-temperature and
Under-voltage lock-out protections. It is combined
power good signal , output discharge function and
large duty operation feature.
TPS568230 is equipped with a MODE pin to select
the desirable mode of operation. To attain high
efficiency at light load, OOA mode and Advanced
Eco-mode™ could be selected. OOA mode will not
allow the part to go below audible frequency ( below
25kHz switching frequency ). FCCM is also available
to support tight output voltage ripple requirement.
The TPS568230 supports both internal and external
soft-start time option. The internal fixed soft-start time
is 1.3 ms. Longer soft-start time can be get by
connecting the external capacitor on SS pin.
The TPS568230 is available in a 20-pin 3.0-mm x
3.0-mm HotRod™ package and the junction
temperature is specified from -40oC to 125oC.
Device Information(1)
PART NUMBER
TPS568230
PACKAGE
VQFN (20)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
TPS568230
VIN
Efficiency vs Output Current ECO-mode
100
L
VOUT
SW
VIN
95
VCC
CBST
COUT
MODE
FB
PGOOD
R2
PGOOD
90
R1
VBST
EN
RM_L
Efficiency (%)
RM_H
CIN
85
80
75
VCC
SS
R5
C1
AGND
GND
70
Could be floating
Css
VVIN=6V, VOUT=5V,FSW=600kHz
VVIN=8.4V,VOUT=5V,FSW=600kHz
VVIN=12V, VOUT=5V,FSW=600kHz
65
60
0.001
0.01
0.1
I-Load (A)
1
10
D034
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS568230
SLVSEY5C – MARCH 2019 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2019) to Revision C
Page
•
Added VENH min value 1.21V.................................................................................................................................................. 6
•
Changed VENH typical value from 1.2V to 1.31V .................................................................................................................... 6
•
Changed VENL min value from 0.8V to 0.95V ......................................................................................................................... 6
•
Changed VENLtypical value from 1.05V to 1.11V .................................................................................................................... 6
•
Added VENL max value 1.19V ................................................................................................................................................ 6
Changes from Revision A (February 2019) to Revision B
•
Changed SW negative voltage for DC change from -2V to -1V............................................................................................. 4
Changes from Original (October 2018) to Revision A
•
2
Page
Page
Changed marketing status from Advance Information to production data. ............................................................................ 1
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5 Pin Configuration and Functions
RJE Package
20-Pin VQFN
Top View
GND
VCC
NC
20
19
7
18
176
16
3
SW
4
SW
15
6
FB
13
AGND
7
4
3
7
VIN
14
4
3
2
3
VIN
MODE
6
1
BST
GND
VIN
4
12
EN
VIN
5
11
SS
7
8
6
9
10
SW
GND
GND
PGOOD
NC
3
7
4
6
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BST
1
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1uF is recommended.
VIN
2,3,4,5
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
GND.
SW
6,19,20
O
Switch node terminal. Connect the output inductor to this pin.
7,8,18,Pad
G
Power GND terminal for the controller circuit and the internal circuitry.
PGOOD
9
O
Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over
voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
SS
11
I
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.3ms.
NC
10,16
EN
12
I
Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal
pull down current to disable converter if leave this pin open.
AGND
13
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB
14
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
AGND.
MODE
15
I
Switching frequency and light load operation mode selection pin. Connect this pin to a resistor divider from
VCC and AGND, the different MODE options are shown in Table 1
VCC
17
O
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor.
GND
Not connect. Can be connected to GND plane for better thermal achieved.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
UNIT
VIN
–0.3
22
V
VBST
–0.3
27
V
VBST-SW
–0.3
6
V
MODE, FB, SS
–0.3
6
V
EN
–0.3
4
V
GND, AGND
–0.3
0.3
V
–1
22
V
V
SW
Output voltage
SW (10-ns transient)
PGOOD
–3
23
–0.3
6
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per JEDEC specification JESD22- V C101
(2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.5
18
V
VBST
–0.3
23
V
VBST-SW
–0.3
5.5
V
MODE, FB, SS
–0.3
5.5
V
EN
–0.3
3.6
V
GND, AGND
VIN
Input voltage
Output voltage
–0.3
0.3
V
SW
–1
18
V
SW (10-ns transient)
–3
19
V
–0.3
5.5
V
PGOOD
IOUT
Output current
TJ
Operating junction temperature
4
UNIT
–40
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8
A
125
°C
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6.4 Thermal Information
TPS568230
THERMAL METRIC (1)
RJE (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.3
°C/W
RθJB
Junction-to-board thermal resistance
13.3
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
13.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
16.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
VIN
IVIN
VIN supply current
No load, VEN=3.3V, non-switching
IVINSDN
Shutdown supply current
No load, VEN=0V
4.5
18
V
105
uA
2
uA
VCC OUTPUT
VCC
VCC output voltage
ICC
VCC current limit
VVIN>5.0V
4.85
VVIN=4.5V
5
5.15
4.5
V
V
20
mA
FEEDBACK VOLTAGE
VFB
FB voltage
TJ = 25°C
594
600
606
mV
TJ = -40°C to 125°C
592
600
611
mV
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
TJ = 25°C , FSW=600kHz,Vo=1V
TON(MIN)
SW minumum on time
TJ = 25°C
TOFF(MIN)
SW minimum off time
VFB = 0.5 V
600
kHz
60
ns
190
ns
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
19.5
mΩ
RDS(ON)L
Low side switch resistance
TJ = 25°C
9.5
mΩ
28
us
OOA FUNCTION
TOOA
OOA mode operation period
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
TJ=25°C, VEN=0V
420
Ω
TSS
Soft start time
Internal soft-start time,SS floating
1.3
ms
ISS
Soft start charge current
5
uA
POWER GOOD
TPGDLY
PG start-up delay
PG from low to high
1
ms
VFB falling (fault)
85
%
VFB rising (good)
90
%
VFB rising (fault)
115
%
VFB falling (good)
110
VPGTH
PG threshold
VPG_L
PG sink current capability
IOL =4mA
IPGLK
PG leak current
VPGOOD =5.5V
%
0.4
V
1
uA
12
A
CURRENT LIMIT
IOCL
Over current threshold
Valley current set point
8.1
9.8
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Electrical Characteristics (continued)
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
INOCL
TEST CONDITION
MIN
Negative over current threshold
TYP
MAX
3.9
UNIT
A
LOGIC THRESHOLD
VENH
EN high-level input voltage
1.21
1.31
1.4
VENL
EN low-level input voltage
0.95
1.11
1.19
IEN
Enable internal pull down current VEN=0.8V
V
V
2
µA
125
%
20
us
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
tOVPDLY
OVP prop deglitch
VUVP
UVP trip threshold
60
%
tUVPDLY
UVP prop deglitch
256
us
TUVPDEL
Output hiccup delay relative to
SS time
256
us
TUVPEN
Output hiccup enable delay
relative to SS time
TJ=25°C
7
cycle
UVLO
Wake up
VUVLOVIN
VIN UVLO threshold
Shutdown
4.2
3.6
4.4
V
3.8
V
Hysteresis
0.4
V
Shutdown temperature
150
°C
20
°C
OVER TEMPERATURE PROTECTION
OTP trip threshold (1)
TOTP
TOTPHSY
(1)
6
OTP hysteresis
(1)
Hysteresis
Not production tested
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6.6 Typical Characteristics
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
120
3
2.75
116
Supply Current (uA)
Supply Current (uA)
118
114
112
110
2.5
2.25
2
108
1.75
106
104
-50
-20
10
40
70
Junction Temperature ( OC)
100
1.5
-50
130
VEN = 3.3 V
610
1.34
605
600
595
130
D002
1.32
1.3
1.28
-20
10
40
70
Junction Temperature ( OC)
100
1.26
-50
130
-20
D003
Figure 3. Feedback Voltage vs Junction Temperature
10
40
70
Junction Temperature (OC)
100
130
D004
Figure 4. Enable On Voltage vs Junction Temperature
1.12
27.5
1.11
25
High-Side RDS(on) (m:)
EN Off Voltage (V)
100
Figure 2. Shutdown Current vs Temperature
1.36
EN On Voltage (V)
VFB Feedbacvk Voltage (mV)
Figure 1. Supply Current vs Junction Temperature
1.1
1.09
1.08
22.5
20
17.5
1.07
1.06
-50
10
40
70
Junction Temperature (OC)
VEN = 0 V
615
590
-50
-20
D001
-20
10
40
70
Junction Temperature (OC)
100
130
15
-50
D005
Figure 5. Enable Off Voltage vs Junction Temperature
-20
10
40
70
Junction Temperature (OC)
100
130
D011
Figure 6. High-Side RDS(on) vs Junction Temperature
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Typical Characteristics (continued)
16
130
14
128
OVP Threshold (%)
Low-side RDS(on) (m:)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
12
10
8
126
124
122
6
-50
-20
10
40
70
Junction Temperature (OC)
100
120
-50
130
440
63
435
62
61
60
100
130
D006
430
425
420
59
-50
-20
10
40
70
Junction Temperature (OC)
100
415
-50
130
10.6
1.33
Soft-start Time (ms)
1.35
10.2
9.8
9.4
10
40
70
Junction Temperature ( OC)
100
130
D008
Figure 10. Discharge Resistor vs Junction Temperature
11
9
-50
-20
D007
Figure 9. UVP Threshold vs Junction Temperature
Valley Current Limit (A)
10
40
70
Juncition Temperature (OC)
Figure 8. OVP Threshold vs Junction Temperature
64
Discharge Resistor (:)
UVP Threshold (%)
Figure 7. Low-Side RDS(on) vs Junction Temperature
1.31
1.29
1.27
-20
10
40
70
Junction Temperature (OC)
100
130
1.25
-50
D009
Figure 11. Valley Current Limit vs Junction Temperature
8
-20
D012
-20
10
40
70
Junction Temperature (OC)
100
130
D010
Figure 12. Soft-Start Time vs Junction Temperature
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Typical Characteristics (continued)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
100
100
95
90
90
80
70
80
Efficiency (%)
Efficiency (%)
85
75
70
65
60
60
50
40
30
55
20
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
50
45
40
0.001
0.01
0.1
I-Load (A)
1
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
0
0.001
10
0.01
D027
Figure 13. Efficiency, Eco-mode, FSW = 600 kHz
0.1
I-Load (A)
1
10
D028
Figure 14. Efficiency, OOA-mode, FSW = 600 kHz
100
100
90
95
90
80
85
Efficiency (%)
Efficiency (%)
70
60
50
40
30
80
75
70
65
60
55
20
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
0
0.001
0.01
0.1
I-Load (A)
1
45
40
0.001
10
0.01
D029
Figure 15. Efficiency, FCCM, FSW = 600 kHz
0.1
I-Load (A)
1
10
D030
Figure 16. Efficiency, Eco-mode, FSW = 1 MHz
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
50
60
50
40
30
60
50
40
30
20
20
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
0
0.001
0.01
0.1
I-Load (A)
1
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
10
0
0.001
0.01
D031
Figure 17. Efficiency, OOA-mode, FSW = 1 MHz
0.1
I-Load (A)
1
10
D032
Figure 18. Efficiency, FCCM, FSW = 1 MHz
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Typical Characteristics (continued)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
700
1
VVIN=6V, VOUT=5V
VVIN=8.4V,VOUT=5V
VVIN=12V, VOUT=5V
Load Regulation (%)
0.6
600
Switching Frequency (kHz)
0.8
0.4
0.2
0
-0.2
-0.4
-0.6
0.01
0.1
I-Load (A)
1
300
200
0.01
D035
Figure 19. Load Regulation, Eco-mode, FSW = 600 kHz
0.1
I-Load (A)
400
300
200
0.01
0.1
I-Load (A)
1
600
500
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
400
0.001
10
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
800
Switching Frequency (kHz)
Switching Frequency (kHz)
1
10
D037
900
600
500
400
300
200
100
700
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
600
500
400
300
200
100
0.01
0.1
I-Load (A)
1
10
0
0.001
D038
Figure 23. FSW Load Regulation, Eco-mode, FSW = 800 kHz
10
0.1
I-Load (A)
Figure 22. FSW Load Regulation, FCCM, FSW = 600 kHz
900
0
0.001
0.01
D036
Figure 21. FSW Load Regulation, OOA-mode, FSW = 600 kHz
700
D023
700
100
800
10
800
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
500
0
0.001
1
Figure 20. FSW Load Regulation, Eco-mode, FSW = 600 kHz
Switching Frequency (kHz)
Switching Frequency (kHz)
400
0
0.001
10
700
600
500
100
-0.8
-1
0.001
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
0.01
0.1
I-Load (A)
1
10
D039
Figure 24. FSW Load Regulation, OOA-mode, FSW = 800 kHz
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Typical Characteristics (continued)
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
800
900
Switching Frequency (kHz)
Switching Frequency (kHz)
1000
800
700
600
500
0.001
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
0.01
0.1
I-Load (A)
1
600
500
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
400
0.001
10
1000
1200
Switching Frequency (kHz)
1300
900
800
700
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
500
0.001
0.01
0.1
I-Load (A)
1
0.1
I-Load (A)
D044
1000
900
700
0.001
D045
Figure 27. FSW Load Regulation, FCCM, FSW = 800 kHz
10
1100
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
800
10
1
Figure 26. FSW Load Regulation, FCCM, FSW = 600 kHz
1100
600
0.01
D040
Figure 25. FSW Load Regulation, FCCM, FSW = 800 kHz
Switching Frequency (kHz)
700
0.01
0.1
I-Load (A)
1
10
D046
Figure 28. FSW Load Regulation, FCCM, FSW = 1 MHz
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7 Detailed Description
7.1 Overview
The TPS568230 is 8-A integrated FET synchronous buck converter which operates from 4.5V to 18V input
voltage (VIN), and the output is from 0.6V to 7V. The proprietary D-CAP3™ mode enables low external
component count, ease of design, optimization of the power design for cost, size and efficiency. The key feature
of the TPS568230 is ultra-low quiescent current (ULQ™) mode. This feature is beneficial for long battery life in
system standby mode. The device employs D-CAP3™ mode control that provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology provides seamless
transition between CCM operating mode at higher load condition and DCM operation at lighter load condition.
Eco-mode™ allows the TPS568230 to maintain high efficiency at light load. OOA (out of audio) mode makes
switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. FCCM
mode has the constant switching frequency at both light and heavy load. The TPS568230 is able to adapt to both
low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
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7.2 Functional Block Diagram
PG high
threshold
UV threshold
+
PGOOD
+
UV
Delay
+
+
PG low
threshold
OV
OV threshold
VIN
FB
+
0.6 V
+
VREGOK
LDO
VCC
4.2 V /
3.8 V
+
+PWM
+
Control Logic
VBST
SS
VIN
Ripple injection
SW
Internal SS
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
OOA/SKIP/FCCM
Soft-Start
PGOOD
SW
XCON
SS
GND
One shot
+
OCL
EN threshold
EN
+
ZC
+
+
NOCL
150°C /20°C
+
THOK
AGND
Light load operation
/Switching frequency set
Discharge control
MODE
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS568230 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3™ control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS568230 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in Equation 1.
fp
1
2 u S u LOUT u COUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS568230. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS568230 has an internal 1.3-ms soft start, and also an external SS pin is provided for setting higher softstart time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a larger soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 2:
Tss
Css(nF) u VREF(V)
Iss(PA)
(2)
where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS568230 can support large duty operations by its internal TON extension function. When the VIN/VOUT
<1.6, and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and
also improve the performance of the load transient performance.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A 100 kΩ pullup resistor is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
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Feature Description (continued)
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
in an OVP, UVP, or thermal shutdown event
during the soft-start period.
7.3.5 Over Current Protection and Undervoltage Protection
The TPS568230 has the over current protection and undervoltage protection. The output over current limit (OCL)
is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state
by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the device will shut off after a wait time of 256us and then re-start after the hiccup time (typically
7*Tss). When the over current condition is removed, the output will be recovered.
7.3.6 Over Voltage Protection
The TPS568230 has the over voltage protection feature. When the output voltage becomes higher than 125% of
the target voltage, the OVP comparator output goes high, the output will be discharged after a wait time of 20 µs.
When the over voltage condition is removed, the output voltage will be recovered.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS568230 has the discharge function by using internal MOSFET about 420Ω RDS(on), which is connected
to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.9 Thermal Shutdown
The TPS568230 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
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7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS568230 has a MODE pin which can setup three different modes of operation for light load running and 600
kHz/800 kHz/1 MHz switching frequency at heavy load .The light load running includes Out-of-Audio mode ,
Advanced Eco-mode and Force CCM mode.
7.4.2
Advanced Eco-mode™ Control
The advanced Eco-mode™ control scheme to maintain high light load efficiency. As the output current decreases
from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The light load current where the
transition to Eco-mode™ operation happens ( IOUT(LL) ) can be calculated from Equation 3.
(V -V
) × VOUT
1
IOUT(LL) =
× IN OUT
2 × LOUT × FSW
VIN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Out of Audio Mode
Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above audible
frequency towards a virtual no-load condition. During Out-of-Audio operation, the OOA control circuit monitors
the states of both high-side and low-side MOSFETs and forces them switching if both MOSFETs are off for more
than 28 μs. When both high-side and low-side MOSFETs are off for more than 28 μs during a light-load
condition, the lowside FET will be on for discharge till reverse OC happens or output voltage drops to trigger the
high-side FET on. This mode initiates one cycle of the low-side MOSFET and the high-side MOSFET turning on.
Then, both MOSFETs stay turned off waiting for another 28 μs.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
7.4.4 Force CCM Mode
Force CCM(FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant level over the entire load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
7.4.5 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in Table 1 . The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom resistor (RM_L)
is shown in Table 1, and 1% resistors are recommended. It is important that the voltage for the MODE pin is
derived from the VCC rail only since internally this voltage is referenced to detect the MODE option. The MODE
pin setting can be reset only by a VIN power cycling or EN toggle.
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Device Functional Modes (continued)
Table 1. MODE Pin Resistor Settings
RM_H(kΩ)
RM_L (kΩ)
LIGHT LOAD OPERATION
SWITCHING FREQUENCY (kHz)
330
5.1
Eco-mode
600
330
15
Eco-mode
800
330
27
Eco-mode
1000
300
43
OOA mode
600
150
33
OOA mode
800
160
51
OOA mode
1000
110
51
FCCM
600
75
51
FCCM
800
51
51
FCCM
1000
Figure 29 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
EN threshold
1.2V
EN
VCC UVLO
4.2V
VCC
MODE9
MODE1
MODE
500us
100us
Tss
90% VOUT
1ms
VOUT
PGOOD
Figure 29. Power-Up Sequence
7.4.6 Standby Operation
The TPS568230 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when float, the part is disabled by
default.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 30 shows a typical application for TPS568230 with 1-V output. This design converts an
input voltage range of 4.5 V to 18 V down to 1 V with a maximum output current of 8 A.
8.2 Typical Application
Figure 30. 1-V, 8-A Reference Design with Eco-mode, FSW = 600 kHz
8.2.1 Design Requirements
Table 2 lists the design parameters for this example.
Table 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
Output voltage
1
IOUT
Output current
8
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
18
mV(P-P)
FSW
Switching frequency
600
kHz
0 A - 8 A load step,2.5A/us
18
A
±40
4.5
Light load operating mode
TA
V
12
mV
18
V
Eco-mode
Ambient temperature
25
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8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See Equation 4
VOUT
0 . 6 u (1
R UPPER
)
R LOWER
(4)
8.2.2.1.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 3 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 5 and Equation 6. It is
important that the inductor is rated to handle these currents.
IL RMS
IL(peak)
§
¨2
¨ I OUT
¨
©
IOUT
1 §¨ VOUT u ( VIN (max) VOUT ) ·¸
u
12 ¨© VIN (max) u L OUT u FSW ¸¹
2·
¸
¸
¸
¹
(5)
IL(ripple)
2
(6)
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the device
so it is safe to choose an inductor with a saturation current higher than the peak current under current limit
condition.
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8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in Table 3.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple).
Table 3. Recommended Component Values
VOUT (V)
0.6
1
RLOWER (kΩ)
10
30
3.3
5.0
20
30
RUPPER
(kΩ)
0
20
90
220
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (PF)
600
0.47
66
500
-
800
0.33
66
500
-
1000
0.27
66
500
-
600
0.68
66
500
-
800
0.47
66
500
1000
0.33
66
500
-
600
1.5
66
500
47-330
800
1.2
66
500
47-330
1000
1
66
500
47-330
600
2.2
66
500
47-330
800
1.5
66
500
47-330
1000
1.2
66
500
47-330
8.2.2.1.4 Input Capacitor Selection
The TPS568230 requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in Equation 7.
IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW
(7)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by Equation 8:
ICIN(rms) = IOUT ×
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
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8.2.3 Application Curves
Figure 31 through Figure 44 apply to the circuit of Figure 30. VIN = 12 V. TJ = 25°C unless otherwise specified.
95
1
90
0.8
85
0.6
Load Regulation (%)
Efficiency (%)
80
75
70
65
60
55
50
40
0.001
0.01
0.1
I-Load (A)
1
0.4
0.2
0
-0.2
-0.4
-0.6
VVIN=5V, VOUT=1V,FSW=600kHz
VVIN=8.4V,VOUT=1V,FSW=600kHz
VVIN=12V, VOUT=1V,FSW=600kHz
45
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
-0.8
-1
0.001
10
0.01
Figure 31. Efficiency Curve
1
10
D019
Figure 32. Load Regulation
800
700
700
600
Switching Frequency (kHz)
Swtiching Frequency (kHz)
0.1
I-Load (A)
D033
600
500
400
300
500
400
300
200
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
100
200
0
4
6
8
10
12
VIN (V)
14
16
18
0
1
2
3
D025
4
5
I-Load (A)
6
7
8
D047
IOUT = 8 A
Figure 34. Switching Frequency vs Output Load
0.1
1
0.08
0.8
0.06
0.6
Line Regulation (%)
Line Regulation (%)
Figure 33. Switching Frequency vs Input Voltage
0.04
0.02
0
-0.02
-0.04
0.4
0.2
0
-0.2
-0.4
-0.06
-0.6
-0.08
-0.8
-0.1
-1
4
6
8
10
12
VIN (V)
14
16
18
4
D021
Figure 35. Line Regulation,IOUT = 0.01 A
6
8
10
12
VIN (V)
14
16
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D021
Figure 36. Line Regulation,IOUT = 8 A
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Vout=20mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=5V/div
SW=5V/div
2us/div
200us/div
Figure 37. Output Voltage Ripple, IOUT = 0.01 A
Figure 38. Output Voltage Ripple, IOUT = 8 A
EN=2V/div
EN=2V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
2ms/div
400us/div
Figure 39. Start-Up Through EN, IOUT = 4A
Figure 40. Shut-down Through EN, IOUT = 4A
Vin=10V/div
Vin=10V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
4ms/div
4ms/div
Figure 41. Start Up Relative to VIN Rising, IOUT = 4 A
22
Figure 42. Start Up Relative to VIN Falling, IOUT = 4 A
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Vout=50mV/div (AC coupled)
Vout=50mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200us/div
200us/div
Slew Rate=2.5A/us
Slew Rate=2.5A/us
Figure 43. Transient Response, 0.8 A to 7.2 A
Figure 44. Transient Response, 0 A to 8 A
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9 Power Supply Recommendations
The TPS568230 is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 to 23 V.
TPS568230 is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS568230 circuit, additional input bulk capacitance is recommended, typical
values are 100 μF to 470 μF.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3inch, four-layer PCB with 2-oz copper is used as example.
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place output inductor and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitor and also as close to the output pin as possible.
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
Feedback could be 20mil and must be routed away from the switching node, BST node or other high
efficiency signal.
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
Figure 45 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 30. Resistor divider for EN is not used in the circuit of Figure 30, but are shown in the
layout for reference.
VIN
VOUT
SW
GND
GND
AGND
Figure 45. Top-Layer Layout
24
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS568230
TPS568230
www.ti.com
SLVSEY5C – MARCH 2019 – REVISED AUGUST 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP3, ULQ, Out-of-Audio, Eco-Mode, HotRod, DCAP3, Eco-mode, E2E are trademarks of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS568230
25
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS568230RJER
ACTIVE
VQFN-HR
RJE
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
568230
TPS568230RJET
ACTIVE
VQFN-HR
RJE
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
568230
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS568230RJER
VQFNHR
RJE
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS568230RJET
VQFNHR
RJE
20
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS568230RJER
VQFN-HR
RJE
20
3000
367.0
367.0
35.0
TPS568230RJET
VQFN-HR
RJE
20
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0020A
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
B
A
(0.25)
DETAIL A
3.1
2.9
PIN 1 INDEX AREA
CHAMFERS ARE OPTIONAL
TYPICAL
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 1.8
PKG
SEE TERMINAL
DETAIL A
10
6
16X 0.45
(0.1) TYP
11
5
(0.018)
2X
1.8
PKG
21
20X 0.25
0.15
1
PIN 1 ID
DETAIL B
0.1
0.05
15
20
16
(0.06)
C B A
C
20X 0.5
0.3
4223546 / B 08/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RJE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(0.675)
(0.06)
16
20
20X (0.6)
20X (0.2)
1
15
(0.018)
16X (0.45)
21
PKG
(2.8)
(0.76)
11
5
(R0.05) TYP
6
PKG
10
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
(PAD 21)
NON- SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223546 / B 08/2017
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0020A
PLASTIC QUAD FLATPACK- NO LEAD
(0.64)
(0.06)
16
20
20X (0.6)
20X (0.2)
1
15
(0.018)
16X (0.45)
21
PKG
(0.72)
(2.8)
5
11
(R0.05) TYP
6
PKG
10
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 21: 90%
SCALE: 20X
4223546 / B 08/2017
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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