Texas Instruments | TPS563240 17-V, 3-A 1.4-MHz Synchronous Step-Down Voltage Regulator (Rev. A) | Datasheet | Texas Instruments TPS563240 17-V, 3-A 1.4-MHz Synchronous Step-Down Voltage Regulator (Rev. A) Datasheet

Texas Instruments TPS563240 17-V, 3-A 1.4-MHz Synchronous Step-Down Voltage Regulator (Rev. A) Datasheet
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TPS563240
SLVSE74A – DECEMBER 2018 – REVISED AUGUST 2019
TPS563240 17-V, 3-A 1.4-MHz Synchronous Step-Down Voltage Regulator
1 Features
3 Description
•
The TPS563240 is a simple, easy-to-use, 3-A
synchronous step-down regulator in SOT-23
package. The peak transient output current can be
3.5 A.
1
•
•
•
•
•
•
•
•
•
•
•
•
3-A converter integrated 70-mΩ and 30-mΩ FETs,
support 3.5-A transient
D-CAP3™ mode control with fast transient
response
Input voltage range: 4.5 V to 17 V
Output voltage range: 0.6 V to 7 V
Pulse-skip mode during light load operation
without going below 25-kHz switching frequency
1.4-MHz switching frequency
Low shutdown current less than 10 µA
1% feedback voltage accuracy (25 ºC)
Startup from pre-biased output voltage
Cycle-by-cycle overcurrent limit
Hiccup-mode overcurrent protection
Non-latch UVP and TSD protections
Fixed soft start: 1.7 ms
2 Applications
•
•
•
•
•
The devices are optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
This switching regulator employs D-CAP3 mode
control providing a fast transient response and
supporting both low-equivalent series resistance
(ESR) output capacitors such as specialty polymer
and ultra-low ESR ceramic capacitors with no
external compensation components.
TPS563240 operates in pulse skip mode, which
maintains high efficiency during light load operation.
The TPS563240 maintain Fsw over 25-kHz under
light load condition. The TPS563240 is available in a
6-pin 1.6-mm × 2.9-mm SOT (DDC) package, and
specified from a –40°C to 125°C junction
temperature.
Device Information(1)
TV, set-top boxes
Broadband modem
Access point networks
Wireless routers
Surveillance
PART NUMBER
TPS563240
PACKAGE
DDC (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
SPACER
Simplified Schematic
TPS563240 Efficiency
Efficiency at 12V input
TPS563240
2
VOUT
COUT
3
VIN
CIN
GND VBST
SW
EN
VIN
VFB
100%
6
5
4
90%
EN
80%
VOUT
70%
Efficiency
1
60%
Vout = 0.9V
Vout = 1.05V
Vout = 1.2V
Vout = 1.5V
Vout = 1.8V
Vout = 2.5V
Vout = 3.3V
Vout = 5V
50%
40%
30%
20%
10%
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS563240
SLVSE74A – DECEMBER 2018 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Original (December 2018) to Revision A
Page
•
Changed from 'with Out-of-Audio™ (OOA) operation...25kHz' to 'during light load...switching frequency'............................ 1
•
Deleted with Out-of-Audio™ (OOA) operation implemented.................................................................................................. 1
•
Changed from 'Out-of-Audio™ (OOA) Operation ' to 'Light Load Operation Maintaining Above Audible Frequency' ......... 10
•
Deleted Out-of-Audio™ (OOA) operation under light-load condition is implemented. ........................................................ 10
2
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5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
6
VBST
SW
2
5
EN
VIN
3
4
VFB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
1
—
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
3
I
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
4
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
VBST
6
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
VIN
–0.3
19
V
VBST
–0.3
24.5
V
VBST (10 ns transient)
–0.3
26.5
V
VBST (vs SW)
–0.3
5.5
V
VFB
–0.3
5.5
V
–2
19
V
SW (10 ns transient)
–3.5
21
V
EN
SW
UNIT
-0.3
VIN + 0.3
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
EN
TJ
NOM
MAX
UNIT
4.5
17
V
EN Input voltage range
–0.1
VIN
V
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS563240
THERMAL METRIC (1)
DDC (SOT)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
117.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
57.3
°C/W
RθJB
Junction-to-board thermal resistance
31.2
°C/W
ψJT
Junction-to-top characterization parameter
11.2
°C/W
ψJB
Junction-to-board characterization parameter
31.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 0.7 V, TJ = 25°C
235
300
µA
IVIN(SDN)
Shutdown supply current
VIN current, EN = 0 V, TJ = 25°C
2.5
10
µA
1.27
1.34
V
LOGIC THRESHOLD
VENH
Enable threshold
Rising
VENL
Enable threshold
Falling
1.08
1.15
REN
EN pin resistance to GND
VEN = 1 V
800
1000
1200
kΩ
Continuous mode operation, TJ = 25°C
594
600
606
mV
Continuous mode operation
588
600
612
mV
0
±50
nA
V
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB
FB voltage
IFB
FB input current
VFB = 0.7 V
RDS(on)h
High-side switch resistance
TJ = 25°C
70
mΩ
RDS(on)l
Low-side switch resistance
TJ = 25°C
30
mΩ
MOSFET
CURRENT LIMIT
Iocl_h_source
High side FET source
Current limit
5.5
6.3
7.1
A
Iocl_l_source
Low side FET source
Current limit
3.1
3.9
4.7
A
Iocl_l_sink
Low side FET sink Current
limit
0
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
160
°C
Hysteresis
25
VIN = 12 V, load = 3 A
50
ns
250
ns
1.7
ms
1400
kHz
ON-TIME TIMER CONTROL
tON(MIN)
Minimum on time (1)
tOFF(MIN)
Minimum off time
SOFT START
tss
Soft-start time
Internal soft-start time
FREQUENCY
Fsw
Switching frequency
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
Output UVP threshold
tUVPDLY
UVP propagation delay
tHIC
UVP protection Hiccup Time
before restart
Hiccup detect (H > L)
65%
0.36
ms
25
ms
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage
(1)
4.2
3.6
4.4
3.8
V
0.4
Not production tested.
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6.6 Typical Characteristics
2.96
252
2.94
248
2.92
VIN Quiescent Current (uA)
VIN Shutdown Current (uA)
VIN = 12 V (unless otherwise noted)
2.9
2.88
2.86
2.84
2.82
2.8
244
240
236
232
228
224
2.78
2.76
-40
-20
0
20
40
60
80
Junction Temperature (°C)
100
120
220
-40
140
-20
0
D001
Figure 1. Shutdown Current vs Junction Temperature
20
40
60
80
Junction Temperature (°C)
100
120
140
D001
Figure 2. Supply Current vs Junction Temperature
610
1.3
608
1.29
EN Threshold - Rising (V)
FB Voltage (mV)
606
604
602
600
598
596
594
1.28
1.27
1.26
1.25
592
590
-40
-20
0
20
40
60
80
Junction Temperature (°C)
100
120
1.24
-40
140
1.17
100
1.16
90
1.15
1.14
1.13
1.12
20
40
60
80
Junction Temperature (°C)
100
120
140
D001
80
70
60
50
40
1.11
-20
0
20
40
60
80
Junction Temperature (°C)
100
120
140
30
-40
-20
D001
Figure 5. EN Falling threshold vs Junction Temperature
6
0
Figure 4. EN Rising threshold vs Junction Temperature
110
+LJK 6LGH 5GVBRQ P
EN Threshold - Falling (V)
Figure 3. VFB Voltage vs Junction Temperature
1.18
1.1
-40
-20
D001
0
20
40
60
80
Junction Temperature (°C)
100
120
140
D001
Figure 6. High-Side Rds-On vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
60
3.4
3.3
50
Output Voltage (V)
/RZ 6LGH 5GVBRQ P
3.2
40
30
3.1
3
2.9
2.8
20
2.7
10
-40
Iout = 3A
Iout = 1.5A
2.6
-20
0
20
40
60
80
Junction Temperature (°C)
100
120
140
5
5.2
D001
Figure 7. Low-Side Rds-On vs Junction Temperature
5.4
5.6
5.8
Input Voltage (V)
6
6.2
D001
Figure 8. Dropout for 3.3 V Output Voltage
90%
5.2
80%
5
60%
4.8
Efficiency
Output Voltage (V)
70%
4.6
50%
40%
30%
4.4
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
4.2
Iout = 3A
Iout = 1.5A
10%
0
0.001
4
7
7.5
8
Input Voltage (V)
8.5
9
0.005
D001
0.9 V Efficiency
0.02 0.05 0.1 0.2
Output Current (A)
L = 0.56 μH
0.5
1
2 3
D001
(Wurth:7443835600
56)
Figure 9. Dropout for 5 V Output Voltage
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
Figure 10. Efficiency vs Output Current, VOUT = 0.9 V
90%
50%
40%
30%
10%
0
0.001
0.005
1.05 V Efficiency
0.02 0.05 0.1 0.2
Output Current (A)
L = 0.56 μH
0.5
1
40%
30%
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
50%
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
10%
2 3
0
0.001
0.005
D001
(Wurth:7443835600
56)
Figure 11. Efficiency vs Output Current, VOUT = 1.05 V
1.2 V Efficiency
0.02 0.05 0.1 0.2
Output Current (A)
L = 0.68 μH
0.5
1
2 3
D001
(Wurth:7443835600
68)
Figure 12. Efficiency vs Output Current, VOUT = 1.2 V
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
90%
100%
80%
90%
70%
80%
70%
Efficiency
Efficiency
60%
50%
40%
30%
10%
0
0.001
0.005
1.5 V Efficiency
0.02 0.05 0.1 0.2
Output Current (A)
L = 0.68 μH
0.5
1
40%
10%
0
0.001
2 3
(Wurth:7443835600
68)
80%
70%
70%
60%
60%
Efficiency
90%
80%
50%
40%
30%
10%
0.02 0.05 0.1 0.2
Output Current (A)
L = 1 μH
0.5
1
50%
40%
Vin = 6.5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
10%
0
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
D001
(Wurth:744311100)
Figure 15. Efficiency vs Output Current, VOUT = 2.5 V
2 3
D001
20%
2 3
1
(Wurth:744311100)
30%
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
L = 1 μH
0.5
Figure 14. Efficiency vs Output Current, VOUT = 1.8 V
90%
2.5 V Efficiency
0.02 0.05 0.1 0.2
Output Current (A)
1.8 V Efficiency
100%
0.005
0.005
D001
100%
0
0.001
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
Figure 13. Efficiency vs Output Current, VOUT = 1.5 V
Efficiency
50%
30%
Vin = 5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
60%
3.3 V Efficiency
L = 1.5 μH
0.5
1
2 3
D001
(Wurth:744311150)
Figure 16. Efficiency vs Output Current, VOUT = 3.3 V
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
10%
0
0.001
5 V Efficiency
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D001
L = 1.5 μH
(Wurth:744311150)
Figure 17. Efficiency vs Output Current, VOUT = 5 V
8
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7 Detailed Description
7.1 Overview
The TPS563240 is a 3-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low
ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output
capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 5
VUVP
+
UVP
Hiccup
Control Logic
3
VIN
6
BST
2
SW
1
GND
VREG5
Regulator
UVLO
FB 4
Voltage
Reference
+
SS
Soft Start
+
+
+
PWM
HS
Ripple Injection
One-Shot
XCON
VREG5
On-time
Reduction
TSD
OCL
threshold
LS
OCL
+
+
ZC
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563240 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.
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Feature Description (continued)
7.3.2 Pulse Skip Control
The TPS563240 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in Equation 1.
(V
VOUT ) u VOUT
1
u IN
IOUT(LL)
2 u L u fSW
VIN
(1)
7.3.3 Light Load Operation Maintaining Above Audible Frequency
As the load current continues to decrease, the switching frequency can decrease into the acoustic audible
frequency range. To prevent this from happening, the control circuit monitors the states of both the high-side and
low-side FETs. When both high-side and low-side FETs are off for a period longer than 30 μs, the on time
generated by one shot timer is decreased by a little step, thus the off time of both FETs will be reduced to a
length lower than 30us. If the load current decreases further, and cause the off time of both FETs longer than
30us again, the above described on time reduction process will repeat. By this means, the switching frequency is
maintained higher than ~33kHz as load decrease. When the on time reduces to ~30% of that in CCM operation,
the on time will keep at this minimum length. If load current decreases further, the switching frequency can't be
maintained at ~33kHz anymore, instead, it will decrease linearly towards zero.
When the load current increases from zero, the on time is kept at minimum length, which is~30% of that in CCM
operation, and the switching frequency increases linearly as load increases. When the off time of both FETs
decreases to a length lower than 20 µs, the on time generated by one shot timer will increase by a step, thus the
off time of both FETs will be increased above 20us. If the load current increases further, and cause the off time
of both FETs shorter than 20 µs again, the above described on time increase process will repeat. By this means,
the switching frequency is maintained lower than ~50 kHz as load increases. When the on time increases to the
length of that in CCM operation, the on time can't be increased anymore. If load current continue increases, the
switching frequency will increase linearly towards 1.4MHz nominal frequency. Below figure shows the frequency
VS load curve at 12Vin/5Vout condition with 1.5 µH inductor used.
12Vin, 5Vout, 1.5uH inductor
60
55
Fsw (kHz)
50
45
40
35
30
25
Full load to no load
No load to full load
20
0
5
10
15
Load (mA)
20
25
30
D001
Figure 18. Frequency VS load current at 12Vin/5Vout condition with 1.5uH inductor used
7.3.4 Soft Start and Pre-Biased Soft Start
The TPS563240 has an internal 1.7-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
10
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Feature Description (continued)
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.5 Current Protection
There are two kinds of current protection in TPS563240: High-side FET source current limit and low-side FET
source current limit.
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the low-side FET switch, the inductor current flow through low-side FET and decreases
linearly. The average value of the inductor current is the load current IOUT. If the monitored current is above the
low-side FET source current limit level, the converter maintains low-side FET on and delays the creation of a
new set pulse, even the voltage feedback loop requires one, until the current cross the low-side FET source
current limit level. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored
in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 0.36 ms) and re-start after the hiccup time (typically 25 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
During the on time of the high-side FET switch, the inductor current flow through high-side FET and increases at
a linear rate determined by VIN, VOUT, the on-time and the output inductor value. The switch current is compared
with high-side FET source current limit after a short blanking time. If the cross-limit event detected before the one
shot timer expires, the high-side FET will be turn off immediately, and will not be allowed on in the following 1uS
period.
7.3.6 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS563240 can operate in normal switching modes. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS563240 operates at a quasi-fixed frequency of
1.4MHz.
7.4.2 Eco-mode Operation
When the TPS563240 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS563240
begins operating in pulse skipping Eco-mode. Each switching cycle is followed by a period of energy saving
sleep time. The sleep time ends when the VFB voltage falls below reference voltage. As the output current
decreases, the sleep time between switching pulses increases.
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Device Functional Modes (continued)
7.4.3 Standby Operation
When the TPS563240 is operating in either normal CCM or Eco-mode, it may be placed in standby by asserting
the EN pin low.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter. It's typically used to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 3 A. The following design procedure can be used to select
component values for the TPS563240. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
The application schematic in Figure 19 was developed to meet the previous requirements. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 19 shows the TPS563240 6.5-V to 17-V input, 3.3-V output converter schematics.
C7 0.1 F
1
VOUT = 3.3V/3A
L1
2
VOUT
R4 0
GND
VBST
SW
EN
VIN
VFB
6
R3 10 k
5
EN
1.5 H
C9
22 F
C8
NC
3
4
VOUT
R1 45.3 k
R2
10 k
1
C1
10 F
C2
NC
C3
0.1 F
Not Installed
C4
1
VIN
1
Figure 19. 3.3-V/3-A Reference Design
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
6.5 to 17 V
Output voltage
3.3 V
Transient response, 1.5-A load step
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
100 mV
Output current rating
3A
Operating frequency
1.4 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1
VOUT 0.6 u (1
)
R2
(2)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
fP
1
2S LOUT u COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided by the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
14
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
C8 + C9 (µF)
1
6.65
10.0
0.33
0.56
1
10 to 44
1.05
7.5
10.0
0.33
0.56
1
10 to 44
1.2
10
10.0
0.47
0.68
1.5
10 to 44
1.5
15
10.0
0.47
0.82
1.5
10 to 44
1.8
20
10.0
0.56
1
2.2
10 to 44
2.5
31.6
10.0
0.68
1
2.2
10 to 44
3.3
45.3
10.0
0.82
1.5
3.3
10 to 44
5
73.2
10.0
1
1.5
3.3
10 to 44
6.5
97.6
10.0
1
1.5
3.3
10 to 44
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The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
VIN(MAX) VOUT
VOUT
IlP P
u
VIN(MAX)
LO u fSW
(4)
IlPEAK
IlP P
2
IO
IO2
ILO(RMS)
(5)
1
IlP
12
2
P
(6)
For this design example, the calculated peak current is 3.63 A and the calculated RMS current is 3.02 A. The
inductor used is a WE 744311150 with a rated current of 11 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563240 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 10 µF to 44 µF. Use Equation 7
to determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(7)
For this design one Murata GRM31CR61A226KE19 22-µF output capacitor is used. The typical ESR is 2 mΩ.
The calculated RMS current is 0.365 A and output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS563240 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
8.2.2.5 Dropout
With a constant 1.4-MHz switching frequency, there is a minimum input voltage limit for a given output voltage to
be regulated. This is due to the minimum off time limit. If the input voltage less than the minimum input voltage
limit, the output voltage drops accordingly, which is called dropout condition. Figure 8 and Figure 9 show the
typical dropout curve for 3.3 V and 5 V output voltage with 3 A and 1.5 A load respectively. Equation 8 can be
used to estimate this minimum input voltage limit.
8+0(/+0)
8176
+ :4@OH + 4. ; × +1 × kPKBB (IEJ ) F P@1 F P@2 o + (8@ + 4. × +1 ) × (P@1 + P@2 )
(
= 59
+ (4@OD + 4. ) × +1
1
F PKBB (IEJ )
(59
where
•
•
•
•
•
•
•
•
•
•
VOUT = target output voltage
FSW = maximum switching frequency including tolerance
toff(min) = minimum off time including tolerance
Rdsl = low side FET on resistance
Rdsh = high side FET on resistance
RL = inductor DC resistance
IO = maximum load current
td1 = dead time between high side FET off and low side FET on, 15nS typical
td2 = dead time between low side FET off and high side FET on, 10nS typical
Vd = forward voltage of low side FET body diode
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8.2.3 Application Curves
TA = 25°C, VIN = 12 V (unless otherwise noted)
3.31
3.33
3.305
3.32
3.31
3.295
Output Voltage (V)
Output Voltage (V)
3.3
3.29
3.285
3.28
3.275
3.27
3.265
0.5
3.27
0A Load
1.5A Load
3A Load
3.25
3.255
0
3.28
3.26
Vin = 6.5V
Vin = 12V
Vin = 17V
3.26
3.3
3.29
1
1.5
2
Output Current (A)
2.5
3
3.24
6.5
7.5
8.5
D001
Figure 20. Load Regulation
9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.517
Input Voltage (V)
D001
Figure 21. Line Regulation
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
Vin = 6.5V
Vin = 9V
Vin = 12V
Vin = 15V
Vin = 17V
20%
10%
0
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D001
IOUT = 3 A
Figure 22. Efficiency
Figure 23. Input Voltage Ripple
IOUT = 0 A
IOUT = 5 mA
Figure 24. Output Voltage Ripple
16
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IOUT = 10 mA
IOUT = 0.25 A
Figure 26. Output Voltage Ripple
IOUT = 3 A
Figure 27. Output Voltage Ripple
Slew rate is 1.6A/µs
Figure 28. Output Voltage Ripple
Slew rate is 1.6A/µs
Figure 29. Transient Response, 0.6 to 2.4A
IOUT = 0 A
Figure 30. Transient Response, 0 to 3 A
Figure 31. Start Up Relative to VIN
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IOUT = 3 A
IOUT = 0 A
Figure 32. Start-Up Relative to EN
Figure 33. Shutdown Relative to VIN
IOUT = 3 A
Figure 34. Shutdown Relative to EN
9 Power Supply Recommendations
TPS563240 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation.
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not suggest routing SW copper under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
Trace on the
bottom layer
GND
VOUT
OUTPUT
CAPACITOR
Additional
Vias to the
GND plane
BOOST
CAPACITOR
GND
BST
SW
EN
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
OUTPUT
INDUCTOR
VIN
VIN
FB
GND trace under IC
On top layer
INPUT BYPASS
CAPACITOR
GND
Figure 35. Example Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
D-CAP3, Out-of-Audio, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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26-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS563240DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
3240
TPS563240DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
3240
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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26-Jul-2019
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
SCALE 4.000
SOT
3.05
2.55
1.75
1.45
PIN 1
INDEX AREA
1.1 MAX
B
1
0.1 C
A
6
4X 0.95
3.05
2.75
1.9
4
3
0.5
0.3
0.2
0.1
TYP
0.0
6X
0 -8 TYP
0.20
TYP
0.12
C A B
C
SEATING PLANE
0.6
TYP
0.3
0.25
GAGE PLANE
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
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EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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