Texas Instruments | TPS65235 LNB Voltage Regulator With I2C Interface (Rev. C) | Datasheet | Texas Instruments TPS65235 LNB Voltage Regulator With I2C Interface (Rev. C) Datasheet

Texas Instruments TPS65235 LNB Voltage Regulator With I2C Interface (Rev. C) Datasheet
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TPS65235
SLVSD80C – NOVEMBER 2015 – REVISED JULY 2019
TPS65235 LNB Voltage Regulator With I2C Interface
1 Features
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3 Description
2
Complete Integrate Solution for LNB and I C
Interface
DiSEqC 2.x, and DiSEqC 1.x Compatible
Supports 5-V, 12-V and 15-V Power Rail
Up to 1000 mA Accurate Output Current Limit
Adjustable by External Resistor
Boost Switch Peak Current Limit Proportional to
LDO Current Limit
Boost Converter with 140-mΩ Low Rds(on) Internal
Power Switch
Boost Switching Frequency 1-MHz or 500-kHz
Selectable
Dedicated Enable Pin for Non-I2C Application
Low Drop Output LDO With Push-pull Output
Stage for VLNB Output
Built-in Accurate 22-kHz Tone Generator and
External Tone Input Support
Supports Both External 44-kHz and 22-kHz Tone
Input
Adjustable Soft-start and 13-V to 18-V Voltage
Transition Time
650 mV to 750-mV, 22-kHz Tone Amplitude
Selection
I2C Registers Accessible with EN Low
Short Circuit Dynamic Protection
Diagnostics for Output Voltage Level, DiSEqC
Tone Input and Output, Current Level, and Cable
Connection
Thermal Protection Available
20-Lead WQFN 3-mm x 3-mm (RUK) Package
Designed for analog and digital satellite receivers, the
TPS65235 is a monolithic voltage regulator with I2C
interface; specifically to provide the 13-V to 18-V
power supply and the 22-kHz tone signal to the LNB
down converter in the antenna dish or to the multiswitch box. It offers a complete solution with
minimum component count, low power dissipation
together with simple design and I2C standard
interface.
TPS65235 features high power efficiency. The boost
converter integrates a 140-mΩ power MOSFET
running at 1 MHz or 500 kHz selectable switching
frequency. Drop out voltage at the linear regulator is
0.8 V to minimize power loss. TPS65235 provides
multiple ways to generate the 22 kHz signal.
Integrated linear regulator with push-pull output stage
generates 22-kHz tone signal superimposed at the
output even at zero loading. Current limit of linear
regulator can be programmed by external resistor
with ±10% accuracy. Full range of diagnostic read by
I2C is available for system monitoring.
TPS65235 supports advanced DiSEqC 2.x standard
with 22-kHz tone detection circuit and output
interface.
Device Information(1)
PART NUMBER
TPS65235
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
TPS65235
100nF
VOUT
2 Applications
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PACKAGE
WQFN
VLNB
Set Top Box Satellite Receiver
TV Satellite Receiver
PC card Satellite Receiver
Satellite TV
0.1PF
VCP
ISET
BOOST
2x22PF
110k
PGND
TCAP
22nF
AGND
VIN
10PH
LX
10PF
VIN
VCC
1PF
1PF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65235
SLVSD80C – NOVEMBER 2015 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 18
7.6 Register Maps ......................................................... 20
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application for DiSEqc1.x Support ............ 23
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision B (July 2018) to Revision C
Page
•
Changed V(drop) at TONEAMP = 0b From: MIN = 0.59 TYP = 0.8 MAX = 1 To: MIN = 0.49 TYP = 0.8 MAX = 1.1 in
the Electrical Characteristics .................................................................................................................................................. 5
•
Changed V(drop) at TONEAMP = 1b From: MIN = 0.71 TYP = 0.9 MAX = 1.12 To: MIN = 0.65 TYP = 0.9 MAX = 1.2
in the Electrical Characteristics .............................................................................................................................................. 5
Changes from Revision A (December 2017) to Revision B
•
Page
Changed the GDR TONE_TRANS = 1b value From: MAX = 24.03V To: MAX = 24.33V in the Electrical
Characteristics ....................................................................................................................................................................... 5
Changes from Original (January 2017) to Revision A
Page
•
Changed the VCP values From: VLNB to 7 V To: –0.3 V to 7 V in the Absolute Maximum Ratings .................................... 4
•
Changed the GDR values From: VLNB to VCP To: –0.3 V to 7 V in the Absolute Maximum Ratings.................................. 4
•
Changed the Operating junction temperature From: 125°C To: 150°C in the Absolute Maximum Ratings .......................... 4
•
Changed VIN MAX value From: 16 V To: 20 V in Recommended Operating Conditions ...................................................... 4
•
Changed VIN MAX value From: 16 V To: 20 V in Electrical Characteristics ......................................................................... 5
•
Changed 4.7 µF To: 4 µF in the line callouts of Figure 12 .................................................................................................. 14
•
Changed 4 µF To: 5 µF in the graph legends of Figure 13 ................................................................................................. 15
•
Changed the description of bit 1 TONE_AUTO From: "controlled by TONE_RECEIVE" To: "controlled by
TONE_TRANS" in Table 7 ................................................................................................................................................... 21
2
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SLVSD80C – NOVEMBER 2015 – REVISED JULY 2019
5 Pin Configuration and Functions
DIN
DOUT
EXTM
SCL
SDA
RUK Package
20 Pin (WQFN-20)
Top View
15
14
13
12
11
VCP
17
9
ADDR
BOOST
18
8
FAULT
GDR
19
7
EN
PGND
20
6
ISET
LX
1
2
3
4
5
TCAP
VCTRL
AGND
10
VCC
16
VIN
VLNB
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
LX
1
I
Switching node of the boost converter
VIN
2
S
Input of internal linear regulator
VCC
3
O
Internal 6.3-V power supply. Connect a 1-μF ceramic capacitor from this pin to ground. When VIN is 5 V,
connect VCC to VIN.
AGND
4
S
Analog ground. Connect all ground pins and power pad together.
TCAP
5
O
Connect a capacitor to this pin to set the rise time of the LNB output.
ISET
6
O
Connect a resistor to this pin to set the LNB output current limit.
EN
7
I
Enable pin to enable the VLNB output; pull to ground to disable output, and output will be pulled to
ground, when the EN is low, the I2C can be accessed
FAULT
8
O
Oopen drain output pin, it goes low if any fault flag is set.
ADDR
9
I
Connecting different resistor to this pin to set different I2C address, see Table 4.
VCTRL
10
I
Voltage level at this pin to set the output voltage, see Table 3.
SDA
11
I/O
SCL
12
I
I2C compatible clock input
EXTM
13
I
External modulation logic input pin which activates the 22-kHz tone output, feeding signal can be 22-kHz
tone or logic high or low.
DOUT
14
O
Tone detection output
DIN
15
I
Tone detection input
VLNB
16
O
Output of the power supply connected to satellite receiver or switch.
VCP
17
O
Gate drive supply voltage, output of charge pump, connect a capacitor between this pin to pin VLNB.
BOOST
18
O
Output of the boost regulator and Input voltage of the internal linear regulator.
GDR
19
O
Control the gate of the external MOSFET for DiSEqc 2.x support.
PGND
20
S
Power ground for Boost Converter
Thermal PAD
(1)
I2C compatible bi-directional data
Must be soldered to PCB for optimal thermal performance. Have thermal Vias on the PCB to enhance
power dissipation.
I = input, O = output, I/O = input and output, S = power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
1
30
VCP, GDR (referenced to VLNB pin)
–0.3
7
VCC, EN, ADDR, FAULT, SCL, SDA, VCTRL, EXTM, DOUT, DIN,
TCAP
–0.3
7
ISET
–0.3
3.6
PGND
–0.3
0.3
Operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–55
150
VIN, LX, BOOST, VLNB
Voltage
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
20
V
TA
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS65235
THERMAL METRIC (1)
RUK (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.3
°C/W
RθJB
Junction-to-board thermal resistance
16.5
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
VIN
4.5
12
20
V
IDD(SDN)
Shutdown supply current
EN = 0
90
120
150
µA
ILDO(Q)
LDO quiescent current
EN = 1, IO = 0 A, VLNB = 18.2 V
mA
UVLO
VIN Undervoltage Lockout
2.2
5
7.8
VIN Rising
4.15
4.3
4.45
V
Hysteresis
280
480
550
mV
V(ctrl) = 1, IO = 500 mA
18
18.2
18.4
V
V(ctrl) = 0, IO = 500 mA
13.25
13.4
13.55
V
SCL = 1, V(ctrl) = 1, IO = 500 mA (Non I C)
19.18
19.4
19.62
V
SCL = 1, V(ctrl) = 0, IO = 500 mA (Non I2C)
14.44
14.6
14.76
R(SET) = 200 kΩ, Full temperature
580
650
720
OUTPUT VOLTAGE
VOUT
Regulated output voltage
2
V
mA
I(OCP)
Output short circuit current limit
TJ = 25°C
629
650
688
mA
Fsw
Boost switching frequency
1 MHz
977
1060
1134
kHz
I(limitsw)
Switching current limit
VIN = 12 V, VOUT = 18.2 V,
R(SET) = 200 kΩ
2.4
3
3.6
A
Rds(on)_LS
On resistance of low side FET
VIN = 12 V
90
140
210
mΩ
IO = 500 mA, TONEAMP = 0
0.49
0.8
1.1
V
IO = 500 mA, TONEAMP = 1
0.65
0.9
1.2
V
V(drop)
Linear regulator voltage drop-out
I(cable)
Cable good detection current threshold
VIN = 12 V, VOUT = 13.4 V or 18.2 V
0.9
5
8.8
mA
I(rev)
Reverse bias current
EN = 1, VLNB = 21 V
49
58
65
mA
I(rev_dis)
Disabled reverse bias current
EN = 0, VLNB = 21 V
3.72
4.6
5.63
mA
LOGIC SIGNALS
V(EN)
I(EN)
V(VCTRL_H)
V(EXTM_H)
V(VCTRL_L)
V(EXTM_L)
VOL(FAULT)
Enable threshold High
1.6
V
Enable threshold Low
Enable internal pull up current
0.8
V
V(EN) = 1.5 V
5
6
7
µA
V(EN) = 1 V
2
3
4
µA
High level input voltage
2
V
VCTRL, EXTM Logic threshold level
Low level input voltage
0.8
V
FAULT output low voltage
FAULT open drain, IOL = 1 mA
0.4
V
Tone frequency
22 kHz tone output
TONE
f(tone)
A(tone)
D(tone)
f(EXTM)
Tone amplitude
20
22
24
kHz
IO = 0 mA to 500 mA, CO = 100 nF,
TONEAMP = 0
617
650
696
mV
IO = 0 mA to 500 mA, CO = 100 nF,
TONEAMP = 1
703
750
803
mV
Tone duty cycle
External tone input frequency range
45%
50%
55%
22 kHz tone output
17.6
22
26.4
kHz
44 kHz tone output
35.2
44
52.8
kHz
22
26.4
kHz
1.5
V
0.4
V
TONE DETECTION
f(DIN)
Tone detector frequency capture range
0.4 VPP sine wave
17.6
V(DIN)
Tone detector input amplitude
Sine wave, 22 kHz
0.3
V(DOUT)
DOUT output voltage
Tone present, Iload = 2 mA
GDR
Bypass FET gate voltage/LNB
TONE_TRANS = 1, V(LNB) = 18.2 V
23.11
23.5
24.33
V
TONE_TRANS = 0, V(LNB) = 18.2 V
18.17
18.2
18.23
V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP)
Thermal protection trip Point
T(HYST)
Thermal protection hysteresis
Temperature Rising
160
°C
20
°C
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C READ BACK FAULT STATUS
V(PGOOD)
T(warn)
PGOOD trip levels
Feedback voltage UVP low
94%
96%
97.1%
Feedback voltage UVP high
93%
94.5%
95.5%
Feedback voltage OVP high
104%
106.6%
108%
Feedback voltage OVP low
102%
104.6%
106%
Temperature warning Threshold
125
°C
I2C INTERFACE
VIH
SDA,SCL input high voltage
VIL
SDA,SCL input low voltage
2
II
Input current
SDA, SCL, VI = 0.4 to 4.5 V
VOL
SDA output low voltage
SDA open drain, IOL = 2 mA
f(SCL)
Maximum SCL clock frequency
V
–10
0.8
V
10
µA
0.4
400
V
kHz
6.6 Timing Requirements
MIN
NOM
75
102
MAX
UNIT
OUTPUT VOLTAGE
tr, tf
13 V to 18 V transition rising falling time
tON(min)
Minimum on time for the Low side FET
C(TCAP) = 22 nF
2
ms
130
ns
TONE
tr(tone)
tf(tone)
Tone rise time
Tone fall time
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0
11
µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has
44 kHz input
5.5
µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 0
10.8
µs
IO = 0 mA to 500 mA, CO = 100 nF,
Control Reg1[0] = 1, and EXTM has
44 kHz input
5.4
µs
PROTECTION
tON
Overcurrent protection ON Time
TIMER=0
2.3
3.75
5.52
ms
tOFF
Overcurrent protection OFF Time
TIMER=0
98.5
118
133.5
ms
2
I C INTERFACE
tBUF
Bus free time between a STOP and START
condition
1.3
µs
tHD_STA
Hold time (repeated) START condition
0.6
µs
tSU_STO
Setup time for STOP condition
0.6
µs
tLOW
LOW period of the SCL clock
1.3
µs
tHIGH
HIGH period of the SCL clock
0.6
µs
tSU_STA
Setup time for a repeated START condition
0.6
µs
tSU_DAT
Data setup time
0.1
tHD_DAT
Data hold time
tRCL
Rise time of SCL signal
µs
0
0.9
µs
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tRCL1
Rise time of SCL Signal after a Repeated START
condition and after an acknowledge BIT
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tFCL
Fall time of SCL signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tRDA
Rise time of SDA signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tFDA
Fall time of SDA signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
CB
Capacitance of one bus line(SCL and SDA)
400
pF
6
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6.7 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = 2 x 22 µF/35 V (unless otherwise noted)
95%
13.45
13.44
90%
13.43
Output Voltage (V)
Efficiency
85%
80%
75%
70%
13.42
13.41
13.4
13.39
13.38
13.37
65%
V(LNB) = 13.4 V
V(LNB) = 18.2 V
13.36
60%
13.35
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
0
0.1
0.2
D001
L = 4.7 µH
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
D002
V(LNB) = 13.4 V
Figure 1. Power Efficiency
Figure 2. Load Regulation
18.3
7
18.28
6.5
IDD Quiesent Current (mA)
18.26
Output Voltage (V)
0.3
18.24
18.22
18.2
18.18
18.16
18.14
6
5.5
5
4.5
4
3.5
18.12
18.1
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
3
-40
1
-20
0
D003
20
40
60
80
100
Junction Temperature (qC)
120
140
D004
V(LNB) = 18.2 V
Figure 4. Input Supply Quiescent Current vs Junction
Temperature
135
680
130
670
IDD Current Limit (mA)
IDD Shutdown Current (mA)
Figure 3. Load Regulation
125
120
115
110
105
-40
660
650
640
630
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
620
-40
-20
D005
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D006
ILOAD = 650 mA
Figure 5. Shutdown Current vs Junction Temperature
Figure 6. LNB Current Limit vs Junction Temperature
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7 Detailed Description
7.1 Overview
TPS65235 is the Power management IC that integrates a boost converter, a LDO and a 22 kHz tone generator
to serve as a LNB power supply. This solution compiles the DiSEqC 2.x standard with or without I2C interface.
Output current limitation can be precisely programmed by an external resistor. There are two ways to generate
the 22 kHz tone signal, with or without I2C. Integrated boost features low Rds(on) MOSFET and internal
compensation. 1 MHz or 500 kHz selectable switching frequency is designed to save passive components size
and be flexible for design.
TPS65235 can support the 44-kHz tone output, when the EXTM has 44-kHz tone input, and the bit EXTM TONE
of Control Register 1 is set to “1”, the LNB tone output is 44 kHz. By default, the TPS65235 has a typical 22-kHz
tone output.
LX
VIN
7.2 Functional Block Diagram
EN
REF_Boost
VCC
Internal Regulator
PWM Controller
PGND
REF_Boost
TCAP
BOOST
REF
VCTRL
VCP
Charge Pump
VLNB
REF_LDO
ADDR
EN
I2C Interface
I2C EN
Tone
Generator
Fault Diagnose
OCP
OTP
VLNB
Tone_Auto
Tone_Trans
EXTM
GDR
Logic
Tone
Det
DIN
DOUT
ISET
EXTM
AGND
FAULT
VLNB
PGOOD
VCP
SDA
SCL
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7.3 Feature Description
7.3.1 Boost Converter
The TPS65235 consists of an internal compensated boost converter and linear regulator. The boost converter
tracks the LNB output voltage within 800 mV even at loading 1000 mA, which minimizes power loss. When the
input voltage VIN is greater than the expected output voltage VLNB, the linear regulator drops the voltage
difference between VIN and VLNB, which causes the lower efficiency and the higher power loss on the internal
linear regulator if the current loading is high. For this application, care must be taken to ensure that the safe
operating temperature range of the TPS65235 is not exceeded. Recommend to work at force PWM mode when
VIN > VOUT to reduce output ripple.
As default, the boost converter operates at 1 MHz. TPS65235 has internal cycle-by-cycle peak current limit in the
boost converter and DC current limit in the LNB output to protect the IC against short circuits and over loading.
When the LNB output is shorted to ground, the LNB output current is clamped at the LDO current limit. The LDO
current limit is set by the external resistor at ISET pin; meanwhile the Boost switch current limit is proportional
with LDO current limit. If overcurrent condition lasts for more than 4 ms, the Boost converter enters hiccup mode
and will re-try startup in 128 ms. This hiccup mode ON/OFF time can be selectable by I2C control register 0x01,
either 4 ms / 128 ms or 8 ms / 256 ms. At extremely light loads, the boost converter operates in a pulse-skipping
mode automatically.
Boost converter is stable with either ceramic capacitor or electrolytic capacitor.
If two or more set top box LNB outputs are connected together, one output voltage could be set higher than
others. The output with lower set voltage would be effectively turned off. Once the voltage drops to the set level,
the LNB output with lower set output voltage returns to normal conditions.
7.3.2 Linear Regulator and Current Limit
The linear regulator is used to generate the 22-kHz tone signal by changing the LDO reference voltage. The
linear regulator features low drop out voltage to minimize power loss while keeps enough head room for the 22kHz tone with 650-mV amplitude. It also implements a tight current limit for overcurrent protection. The current
limit is set by an external resistor connected to ISET pin. Figure 7 shows the relationship between the current
limit threshold and the resistor value.
550
y = 117.08x-1.267
500
450
RSET (K)
400
350
300
250
200
150
100
0.3
0.4
0.5
0.6
0.7
0.8
ISET (A)
0.9
1
1.1
1.2
D007
Figure 7. Linear Regulator Current Limit Vs Resistor
RSET (k:) 117.08 x ISET 1.267 (A)
(1)
A 200-kΩ resistor sets the current to be 0.65 A, and 110-kΩ resistor sets the current to approximately 1 A.
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Feature Description (continued)
7.3.3 Boost Converter Current Limit
The boost converter has the cycle-by-cycle peak current limit on the internal Power MOSFET switch to serve as
the secondary protection when LNB output is hard short. With ISW bit default setting “0” on I2C control register
0x01, the switch current limit ISW is proportional as LDO current limit I(OCP) set by ISET pin resistor, and the
relationship can be expressed as:
ISW
3 x I(OCP)
0.8A
(2)
For the 5 V VIN, if LNB current load is up to 1 A, the ISW bit should be written as “1”, the switch current limit ISW
for the internal Power MOSFET is:
ISW
5 x I(OCP)
0.8A
(3)
While due to the high power loss at 5 V, VIN, it has a chance to trigger the thermal shutdown before the loading is
up to 1 A, especially the VLNB output is high.
7.3.4 Charge Pump
The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. The voltage across the
charge pump capacitor between VLNB and VCP is about 5.4 V, so the absolute value of the VCP voltage will be
VLNB + 5.4 V.
7.3.5 Slew Rate Control
When LNB output voltage transits from 13.4 V to 18.2 V or 18.2 V to 13.4 V, the cap at pin TCAP controls the
transition time. This transition time makes sure the boost converter output to follow LNB output change. Usually
boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage
of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to
generate a 0.8 V above the LNB output.
The charging and discharging current is 10 µA, thus the transition time can be estimated as:
t TCAP (ms)
0.8 x
CSS (nF)
ISS (PA)
(4)
A 22-nF capacitor generates about 2 ms transition time.
In light load conditions, when LNB output voltage is set from 18.2 V to 13.4 V, the voltage drops very slow, which
causes wrong VOUT_GOOD (Bit 0 at status register 0x02) logic for LNB output voltage detection. TPS65235 has
integrated a pull down circuit to pull down the output during the transition. This ensures the voltage change can
follow the voltage at TCAP. When the 22-kHz tone signal is superimposing on the LNB output voltage, the pull
down current can also provide square wave instead of a distorted waveforms.
7.3.6 Short Circuit Protection, Hiccup and Overtemperature Protection
The LNB output current limit can be set by an external resistor. When short circuit conditions occur or current
limit is triggered, the output current is clamped at the current limit for 4 ms with LDO on. If the condition retains,
the converter will shut down for 128 ms and then restart. This hiccup behavior prevents IC from being overheat.
The hiccup ON/OFF time can be set by I2C register. Refer to Control Register 1 for detail.
The low side MOSFET of the boost converter has a peak current limit threshold which serves as the secondary
protection. If boost converter’s peak current limit is triggered, the peak current will be clamped as high as 3.8 A
when setting ISW default and LNB current limit up to 1 A. If loading current continues to increase, output voltage
starts to drop and output power drops.
Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the junction
temperature exceeds 160°C, the output shuts down. When the die temperature drops below its lower threshold
typically 140°C, the output is enabled.
10
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Feature Description (continued)
When the chip is in overcurrent protection or thermal shutdown, the I2C interface and logic are still active. The
Fault pin is pulled down to signal the processor. The Fault pin signal remains low unless the following action is
taken:
1. If I2C interface is not used to control, EN pin must be recycled in order to pull Fault pin back to high.
2. If I2C interface is used, the I2C master need to read the status Control Register 2, then the Fault pin will be
back to high.
7.3.7 Tone Generation
22 kHz tone signal is implemented at the LNB output voltage as a carrier for DiSEqC command. This tone signal
can be generated by feeding an external 22-kHz clock at the EXTM pin, and it can also be generated with its
internal tone generator controlled by EXTM pin. If EXTM pin is toggled to high, the internal tone signal will be
superimposed at the LNB output, if EXTM pin is low, there will be no tone superimposed at the output stage of
the regulator facilitates a push-pull circuit, so even at zero loading; the 22-kHz tone at the output is still clean
without distortion.
There are two ways to generate the 22 kHz tone signal at the output.
For option1, if the EXTM has 44-kHz tone input, and the bit EXTM TONE of the Control Register 1 is set to "1",
the LNB tone output is 44 kHz.
EXTM
TONE
VLNB(V)
Option 1. Use external tone, gated by EXTM logic pulse
EXTM
TONE
VLNB(V)
Option 2. Use internal tone, gated by EXTM logic envelop
Figure 8. Two Ways to Generate 22 kHz Tone
7.3.8 Tone Detection
A 22-kHz tone detector is implemented in the TPS65235 solution. The detector extracts the AC coupled tone
signal from the DIN input and provides it as an open-drain signal on the DOUT pin. With bit DOUTMODE default
setting of the Control Register 2, if tone is present, the DOUT output is logic low; if tone is not present, the
internal output FET is off. If a pull high resistor is connected to the DOUT pin, the output is logic high. The
maximum tone out delay with respect to the input is one and half tone cycle.
Bit DOUTMODE of Control Register 2 is reserved and should not be used.
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Feature Description (continued)
7.3.9 Disable and Enable
TPS65235 has a dedicated EN pin to disable and enable the LNB output. At non-I2C application, when the EN
pin is pulled to high, the LNB output is enabled, when the EN pin is pull to low, the LNB output is disabled. At I2C
application, either EN pin is low or high, the I2C registers can be accessed, which allows customer to change the
default LNB output when system power up. When the bit I2C_CON of Control Register 1 is set to “1”, the LNB
output enable or disable is controlled by bit EN of Control Register 2. By default, the bit I2C_CON of the control
register is set to “0”, which makes the LNB output is controlled by the EN pin. Figure 9 and Figure 10 shows the
detail control behavior.
EN pin = 0 V
Bit I2C_CON = 1
Bit I2C_CON = 0
Figure 9. VLNB Output Controlled by bit EN of Control
Register 2
Figure 10. VLNB Output Controlled by EN Pin
7.3.10 Component Selection
7.3.10.1 Boost Inductor
TPS65235 is recommended to operate with a boost inductor value of 4.7 µH or 10 µH. The boost inductor must
be able to support the peak current requirement to maintain the maximum LNB output current without saturation.
Below formula can be used to estimate the peak current of the boost inductor.
IOUT
1- D
Ipeak
D
1-
V xD
1
x IN
2
L x fS
(5)
VIN
VLNB 0.8
(6)
With the different inductance, the system will have different gain and phase margins, Figure 11 shows a Bode
plot of boost loop with 2 x 10 µF / 35 V of boost capacitor and 4.7 µH, 5.6 µH, 6.8 µH, 8.2 µH and 10 µH of boost
inductance. As the boost inductance increases, the 0 dB crossover frequency keeps relatively constant while the
phase and gain margins reduced. With 4.7 µH, the phase margin is 66.96° and with 10 µH the phase margin is
39.63°.
12
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Feature Description (continued)
Loop Gain (dB)
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
4.7 mH, 66.96 deg
10 mH, 39.63 deg
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
Figure 11. Gain and Phase Margin of the Boost Loop with Different Inductance
(VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, FSW = 1 MHz, 5 µF, Typical Bode Plot)
7.3.10.2 Capacitor Selection
TPS65235 has a 1 MHz non-synchronous boost converter integrated and the boost converter features the
internal compensation network. TPS65235 works well with both ceramic capacitor and electrolytic capacitor.
In TPS65235 application, the recommended ceramic capacitors rated are at least X7R/X5R, 35 V rating and
1206 size for the achieving lower LNB output ripple. Table 1 shows the recommended ceramic capacitors list for
both 4.7uH and 10uH boost inductors.
If lower cost is demanded, a 100-µF electrolytic (Low ESR) and a 10-µF/35-V ceramic capacitor also work well,
this solution provides lower system cost.
Table 1. Boost Inductor and Capacitor Selections
Boost Inductor
10 µH
4.7 µH
Capacitors
Tolerance (%)
Rating (V)
Size
2 x 22 µF
±10
35
1206
2 x 10 µF
±10
35
1206
2 x 22 µF
±10
35
1206
2 x 10 µF
±10
35
1206
22 µF
±10
35
1206
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Loop Gain (dB)
Figure 12 and Figure 13 show a Bode plot of boost loop with 4.7 µH / 10 µH inductance and 4 µF, 5 µF, 7.5 µF,
10 µF, 15 µF and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the phase
margin decreases.
4 mF
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
20 mF
4 mF, 57.45 deg
20 mF, 84.49 deg
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
Figure 12. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance
(VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, FSW = 1 MHz, 4.7 µH, Typical Bode Plot)
14
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Loop Gain (dB)
5 mF
7.5 mF
10 mF
15 mF
20 mF
5 mF
20 mF
5 mF, 37.23 deg
20 mF, 78.74 deg
5 mF
7.5 mF
10 mF
15 mF
20 mF
Figure 13. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance
(VIN = 12 V, VOUT = 18.2 V, ILOAD = 1 A, FSW = 1 MHz, 10 µH, Typical Bode Plot)
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7.3.10.3 Surge Components
If surge test is needed for the application, D0 and D2 should be added as the external protection components. If
no surge test needed. The D0 and D2 can be removed.
Table 2. Surge Components
Designator
Description
Part Number
Manufacturer
D0
D2
Diode, TVS, Uni, 28 V, 1500 W, SMC
SMCJ28A
Fairchild Semiconductor
Diode, Schottky, 40 V, 2 A, SMA
B240A-13-F
Diodes Inc.
100nF 0.1PF
VOUT
16 VLNB
D3
D0
D2
17 VCP
18 BOOST
2x22PF
19 GDR
VIN
10PH
TPS65235
VIN
20 PGND
LX
D1
1
2
10PF
1PF
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Surge Components Selection
7.3.10.4 Consideration for Boost Filtering and LNB Noise
Smaller capacitance on boost will lead the cost down for the system, while when the inductor in system is same,
the smaller capacitance on the boost and the larger ripple on the LNB output.
16
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7.4 Device Functional Modes
Table 3. Logic table
EN
12C_CON
VCTRL
VLNB (4)
0
H
H
19.4 V
H
0
H
L
14.6 V
H
0
L
H
18.2 V
H
0
L
L
13.4 V
Controlled by VSET[3:0]
bits at 0x01 register (5)
L
(5)
SCL
H
X
(1)
(2)
(3)
(4)
(1) (2) (3)
1
X
X
0
X
X
2
0V
2
I2C_CON is the bit7 of the I C control register 0x01, which is used to set the VLNB output controlled by the I C register or not.
When I2C interface is used in design, all the I2C registers are accessible even if the I2C_CON bit is “0”.
When I2C_CON is “1”, the VLNB output is controlled by the I2C control register even if the EN pin is low.
When I2C interface is used in design, it is recommended to set the I2C_CON with “1”, if not, the LNB output will be variable because the
SCL is toggled by the I2C register access as the clock signal.
Bit EN of the control register2 is used to disable or enable the LNB output, by default , the bit EN is "1" which enable the LNB output
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7.5 Programming
7.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high external. All the I2C compatible devices connect to the I2C
bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS65235 device works as a slave and supports the following data transfer modes, as defined in the I2CBus
Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the power
supply solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V
(typical).
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The TPS65235 device supports 7-bit addressing; 10-bit addressing and general call
address are not supported.
The TPS65235 device has a 7-bit address set by ADDR pin. Table 4 shows how to set the I2C address.
Table 4. I2C Address Selection
I2C ADDRESS
Address Format (A6 ≥ A0)
Connect to VCC
0x08H
000 1000
Floating
0x09H
000 1001
Connected to GND
0x10H
001 0000
Resistor divider to make ADDR pin voltage in 3 V ~ VCC - 0.8 V
0x11H
001 0001
ADDR PIN
SDA
tSU, DAT
tLOW
tHD, DAT
tBUF
tSU, STO
tSU, STA
tHD, STA
SCL
tHD, STA
Start
Condition
tHIGH
tr
tSP
tf
Repeated Start
Condition
Stop
Condition
Start
Condition
Figure 15. I2C Interface Timing Diagram
18
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7.5.2 TPS65235 I2C Update Sequence
The TPS65235 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS65235 device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. TPS65235 performs an update on the falling edge of the LSB byte.
When the TPS65235 is disabled (EN pin tied to ground) the device cannot be updated via the I2C interface.
S
7-Bit Slave Address
A6«.A0
0
A
A
Register Address
A
Data Byte
P
Figure 16. I2C Write Data Format
S
7-Bit Slave Address
A6«.A0
0
A
Register1 Address
N
Data Byte
A Sr
7-Bit Slave Address
1
A
P
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
P: Stop
Sr: Repeated Start
Chip
Figure 17. I2C Read Data Format
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7.6 Register Maps
7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
Figure 18. Control Register 1
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Control Register 1
Bit
Field
Type
Reset
Description
7
I2C_CON
R/W
0
1: I2C control enabled
0: I2C control disabled
6
PWM/PSM
R/W
0
0: PSM at light load
1: Forced PWM
5
R/W
4
VSET3
R/W
0
3
VSET2
R/W
1
2
VSET1
R/W
0
1
VSET0
R/W
0
0
EXTM TONE
R/W
See Table 6 for output voltage selection
1: EXTM 44-kHz tone input support, with 44-kHz tone output at
LNB
0: EXTM 44-kHz tone input not support, with only 22-kHz tone
output at LNB
0
Table 6. LNB Output Voltage Selection
20
VSET3
VSET2
VSET1
VSET0
0
0
0
0
11
0
0
0
1
11.6
0
0
1
0
12.2
0
0
1
1
12.8
0
1
0
0
13.4
0
1
0
1
14
0
1
1
0
14.6
0
1
1
1
15.2
1
0
0
0
15.8
1
0
0
1
16.4
1
0
1
0
17
1
0
1
1
17.6
1
1
0
0
18.2
1
1
0
1
18.8
1
1
1
0
19.4
1
1
1
1
20
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7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
Figure 19. Control Register 2
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Control Register 2
Bit
Field
Type
Reset
Description
7
TONEAMP
R/W
0
1: 22 kHz tone amplitude is 750 mV (typ)
0: 22 kHz tone amplitude is 650 mV (typ)
6
TIMER
R/W
0
1: Hiccup ON/OFF time set to 8 ms / 256 ms
0: Hiccup ON/OFF time set to 4 ms / 128 ms
5
ISW
R/W
0
1: Boost switch peak current limit set to 5 x Iocp + 0.8 A
0: Boost switch peak current limit set to 3 x Iocp + 0.8 A
4
FSET
R/W
0
1: 500 kHz switching frequency
0: 1 MHz switching frequency
3
EN
R/W
1
1: LNB output voltage Enabled
0: LNB output disabled
2
DOUTMODE
R/W
0
1: Reserved, cannot set to "1"
0: DOUT is kept to low when DIN has the tone input
1
TONE_AUTO
R/W
0
1: GDR (External bypass FET control) is automatically controlled
by 22 kHz tones transmit
0: GDR (External bypass FET control) is controlled by
TONE_TRANS
1
1: GDR output with VCP voltage. Bypass FET is ON for tone
transmit from TPS65235
0: GDR output with VLNB voltage for tone receive. Bypass FET
is OFF for tone receiving from satellite
0
TONE_TRANS
R/W
Table 8. 22-kHz Tone Receive Mode Selection
TONE_AUTO
TONE_TRANS
Bypass FET
0
0
OFF
0
1
ON
1
x
Auto Detect
TPS65235 has full range of diagnostic flags for operation and debug. Processor can read the status register to
check the error conditions. Once the error happens, the flags are changed, once the errors are gone, the flags
are set back without I2C access.
If flags TSD and OCP are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to
processor. Once TSD and OCP are set to “1”, the FAULT pin logic is latched to low, processor need to read this
status register in order to release the fault conditions.
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7.6.3 Status Register (address = 0x02H) [reset = x0100000]
Figure 20. Status Register
7
0
R
6
0
R
5
0
R
4
0
R
3
1
R
2
0
R
1
0
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Status Register
Bit
Field
Type
7
Reserved
R
6
TDETGOOD
R
0
1: 22 kHz tone detected on DIN pin is in range
0: 22 kHz tone detected on DIN pin is out of range
5
LDO_ON
R
1
1: Internal LDO is turned on and boost converter is on
0: Internal LDO is turned off but boost converter is on
4
T125
R
0
Die temperature > 125°C
Die temperature < 125°C
3
TSD
R
0
1: Thermal shutdown triggered. The Fault pin logic is latched to
low, processor need to read this register in order to release the
fault conditions
0: No thermal shutdown triggered
R
0
1: Over current protection triggered. The Fault pin logic is
latched to low, processor need to read this register in order to
release the fault conditions
0: Overcurrent protection conditions released
R
0
1: Cable connection good
0: Cable not connected
R
0
1: LNB output voltage in range
0: LNB output voltage out of range
2
22
Reset
Reserved
OCP
1
CABLE_GOOD
0
VOUT_GOOD
Description
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application for DiSEqc1.x Support
VOUT
100nF
15
14
13
12
11
DIN
DOUT
EXTM
SCL
SDA
TPS65235 can work at both I2C and non I2C interface mode, Figure 21 shows the application with I2C interface
for supporting DiSEqC 1.x application. With non I2C mode, the SCL, SDA and ADDR pins can be floating.
0.1PF
16 VLNB
D0
VCTRL 10
D3
D2
ADDR 9
17 VCP
10k
2x22PF
TPS65235
18 BOOST
FAULT 8
EN 7
19 GDR
D1
ISET 6
VIN
LX
VIN
VCC
AGND
TCAP
20 PGND
1
2
3
4
5
110k
10PH
22nF
1PF
10PF
1PF
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Application for DiSEqc1.x Support
8.2.1 Design Requirements
For this design example, see the parameters in Table 10.
Table 10. Design Parameters
PARAMETER
VALUE
Input voltage range, VIN
4.5 V to 16 V
Output voltage range VLNB
11 V to 20 V
Output current range
0 A to 1 A
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8.2.2 Detailed Design Procedure
To begin the design process, following need to be done:
• Inductor choose
– Based on the cost requirement, ripple requirement and Component Selection to choose the appropriate
inductor.
• Boost capacitor choose
– Based on the cost requirement, ripple requirement and Component Selection to choose the appropriate
capacitors.
• Diodes choose.
– D0 and D2 are for the surge protection requirement, if not requirement for surge, it can be removed. Refer
to Surge Components for the part selection.
– D1 is for the boost loop, schottky diode is recommended. The current and voltage capability of the D1 can
be determined by the detail application which including input and output power range, and current
requirement.
– D3 is for the VLNB output protection, schottky diode is recommended. The current and voltage capability of
the D3 can be determined by the detail application for the output.
24
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8.2.3 Application Curves
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = 2 x 22 µF/35 V (unless otherwise noted)
VLNB = 13.4 V
VLNB = 13.4 V
Figure 22. Soft Start, Delay from EN High to
LNB Output High
Figure 23. Disabled, Delay From EN Low to
LNB Output Low
VLNB = 18.2 V
VLNB = 18.2 V
Figure 24. Soft Start,Delay from EN High to
LNB Output High
Figure 25. Disabled, Delay From EN Low to
LNB Output Low
EN = 0
EN = 0
VLNB = 13.4 V
2
Figure 26. Soft Start, Delay From I C Enable (I2C_CON=1)
to LNB Output High
VLNB = 13.4 V
Figure 27. Delay From I2C Disable (I2C_CON=0) to
LNB Output Low
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VLNB = 13.4 V
VLNB = 13.4 V
Figure 28. No Load, 22 kHz Tone Output
VLNB = 18.2 V
26
Figure 29. 950 mA Load, 22 kHz Tone Output
VLNB = 18.2 V
Figure 30. No Load, 22 kHz Tone Output
Figure 31. 950 mA Load, 22 kHz Tone Output
Figure 32. No load, 22 kHz Tone Delay from EXTM 22 kHz
Input Turns High To Output Tone On
Figure 33. No load, 22 kHz Tone Delay from EXTM 22 kHz
Input Turns Low To Output Tone Off
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Figure 34. No Load, 22 kHz Tone Delay From EXTM Tone
Envelop Input Turns High To Output Tone On
Figure 35. No Load, 22 kHz Tone Delay From EXTM Tone
Envelop Input Turns Low To Output Tone Off
Figure 36. No Load, 44 kHz Tone Delay From EXTM 22 kHz
Input Turns High To Output Tone On
Figure 37. No Load, 44 kHz Tone Delay From EXTM 22 kHz
Input Turns Low To Output Tone Off
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8.2.4 Typical Application for DiSEqc2.x Support
TPS65235 can support both DiSEqC 1.x application and DiSEqC 2.x application, Figure 38 shows the application
for supporting DiSEqC 2.x application.
10k
220PH
VOUT
D2
22nF
14
13
12
11
EXTM
SCL
SDA
0.1PF
16 VLNB
100nF
D0
15
DOUT
10k
DIN
10nF
D3
VCTRL 10
ADDR 9
17 VCP
10k
15 Ohm
TPS65235
18 BOOST
2x22PF
FAULT 8
EN 7
19 GDR
VIN
ISET 6
VIN
VCC
AGND
TCAP
20 PGND
LX
D1
1
2
3
4
5
110k
10PH
22nF
1PF
10PF
1PF
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Application for DiSEqc2.x Support
8.2.4.1 Design Requirements
Refer to Typical Application for DiSEqc1.x Support for design requirements.
8.2.4.2 Detailed Design Procedure
Refer to Typical Application for DiSEqc1.x Support for detailed design procedures.
28
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8.2.4.3 Application Curves
Refer to Typical Application for DiSEqc1.x Support for application curves. While Figure 39 is special for DiSEqC
2.x application for tone detection.
Figure 39. DOUT Tone Detection Output
9 Power Supply Recommendations
The devices are designed to operate from an input supply ranging from 4.5 V to 16 V. The input supply should
be well regulated. If the input supply is located more than a few inches from the converter, an additional bulk
capacitance typically 100 µF may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
TPS65235 is designed to layout in 2-layer PCB. To ensure reliability of the device, following common printedcircuit board layout guidelines is recommended.
• It is critical to make sure the GND of input capacitor, output capacitor and the boost converter are connected
at one point at same layer.
• PGND and AGND are in different region, they are connected to the thermal pad. Other components are
connected AGND.
• Put the capacitors for boost as close as possible.
• The loop from VIN, inductor to LX should be as short as possible.
• The loop from VIN, inductor, D1 Schottky diode to Boost should be as short as possible.
• The loop for boost capacitors to PGND should be within the loop from LX, D1 Schottky diode to Boost.
10.2 Layout Example
Polygonal Copper Pour
13
12
11
EXTM
SCL
SDA
100nF
14
DOUT
D3
15
DIN
VIA to GND Plane (Inner Layer)
VOUT
16 VLNB
0.1uF
D2
17 VCP
VCTRL
10
ADDR
9
FAULT
8
EN
7
ISET
6
10k
18 BOOST
2x22uF
19 GDR
VIN
10uH
VIN
VCC
AGND
TCAP
D1
LX
20 PGND
1
2
3
4
5
1uF
110k
1uF
22nF
10uF
Figure 40. Layout
30
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65235RUKR
ACTIVE
WQFN
RUK
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65235
TPS65235RUKT
ACTIVE
WQFN
RUK
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65235
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65235RUKR
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS65235RUKR
WQFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS65235RUKT
WQFN
RUK
20
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65235RUKR
WQFN
RUK
20
3000
367.0
367.0
35.0
TPS65235RUKR
WQFN
RUK
20
3000
367.0
367.0
35.0
TPS65235RUKT
WQFN
RUK
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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