Texas Instruments | TPS2662x 60-V, 800-mA Industrial eFuse with Integrated Input and Output Reverse Polarity Protection (Rev. E) | Datasheet | Texas Instruments TPS2662x 60-V, 800-mA Industrial eFuse with Integrated Input and Output Reverse Polarity Protection (Rev. E) Datasheet

Texas Instruments TPS2662x 60-V, 800-mA Industrial eFuse with Integrated Input and Output Reverse Polarity Protection (Rev. E) Datasheet
Order
Now
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
TPS2662x 60-V, 800-mA Industrial eFuse with Integrated Input and Output Reverse
Polarity Protection
1 Features
3 Description
•
The TPS2662x family are compact, feature rich high
voltage eFuses with a full suite of protection features.
The wide supply input range of 4.5 V to 60 V allows
control of many popular DC bus voltages. The device
can withstand and protect the loads from positive and
negative supply voltages up to ±60 V. The TPS26624
and TPS26625 devices support both input as well as
output reverse polarity protection feature. Integrated
back to back FETs provide reverse current blocking
feature making the device suitable for systems with
output voltage holdup requirements during power fail
and brownout conditions. Load, source and device
protection are provided with many adjustable features
including overcurrent, output slew rate and
overvoltage, undervoltage thresholds. The internal
robust protection control blocks along with the high
voltage rating of the TPS2662x family helps to
simplify the system designs for Surge protection.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
4.5-V to 60-V Operating voltage,
62-V Absolute maximum
Integrated reverse input polarity protection to –60
V
Integrated reverse output polarity protection to –
(60 – VIN) (TPS26624 and TPS26625 Only)
Integrated back to back MOSFETs with 478-mΩ
total RON
25-mA to 880-mA Adjustable current limit
(±5% accuracy at 880 mA)
Load protection during surge (IEC 61000-4-5) with
minimum external components
Electrical fast transients immunity according to
IEC 61000-4-4
Fast reverse current blocking response (0.3 µs)
Adjustable UVLO, OVP cut off,
output slew rate control for inrush current limiting
Fixed 38-V overvoltage clamp
(TPS26622 and TPS26623 only)
Low quiescent current, 340 µA in operating,
12 µA in shutdown
Small foot print - 10L (3 mm × 3 mm) VSON
UL 2367 Recognized
– File No. 169910
– RILIM ≥ 7.5kΩ (0.91A Maximum )
IEC 62368-1 Certified
2 Applications
•
•
•
•
•
PLC I/O modules
AC and Servo drives
Sensor and controls
Thermostat
PoE Highside protection
R1
The devices are available in a 3 mm × 3 mm 10-pin
SON package and are specified over a –40°C to
+125°C temperature range.
Device Information(1)
PART NUMBER
TPS26620
TPS26621
TPS26622
TPS26623
TPS26624
TPS26625
PACKAGE
SON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Reverse Input Polarity Protection at –60-V Supply
Simplified Schematic
VIN: 4.5 V - 60 V
The TPS26620, TPS26622 and TPS26624 feature
Latch off and TPS26621, TPS26623 and TPS26625
feature Auto-Retry functionality are the over
temperature and over current fault events.
VIN
OUT
IN
VOUT
COUT
CIN
478 PŸ
R4
UVLO
OVP
R2
FLT
TPS2662x
SHDN
MODE
dVdT
R3
CdVdT
RTN
Health
Monitor
ON/OFF
Control
VOUT
IIN
ILIM
GND
RILIM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 8
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 25
10 Application and Implementation........................ 26
10.1
10.2
10.3
10.4
Application Information..........................................
Typical Application ...............................................
System Examples ................................................
Do's and Don'ts .....................................................
26
26
32
33
11 Power Supply Recommendations ..................... 34
11.1 Transient Protection .............................................. 34
12 Layout................................................................... 36
12.1 Layout Guidelines ................................................. 36
12.2 Layout Example .................................................... 37
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
Changes from Revision D (February 2019) to Revision E
Page
•
Changed from UL 2367 Recognition Pending to UL 2367 Recognized IEC 62368-1 Certified in the Features section ...... 1
•
Replaced TPS26623 with TPS26624 for Pin No. 4 SHDN in the Pin Functions table........................................................... 4
•
Added UVLO Recovery Time in the Timing Requirements table in the Specifications section ............................................ 6
•
Changed Input voltage range MAX from 60 V to 62 V in tne Absolute Maximum Ratings table in the Specifications
section ................................................................................................................................................................................... 6
•
Changed Input voltage MAX from 57 V to 60 V in the Recommended Operating Conditions table in the
Specifications section ............................................................................................................................................................. 6
•
Updated the Parameter Measurement Information graph to explain the UVLO_tREC .......................................................... 15
•
Updated the Feature Description Undervoltage Lockout (UVLO) section to explain the UVLO_tREC timer ......................... 18
•
Removed UVLO from the Overload Protection section ....................................................................................................... 22
Changes from Revision C (July 2018) to Revision D
•
Changed SHDN pin voltage MAX from 4 V to 6 V in the Recommended Operating Conditions table in the
Specifications section ............................................................................................................................................................. 6
Changes from Revision B (April 2018) to Revision C
•
2
Page
Changed status from Advanced Information to Production Data .......................................................................................... 1
Changes from Revision A (March 2018) to Revision B
•
Page
Page
Changed Repinse to Response in the Device Comparison table header ............................................................................. 4
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Changes from Original (October 2017) to Revision A
•
Page
Changed from one page to full data sheet ............................................................................................................................ 1
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
3
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
5 Device Comparison Table
PART NUMBER
OVERVOLTAGE PROTECTION
OVERLOAD and THERMAL FAULT
RESPONSE
REVERSE POLARITY PROTECTION
TPS26620
Overvoltage cut-off, adjustable
Latch Off
Input side
TPS26621
Overvoltage cut-off, adjustable
Auto-Retry
Input side
TPS26622
Overvoltage clamp, fixed (38 V)
Latch Off
Input side
TPS26623
Overvoltage clamp, fixed (38 V)
Auto-Retry
Input side
TPS26624
Overvoltage cut-off, adjustable
Latch Off
Input and Output side
TPS26625
Overvoltage cut-off, adjustable
Auto-Retry
Input and Output side
6 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
1
10
OUT
UVLO 2
9
FLT
8
dVdT
IN
OVP
3
SHDN
4
7
ILIM
RTN
5
6
GND
PowerPad TM
Pin Functions
PIN
4
TYPE
DESCRIPTION
NO.
NAME
1
IN
Power
2
UVLO
I
Resistor programmable undervoltage lockout threshold setting input. An undervoltage
event will open the internal FET. If the Undervoltage Lock Out function is not needed,
the UVLO terminal must be connected to the IN terminal with atleast 1 MΩ resistor.
UVLO pin is 5 V rated and this resistor limits the UVLO pin current to < 60 µA
Input supply voltage.
3
OVP
I
Resistor programmable overvoltage protection threshold. An overvoltage event will
open internal FET. In TPS26620, TPS26621, TPS26624, TPS26625 devices if over
voltage protection feature is not to be used then connect OVP terminal to RTN. For
overvoltage clamp response (TPS26622 and TPS26623 Only) connect OVP to RTN
externally.
4
SHDN
I
Shutdown PIN. Pulling it low makes the device to enter into low power shutdown
mode. Cycling SHDN low and then back high resets the device that has latched off
(TPS26620, TPS26622, TPS26624 only) due to a fault condition.
5
RTN
–
Reference ground for all internal voltages.
6
GND
–
System Ground.
7
ILIM
I/O
A resistor from this pin to RTN sets the overload and short-circuit current limit. See
the Overload and Short Circuit Protection section.
8
dVdT
I/O
A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In
and In-Rush Current Control section.
Fault event indicator. It is an open drain output. If unused, leave floating.
9
FLT
O
10
OUT
Power
Output Voltage.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Pin Functions (continued)
PIN
NO.
NAME
–
PowerPadTM
TYPE
DESCRIPTION
–
Connect PowerPad to RTN plane for heat sinking. Do not use PowerPad as the only
electrical connection to RTN.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
5
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted) (1)
IN, IN–OUT
OUT (TPS26624 and TPS26625 Only)
Input voltage range
62
–70
70
[IN, OUT, FLT, SHDN] to RTN
–0.3
62
[UVLO, OVP, dVdT, ILIM] to RTN
–0.3
5
RTN
–60
0.3
Source current
IdVdT, IILIM
Storage temperature
(1)
62
–(60–VIN)
IFLT, IdVdT, ISHDN
Transient junction
temperature
MAX
–60
IN, IN–OUT (10 ms transient), TA = 25 ℃
Sink current
Operating junction
temperature
MIN
UNIT
V
10
mA
–40
150
°C
–65
T(TSD)
°C
–65
150
°C
Internally limited
TJ
Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1)
±1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
IN
Input voltage
4.5
60
V
OUT, FLT
Input voltage
0
60
V
UVLO, OVP,
dVdT, ILIM
Input voltage
0
4
V
SHDN
Input voltage
0
6
V
ILIM
Resistance
7.5
267
kΩ
IN, OUT
dVdT
Tj
0.1
External capacitance
µF
6.8
Operating junction temperature
–40
nF
25
125
°C
7.4 Thermal Information
TPS2662
THERMAL METRIC
(1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
44.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.5
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Thermal Information (continued)
TPS2662
THERMAL METRIC (1)
DRC (VSON)
UNIT
10 PINS
RθJB
Junction-to-board thermal resistance
20.7
°C/W
ΨJT
Junction-to-top characterization parameter
0.5
°C/W
ΨJB
Junction-to-board characterization parameter
20.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
°C/W
7.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(IN)
Operating input voltage
V(PORR)
Internal POR threshold, rising
V(PORHys)
Internal POR hysteresis
IQ(ON)
IQ(OFF)
I(VINR)
V(OVC)
Supply current
4.5
3.54
60
3.73
4.2
110
Enabled: V(SHDN) = 2 V
343
V(SHDN) = 0 V
Reverse Input supply current
V(IN) = – 24 V, V(OUT) = 0 V
Over voltage clamp
V(IN) > 40 V, ILOAD = 10 mA,TPS26622,
TPS26623 Only
V
V
mV
482
µA
11.5
25
µA
50
130
µA
36
37.5
40
V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(UVLOR)
UVLO threshold voltage, rising
1.18
1.2
1.23
V
V(UVLOF)
UVLO threshold, Falling
1.09
1.1
1.135
V
I(UVLO)
UVLO Input Leakage Current
0 V ≤ V(UVLO) ≤ 3.5 V
0
100
nA
I(UVLO)
UVLO Input Leakage Current
V(UVLO) = 5 V
18.8
38
µA
V
–100
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR)
Overvoltage threshold voltage, rising
1.18
1.2
1.23
V(OVPF)
Overvoltage threshold, falling
1.09
1.12
1.135
V
I(OVP)
OVP Input Leakage Current
0 V ≤ V(OVP) ≤ 5 V
–100
0
100
nA
OVPMAX
Maximum external OVP setting
TPS26620, TPS26621, TPS26624 and
TPS26625 only
57
V
3.1
V
LOW IQ SHUTDOWN (SHDN) INPUT
V(SHDN)
Output voltage
V(SHUTF)
SHDN Threshold Voltage for Low
IQ Shutdown, Falling
V(SHUTR)
SHDN Threshold, rising
I(SHDN)
Input current
I(SHDN) = 0.1 µA
2.39
2.781
0.9
V
1.8
V
V(SHDN) = 0.4 V
–10
–2.4
µA
dVdT Charging Current
V(dVdT) = 0V
1.68
1.98
2.33
µA
R(dVdT)
dVdT Discharging Resistance
V(SHDN) = 0 V, with I(dVdT) = 10mA
sinking
13.1
22
Ω
V(dVdTmax)
dVdT Max Capacitor Voltage
4
4.34
4.75
V
GAIN(dVdT)
dVdT to OUT Gain
23.9
24.6
25.2
V/V
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
V(OUT) /V(dVdT)
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM bias voltage
1
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
V
7
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
I(OL)
Overload Current Limit
MIN
TYP
MAX
R(ILIM) = 267 kΩ, V(IN) – V(OUT) = 1 V
TEST CONDITIONS
0.02
0.025
0.032
R(ILIM) = 44.2 kΩ, V(IN) – V(OUT) = 1 V
0.145
0.152
0.159
R(ILIM) = 26.7 kΩ, V(IN) – V(OUT) = 1 V
0.237
0.25
0.257
R(ILIM) = 13.3 kΩ, V(IN) – V(OUT) = 1 V
0.47
0.5
0.52
R(ILIM) = 8.25 kΩ, V(IN) – V(OUT) = 1 V
0.757
0.8
0.827
0.83
0.88
0.91
8
15.5
27
mA
31
39.3
51
mA
R(ILIM) = 7.5 kΩ, V(IN) – V(OUT)= 1 V
I(OL_R-OPEN)
R(ILIM)= OPEN, Open Resistor Current
Limit (single point failure test: UL60950)
I(OL_R-SHORT)
R(ILIM)= SHORT, Shorted Resistor
Current Limit (single point failure test:
UL60950)
I(SCL)
Short-Circuit Current Limit
I(FASTRIP)
Fast-Trip Comparator Threshold
R(ILIM) = 7.5 kΩ, V(IN) – V(OUT)= 24 V
UNIT
A
0.885
A
1.6
A
PASS FET OUTPUT (OUT)
0.025 A ≤ I(OUT) ≤ 0.8 A, TJ = 25°C,
R(ILIM) = 7.5 kΩ
435
478
521
626
685
478
800
V(IN) = 57 V, V(SHDN)= 0 V, V(OUT) = 0 V,
Sourcing
4.38
12
V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24 V,
Sinking
7.27
102
0.025 A ≤ I(OUT) ≤ 0.8A, TJ = 85°C,
R(ILIM) = 7.5 kΩ
RON
0.025 A ≤ I(OUT) ≤ 0.8A, –40ºC ≤ TJ
≤125°C, R(ILIM) = 7.5 kΩ
OUT Leakage Current in Off State
Ilkg(OUT)
250
µA
V(IN) = – 57V, V(SHDN)= 0V, V(OUT) = 0V,
Sinking
OUT leakage current under output
reverse polarity condition
mΩ
168
V(IN) = 24 V, V(OUT) = – 24 V, V(SHDN) = 2
V, TP26624, TPS26625 Only
450
V(REVTH)
V(IN) – V(OUT) threshold for reverse
protection comparator, falling
–71
–54
–40
mV
V(FWDTH)
V(IN) – V(OUT) threshold for reverse
protection comparator, rising
1.4
15
30
mV
45
82.3
145
Ω
–100
0
100
nA
FAULT FLAG (FLT): ACTIVE LOW
R(FLT)
FLT Pull-Down Resistance
V(OVP) = 2 V, I(FLT) = 5mA sinking
I(FLT)
FLT Input Leakage Current
0 V ≤ V(FLT) ≤ 57 V
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD Threshold, rising
T(TSDhyst)
TSD Hysteresis
Thermal Fault (Latch or Auto-Retry)
155
°C
10
°C
TPS26620, TPS26622, TPS26624
Latch
TPS26621, TPS26623, TPS26625
Auto–re
try
7.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
IN and UVLO INPUT
8
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Timing Requirements (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 267 kΩ, FLT = OPEN, C(OUT) = 1 µF, C(dVdT) = OPEN. (All
voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
UVLO ↑ (100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dVdT) = Open
UVLO_tON(dly)
UVLO Turnon Delay
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100
mV, C(dVdT) > 4.7 nF, [C(dVdT) in nF]
NOM
MAX
UNIT
51
µs
51 +
27.4 x
C(dVdT)
µs
UVLO_tREC
UVLO Recovery time
TPS26620, TPS26622 and TPS26624 Only
512
ms
UVLO_toff(dly)
UVLO Turnoff delay
UVLO↓ (100 mV below V(UVLOF)) to FLT↓
6.14
µs
SHUTDOWN CONTROL INPUT (SHDN)
SHDN↑ to V(OUT) = 100 mV, C(dVdT) = Open
tSD(dly)
SHUTDOWN exit delay
SHDN↑ to V(OUT) = 100 mV, C(dVdT) > 4.7 nF,
[C(dVdT) in nF]
SHUTDOWN entry delay
SHDN↓ (below SHUTF) to FLT↓
156
µs
156 +
27.4 x
C(dVdT)
µs
6.83
µs
77
µs
4.84
µs
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP Exit delay
OVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV,
TPS26620/21/24/25 Only
OVP Disable delay
OVP↑ (20mV above V(OVPR)) to FLT↓ ,
TPS26620/21/24/25 Only
tOVP(dly)
CURRENT LIMIT
tCL(dly)
tFASTTRIP(dly)
Maximum duration in current limit I(ILIM) < I(OUT) < I(FASTRIP), V(IN) – V(OUT) < 2.6 V
Fast-Trip Comparator Delay
512
ms
I(OUT) > I(FASTRIP), V(IN) – V(OUT) = 2 V
1.5
µs
I(OUT) > I(FASTRIP), 4.5 V < V(IN) ≤ 6 V, V(IN) –
V(OUT) ≥ 2.6 V
1.4
µs
I(OUT) > I(FASTRIP), 6 V < V(IN) ≤ 57 V, V(IN) – V(OUT) ≥
2.6 V
220
ns
(V(IN) – V(OUT)) ↓ (10 mV overdrive below V(REVTH))
to internal FET turn OFF
15
REVERSE PROTECTION COMPARATOR
tREV(dly)
Reverse Protection Comparator
Delay
tFWD(dly)
(V(IN) – V(OUT)) ↓ (1 V overdrive below V(REVTH)) to
internal FET turn OFF
3.71
(V(IN) – V(OUT)) ≤ – 2.6 V to internal FET turn OFF
0.31
(V(IN) – V(OUT)) ↓ (150 mV overdrive below V(REVTH))
to FLT↓
45
(V(IN) – V(OUT)) ↑ (100 mV overdrive above
V(FWDTH)) to FLT↑
63
µs
THERMAL SHUTDOWN
Retry Delay in
TSD
512
ms
OUTPUT RAMP CONTROL (dVdT)
tdVdT
Output Ramp Time
SHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = 22 nF
SHDN ↑ to V(OUT) = 23.9 V, with C(dVdT) = open
11
0.664
ms
FAULT FLAG (FLT)
tPGOODF
Falling edge
Rising edge, C(dVdT) = Open
tPGOODR
PGOOD Delay
Rising edge, C(dVdT) > 4.7 nF, [C(dVdT) in nF]
875
µs
1.4
ms
750 +
573 x
C(dVdT)
µs
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
9
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
7.7 Typical Characteristics
1.22
700
1.2
UVLO Threshold Voltage (V)
800
RON (m:)
600
500
400
300
200
0.8 A
0.4 A
0.025 A
100
0
-50
0
50
Temperature (qC)
100
1.18
1.16
1.14
V(UVLOR)
V(UVLOF)
1.12
1.1
1.08
-50
150
-30
-10
10
D001
Figure 1. On-Resistance vs Temperature Across Load
Current
30
50
70
Temperature (qC)
90
110
130
150
D002
Figure 2. UVLO Threshold Voltage vs Temperature
1.22
-50
-52
-53
1.18
V(REVTH) (mV)
OVP Threshold Voltage (V)
-51
1.2
1.16
V(OVPR)
V(OVPF)
1.14
-54
-55
-56
-57
-58
1.12
-59
1.1
-50
0
50
Temperature (qC)
100
-60
-50
150
Figure 3. OVP Threshold Voltage vs Temperature
39.5
Over Voltage Clamp Threshold (V)
40
23
21
V(FWDTH) (mV)
19
17
15
13
11
9
7
0
50
Temperature (Cq)
100
150
10
100
150
D005
39
38.5
38
37.5
37
36.5
36
35.5
35
-50
D006
Figure 5. V(FWDTH) vs Temperature
50
Temperature (qC)
Figure 4. Reverse Voltage Threshold vs Temperature
25
5
-50
0
D003
0
50
Temperature (qC)
100
150
D023
Figure 6. Overvoltage Clamp Threshold vs Temperature
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Typical Characteristics (continued)
20
V(PORR)
V(PORF)
Supply Current, IQ(OFF) (PA)
Internal POR Threshold Voltage (V)
4
3.95
3.9
3.85
3.8
3.75
3.7
3.65
3.6
15
10
5
125
85
25
40
3.55
0
3.5
-50
0
50
Temperature (qC)
100
0
150
Figure 7. Internal POR Threshold Voltage vs Temperature
20
30
40
Input Voltage (V)
50
60
70
D021
Figure 8. Input Supply Current vs Supply Voltage in
Shutdown
5
500
450
-5
400
-15
350
300
I(VINR)
Supply Current, IQ(ON) (PA)
10
D008
250
200
150
-25
-35
-45
125
85
25
40
100
50
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Input Voltage (V)
D020
125
85
25
-40
-55
-65
-70
-60
-50
-40
-30
-20
Input Voltage (V)
-10
0
10
D027
V(OUT) = 0 V
Figure 10. Input Supply Current vs Reverse Supply Voltage,
–V(IN)
7
9
6
8
SHUTDOWN Entry Delay.
SHDN_toff(dly)
OVP Disable Delay, tOVP(dly) (Ps)
Figure 9. Input Supply Current vs Supply Voltage During
Normal Operation
5
4
3
2
1
7
6
5
4
3
2
1
0
-50
0
50
Temperature (qC)
100
150
0
-50
D022
Figure 11. OVP Disable Delay vs Temperature
0
50
Temperature (qC)
100
150
D012
Figure 12. Shutdown Entry Delay vs Temperature
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
11
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Typical Characteristics (continued)
1.19
540
1.185
538
1.18
T(CL) (ms)
V(SHUTF) (V)
1.175
1.17
1.165
536
534
1.16
532
1.155
1.15
-50
0
50
Temperature (qC)
100
530
-50
150
44.2 k
26.7 k
13.3 k
8.25 k
7.5 k
150
D019
15%
10%
5%
0
-5%
267 k
0
50
Temperature (qC)
100
-10%
-50
150
0
D014
50
Temperature (qC)
100
150
D015
Figure 16. Current Limit (% Normalized) vs Temperature
0.05
1.2
267 k:
44.2 k:
1.1
1
26.7 k:
13.3 k:
8.25 k:
7.5 k:
0.045
0.04
0.9
Current Limit, I (LIM) (A)
Current Limit, I(ILIM) (A)
100
20%
2%
1.75%
1.5%
1.25%
1%
0.75%
0.5%
0.25%
0
-0.25%
-0.5%
-0.75%
-1%
-1.25%
-1.5%
-50
Figure 15. Current Limit (% Normalized) vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.035
0.03
0.025
0.02
0.015
0.01
0.2
R(ILIM) = Open
R(ILIM) = Short
0.005
0.1
-30
-10
10
30
50
70
90
Temperature (qC)
110
130
150
0
-50
D009
Figure 17. Over Load Current Limit vs Temperature
12
50
Temperature (qC)
Figure 14. Max Duration in Current Limiting t(CL) vs
Temperature
I(LIM) (% Normalized)
I(LIM) (% Normalized)
Figure 13. Shutdown Threshold Voltage Shutdown vs
Temperature
0
-50
0
D013
0
50
Temperature (qC)
100
150
D004
Figure 18. Current Limit for R(ILIM) = Open and Short vs
Temperature
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Typical Characteristics (continued)
30
Accuracy ( ) (Voltage, Temperature)
1.8
1.7
I(FASTRIP) (A)
1.6
1.5
1.4
1.3
1.2
1.1
1
-50
50
Temperature (qC)
100
150
15
10
5
0
0.1
0.2
0.3
D017
Reverse Current Blocking Response (Ps)
6.8
6.6
6.4
6.2
0.4 0.5 0.6
Current Limit (A)
0.7
0.8
0.9
1
D024
Figure 20. Current Limit Accuracy vs Current Limit, I(OL)
7
UVLO_toff(dly) (Ps)
20
0
0
Figure 19. Fast-trip Comparator Threshold I(FASTTRIP) vs
Temperature Threshold
6
-50
25
100
10
1
0.1
0
50
Temperature (qC)
100
150
1
10
D016
Figure 21. UVLO Turnoff Delay vs Temperature
100
Vrev_overdrive (mV)
1000
10000
D026
Figure 22. Reverse Current Blocking Response Time vs
Reverse Comparator Overdrive Voltage
Thermal Shutdown Time (ms)
100000
Temp = 40qC
Temp = 25qC
Temp = 85qC
Temp = 105qC
Temp = 125qC
10000
VIN
VOUT
1000
FLTb
100
10
IIN
1
0.2
1
10
Power Dissipation (W)
50
D025
Taken on 2-Layer board, 2 oz.(0.08-mm thick) with RTN plane
area: 0.8 cm2 (Top) and 4.5 cm2 (Bottom)
Figure 23. Thermal Shutdown Time vs Power Dissipation
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
OVP setting at 33 V
RLOAD = 80 Ω
Figure 24. OVP Overvoltage Cut-Off Response
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
13
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Typical Characteristics (continued)
VIN
VOUT
FLTb
IIN
RILIM = 7.5 kΩ
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
RLOAD = 80 Ω
Figure 25. OV Clamp Response (TPS26602 Only)
RFLTb = 100 kΩ
Figure 26. Hot-Short: Fast Trip Response and Current
Regulation
VIN
SHDNb
VOUT
VOUT
FLTb
IIN
IIN
RILIM = 7.5 kΩ
RILIM = 7.5 kΩ
Figure 27. Hot-Short: Fast Trip Response (Zoomed)
RFLTb = 100 kΩ
RLOAD = 80 Ω
Figure 28. Turnon Control With SHDN
SHDNb
VOUT
FLTb
IIN
RILIM = 7.5 kΩ
RFLTb = 100 kΩ
RLOAD = 80 Ω
Figure 29. Turnoff Control With SHDN
14
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
8 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
0
10%
time
0
time
UVLO_tON(dly)
UVLO_toff(dly)
-54 mV
V(IN) -V(OUT)
15 mV
V(IN) -V(OUT)
90%
FLT
FLT
10%
0
time
tREV(dly)
I(FASTRIP)
0
time
tFWD(dly)
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
0
tFASTRIP(dly)
time
tOVP(dly)
UVLO_tREC
UVLO_tREC
V(IN)
V(IN)
V(PORR)
V(PORR)
VUVLO
V(UVLOF)
V(UVLOR)
VUVLO
V(OUT)
V(UVLOR)
V(UVLOF)
V(OUT)
0
tdVdT
time
tOFF
0
tOFF
time
tOFF + tdVdT > UVLO_tREC
tOFF + tdVdT < UVLO_tREC
TPS26620, TPS26622, TPS26624 only
Figure 30. Timing Waveforms
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
15
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
9 Detailed Description
9.1 Overview
The TPS2662x is a family of high voltage industrial eFuses with integrated back-to-back MOSFETs and
enhanced built-in protection circuitry. It provides robust protection for all systems and applications powered from
4.5 V to 60 V. The device can withstand ±60 V positive and negative supply voltages without damage. The
device feature fully integrated reverse polarity protection and require zero additional power components. For hotpluggable boards, the device provides hot-swap power management with in-rush current control. Load, source
and device protections are provided with many programmable features including overcurrent, overvoltage,
undervoltage. The precision overcurrent limit (±5% at 880 mA) helps to minimize over design of the input power
supply, while the fast response short circuit protection 220 ns (typical) immediately isolates the faulty load from
the input supply when a short circuit is detected.
The internal robust protection control blocks of the TPS2662x along with its ±60 V rating helps to simplify the
system designs for the surge compliance ensuring complete protection of the load and the device. TPS2662x
devices are immune to noise tests like Electrical Fast Transients that are common in industrial applications and
simplifies the system design that require criterion-A performance during this test.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The TPS2662x monitor functions threshold accuracy of ±3% ensures tight
supervision of the supply bus, eliminating the need for a separate supply voltage supervisor chip.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected.
16
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
9.2 Functional Block Diagram
OUT
IN
478PŸ
+
-54mV
PORb
Charge
Pump
15mV
3.8V
3.7V
CP
+
+
UVLO
UVLOb
1.2V
REVERSE
4.4V
1.1V
SWEN
Gate Control Logic
Thermal
Shutdown
* TPS26620/1/4/5 Only
+
OVP
Current Limit Amp
TSD
Fast-Trip Comp
(I(FASTTRIP), VIN, VOUT)
OVP
1.2V
1.1V
* TPS26622/3 Only
1V
Over Voltage
Clamp detect
(38V)
SHDNb
ILIM
Short detect
Ramp Control
24.6x
SWEN
Avdd
I(LOAD) • ,(OL)
1.98µA
FLT
* TPS26620/2/4 Only
512msec
timer
Timeout
SET
S
82Ÿ
Q
dVdT
UVLOb
13Ÿ
R
PORb
TSD
RTN
PORb
SHDNb
CLR
Q
1.4 msec
Fault Latch
875 µs
Gate Enhanced (tPGOOD)
Avdd
Reverse Polarity Protection
circuit
0.9V
SHDNb
+
GND
RTN
TPS2662x
SHDN
9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
When the voltage at UVLO pin falls below V(UVLOF) during input power fail or input undervoltage fault, the internal
FET quickly turns off and FLT is asserted. The UVLO comparator has a hysteresis of 100 mV. To set the input
UVLO threshold, connect a resistor divider network from IN supply to UVLO terminal to RTN as shown in
Figure 31.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
17
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Feature Description (continued)
V(IN)
IN
TPS26620/1/4/5
R1
UVLO
+
UVLOb
1.2 V
R2
1.1 V
OVP
+
OVP
1.2 V
R3
RTN
1.1 V
GND
Figure 31. UVLO and OVP Thresholds Set by R1, R2 and R3
If the Undervoltage Lockout function is not needed, the UVLO terminal must be connected to the IN terminal with
a 1 MΩ resistor. UVLO pin is 5 V rated and this resistor limits the UVLO pin current to < 60 µA. The UVLO
terminal must not be left floating.
The TPS26620, TPS26622 and TPS26624 variants feature a UVLO_tREC timer. If the tOFF time + tdVdT time
exceed UVLO_tREC time, the device latches off. tOFF time is the time when VUVLO falls below V(UVLOF) and not
rises above V(UVLOR) and VIN is above V(PORR). tdVdT is the output ramp time as defined in Equation 2 The latch off
can be reset by cycling SHDN or VIN. More details of this feature are shown in Figure 30.
9.3.2 Overvoltage Protection (OVP)
The TPS2662x family incorporate circuitry to protect the system during overvoltage conditions. The TPS26620,
TPS26621, TPS26624 and TPS26625 feature overvoltage cut off functionality. A voltage more than V(OVPR) on
OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally,
connect a resistor divider from IN supply to OVP terminal to RTN as shown in Figure 31. If the over voltage
feature is not to be used then connect OVP terminal to RTN directly and ensure VIN is not exceeded beyond
OVPMAX.
The TPS26622 and TPS26623 features an internally fixed 38 V overvoltage clamp (VOVC) functionality. The OVP
terminal of these devices must be connected to the RTN terminal directly. These devices clamp the output
voltage to VOVC, when the input voltage exceeds 38 V. During the output voltage clamp operation, the power
dissipation in the internal MOSFET is PD = (VIN – VOVC) × IOUT. Excess power dissipation for prolonged period
can make the device to enter into thermal shutdown. Figure 25 illustrates the overvoltage clamp functionality.
9.3.3 Hot Plug-In and In-Rush Current Control
The devices are designed to control the inrush current upon insertion of a card into a live backplane or other
"hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets
of the system power. The controlled start-up also helps to eliminate conductive and radiative interferences. An
external capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on
as shown in Figure 32 and Figure 33.
18
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Feature Description (continued)
TPS2662x
4.34 V
1.98µA
dVdT
13 Ÿ
C(dVdT)
SWENb
RTN
GND
Figure 32. Output Ramp Up Time tdVdT is Set by C(dVdT)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 24V/660 µs. A capacitor can be connected
from dVdT pin to RTN to program the output voltage slew rate slower than 24V/660 µs. Use Equation 1 and
Equation 2 to calculate the external C(dVdT) capacitance.
Equation 1 governs slew rate at start-up.
æ C(dVdT ) ö æ dV(OUT ) ö
÷´ç
I(dVdT) = ç
÷
ç Gain(dVdT ) ÷ ç dt ÷
ø
è
ø è
where
•
I(dVdT) = 1.98 µA (typical)
dV
•
•
OUT
dt
= Desired output slew rate
Gain(dVdT) = dVdT to VOUT gain = 24.6
(1)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 20.5 × 103 × V(IN) × C(dVdT)
(2)
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
19
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Feature Description (continued)
VIN
VOUT
FLTb
IIN
CdVdT = 22 nF
COUT = 22 µF
RILIM = 7.5 kΩ
Figure 33. Hot Plug In and Inrush Current Control at 24-V Input
9.3.4 Reverse Polarity Protection
9.3.4.1 Input Side Reverse Polarity Protection
The TPS26620, TPS26621, TPS26622 and TPS26623 eFuses feature fully integrated input side reverse polarity
protection. The internal FETs of the eFuse turn OFF during the input reverse polarity event and protect the
downstream loads from negative supply voltages that can appear due to field mis-wiring on the input power
terminals. Figure 34 illustrates the reverse input polarity protection functionality.
VIN
VOUT
IIN
Figure 34. Reverse Input Supply Protection at –60 V
20
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Feature Description (continued)
9.3.4.2 Output Side Reverse Polarity Protection
TheTPS26624 and TPS26625 eFuses feature fully integrated input as well as output reverse polarity protection.
The internal FETs of the eFuse turn OFF during the output reverse polarity event and protects the upstream
circuits from negative voltage that can appear at the output of the eFuse due to field miswiring at the output side
with an external isolated power supplies. Figure 35 illustrates the performance during output side reverse polarity
event with V(IN) un-powered and Figure 36 illustrates the performance with V(IN) powered. Figure 37 illustrates the
output recovery performance after the reverse polarity is removed.
VIN
VOUT
IOUT
Figure 35. Reverse Output Polarity Protection with –60 V at OUT and VIN = 0 V
VIN
VIN
VOUT
VOUT
IIN
IIN
Figure 36. Reverse Output Polarity Protection with –24 V
at OUT and 24 V at IN
Figure 37. Response During Coming Out of Output
Reverse Polarity Fault Condition
9.3.5 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
21
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Feature Description (continued)
9.3.5.1 Overload Protection
Connect a resistor across ILIM to RTN to program the over load current limit I(OL). During over load conditions the
device regulates the current through it at I(OL) programmed by the R(ILIM) resistor as shown in Equation 3 for a
maximum duration of tCL(dly).
6.636
IOL =
RILIM
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(3)
During the current limit operation the output voltage droops and this may cause the device to hit the thermal
shutdown threshold T(TSD) before tCL(dly) time. Once the thermal shutdown threshold is hit or tCL(dly) is elapsed, the
internal FETs of TPS2662x will turn OFF. FETs in TPS26620, TPS26622 and TPS26624 remain OFF and
latched. To reset the latch, cycle the SHDN, or recycle the VIN. TPS26621, TPS26623 and TPS26625
commences an auto-retry cycle after a retry time of 512 msec. The internal FETs turn back on in dVdT mode
after this retry time. If the overload still exists then the device regulates the current at programmed current limit
I(OL).
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
Load transition
from 120 Ω to 20 Ω
VIN = 24 V, RILIM =
7.5 kΩ
Figure 38. Auto-Retry Fault Behavior
Load transition
from 20 Ω to 120 Ω
VIN = 24 V, RILIM =
7.5 kΩ
Figure 39. Response During Coming Out of Overload Fault
9.3.5.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator. The fast-trip comparator architecture is designed for fast turn OFF (tFASTTRIP(dly) = 220 ns (typical)) of
the internal FET during an output short circuit event. The fast-trip threshold is internally set to I(FASTRIP). The fasttrip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly,
allowing the current-limit loop to regulate the output current to I(OL). Then the device functions similar to the
overload condition. Figure 40 and Figure 41 illustrates the behavior of the system during output short circuit
condition.
22
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Feature Description (continued)
VIN
VOUT
IIN
VIN = 24 V, RILIM = 7.5 kΩ
Figure 40. Output Hot Short Functionality at 24-V
Input
Figure 41. Hot-Short: Fast Trip Response (Zoomed)
The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This is achieved by controlling the turn OFF time of the internal FET based on the differential
voltage across V(IN) and V(OUT) once the current through the device exceeds I(FASTTRIP). Higher the voltage
difference V(IN) – V(OUT), faster the turn OFF time, tFASTTRIP(dly).
9.3.5.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, it limits the load current to the current limit I(OL) and
functions similar to the overload condition. Figure 42 illustrates the function of the device in this condition. This
feature helps in quick isolation of the fault and ensures stability of the DC bus.
VIN
VOUT
FLTb
IIN
VIN = 24 V RILIM = 7.5 kΩ
Figure 42. Start-Up With Short on Output
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
23
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
Feature Description (continued)
9.3.6 Reverse Current Protection
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected. The reverse comparator turns OFF the internal FET within 310 ns (typical) as
soon as V(IN) – V(OUT) falls below –2.6 V. It turns on within 63 µs (typical) once the differential forward voltage
V(IN)– V(OUT) exceeds 115 mV. Figure 43 and Figure 44 illustrates the behavior of the system during input hot
short circuit condition.
Figure 43. Input Hot Short Functionality at 24-V Supply
Figure 44. Hot-Short: Fast Trip Response (Zoomed)
The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive
differential voltage V(IN) – V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tREV(dly). Figure 22
shows the reverse current blocking response time versus over-drive voltage.
9.3.7 FAULT Response
The FLT open-drain output asserts (active low) under the following conditions:
• Fault events such as undervoltage, overvoltage, over load, reverse current and thermal shutdown conditions
• The device enters low current shutdown mode when SHDN is pulled low
• During start-up when the internal FET GATE is not fully enhanced
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An
internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in
dVdT mode, PGOOD and FLT it remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced. The PGOOD signal has deglitch time incorporated to ensure that internal FET is
fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined
by tPGOOD(degl) = Maximum {(750 + 573× C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT can
be left open or connected to RTN when not used. V(IN) falling below V(PORF) = 3.6 V resets FLT.
9.3.8 IN, OUT, RTN, and GND Pins
A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The
recommended input operating voltage range is 4.5 to 60 V. V(OUT), in the ON condition, is calculated using
Equation 4.
V
24
OUT
V
IN
RON u I
OUT
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Feature Description (continued)
Where,
•
RON is the total ON resistance of the internal FETs.
(4)
GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control
blocks. Connect the TPS2662x family support components: R(ILIM), C(dVdT) and resistors for UVLO and OVP with
respect to the RTN pin. Internally, the device has reverse input polarity protection block between RTN and the
GND terminal. Connecting RTN pin to GND pin disables the reverse polarity protection feature and the
TPS2662x gets permanently damaged when operated under this fault event.
9.3.9 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 512 ms after TJ < [T(TSD) – 13.5°C]. During the
thermal shutdown, the fault pin FLT pulls low to indicate a fault condition.
9.4 Device Functional Modes
9.4.1 Low Current Shutdown Control (SHDN)
The internal FETs and the load current can be switched off by pulling the SHDN pin below 0.9 V threshold with a
micro-controller GPIO pin or can be controlled remotely with an opto-isolator device as shown in Figure 45 and
Figure 46. The device quiescent current reduces to 10 μA (typical) in shutdown state. To assert SHDN low, the
pull down must sink at least 10 µA at 400 mV. To enable the device, SHDN must be pulled up to at least 1.8 V.
Once the device is enabled, the internal FETs turnon with dVdT mode.
TPS2662x
AVdd
ON OFF
AVdd
TPS2662x
Rpu
Rpu
SHDN
SHDN
from µC GPIO
+
0.9 V
a
C
k
E
Opto Isolator
SHDNb
0.9V
±
GND
+
SHDNb
GND
OFF ON
Figure 45. Shutdown Control
Figure 46. Opto-Isolator Shutdown Control
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
25
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS2662x family is an industrial eFuse, typically used for Hot-Swap and power rail protection applications. It
operates from 4.5 V to 60 V with programmable current limit, overvoltage, undervoltage and reverse polarity
protections. The device aids in controlling in-rush current and provides robust protection against reverse current
and field miss-wiring conditions for systems such as PLC I/O modules and Sensor power supplies. The device
also provides robust protection for multiple faults on the system rail.
The Detailed Design Procedure section can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS2662 Design Calculator is available in the web product folder.
10.2 Typical Application
IN: 18 V-30 V
IN
CIN
1 µF
R1
715 k
OUT
OUT
COUT
RFLTb 22 µF
100 k
478 m
UVLO
R2
20 k
OVP
TPS2662x
dVdT
R3
30.1 k
CdVdT
RTN
Health Monitor
ON/OFF Control
FLT
SHDN
ILIM
GND
10 nF
RILIM
13.3 k
Figure 47. 24-V, 500 mA eFuse Input Protection Circuit for PLC I/O Module
10.2.1 Design Requirements
Table 1 shows the Design Requirements for TPS2662x.
Table 1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
V(IN)
Typical input voltage
24 V
V(UV)
Undervoltage lockout set point
18 V
V(OV)
Overvoltage cutoff set point
30 V
T(SU)
Load during start-up
96 Ω
I(LIM)
Current limit
C(OUT)
Load capacitance
22 µF
TA
Maximum ambient temperature
125ºC
26
500 mA
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
10.2.2 Detailed Design Procedure
10.2.2.1 Step by Step Design Procedure
To
•
•
•
•
•
begin the design process, the designer must know the following parameters:
Input operating voltage range
Maximum output capacitance
Maximum current limit
Load during start-up
Maximum ambient temperature
This design procedure below seeks to control junction temperature of the device in both steady state and
start-up conditions by proper selection of the output ramp-up time and associated support components. The
designer can adjust this procedure to fit the application and design criteria.
10.2.2.2 Programming the Current-Limit Threshold R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 5.
6.636
RILIM =
= 13.27 kW
ILIM
where
•
ILIM = 500 mA
(5)
Choose the closest standard 1% resistor value : R(ILIM) = 13.3 kΩ
10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between IN, UVLO, OVP and RTN pins of the device. The values required
for setting the undervoltage and overvoltage are calculated by solving Equation 6 and Equation 7.
V(OVPR)
V (UVLOR)
R3
u V(OV)
R 2 R3
(6)
R 2 R3
u V (UV)
R1 R 2 R3
(7)
R1
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1+R2+R3)}, it is recommended to
use higher value resistance for R1, R2 and R3.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20 times greater than the leakage
current of UVLO and OVP pins.
From the device electrical specifications, V(OVPR) = 1.19 V and V(UVLOR) = 1.19 V. From the design requirements,
V(OV) is 30 V and V(UV) is 18 V. To solve the equation, first choose the value of R3 = 30.1 kΩ and use Equation 6
to solve for (R1 + R2) = 728.7 kΩ. Use Equation 7 and value of (R1 + R2) to solve for R2 = 20.05 kΩ and finally
R1= 708.6 kΩ.
Choose the closest standard 1% resistor values: R1 = 715 kΩ, R2 = 20 kΩ, and R3 = 30.1 kΩ.
10.2.2.4 Setting Output Voltage Ramp Time—(tdVdT)
For a successful design, the junction temperature of the device must be kept below the absolute-maximum rating
during dynamic (start-up) and steady state conditions. The dynamic power dissipation is often an order
magnitude greater than the steady state power dissipation. It is important to determine the right start-up time and
the in-rush current limit for the system to avoid thermal shutdown during start-up with and without load. The
ramp-up capacitor C(dVdT) is calculated considering the two possible cases:
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
27
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
10.2.2.4.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipation decreases. Typical ramp-up of the output voltage, inrush current and instantaneous power
dissipated in the device during start-up are shown in Figure 48. The average power dissipated in the device
during start-up is equal to the area of triangular plot (red curve in Figure 49) averaged over tdVdT.
Input Current (A), Power Dissipation (W)
2
24
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
1.5
18
1
12
0.5
6
0
0
VIN = 24 V
CdVdT = 10 nF
COUT = 22 µF
20
VIN = 24 V
Figure 48. Start-Up Without Load
40
60
Start-up Time, tdVdT (%)
CdVdT = 10 nF
80
0
100
D029
COUT = 22 µF
Figure 49. PD(INRUSH) Due to Inrush Current
The inrush current is determined as shown in Equation 8.
I
Cu
dV
t I(INRUSH)
dT
C(OUT) u
V (IN)
tdVdT
(8)
Average power dissipated during start-up is given by Equation 9.
PD(INRUSH)
0.5 u V(IN) u I(INRUSH)
(9)
Equation 9 assumes that the load does not draw any current until the output voltage reaches its final value.
10.2.2.4.2 Case 2: Start-Up With Load —Output Capacitance C(OUT) and Load Draws Current During Start-Up
When the load draws current during the turnon sequence, additional power is dissipated in the device.
Considering a resistive load RL(SU) during start-up, typical ramp-up of output voltage, load current and the
instantaneous power dissipation in the device are shown in Figure 50. Instantaneous power dissipation with
respect to time is plotted in Figure 51.
28
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Input Current (A), Power Dissipation (W)
5
30
Input Current (A)
Power Dissipation (W)
Output Voltage (V)
4.5
4
24
3.5
21
3
18
2.5
15
2
12
1.5
9
1
6
0.5
3
0
0
100
0
VIN = 24 V
CdVdT = 10 nF
RL(SU) = 96 Ω
COUT = 22 µF
27
20
VIN = 24 V
CdVdT = 10 nF
40
60
Start-up Time, tdVdT (%)
80
D030
RL(SU) = 96 Ω
COUT = 22 µF
Figure 51. PD(INRUSH) Due to Inrush and Load Current
Figure 50. Start-Up With Load
The additional power dissipation during start-up is calculated using
PD(LOAD)
1 V (IN)2
u
6 RL(SU)
(10)
Total power dissipated in the device during start-up is given by
PD(STARTUP)
PD(INRUSH) PD(LOAD)
(11)
Total current during start-up is given by .
I(STARTUP)
I(INRUSH) IL(t)
(12)
For the design example under discussion,
Select the inrush current I(INRUSH) = 0.1 A and tdVdT calculated using Equation 8 is 5.28 ms.
For a given start-up time, CdVdT capacitance value calculated using Equation 2 is 10.7 nF for tdVdT = 5.28 ms and
VIN = 24 V.
Choose the closest standard value: 10.0 nF and 16-V capacitor.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
29
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
The inrush power dissipation due to output capacitor alone is calculated using Equation 9 and it is 1.2 W.
Considering the start-up with 96-Ω load, the additional power dissipation calculated using Equation 10 is 1 W.
The total device power dissipation during start-up is 2.2 W
The power dissipation with or without load, for a selected start-up time must not exceed the thermal shutdown
limits as shown in Figure 52.
From the thermal shutdown limit graph, at TA = 125°C, thermal shutdown time for 2.2 W is close to 580 ms. It is
safe to have a minimum 30% margin to allow for variation of the system parameters such as load, component
tolerance, input voltage and layout. Selected 10-nF CdVdT capacitor and 5.28-ms start-up time (tdVdT) are well
within the limit for successful start-up with 96 Ω load.
Higher value C(dVdT) capacitor can be selected to further reduce the power dissipation during start-up.
Thermal Shutdown Time (ms)
100000
Temp = 40qC
Temp = 25qC
Temp = 85qC
Temp = 105qC
Temp = 125qC
10000
1000
100
10
1
0.2
1
10
Power Dissipation (W)
50
D025
Figure 52. Thermal Shutdown Time vs Power Dissipation
10.2.2.4.3 Support Component Selections - RFLT and C(IN)
The RFLT Absolute Maximum Ratings serves as pull-up for the open-drain fault output. The current sink by this
pin must not exceed 10 mA (see the Absolute Maximum Ratings table). Typical resistance value in the range of
10 kΩ to 100 kΩ is recommended for RFLT. The CIN is a local bypass capacitor to suppress noise at the input.
Typical capacitance value in the range of 0.1 µF to 1 µF is recommended for C(IN).
30
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
10.2.3 Application Curves
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
Figure 53. Hot Plug With VIN - No Load
Figure 54. Hot-Plug With VIN - 96-Ω Load
Figure 55. Start-Up With Shutdown Pin - 96-Ω Load
Figure 56. Power Down With Shutdown Pin - 96-Ω Load
VIN
VIN
VOUT
VOUT
FLTb
FLTb
IIN
IIN
Figure 57. Over Load Response - Load Stepped From
136-Ω to 36-Ω Load
Figure 58. Turn ON with Short Circuit on Output
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
31
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
10.3 System Examples
10.3.1 Field Supply Protection in PLC, DCS I/O Modules
TPS26624 / TPS26625
24-V nominal (from field
SELV power supply)
IN
Power FET isolation during over
voltage , Input Reverse Polarity,
Output Reverse Polarity and short
circuit faults
Inrush Current
Control
Fault Diagnostics
To Field Loads
(Sensors & Actuators)
FLT
SHDN
FLT
ON/OFF
Control
DC/DC
OUT
Fault
MCU
Field side
Digital Isolator
PLC side
Figure 59. Power Delivery Circuit Block Diagram in I/O Modules
The PLC or Distributed Control System (DCS) I/O modules are often connected to an external field power supply
to support higher power requirements of the field loads like sensors and actuators. Power-supply faults or
miswiring can damage the loads or cause the loads not to operate correctly. The TPS26624 and TPS26625 can
be used as a front end protection circuit to protect and provide stable supply to the field loads. Undervoltage,
Overvoltage and input and output side reverse polarity protection features of these devices prevent the loads to
experience voltages outside the operating range, which can permanently damage the loads.
Field power supply is often connected to multiple I/O modules that can deliver more current than a single I/O
module can handle. Overcurrent protection scheme of the TPS2662x family limits the current from the power
supply to the module so that the maximum current does not rise above what the board is designed for. Fast short
circuit protection scheme isolates the faulty load from the field supply quickly and prevents the field supply to dip
and cause interrupts in the other I/O modules connected to the same field supply. High accurate (±5% at 0.88 A)
current limit facilitates more I/O modules to be connected to field supply. Fault indication (FLT) features facilitate
continuous load monitoring.
The TPS26624 and TPS26625 also acts as a smart diode with protection against reverse current during output
side miswiring. Reverse current can potentially damage the field power supply and cause the I/O modules to run
hot or may cause permanent damage.
If the field power supply is connected in reverse polarity on the input side (which is not unlikely as field power
supplies are usually connected with screw terminals), field loads can permanently get damaged due to the
reverse voltage. Also, during the installation the field power supply could be miswired on the output side instead
of on the input side which could damage the upstream power supply and electronics. The input and output
reverse polarity protection feature of the TPS26624 and TPS26625 prevents the reverse voltage to appear at the
load side as well as supply side offering complete system protection during field miswiring.
32
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
System Examples (continued)
10.3.2 Simple 24-V Power Supply Path Protection
With the TPS2662x, a simple 24-V power supply path protection can be realized using a minimum of four
external components as shown in the schematic diagram in Figure 60. The external components required are: a
1Meg Ω R(1) resistor across IN and UVLO pins, a R(ILIM) resistor to program the current limit, C(IN) and C(OUT)
capacitors.
System Load
OUT
IN
CIN
Input from a 24V
power supply
VOUT
COUT
R1
1Meg
478 PŸ
UVLO
OVP
FLT
TPS2662x
SHDN
dVdT
ILIM
RTN
GND
RILIM
Figure 60. TPS2662x Configured for a Simple 24-V Supply Path Protection
Protection features with this configuration include:
• Load and device protection from reverse input polarity fault down to –60 V
• Upstream supply and device protection from reverse output polarity fault down to –(60 – VIN) V with
TPS26624 and TPS26625 variants
• Protection from 60 V from the external SELV supply: Over Voltage Clamp at 38 V with TPS26622 and
TPS26623 variants
• Inrush current control with 24V and 660 µs output voltage slew rate
• Reverse Current Blocking
• Accurate current limiting with Auto-Retry with TPS26621, TPS26623, TPS26625 variants
• Accurate current limiting with Latch-off with TPS26620, TPS26622, TPS26624 variants
10.3.3 Power Stealing in Smart Thermostat
The adjustable protection features of the TPS2662x eFuse like the inrush current limiting, over voltage and
over current protection simplifies the input power management design in smart thermostats. Refer to the TI
Design report, Power Stage Reference Design for Power Stealing Thermostat for further information.
10.4 Do's and Don'ts
•
•
•
Do not connect RTN to GND. Connecting RTN to GND disables the Reverse Polarity protection feature.
Do connect the TPS2662x support components R(ILIM), C(dVdT), and UVLO, OVP resistors with respect to RTN
pin.
Do connect device PowerPAD to the RTN plane for an enhanced thermal performance.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
33
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
11 Power Supply Recommendations
The TPS2662x eFuse is designed for the supply voltage range of 4.5 V ≤ VIN ≤ 60 V. If the input supply is
located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is
recommended. Power supply must be rated higher than the current limit set to avoid voltage droops during
overcurrent and short circuit conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the
input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Use of a Schottky diode across the output and GND to absorb negative spikes in the designs with TPS26620,
TPS26621, TPS26622, TPS26623 devices and a TVS clamp in the designs withTPS26624 and TPS26625
devices
• A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 13.
Vspike(Absolute ) = V(IN) + I(Load) ´
L(IN)
C(IN)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(13)
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and negative
surge tests on the supply lines. In such applications it is recommended to place at least 1 µF of input capacitor to
limit the falling slew rate of the input voltage within a maximum of 20 V/µs.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 61 and Figure 62.
INPUT
IN
R1
CIN
UVLO
OVP
R2
FLT
RTN
*
SHDN
TPS26620/1/2/3
dVdT
*
COUT
R4
478 m
*
R3
OUTPUT
OUT
ILIM
GND
RILIM
CdVdT
Optional components needed for suppression of transients
Figure 61. Circuit Implementation With Optional Protection Components for TPS26620, TPS26621,
TPS26622 and TPS26623
34
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
Transient Protection (continued)
INPUT
IN
R1
CIN
R4
UVLO
OVP
R2
FLT
TPS26624/5
dVdT
*
COUT
478 m
*
R3
OUTPUT
OUT
RTN
*
SHDN
ILIM
GND
RILIM
CdVdT
Optional components needed for suppression of transients
Figure 62. Circuit Implementation With Optional Protection Components for TPS26624 and TPS26625
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
35
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
36
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 63 for a typical PCB layout example.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
RTN, which is the reference ground for the device must be a copper plane or island.
Locate all the TPS2662x family support components R(ILIM), C(dVdT), UVLO, OVP resistors close to their
connection pin. Connect the other end of the component to the RTN with shortest trace length.
The trace routing for the RILIM component to the device must be as short as possible to reduce parasitic
effects on the current limit and current monitoring accuracy. These traces must not have any coupling to
switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
TPS2662
www.ti.com
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
12.2 Layout Example
Top Layer
Bottom layer GND plane
Via to Bottom Layer
Top Layer RTN Plane
Track in bottom layer
Bottom Layer RTN Plane
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
VIN PLANE
IN
OUT
UVLO
FLT
OVP
dVdT
SHDN
ILIM
RTN
GND
VOUT PLANE
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 63. Typical PCB Layout Example With a 2 Layer PCB
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
37
TPS2662
SLVSDT4E – OCTOBER 2017 – REVISED AUGUST 2019
www.ti.com
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS2662
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS26620DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED00
TPS26620DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED00
TPS26621DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED01
TPS26621DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED01
TPS26622DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED02
TPS26622DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED02
TPS26623DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED03
TPS26623DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED03
TPS26624DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED04
TPS26624DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED04
TPS26625DRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED05
TPS26625DRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ED05
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2019
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS26620DRCR
VSON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26620DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26621DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26621DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26622DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26622DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26623DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26623DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26624DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26624DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26625DRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS26625DRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS26620DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26620DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS26621DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26621DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS26622DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26622DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS26623DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26623DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS26624DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26624DRCT
VSON
DRC
10
250
210.0
185.0
35.0
TPS26625DRCR
VSON
DRC
10
3000
367.0
367.0
35.0
TPS26625DRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising