Texas Instruments | LM25180 42-VIN PSR Flyback DC/DC Converter with 65-V, 1.5-A Integrated Power MOSFET (Rev. A) | Datasheet | Texas Instruments LM25180 42-VIN PSR Flyback DC/DC Converter with 65-V, 1.5-A Integrated Power MOSFET (Rev. A) Datasheet

Texas Instruments LM25180 42-VIN PSR Flyback DC/DC Converter with 65-V, 1.5-A Integrated Power MOSFET (Rev. A) Datasheet
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LM25180
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
LM25180 42-VIN PSR Flyback DC/DC Converter with 65-V, 1.5-A Integrated Power MOSFET
1 Features
3 Description
•
The LM25180 is a primary-side regulated (PSR)
flyback converter with high efficiency over a wide
input voltage range of 4.5 V to 42 V. The isolated
output voltage is sampled from the primary-side
flyback voltage, eliminating the need for an
optocoupler, voltage reference, or third winding from
the transformer for output voltage regulation. The
high level of integration results in a simple, reliable
and high-density design with only one component
crossing the isolation barrier. Boundary conduction
mode (BCM) switching enables a compact magnetic
solution and better than ±1.5% load and line
regulation performance. An integrated 65-V power
MOSFET provides output power up to 7 W with
enhanced headroom for line transients.
1
•
•
•
Designed for reliable and rugged applications
– Wide input voltage range of 4.5 V to 42 V
– Robust solution with only one component
crossing the isolation barrier
– ±1.5% total output regulation accuracy
– Optional VOUT temperature compensation
– 6-ms internal or programmable soft start
– Input UVLO and thermal shutdown protection
– Hiccup-mode overcurrent fault protection
– –40°C to +150°C junction temperature range
Integration reduces solution size and cost
– Integrated 65-V, 0.4-Ω power MOSFET
– No opto-coupler or transformer auxiliary
winding required for VOUT regulation
– Internal loop compensation
– Low EMI operation to meet CISPR 32
High efficiency PSR flyback operation
– Quasi-resonant switching in boundary
conduction mode (BCM) at heavy load
– Low input quiescent current
– External bias option for improved efficiency
– Single- and multi-output implementations
Create a custom regulator design using
WEBENCH® Power Designer
The LM25180 converter simplifies implementation of
isolated DC/DC supplies with optional features to
optimize performance for the target end equipment.
The output voltage is set by one resistor, while an
optional resistor improves output voltage accuracy by
negating the thermal coefficient of the flyback diode
voltage drop. Additional features include an internallyfixed or externally-programmable soft start, optional
bias supply connection for higher efficiency, precision
enable input with hysteresis for adjustable line UVLO,
hiccup-mode overload protection, and thermal
shutdown protection with automatic recovery.
The LM25180 flyback converter is available in a 8pin, 4-mm × 4-mm, thermally-enhanced WSON
package with 0.8-mm pin pitch.
2 Applications
•
•
•
•
Device Information(1)
Isolated field transmitters and field actuators
Multi-output rails for analog input modules
Motor drive: IGBT gate drive supplies
Building automation HVAC systems
PART NUMBER
LM25180
T1
DZ
RFB
LM25180
GND
3:1
SW
EN/UVLO
DFLY
VOUT = 5 V
85
COUT
100 F
DF
VIN
Typical Efficiency, VOUT = 5 V
90
158 k:
FB
Efficiency (%)
CIN
2.2 F
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN = 4.5 V...42 V
PACKAGE
WSON (8)
80
75
70
RSET
RSET
SS/BIAS
VIN = 12V
VIN = 24V
VIN = 36V
65
12.1 k:
TC
60
0
0.2
0.4
0.6
0.8
Output Current (A)
1
1.2
1.4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25180
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 32
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Examples................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2018) to Revision A
Page
•
Changed EC table specs for current limit............................................................................................................................... 4
•
Added note about failsafe current limit ................................................................................................................................. 14
2
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SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
5 Pin Configuration and Functions
NGU Package
8-Pin WSON With Wettable Flanks
Top View
SW
1
8
GND
FB
2
7
RSET
VIN
3
6
TC
EN/UVLO
4
5
SS/BIAS
Pin Functions
PIN
NO.
NAME
I/O (1)
DESCRIPTION
1
SW
P
Switch node that is internally connected to the drain of the N-channel power MOSFET. Connect
to the primary-side switching terminal of the flyback transformer.
2
FB
I
Primary side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to the
resistor at the RSET pin sets the output voltage.
3
VIN
P/I
Input supply connection. Source for internal bias regulators and input voltage sensing pin.
Connect directly to the input supply of the converter with short, low impedance paths.
4
EN/UVLO
I
Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO
voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
5
SS/BIAS
I
Soft-start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up
time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is
activated. Connect an external supply to SS/BIAS to supply bias to the internal voltage regulator
and enable internal soft start.
6
TC
I
Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the
temperature coefficient of the forward voltage drop of the secondary diode, thus improving
regulation at the secondary-side output.
7
RSET
I
Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor
from RSET to GND.
8
GND
G
Analog and power ground. Ground connection of internal control circuits and power MOSFET.
-
DAP
G
Die attach pad. Connect to PCB ground plane.
(1)
P = Power, G = Ground, I = Input, O = Output.
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
Input voltage
Output voltage
MIN
MAX
VIN to GND
–0.3
45
EN/UVLO to GND
–0.3
45
TC to GND
–0.3
6
SS/BIAS to GND
–0.3
14
FB to GND
–0.3
45.3
FB to VIN
–0.3
0.3
RSET to GND
–0.3
3
SW to GND
–1.5
70
SW to GND (20-ns transient)
–3
UNIT
V
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1)
HBM ESD Classification Level 2
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
CDM ESD Classification Level C4B
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
VIN
Input voltage after turn on
VSW
NOM
MAX
4.5
UNIT
42
V
SW voltage
65
V
VEN/UVLO
EN/UVLO voltage
42
V
VSS/BIAS
SS/BIAS voltage
13
V
TJ
Operating junction temperature
150
°C
–40
6.4 Thermal Information
LM25180
THERMAL METRIC (1)
NGU (WSON)
UNIT
8 PINS
RΘJA
Junction-to-ambient thermal resistance
41.3
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
34.7
°C/W
RΘJB
Junction-to-board thermal resistance
19.1
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
19.2
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
3.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISHUTDOWN
VIN shutdown current
VEN/UVLO = 0 V
IACTIVE
VIN active current
VEN/UVLO = 2.5 V, VRSET = 1.8 V
IACTIVE-BIAS
VIN current with BIAS connected
VSS/BIAS = 6 V
VSD-FALLING
Shutdown threshold
VEN/UVLO falling
3
µA
260
350
µA
25
40
µA
0.3
V
ENABLE AND INPUT UVLO
VSD-RISING
Standby threshold
VEN/UVLO rising
0.8
1
V
VUV-RISING
Enable threshold
VEN/UVLO rising
1.45
1.5
1.53
V
VUV-HYST
Enable voltage hysteresis
VEN/UVLO falling
0.04
0.05
IUV-HYST
Enable current hysteresis
VEN/UVLO = 1.6 V
4.2
5
IRSET
RSET current
RRSET = 12.1 kΩ
VRSET
RSET regulation voltage
RRSET = 12.1 kΩ
1.191
1.21
VFB-VIN1
FB to VIN voltage
IFB = 80 µA
VFB-VIN2
FB to VIN voltage
IFB = 120 µA
V
5.5
µA
FEEDBACK
100
µA
1.224
–40
V
mV
40
mV
SWITCHING FREQUENCY
FSW-MIN
Minimum switching frequency
12
kHz
FSW-MAX
Maximum switching frequency
350
kHz
tON-MIN
Minimum switch on-time
140
ns
DIODE THERMAL COMPENSATION
VTC
TC voltage
ITC = ±10 µA, TJ = 25°C
1.2
ISW = 100 mA
0.4
1.27
V
POWER SWITCHES
RDS(on)
MOSFET on-state resistance
Ω
SOFT-START AND BIAS
ISS
SS ext capacitor charging current
5
µA
tSS
Internal SS time
6
ms
VBIAS-UVLO-
BIAS enable voltage
VSS/BIAS rising
5.5
BIAS UVLO hysteresis
VSS/BIAS falling
190
RISE
VBIAS-UVLOHYST
5.75
V
mV
CURRENT LIMIT
ISW-PEAK
Peak current limit threshold
1.23
1.5
1.73
A
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
TSD-HYS
Thermal shutdown hysteresis
TJ rising
175
°C
6
°C
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6.6 Typical Characteristics
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
90
5.2
5.15
85
Output Voltage (V)
Efficiency (%)
5.1
80
75
70
5.05
5
4.95
4.9
VIN = 12V
VIN = 24V
VIN = 36V
65
VIN = 12V
VIN = 24V
VIN = 36V
4.85
60
4.8
0
0.2
0.4
0.6
0.8
Output Current (A)
1
1.2
1.4
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
See Figure 23
See Figure 23
Figure 1. Efficiency vs. Load
Figure 2. Output Voltage vs. Load
SW 20V/DIV
VDFLY 5V/DIV
1 Ps/DIV
1 Ps/DIV
See Figure 23
IOUT = 1 A
See Figure 23
IOUT = 1 A
Figure 4. Flyback Diode Switching Waveform in BCM
Figure 3. Primary-side Switching Waveform in BCM
Shutdown Quiescent Current (PA)
18
VOUT 1V/DIV
VIN 10V/DIV
IOUT 500mA/DIV
2 ms/DIV
15
12
9
6
3
0
-50
See Figure 23
Figure 5. Startup Characteristic
6
VIN = 12 V
VIN = 24 V
VIN = 42 V
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D001
Figure 6. Shutdown Quiescent Current vs. Temperature
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Typical Characteristics (continued)
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
35
Active Quiescent Current (PA)
Active Quiescent Current (PA)
290
280
270
260
250
VIN = 12 V
VIN = 24 V
VIN = 42 V
240
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
30
25
20
VIN = 12 V
VIN = 24 V
VIN = 42 V
15
-50
150
-25
0
D002
25
50
75
100
Junction Temperature (qC)
125
150
D003
VSS/BIAS = 6 V
Figure 8. Active Quiescent Current with BIAS vs.
Temperature
102
104
101
102
RSET Current (PA)
RSET Current (PA)
Figure 7. Active Quiescent Current vs. Temperature
100
100
98
99
96
-50
98
0
6
12
18
24
Input Voltage (V)
30
36
42
Figure 9. RSET Current vs. Input Voltage
25
50
75
100
Junction Temperature (qC)
125
150
D005
EN/UVLO Threshold Voltage (V)
1.54
1.6
TC Voltage (V)
0
Figure 10. RSET Current vs. Temperature
1.8
1.4
1.2
1
0.8
-50
-25
D004
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
1.52
1.5
1.48
1.46
1.44
1.42
1.4
-50
D006
Figure 11. TC Voltage vs. Temperature
VEN/UVLO Rising
VEN/UVLO Falling
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D007
Figure 12. EN/UVLO Threshold Voltages vs. Temperature
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Typical Characteristics (continued)
5.3
0.8
5.2
0.7
Switch RDS(on) (:)
EN/UVLO Hysteresis Current (PA)
VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated).
5.1
5
4.9
4.8
4.7
-50
0.6
0.5
0.4
0.3
-25
0
25
50
75
100
Junction Temperature (qC)
125
0.2
-50
150
1.5
155
1.2
BCM
FFM
0.6
0.3
0
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D009
145
140
-25
0
D010
25
50
75
100
Junction Temperature (qC)
125
150
D011
Figure 16. Minimum Switch On-Time vs. Temperature
380
Max. Switching Frequency (kHz)
Min. Switching Frequency (kHz)
125
150
130
-50
150
Figure 15. Switch Peak Current Limits vs. Temperature
12.5
12
11.5
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
370
360
350
340
330
320
-50
D012
Figure 17. Minimum Switching Frequency vs. Temperature
8
25
50
75
100
Junction Temperature (qC)
135
13
11
-50
0
Figure 14. MOSFET RDS(on) vs. Temperature
160
Minimum on-time (ns)
Peak Current Limit (A)
Figure 13. EN/UVLO Hysteresis Current vs. Temperature
1.8
0.9
-25
D008
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D013
Figure 18. Maximum Switching Frequency vs. Temperature
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7 Detailed Description
7.1 Overview
The LM25180 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for
industrial systems requiring less than 7 W of isolated DC/DC power. This compact, easy-to-use flyback converter
with low IQ can be applied over a wide input voltage range from 4.5 V to 42 V, with operation down to 3.5 V after
startup. Innovative frequency and current amplitude modulation enables high conversion efficiency across the
entire load and line range. Primary-side regulation of the isolated output voltage using sampled values of the
primary winding voltage eliminates the need for an opto-coupler or an auxiliary transformer winding for feedback.
Regulation performance that rivals that of traditional opto-coupler solutions is achieved without the associated
cost, solution size and reliability concerns. The LM25180 converter services a wide range of applications
including IGBT-based motor drives, factory automation, and medical equipment.
7.2 Functional Block Diagram
VIN
NP : NS
CIN
DZ
LM25180
5 PA
EN/UVLO
DFLY
BIAS
REGULATOR
Standby
1.5 V
1.45 V
VOUT
COUT
SS/BIAS
VDD
VIN
VDD UVLO
Shutdown
DF
SAMPLED
FEEDBACK
1.1 V
VIN
THERMAL
SHUTDOWN
FB
65-V Power
MOSFET
RSET
gm
COMP
SW
VDD
VREF
TRIMMED
REFERENCE
RTC
CONTROL
LOGIC
RSET
FB
ILIM
TC
1.5 A
TC
REGULATION
VDD
GND
RFB
SS/BIAS
Internal SS
CSS
7.3 Feature Description
7.3.1 Integrated Power MOSFET
The LM25180 is a flyback dc/dc converter with integrated 65-V, 1.5-A N-channel power MOSFET. During the
MOSFET on-time, the transformer primary current increases from zero with slope VIN / LMAG (where LMAG is the
transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current. When
the high-side MOSFET is turned off by the control logic, the SW voltage VSW swings up to approximately VIN +
(NPS × VOUT), where NPS = NP/NS is the primary-to-secondary turns ratio of the transformer. The magnetizing
current flows in the secondary side through the flyback diode, charging the output capacitor and supplying
current to the load. Duty cycle D is defined as tON / tSW, where tON is the MOSFET conduction time and tSW is the
switching period.
Figure 19 shows a typical schematic of the LM25180 PSR flyback circuit. Components denoted in red are
optional depending on the application requirements.
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Feature Description (continued)
T1
DFLY
VIN
VOUT
DCLAMP
COUT
RUV1
CIN
EN/UVLO
RUV2
SW
RFB
LM25180
GND
NP : NS
DF
VIN
DOUT
FB
RSET
SS/BIAS
CSS
RTC
RSET
TC
Figure 19. LM25180 Flyback Converter Schematic (Optional Components in Red)
7.3.2 PSR Flyback Modes of Operation
The LM25180 uses a variable-frequency, peak current-mode (VFPCM) control architecture with three possible
modes of operation as illustrated in Figure 20.
Frequency
foldback mode
(FFM)
Discontinuous conduction mode (DCM)
Boundary conduction mode (BCM)
400
Switching Frquency (kHz)
350
300
250
200
150
100
50
0
0
20
40
60
80
100
% Total Rated Output Power
Figure 20. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load
10
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Feature Description (continued)
The LM25180 operates in boundary conduction mode (BCM) at heavy loads. The power MOSFET turns on when
the current in the secondary winding reaches zero, and the MOSFET turns off when the peak primary current
reaches the level dictated by the output of the internal error amplifier. As the load is decreased, the frequency
increases in order to maintain BCM operation. The duty cycle of the flyback converter is given Equation 1, where
VD is the forward voltage drop of the flyback diode as its current approaches zero.
DBCM
VOUT
VIN
VD ˜ NPS
VOUT
VD ˜ NPS
(1)
The output power in BCM is given by Equation 2, where the applicable switching frequency and peak primary
current in BCM are specified by Equation 3 and Equation 4, respectively.
LMAG ˜ IPRI-PK(BCM)
POUT(BCM)
FSW(BCM)
2
˜ FSW(BCM)
2
(2)
1
§L
IPRI-PK(BCM) ˜ ¨ MAG
¨ VIN
©
IPRI-PK(BCM)
2 ˜ VOUT
LMAG
NPS ˜ VOUT
VD
·
¸¸
¹
(3)
VD ˜ IOUT
VIN ˜ D
(4)
As the load decreases, the LM25180 clamps the maximum switching frequency to 350 kHz, and the converter
enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is proportional to the
peak primary current squared as given by Equation 5 and Equation 6. Thus, as the load decreases, the peak
current reduces to maintain regulation at 350-kHz switching frequency.
POUT(DCM)
IPRI-PK(DCM)
DDCM
LMAG ˜ IPRI-PK(DCM)
2
2
˜ FSW(DCM)
(5)
2 ˜ IOUT ˜ VOUT
VD
LMAG ˜ FSW(DCM)
(6)
LMAG ˜ IPRI-PK(DCM) ˜ FSW(DCM)
VIN
(7)
At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum
level of 0.3 A, or 20% of its 1.5-A peak value, and the MOSFET off-time extends to maintain the output load
requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases as
the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM25180 is 12
kHz, which sets a minimum load requirement of approximately 0.5% full load.
7.3.3 Setting the Output Voltage
To minimize output voltage regulation error, the LM25180 senses the reflected secondary voltage when the
secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB as shown
in Figure 19, is determined using Equation 8, where RSET is nominally 12.1 kΩ.
RFB
VOUT
VD ˜ NPS ˜
RSET
VREF
(8)
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Feature Description (continued)
7.3.3.1 Diode Thermal Compensation
The LM25180 employs a unique thermal compensation circuit that adjusts the feedback setpoint based on the
thermal coefficient of the flyback diode's forward voltage drop. Even though the output voltage is measured when
the secondary current is effectively zero, there is still a non-zero forward voltage drop associated with the flyback
diode. Select the thermal compensation resistor using Equation 9.
RFB 3mV qC
RTC
˜
NPS TCDiode
(9)
The temperature coefficient of the diode voltage drop may not be explicitly provided in the diode datasheet, so
the effective value can be estimated based on the measured output voltage shift over temperature when the TC
resistor is not installed.
7.3.4 Control Loop Error Amplifier
The inputs of the error amplifier include a level-shifted version of the FB voltage and an internal 1.21-V reference
set by the resistor at RSET. A type-2 internal compensation network stabilizes the converter. In BCM operation
when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.
The power MOSFET is subsequently turned off when an amplified version of the peak primary current exceeds
the error amplifier output.
7.3.5 Precision Enable
The precision EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis for
application specific power-up and power-down requirements. EN/UVLO connects to a comparator with a 1.5-V
reference voltage and 50-mV hysteresis. An external logic signal can be used to drive the EN/UVLO input to
toggle the output on and off for system sequencing or protection. The simplest way to enable the LM25180 is to
connect EN/UVLO directly to VIN. This allows the LM25180 to start up when VIN is within its valid operating
range. However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 21 to
establish a precision UVLO level.
LM25180
VCC
VIN
5 A
RUV1
EN/UVLO
+
RUV2
1.5 V
1.45 V
UVLO
Comparator
Figure 21. Programmable Input Voltage UVLO With Hysteresis
Use Equation 10 and Equation 11 to calculate the input UVLO voltages turn-on and turn-off voltages,
respectively, where VUV-RISING and VUV-FALLING are the UVLO comparator thresholds and IUV-HYST is the hysteresis
current.
VIN(on)
12
§
RUV1 ·
VUV-RISING ¨ 1
¸
© RUV2 ¹
(10)
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Feature Description (continued)
VIN(off)
§
RUV1 ·
VUV-FALLING ¨ 1
¸ IUV-HYST ˜ RUV2
© RUV2 ¹
(11)
The LM25180 also provides a low-IQ shutdown mode when the EN/UVLO voltage is pulled below a base-emitter
voltage drop (approximately 0.6 V at room temperature). If the EN/UVLO voltage is below this hard shutdown
threshold, the internal LDO regulator powers off, and the internal bias-supply rail collapses, shutting down the
bias currents of the LM25180. The LM25180 operates in standby mode when the EN/UVLO voltage is between
the hard shutdown and precision-enable thresholds.
7.3.6 Configurable Soft Start
The LM25180 has a flexible and easy-to-use soft-start control pin, SS/BIAS. The soft-start feature prevents
inrush current impacting the LM25180 and the input supply when power is first applied. This is achieved by
controlling the voltage at the output of the internal error amplifier. Soft start is achieved by slowly ramping up the
target regulation voltage when the device is first enabled or powered up. Selectable and adjustable start-up
timing options include a 6-ms internally-fixed soft start and an externally-programmable soft start.
The simplest way to use the LM25180 is to leave SS/BIAS open. The LM25180 employs an internal soft-start
control ramp and starts up to the regulated output voltage in 6 ms.
However, in applications with a large amount of output capacitance, higher VOUT or other special requirements,
the soft-start time can be extended by connecting an external capacitor CSS from SS/BIAS to GND. A longer softstart time further reduces the supply current needed to charge the output capacitors while sourcing the required
load current. When the EN/UVLO voltage exceeds the UVLO rising threshold and a delay of 20 µs expires, an
internal current source ISS of 5 µA charges CSS and generates a ramp to control the primary current amplitude.
Calculate the soft-start capacitance for a desired soft-start time, tSS, using Equation 12.
CSS ª¬nF º¼
5 ˜ t SS ª¬ms º¼
(12)
CSS is discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.
7.3.7 External Bias Supply
DFLY
T1
VIN
VOUT
DCLAMP
COUT
RUV1
CIN
EN/UVLO
RUV2
SW
RFB
LM25180
GND
RSET
NP : NS
DF
VIN
FB
DBIAS1
SS/BIAS
DBIAS2
RSET
TC
DOUT
12 V
CBIAS
22 nF
NP : NAUX
Figure 22. External Bias Supply Using Transformer Auxiliary Winding
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Feature Description (continued)
The LM25180 has an external bias supply feature that reduces input quiescent current and increases efficiency.
When the voltage at SS/BIAS exceeds a rising threshold of 5.5 V, bias power for the internal LDO regulator can
be derived from an external voltage source or from a transformer auxiliary winding as shown in Figure 22. With a
bias supply connected, the LM25180 then uses its internal soft-start ramp to control the primary current during
start-up.
When using a transformer auxiliary winding for bias power, the total leakage current related to diodes DBIAS1 and
DBIAS2 in Figure 22 should be less than 1 µA across the full operating temperature range.
7.3.8 Minimum On-Time and Off-Time
When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the
SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage
inductance and may corrupt the secondary zero-current detection. In order to prevent such a situation, a
minimum switch off-time, designated as tOFF-MIN, of maximum 450 ns is set internally to ensure proper
functionality. This sets a lower limit for the transformer magnetizing inductance as discussed in Detailed Design
Procedure.
Furthermore, noise effects as a result of power MOSFET turn-on can impact the internal current sense circuit
measurement. To mitigate this effect, the LM25180 provides a blanking time after the MOSFET turns on. This
blanking time forces a minimum on-time, tON-MIN, of 140 ns.
7.3.9 Overcurrent Protection
In case of an overcurrent condition on the isolated output(s), the output voltage drops lower than the regulation
level since the maximum power delivered is limited by the peak current capability on the primary side. The peak
primary current is maintained at 1.5 A (plus an amount related to the 100-ns propagation delay of the current limit
comparator) until the output decreases to the secondary diode voltage drop to impact the reflected signal on the
primary side. At this point, the LM25180 assumes the output cannot be recovered and re-calibrates its switching
frequency to 9 kHz until the overload condition is removed. The LM25180 responds with similar behavior to an
output short circuit condition.
For a given input voltage, Equation 13 gives the maximum output current prior to the engagement of overcurrent
protection. The typical threshold value for ISW-PEAK from Specifications is 1.5 A.
IOUT(max)
ISW-PEAK
§V
VD
2 ˜ ¨ OUT
VIN
©
1 ·
¸
NPS ¹
(13)
A failsafe current limit set at 2.4A, or 1.6 times the nominal peak current limit, provides redundant fault protection
in case of transformer short circuit or saturation effects. This initiates a 7.5ms hiccup interval after eight
overcurrent events.
7.3.10 Thermal Shutdown
Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to
overheating. Thermal shutdown turns off the device when the junction temperature exceeds 175°C to prevent
further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the restarts
when the junction temperature falls to 169°C.
14
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
EN/UVLO facilitates ON and OFF control for the LM25180. When VEN/UVLO is below approximately 0.6 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 3 μA at VIN = 24 V. The LM25180 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.
7.4.2 Standby Mode
The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is
above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating.
The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action
and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.
7.4.3 Active Mode
The LM25180 is in active mode when VEN/UVLO is above the precision-enable threshold and the internal bias rail
is above its UV threshold. The LM25180 operates in one of three modes depending on the load current
requirement:
1. Boundary conduction mode (BCM) at heavy loads.
2. Discontinuous conduction mode (DCM) at medium loads.
3. Frequency foldback mode (FFM) at light loads.
Refer to PSR Flyback Modes of Operation for more detail.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM25180 requires only a few external components to convert from a wide range of supply voltages to one or
more isolated output rails. To expedite and streamline the process of designing of a LM25180-based converter, a
comprehensive LM25180 quick-start calculator is available for download to assist the designer with component
selection for a given application. WEBENCH® online software is also available to generate complete designs,
leveraging iterative design procedures and access to comprehensive component databases. The following
sections discuss the design procedure for both single- and dual-output implementations using specific circuit
design examples.
As mentioned previously, the LM25180 also integrates several optional features to meet system design
requirements, including precision enable, input UVLO, programmable soft start, output voltage thermal
compensation, and external bias supply connection. Each application incorporates these features as needed for
a more comprehensive design.
The application circuits detailed in Typical Applications show LM25180 configuration options suitable for several
application use cases. Refer to the LM5180EVM-S05 and LM5180EVM-DUAL EVM user's guides for more detail.
8.2 Typical Applications
For step-by-step design procedures, circuit schematics, bill of materials, PCB files, simulation and test results of LM25180-powered
implementations, refer to the TI reference designs library.
8.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 5 V, 1 A
The schematic diagram of a 5-V, 1-A PSR flyback converter is given in Figure 23.
VIN = 10 V...36 V
DFLY
T1
VOUT = 5 V
DCLAMP
24 V
RUV1
COUT
100 F
536 k:
CIN
10 F
EN/UVLO
RUV2
100 k:
SW
RFB
158 k:
LM25180
GND
SS/BIAS
FB
RSET
CSS
47 nF
IOUT = 1 A
3:1
30 PH
DF
VIN
DOUT
5.6 V
RTC
RSET
130 k:
12.1 k:
TC
Figure 23. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 5 V, IOUT = 1 A
8.2.1.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in Table 1.
16
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Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range
10 V to 36 V
Input UVLO thresholds
9.5 V on, 6.5 V off
Output voltage
5V
Rated load current, VIN = 24 V
1A
Output voltage regulation
±1.5%
Output voltage ripple
< 100 mV
The target full-load efficiency is 86% based on a nominal input voltage of 24 V and an isolated output voltage of
5 V. The LM25180 is chosen to deliver a fixed 5-V output voltage set by resistor RFB connected between the SW
and FB pins. The input voltage turn-on and turn-off thresholds are established by RUV1 and RUV2. The required
components are listed in Table 2.
Table 2. List of Components for Design 1
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
10 µF, 50 V, X7R, 1210, ceramic
Taiyo Yuden
UMK325AB7106KM-T
Murata
GRM32EC70J107ME15
Taiyo Yuden
JMK325AC7107MM-P
TDK
C3225X5R0J107M250AC
Würth Electronik
885012109004
100 µF, 6.3 V, X7S, 1210, ceramic
COUT
1
100 µF, 6.3 V, X5R, 1210, ceramic
CSS
1
47 nF, 16 V, X7R, 0402
Std
Std
DCLAMP
1
Zener, 24 V, 1 W, PowerDI-123
DFLZ24-7
Diodes Inc.
DF
1
Switching diode, 75 V, 0.25 A, SOD-323
CMDD4448
Central Semi
DFLY
1
Schottky diode, 40 V, 2 A, SOD-123
FSV340FP
ONsemi
DOUT
1
Zener, 5.6 V, 5%, SOD-523
BZX585-C5V6
Nexperia
RFB
1
158 kΩ, 1%, 0402
Std
Std
RSET
1
12.1 kΩ, 1%, 0402
Std
Std
RTC
1
130 kΩ, 1%, 0402
Std
Std
RUV1
1
536 kΩ, 1%, 0603
Std
Std
RUV2
1
100 kΩ, 1%, 0402
Std
Std
Coilcraft
YA8779-BLD
30 µH, 2 A, turns ratio 3 : 1, 9.3 × 10.2 mm
T1
U1
1
1
Würth Electronik
750317605
30 µH, 2.6 A, turns ratio 3 : 1, 12.5 × 15.5 mm
Sumida
12387-T151
40 µH, 2 A, turns ratio 3 : 1, 13.3 × 15.2 mm
Würth Electronik
750313974
LM25180 PSR flyback converter, VSON-8
Texas Instruments
LM25180NGUR
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25180 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
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Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the converter specifications using the LM25180 quick-start calculator.
8.2.1.2.3 Flyback Transformer – T1
Choose a turns ratio based on an approximate 60% max duty cycle at minimum input voltage using Equation 14,
rounding up or down as needed.
NPS
VIN(min)
DMAX
˜
1 DMAX VOUT VD
0.6
10 V
˜
1 0.6 5 V + 0.3 V
3
(14)
Select a magnetizing inductance based on the minimum off-time constraint using Equation 15. Choose a value of
30 µH with a saturation current of minimum 2 A for this application.
LMAG t
VOUT
VD ˜ NPS ˜ t OFF-MIN
5 V + 0.3 V ˜ 3 ˜ 450ns
IPRI-PK(FFM)
0.3 A
23.9 +
(15)
Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage
inductance may increase based on a higher number of primary turns, NP. The primary and secondary winding
RMS currents are given by Equation 16 and Equation 17, respectively.
IPRI-RMS
ISEC-RMS
D
˜ IPRI-PK
3
(16)
2 ˜ IOUT ˜ IPRI-PK ˜ NPS
3
(17)
Find the maximum output current for a given turns ratio using Equation 18, where the typical value for IPRI-PK(max)
is the 1.5 A switch current peak threshold. Iterate by increasing the turns ratio if the output current capability is
too low at minimum input voltage.
IOUT(max)
IPRI-PK(max)
ªV
VD
2 ˜ « OUT
VIN
¬
1 º
»
NPS ¼
(18)
8.2.1.2.4 Flyback Diode – DFLY
The flyback diode reverse voltage is given by Equation 19.
VD-REV t
VIN(max)
NPS
VOUT
36 V
3
5V
17 V
(19)
Select a 40-V, 3-A Schottky diode for this application to account for inevitable diode voltage overshoot and
ringing related to the resonance of transformer leakage inductance and diode parasitic capacitance. Connect an
appropriate RC snubber circuit (for example, 100 Ω and 22 pF) across the flyback diode if needed.
In general, choose a flyback diode with current rating greater than the maximum peak secondary winding current
of NPS*IPRI-PK(max). As mentioned in Layout, place adequate copper at the cathode of the diode to improve its
thermal performance and prevent overheating during high ambient temperature or overload conditions. Beware
of the high leakage current typical of a Schottky diode at elevated operating temperatures.
8.2.1.2.5 Zener Clamp Circuit – DF, DCLAMP
Connect a diode-Zener clamping circuit across the primary winding to limit the peak switch-node voltage after
MOSFET turn-off below the maximum level of 65 V, as given by Equation 20.
18
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VDZ(clamp)
VSW(max)
VIN(max)
(20)
Choosing the zener, DCLAMP, with clamp voltage of approximately 1.5 times the reflected output voltage, as
specified by Equation 21, provides a balance between the maximum SW voltage excursion and the leakage
inductance demagnetization time.
VDZ(clamp)
1.5 ˜ NPS ˜ VOUT
VD
1.5 ˜ 3 ˜ 5 V 0.3 V | 24 V
(21)
Select an ultra-fast switching diode or Schottky diode for DF with rated voltage greater than the maximum input
voltage and with low forward recovery voltage drop.
8.2.1.2.6 Output Capacitor – COUT
The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during a
load transient, and sets the dominant pole of the converter's small-signal response. For a flyback converter
specifically, the output capacitor supplies the load current when the main switch is on, and therefore the output
voltage ripple is a function of load current and duty cycle.
Select an output capacitance using Equation 22 to limit the ripple voltage amplitude to less than 1% of the output
voltage at minimum input voltage.
COUT t
IOUT(max) LMAG ˜ IPRI-PK(max)
˜
VIN
'VOUT
(22)
Substituting the maximum load current at minimum input voltage from Equation 18, transformer inductance, peak
switch current and peak-to-peak ripple voltage specification gives COUT greater than 72 μF.
Mindful of the voltage coefficient of ceramic capacitors, select a 100-µF, 6.3-V capacitor in 1210 case size with
X5R or better dielectric. Equation 23 gives the output capacitor RMS ripple current.
ICOUT-RMS
IOUT ˜
2 ˜ NPS ˜ IPRI-PK
3 ˜ IOUT
1
(23)
8.2.1.2.7 Input Capacitor – CIN
Select an input capacitance using Equation 24 to limit the ripple voltage amplitude to less than 5% of the input
voltage when operating at nominal input voltage.
CIN
§ D·
IPRI-PK ˜ D ˜ ¨ 1
2 ¸¹
©
t
2 ˜ FSW ˜ 'VIN
2
(24)
Substituting the input current at full load, switching frequency, peak primary current and peak-to-peak ripple
specification gives CIN greater than 2 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 10-µF,
50-V ceramic input capacitor with X7R dielectric in 1210 case size. Equation 25 gives the input capacitor RMS
ripple current.
ICIN-RMS
D ˜ IPRI-PK
4
1
˜
2
3 ˜D
(25)
8.2.1.2.8 Feedback Resistor – RFB
Select a feedback resistor, designated RFB, of 158 kΩ based on the secondary winding voltage at the end of the
flyback conduction interval (the sum of the 5-V output voltage and the Schottky diode forward voltage drop)
reflected by the transformer turns ratio of 3 : 1. The forward voltage drop of the flyback diode is 0.3 V as its
current approaches zero.
RFB
VOUT
VD ˜ NPS
0.1 mA
5 V 0.3 V ˜ 3
0.1 mA
158 k:
(26)
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8.2.1.2.9 Thermal Compensation Resistor – RTC
Select a resistor for output voltage thermal compensation, designated RTC, based on Equation 27.
RTC
RFB 3 mV qC
˜
NPS TCDiode
158 k: ˜ 3
3 ˜ 1.2
130 k:
(27)
8.2.1.2.10 UVLO Resistors – RUV1, RUV2
Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds of 9.5 V and 6.5 V, respectively,
select the upper and lower UVLO resistors using the following expressions:
VIN(on) ˜
RUV1
RUV2
RUV1 ˜
VUV-FALLING
VUV-RISING
IUV-HYST
VIN(off)
VUV-RISING
VIN(on) VUV-RISING
9.5 V ˜
536 k: ˜
1.45 V
1.5 V
5 $
6.5 V
536k:
(28)
1.5 V
9.5 V 1.5 V
100 k:
(29)
8.2.1.2.11 Soft-Start Capacitor – CSS
Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start
capacitance of 47 nF based on Equation 12 to achieve a soft-start time of 9 ms.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's
Power Management technical articles.
8.2.1.3 Application Curves
Unless otherwise stated, application performance curves were taken at TA = 25°C.
100
90
90
85
Efficiency (%)
Efficiency (%)
80
80
75
70
70
60
50
VIN = 12V
VIN = 24V
VIN = 36V
65
60
0
0.2
0.4
0.6
0.8
Output Current (A)
1
1.2
1.4
30
0.001
Figure 24. Efficiency (Linear Scale)
20
VIN = 12V
VIN = 24V
VIN = 36V
40
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0.01
0.1
Output Current (A)
1
2
Figure 25. Efficiency (Log Scale)
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5.2
5.2
5.15
5.1
Output Voltage (V)
Output Voltage (V)
5.1
5.05
5
4.95
5
4.9
4.9
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
4.85
4.8
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
4.8
0.001
0.01
0.1
Output Current (A)
1
2
Figure 27. Load Regulation (Log Scale)
Figure 26. Load Regulation (Linear Scale)
EN 1V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
VIN 10V/DIV
2 ms/DIV
2 ms/DIV
VIN stepped to 24 V
5-Ω Load
VIN = 24 V
Figure 28. Start-up Characteristic
5-Ω Load
Figure 29. Enable ON Characteristic
SW 20V/DIV
VDFLY 5V/DIV
1 Ps/DIV
1 Ps/DIV
VIN = 24 V
IOUT = 1 A
VIN = 24 V
IOUT = 1 A
Figure 31. Flyback Diode Voltage
Figure 30. SW Node Voltage
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Average detector
Peak detector
Peak detector
Average detector
Start 150 kHz
VIN = 24 V
IOUT = 0.85 A
Stop 30 MHz
150 kHz to 30 MHz
LIN = 4.7 µH
CIN = 10 µF
Figure 32. CISPR 25 Class 5 Conducted EMI Plot
22
Start 30 MHz
VIN = 24 V
IOUT = 0.85 A
Stop 108 MHz
30 MHz to 108 MHz
LIN = 4.7 µH
CIN = 10 µF
Figure 33. CISPR 25 Class 5 Conducted EMI Plot
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8.2.2 Design 2: PSR Flyback Converter With Dual Outputs of 15 V and –7.7 V at 200 mA
The schematic diagram of a dual-output flyback converter intended for isolated IGBT and SiC MOSFET gate
drive power supply applications is given in Figure 34.
VIN = 9.5 V...36 V
T1
DFLY1
VOUT1 = 15 V
IOUT1 = 0.2 A
DCLAMP
24 V
RUV1
340 k:
CIN
DF
VIN
10 F
DOUT1
18 V
1 : 1 : 0.52
30 PH
SW
EN/UVLO
RUV2
68.1 k:
COUT1
22 F
COUT2
47 F
RFB
LM25180
154 k:
VOUT2 = ±7.7 V
FB
GND
IOUT2 = ±0.2 A
DFLY2
RSET
SS/BIAS
DOUT2
8.2 V
RTC
RSET
200 k:
12.1 k:
TC
Figure 34. Schematic for Design 2 With VIN(nom) = 24 V, VOUT1 = 15 V, VOUT2 = –7.7 V, IOUT = 200 mA
8.2.2.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady state)
9.5 V to 36 V
Output 1 voltage and current
15 V, 0.2 A
Output 2 voltage and current
–7.7 V, –0.2 A
Input UVLO thresholds
9 V on, 7 V off
Output voltage regulation
±2%
The target full-load efficiency of this LM25180 design is 88% based on a nominal input voltage of 24 V and
isolated output voltages of 15 V and –7.7 V sharing a common return. The selected flyback converter
components are cited in Table 4, including multi-winding flyback transformer, input and output capacitors,
rectifying diodes and flyback converter IC.
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Table 4. List of Components for Design 2
REF DES
QTY
SPECIFICATION
VENDOR
PART NUMBER
CIN
1
10 µF, 50 V, X7R, 1210, ceramic
Taiyo Yuden
UMK325AB7106KM-T
TDK
C3225X7R1E226M
COUT1
1
22 µF, 25 V, X7R, 1210, ceramic
Murata
GRM32ER71E226KE15L
Taiyo Yuden
TMK325B7226MM-TR
TDK
C3225X7R1A476M
Murata
GRM32ER71A476ME15L
Taiyo Yuden
LMK325B7476MM-TR
COUT2
1
47 µF, 10 V, X7R, 1210, ceramic
DFLY1
1
Schottky diode, 100 V, 1 A, PowerDI-123
DFLS1100-7
Diodes Inc.
DFLY2
1
Schottky diode, 60 V, 1 A, PowerDI-123
DFLS160-7
Diodes Inc.
DCLAMP
1
Zener, 24 V, 1 W, PowerDI-123
DFLZ24-7
Diodes Inc.
DF
1
Switching diode, 75 V, 0.3 A, SOD323
1N4148WS
Diodes Inc.
DOUT1
1
Zener, 18 V, 5%, SOD523
BZX585-C18
Nexperia
DOUT2
1
Zener, 8.2 V, 2%, SOD523
BZX585-B8V2
Nexperia
RFB
1
154 kΩ, 1%, 0402
Std
Std
RSET
1
12.1 kΩ, 1%, 0402
Std
Std
RTC
1
200 kΩ, 1%, 0402
Std
Std
RUV1
1
340 kΩ, 1%, 0603
Std
Std
RUV2
1
68.1 kΩ, 1%, 0402
Std
Std
T1
1
30 µH, 2 A, turns ratio 1 : 1: 0.52, 9 × 10 mm, SMT
Coilcraft
YA8916-BLD
Würth Electronik
750317595
U1
1
LM25180 PSR flyback converter, VSON-8
Texas Instruments
LM25180NGUR
8.2.2.2 Detailed Design Procedure
Using the LM25180 quick-start calculator, components are selected based on the flyback converter
specifications.
8.2.2.2.1 Flyback Transformer – T1
Set the turns ratio of the transformer secondary windings using Equation 30, where NS1 and NS2 are the number
of secondary turns for the respective outputs.
NS2
NS1
VOUT2
VOUT1
VD2
VD1
7.7 V 0.3 V
15 V 0.3 V
0.52
(30)
Choose a primary-secondary turns ratio for the 15-V output based on an approximate 60% max duty cycle at
minimum input voltage using Equation 31. The transformer turns ratio for both outputs is thus specified as 1 : 1 :
0.52.
NPS
VIN(min)
DMAX
˜
1 DMAX VOUT VD
0.6
9.5 V
˜
|1
1 0.6 15 V + 0.3 V
(31)
Select a magnetizing inductance based on the minimum off-time constraint using Equation 32. Choose a value of
30 µH with a saturation current of 2 A for this application.
LMAG t
VOUT
VD ˜ NPS ˜ tOFF-MIN
IPRI-PK(FFM)
15 V + 0.35 V ˜ 1˜ 450ns
0.3 A
23.0 +
(32)
8.2.2.2.2 Flyback Diodes – DFLY1 and DFLY2
The flyback diode reverse voltages for the positive and negative outputs are given respectively by Equation 33
and Equation 25.
24
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VD1-REV t
VD2-REV t
VIN(max)
NPS
VIN(max)
NPS
36 V
1
VOUT1
VOUT2
15 V
51V
(33)
36 V ˜ 0.52 7.7 V
26.4 V
(34)
Choose 100-V, 1-A and 60-V, 1-A Schottky diodes for the positive and negative outputs, respectively, to allow
some margin for inevitable voltage overshoot and ringing related to leakage inductance and diode capacitance. If
needed, use a diode RC snubber circuit, for example 100 Ω and 22 pF, to mitigate such overshoot and ringing.
8.2.2.2.3 Input Capacitor – CIN
The input capacitor, CIN, filters the primary-side triangular current waveform. To prevent large ripple voltage, use
a low-ESR ceramic input capacitor sized according to Equation 24 for the RMS ripple current given by
Equation 25. In this design example, choose a 10-µF, 50-V ceramic input capacitor with X7R dielectric and 1210
footprint.
8.2.2.2.4 Feedback Resistor – RFB
Install a 154-kΩ resistor from SW to FB based on an output voltage setpoint of 15 V (plus a flyback diode voltage
drop) reflected to the primary by a transformer turns ratio of unity.
RFB
VOUT
VD ˜ NPS
0.1 mA
15 V
0.3 V ˜ 1
154 k:
0.1 mA
(35)
8.2.2.2.5 UVLO Resistors – RUV1, RUV2
Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds of 9 V and 7 V, respectively, select
the upper and lower UVLO resistors using Equation 36 and Equation 37.
VIN(on) ˜
RUV1
RUV2
RUV1 ˜
VUV-FALLING
VUV-RISING
IUV-HYST
VIN(off)
VUV-RISING
VIN(on) VUV-RISING
9 V˜
1.45 V
1.5 V
5 $
340 k: ˜
7V
340k:
(36)
1.5 V
9 V 1.5 V
68 k:
(37)
8.2.2.3 Application Curves
100
100
95
90
90
80
Efficiency (%)
Efficiency (%)
85
80
75
70
65
70
60
50
60
VIN = 12V
VIN = 24V
VIN = 36V
55
50
VIN = 12V
VIN = 24V
VIN = 36V
40
30
0
50
100
150
200
Output Current (mA)
250
300
1
Figure 35. Efficiency (Linear Scale)
10
Output Current (mA)
100
Figure 36. Efficiency (Log Scale)
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24
23.4
VIN = 12V
VIN = 24V
VIN = 36V
23
22.8
22.6
22.4
VIN = 12V
VIN = 24V
VIN = 36V
23.6
Output Voltage (V)
Output Voltage (V)
23.2
23.2
22.8
22.4
22.2
22
22
0
50
100
150
200
250
Output Current (mA)
300
350
400
Total of VOUT1 and VOUT2
1
10
Output Current (mA)
100
400
Total of VOUT1 and VOUT2
Figure 37. Load Regulation (Linear Scale)
Figure 38. Load Regulation (Log Scale)
EN 1V/DIV
VIN 10V/DIV
VOUT1 5V/DIV
VOUT1 5V/DIV
IOUT1 100mA/DIV
IOUT1 50mA/DIV
VOUT2 5V/DIV
VOUT2 5V/DIV
2 ms/DIV
2 ms/DIV
VIN stepped to 24 V
75 Ω and 40 Ω Loads
VIN = 24 V
75 Ω and 40 Ω Loads
Figure 39. Start-Up Characteristic
Figure 40. ENABLE ON Characteristic
VDFLY1 20V/DIV
SW 20V/DIV
VDFLY2 20V/DIV
1 Ps/DIV
1 Ps/DIV
VIN = 24 V
VIN = 24 V
Figure 41. SW Node Voltage, Full Load
26
Figure 42. Flyback Diode Voltages, Full Load
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VOUT1 1V/DIV
VOUT1 1V/DIV
IOUT1 100mA/DIV
IOUT1 100mA/DIV
IOUT2 100mA/DIV
IOUT2 100mA/DIV
VOUT2 0.5V/DIV
VIN = 24 V
VOUT2 0.5V/DIV
200 Ps/DIV
IOUT1 = 200 mA
Figure 43. Output 1 Load Transient, 50 mA to 200 mA
200 Ps/DIV
VIN = 24 V
IOUT2 = 200 mA
Figure 44. Output 2 Load Transient, 50 mA to 200 mA
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8.2.3 Design 3: PSR Flyback Converter With Stacked Dual Outputs of 24 V and 5 V
The schematic diagram of a dual-output flyback converter with high-voltage secondary stacked on the lowvoltage secondary winding is given in Figure 45. This configuration reduces the number of turns for the highvoltage output, resulting in lower secondary-to-secondary leakage inductance for improved output voltage cross
regulation.
VIN = 8.5 V...42 V
T1
CIN
EN/UVLO
RUV2
34 k:
COUT1
10 F
SW
DFLY2
VOUT2 = 5 V
RFB
LM25180
GND
DOUT1
27 V
1 : 1.5 : 0.4
30 PH
DF
VIN
VOUT1 = 24 V
IOUT1 = 0.1 A
DCLAMP
22 V
RUV1
147 k:
10 F
DFLY1
130 k:
IOUT2 = 0.3 A
COUT2
47 F
FB
RSET
SS/BIAS
RTC
RSET
301 k:
12.1 k:
DOUT2
5.6 V
TC
Figure 45. Schematic for Design 3 With VIN(nom) = 24 V, VOUT1 = 24 V, VOUT2 = 5 V
8.2.3.1 Design Requirements
The required input, output, and performance parameters for this application example are shown in Table 5.
Table 5. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady state)
8.5 V to 42 V
Output 1 voltage and current
24 V, 0.1 A
Output 2 voltage and current
5 V, 0.3 A
Input UVLO thresholds
8 V on, 7 V off
Output voltage regulation
±2%
The target full-load efficiency of this LM25180 design is 88% based on a nominal input voltage of 24 V and
isolated output voltages of 24 V and 5 V. The selected flyback converter components are cited in Table 6,
including multi-winding flyback transformer, input and output capacitors, rectifying diodes, and converter IC.
28
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Table 6. List of Components for Design 3
REF DES
QTY
CIN, COUT1 2
SPECIFICATION
VENDOR
PART NUMBER
10 µF, 50 V, X7R, 1210, ceramic
Taiyo Yuden
UMK325AB7106MM-T
10 µF, 50 V, X7S, 1210, ceramic
TDK
C3225X7R1H106M
COUT2
1
47 µF, 10 V, X7R, 1210, ceramic
Murata
GRM32ER71A476ME15L
DFLY1
1
Switching diode, fast recovery, 200 V, 1 A, SOD-123
DFLU1200
Diodes Inc.
DFLY2
1
Schottky diode, 40 V, 1 A, SOD-123
B140HW
Diodes Inc.
DCLAMP
1
Zener, 22 V, 1 W, PowerDI-123
DFLZ22-7
Diodes Inc.
DF
1
Switching diode, 75 V, 0.25 A, SOD-323
CMDD4448
Central Semi
DOUT1
1
Zener, 27 V, 2%, SOD-523
BZX585-B27
Nexperia
DOUT2
1
Zener, 5.6 V, 2%, SOD-523
BZX585-B5V6
Nexperia
RFB
1
130 kΩ, 1%, 0402
Std
Std
RSET
1
12.1 kΩ, 1%, 0402
Std
Std
RTC
1
301 kΩ, 1%, 0402
Std
Std
RUV1
1
147 kΩ, 1%, 0603
Std
Std
RUV2
1
34 kΩ, 1%, 0402
Std
Std
30 µH, 2 A, turns ratio 1 : 1.5 : 0.4, 9 × 10 mm, SMT
Coilcraft
YA8864-BLD
Coilcraft
YA8916-BLD
Würth Electronik
750317595
Texas Instruments
LM25180NGUR
T1
1
U1
30 µH, 2 A, turns ratio 1 : 1 : 0.55, 9 × 10 mm, SMT
1
LM25180 PSR flyback converter, VSON-8
8.2.3.2 Detailed Design Procedure
Components are selected based on the converter specifications using the LM25180 quick-start calculator. The
design procedure is similar to that outlined for Designs 1 and 2 previously.
8.2.3.2.1 Flyback Transformer – T1
The 24-V output is DC stacked on top of the 5-V output as they share a common return connection. This enables
lower secondary-to-secondary leakage inductance for better cross regulation and also reduced rectifier diode
reverse voltage stress. Choose a primary-secondary turns ratio for the effective 19-V secondary based on an
approximate 60% max duty cycle at minimum input voltage using Equation 38.
NPS
VIN(min)
DMAX
˜
1 DMAX VOUT VD
0.6
8.5 V
˜
1 0.6 19 V + 0.3 V
0.66
(38)
Set the turns ratio of the transformer secondary windings using Equation 39. The transformer turns ratio for both
outputs is thus specified as 1 : 1.5 : 0.4.
NS2
NS1
VOUT2
VOUT1
VD2
VD1
5 V 0.3 V
19 V 0.3 V
0.275
(39)
Select a magnetizing inductance based on the minimum off-time constraint using Equation 40. Choose a value of
30 µH with a saturation current of minimum 2 A for this application.
LMAG t
VOUT1
VD1 ˜ NPS1 ˜ tOFF-MIN
19 V + 0.35 V ˜ 0.66 ˜ 450ns
IPRI-PK(FFM)
0.3 A
19.2 +
(40)
8.2.3.2.2 Feedback Resistor – RFB
Install a 130-kΩ resistor from SW to FB based on the secondary winding voltage (the sum of the 5-V output
voltage and the Schottky diode forward voltage drop) reflected by the relevant transformer turns ratio, which in
this design is 1 : 0.4 or 2.5 : 1.
RFB
VOUT
VD ˜ NPS
0.1 mA
5 V 0.25 V ˜ 2.5
0.1 mA
130 k:
(41)
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8.2.3.2.3 UVLO Resistors – RUV1, RUV2
Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds of 8 V and 7 V, respectively, select
the upper and lower UVLO resistors using the following expressions:
VIN(on) ˜
RUV1
RUV2
RUV1 ˜
VUV-FALLING
VUV-RISING
IUV-HYST
VIN(off)
VUV-RISING
VIN(on) VUV-RISING
8 V˜
1.45 V
1.5 V
5 $
147 k: ˜
7V
147k:
(42)
1.5 V
8 V 1.5 V
34 k:
(43)
8.2.3.3 Application Curves
100
95
90
Efficiency (%)
VIN 10V/DIV
85
VOUT1 10V/DIV
80
75
IOUT2 100mA/DIV
70
65
VIN = 24V
VIN = 42V
VOUT2 5V/DIV
60
0
20
40
60
80
Total Output Power (% Full Load)
100
2 ms/DIV
VIN ramped to 24 V
Figure 46. Efficiency
240-Ω and 20-Ω Loads
Figure 47. Start-Up Characteristic
EN 2V/DIV
VOUT1 10V/DIV
IOUT1 100mA/DIV
VOUT1 10V/DIV
IOUT2 100mA/DIV
IOUT2 100mA/DIV
VOUT2 5V/DIV
VOUT2 5V/DIV
2 ms/DIV
VIN = 24 V
240-Ω and 20-Ω Loads
400 Ps/DIV
VIN = 24 V
Figure 48. ENABLE ON Characteristic
30
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240-Ω and 20-Ω Loads
Figure 49. Recovery From Short Circuit
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VDFLY1 50V/DIV
SW 20V/DIV
VDFLY2 10V/DIV
1 Ps/DIV
VIN = 24 V
1 Ps/DIV
VIN = 24 V
Figure 50. SW Node Voltage, Full Load
Figure 51. Flyback Diode Voltages, Full Load
IOUT2 50mA/DIV
IOUT1 20mA/DIV
IOUT1 50mA/DIV
IOUT2 100mA/DIV
VOUT1 200mV/DIV
VOUT1 200mV/DIV
VOUT2 100mV/DIV
VIN = 24 V
VOUT2 100mV/DIV
400 Ps/DIV
IOUT2 = 150 mA
Figure 52. Output 1 Load Transient, 50 mA to 100 mA
VIN = 24 V
400 Ps/DIV
IOUT1 = 50 mA
Figure 53. Output 2 Load Transient, 100 mA to 200 mA
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9 Power Supply Recommendations
The LM25180 flyback converter is designed to operate from a wide input voltage range from 4.5 V to 42 V. The
characteristics of the input supply must be compatible with the Specifications. In addition, the input supply must
be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input
current with Equation 44.
VOUT ˜ IOUT
VIN ˜ K
IIN
where
•
η is the efficiency
(44)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special
care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may
have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at
VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip
during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false
UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the
input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients. A typical ESR of 0.25 Ω provides enough damping
for most input circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for
DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.
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10 Layout
The performance of any switching converter depends as much upon PCB layout as it does the component
selection. The following guidelines are provided to assist with designing a PCB with the best power conversion
performance, thermal performance, and minimized generation of unwanted EMI. Figure 54 and Figure 55 provide
layout examples for single-output and dual-output designs, respectively.
10.1 Layout Guidelines
PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate
noise and EMI or degrade the power supply's performance.
1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place CIN
as close as possible to the LM25180 VIN and GND pins. Ground return paths for the input capacitor(s) must
consist of localized top-side planes that connect to the GND pin and exposed PAD.
2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
e-field or capacitive coupling.
4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding
terminals of the transformer.
5. Minimize the loop area formed by the flyback rectifying diode, output capacitor and the secondary winding
terminals of the transformer.
6. Connect adequate copper at the cathode of the flyback diode to prevent overheating during overload or high
ambient temperature conditions.
7. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
8. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
9. Have a single-point ground connection to the plane. Route the return connections for the reference resistor,
soft-start, and enable components directly to the GND pin. This prevents any switched or load currents from
flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation
or erratic output voltage ripple behavior.
10. Make VIN+, VOUT+ and ground bus connections short and wide. This reduces any voltage drops on the input
or output paths of the converter and maximizes efficiency.
11. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin.
12. Locate components RSET, RTC and CSS as close as possible to their respective pins. Route with minimal
trace lengths.
13. Place a capacitor between input and output return connections to route common-mode noise currents
directly back to their source.
14. Provide adequate heatsinking for the LM25180 to keep the junction temperature below 150°C. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper
layers, connect these thermal vias to inner-layer ground planes. The connection to VOUT+ provides
heatsinking for the flyback diode.
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10.2 Layout Examples
Figure 54. LM25180 Single-Output PCB Layout
Figure 55. LM25180 Dual-Output PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For development support, see the following:
• LM25180 Quick-start Calculator
• LM25180 Simulation Models
• For TI's reference design library, visit TIDesigns
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
• To view a related device of this product, see the LM5180
11.1.3 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25180 device with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• LM5180EVM-S05 EVM User's Guide (SNVU592)
• LM5180EVM-DUAL EVM User's Guide (SNVU609)
• Under the Hood of Flyback SMPS Designs (SLUP261)
• Flyback Transformer Design Considerations for Efficiency and EMI (SLUP338)
• TI Designs:
– Isolated IGBT Gate-Drive Power Supply Reference Design With Integrated Switch PSR Flyback Controller
– Compact, Efficient, 24-V Input Auxiliary Power Supply Reference Design for Servo Drives
– Reference Design for Power-Isolated Ultra-Compact Analog Output Module
– HEV/EV Traction Inverter Power Stage with 3 Types of IGBT/SiC Bias-Supply Solutions Reference Design
– 4.5-V to 65-V Input, Compact Bias Supply With Power Stage Reference Design for IGBT/SiC Gate Drivers
• TI Blogs:
– Flyback Converters: Two Outputs are Better Than One
– Common Challenges When Choosing the Auxiliary Power Supply for Your Server PSU
– Maximizing PoE PD Efficiency on a Budget
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM25180
35
LM25180
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
www.ti.com
Documentation Support (continued)
•
•
•
•
•
White Papers:
– Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications
(SLYY104)
– An Overview of Conducted EMI Specifications for Power Supplies (SLYY136)
– An Overview of Radiated EMI Specifications for Power Supplies (SLYY142)
AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
Automotive Cranking Simulator User's Guide (SLVU984)
Using New Thermal Metrics (SBVA025)
Semiconductor and IC Package Thermal Metrics (SPRA953)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, go to the device product folder on ti.com. In the upper right
corner, click on Alert me to register for a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages have mechanical, packaging, and orderable information. This information is the most current
data available for the designated devices. This data is subject to change without notice and revision of this
document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM25180
LM25180
www.ti.com
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
PACKAGE OUTLINE
NGU0008C
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.1 MIN
(0.05)
SECTION A-A
A-A 30.000
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.98 0.05
(0.2) TYP
4
5
A
2X
2.4
A
SYMM
9
3 0.05
8
1
6X 0.8
PIN 1 ID
8X
SYMM
8X
0.35
0.25
0.1
0.05
0.5
0.3
C A B
C
4224001/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM25180
37
LM25180
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
www.ti.com
EXAMPLE BOARD LAYOUT
NGU0008C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.98)
8X (0.6)
SYMM
1
8
8X (0.3)
SYMM
9
(3)
(1.25)
6X (0.8)
4
(R0.05) TYP
5
( 0.2) VIA
TYP
(0.74)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224001/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
38
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM25180
LM25180
www.ti.com
SNVSB79A – NOVEMBER 2018 – REVISED JULY 2019
EXAMPLE STENCIL DESIGN
NGU0008C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.755)
9
SYMM
(1.31)
6X (0.8)
5
4
(R0.05) TYP
(1.75)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4224001/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: LM25180
39
PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM25180NGUR
Package Type Package Pins Package
Drawing
Qty
ACTIVE
WSON
NGU
8
4500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 150
LM25180
NGU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM25180 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
• Automotive: LM25180-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM25180NGUR
Package Package Pins
Type Drawing
WSON
NGU
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
4500
330.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM25180NGUR
WSON
NGU
8
4500
370.0
355.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
NGU0008B
SDC08B (Rev A)
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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