Texas Instruments | TLV702-Q1 300-mA, Low-IQ, Low-Dropout Regulator (Rev. D) | Datasheet | Texas Instruments TLV702-Q1 300-mA, Low-IQ, Low-Dropout Regulator (Rev. D) Datasheet

Texas Instruments TLV702-Q1 300-mA, Low-IQ, Low-Dropout Regulator (Rev. D) Datasheet
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TLV702-Q1
SLVSC35D – AUGUST 2013 – REVISED JULY 2019
TLV702-Q1 300-mA, Low-IQ, Low-Dropout Regulator
1 Features
3 Description
•
•
The TLV702-Q1 series of low-dropout (LDO) linear
regulators are low quiescent current devices with
excellent line and load transient performance. These
LDOs are designed for power-sensitive applications.
1
•
•
•
•
•
•
•
•
(1)
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Very Low Dropout:
– 37 mV at IOUT = 50 mA, VOUT = 2.8 V
– 75 mV at IOUT = 100 mA, VOUT = 2.8 V
– 220 mV at IOUT = 300 mA, VOUT = 2.8 V
2% Accuracy Over Temperature
Low IQ: 35 µA
Fixed-Output Voltage Combinations Possible from
1.2 V to 4.8 V
High PSRR: 68 dB at 1 kHz
Stable with Effective Capacitance of 0.1 µF(1)
Thermal Shutdown and Overcurrent Protection
Packages: 5-Pin SOT (DBV and DDC) and
1.5-mm × 1.5-mm, 6-Pin WSON
A precision bandgap and an error amplifier provide
overall 2% accuracy. Low output noise, very high
power-supply rejection ratio (PSRR), and low-dropout
voltage make this series of devices ideal for a wide
selection of battery-operated equipment. All device
versions have thermal shutdown and current limit
protections for safety.
Furthermore, these devices are stable with an
effective output capacitance of only 0.1 µF. This
feature enables the use of cost-effective capacitors
that have higher bias voltages and temperature
derating. The devices regulate to specified accuracy
with no output load.
The TLV702-Q1 series of LDO linear regulators is
available in SOT and WSON packages.
Device Information(1)
PART NUMBER
See the Input and Output Capacitor Requirements in the
Application Information section.
TLV702-Q1
BODY SIZE (NOM)
2.90 mm × 1.60 mm
WSON (6)
1.50 mm × 1.50 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
SOT (5)
Automotive Camera Modules
Image Sensor Power
Microprocessor Rails
Automotive Infotainment Head Units
Automotive Body Electronics
Typical Application
VIN
IN
VOUT
OUT
COUT
CIN
1 F
Ceramic
TLV702-Q1
On
Off
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV702-Q1
SLVSC35D – AUGUST 2013 – REVISED JULY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
9
Power Supply Recommendations...................... 15
9.1 Power Dissipation ................................................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2018) to Revision D
Page
•
Changed OUT pin number from 5 to 3 in DSE column of Pin Functions table ..................................................................... 4
•
Added footnote to maximum EN voltage specification .......................................................................................................... 5
•
Added parameter names to Recommended Operating Conditions table............................................................................... 5
Changes from Revision B (June 2015) to Revision C
Page
•
Added DBV package to document ......................................................................................................................................... 1
•
Changed Packages Features bullet to include DBV package ............................................................................................... 1
•
Added DBV package to Pin Configuration and Functions section ......................................................................................... 4
•
Added DBV column to Thermal Information table .................................................................................................................. 5
•
Changed title of Layout Example for the DDC and DBV Packages figure to include DBV package ................................... 16
Changes from Revision A (August 2013) to Revision B
Page
•
Added DSE (6-Pin WSON) package to data sheet ................................................................................................................ 1
•
Added Device Information, ESD Ratings, and Recommended Operating Conditions tables, and Detailed
Description, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation
Support, and Mechanical, Packaging, and Orderable Information sections to data sheet .................................................... 1
•
Deleted all references to P version of device throughout data sheet..................................................................................... 1
•
Added "Over Temperature" to 2% accuracy Features bullet ................................................................................................ 1
•
Changed DDC package name from TSOT23 to SOT throughout data sheet........................................................................ 1
•
Changed Applications bullets ................................................................................................................................................. 1
•
Changed Description section text........................................................................................................................................... 1
•
Changed ceramic capacitor units on Typical Application circuit from mF to µF (typo) ......................................................... 1
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement .................... 5
•
Added TJ to TA condition in Electrical Characteristics condition statement............................................................................ 6
2
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SLVSC35D – AUGUST 2013 – REVISED JULY 2019
Changed TA to TJ for typical values in Electrcial Characteristics condition statement ........................................................... 6
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5 Pin Configuration and Functions
DDC and DBV Package
5-pin SOT
Top View
IN
GND
EN
5
1
DSE Package
6-Pin WSON
Top View
OUT
2
3
4
IN 1
6
EN
GND 2
5
N/C
OUT 3
4
N/C
NC
Pin Functions
PIN
DDC, DBV
(SOT)
DSE
(WSON)
I/O
DESCRIPTION
IN
1
1
I
Input pin. A small, 1-μF ceramic capacitor is recommended from this pin to ground to
assure stability and good transient performance. See Input and Output Capacitor
Requirements in the Application Information section for more details.
GND
2
2
—
EN
3
6
I
NC
4
4, 5
—
No connection. Tie this pin to ground to improve thermal dissipation.
OUT
5
3
O
Regulated output voltage pin. A small, 1-μF ceramic capacitor is needed from this pin
to ground for stability. See Input and Output Capacitor Requirements in the
Application Information section for more details.
NAME
4
Ground pin
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts
the regulator into shutdown mode and reduces operating current to 1 μA, nominal.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
6
V
EN
–0.3
(3)
V
OUT
–0.3
6
V
IN
Voltage
(2)
Current (source)
OUT
Internally limited
Output short-circuit duration
Temperature
(1)
(2)
(3)
6
A
Indefinite
Operating virtual junction, TJ
–55
150
°C
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
±2000
Charged-device model (CDM), per AEC Q100-011
UNIT
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Output voltage
IOUT
Output current
TA
Ambient temperature
TJ
Operating virtual junction temperature
–40
NOM
MAX
UNIT
2
5.5
V
1.2
4.8
V
0
300
mA
–40
125
°C
125
°C
6.4 Thermal Information
TLV702-Q1
THERMAL METRIC
(1)
DDC (SOT)
DBV (SOT)
DSE (WSON)
5 PINS
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
262.8
249.2
321.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.2
136.4
207.9
°C/W
RθJB
Junction-to-board thermal resistance
81.6
85.9
281.5
°C/W
ψJT
Junction-to-top characterization parameter
1.1
19.5
42.4
°C/W
ψJB
Junction-to-board characterization parameter
80.9
85.3
284.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
142.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
At VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and TJ, TA = –40°C to
+125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
DC output accuracy
ΔVO(ΔVI)
Line regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V,
IOUT = 10 mA
ΔVO(ΔIO)
Load regulation
0 mA ≤ IOUT ≤ 300 mA
VDO
Dropout voltage (1)
VIN = 0.98 × VOUT(nom), IOUT = 300 mA
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
IGND
Ground pin current
ISHDN
Ground pin current (shutdown)
MIN
TYP
MAX
–2%
0.5%
2%
1
5
mV
320
IOUT = 0 mA
1
15
mV
260
375
mV
500
860
mA
35
55
μA
IOUT = 300 mA, VIN = VOUT + 0.5 V
370
VEN ≤ 0.4 V, VIN = 2 V
400
VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V
UNIT
1
μA
nA
2.5
μA
PSRR
Power-supply rejection ratio
VIN = 2.3 V, VOUT = 1.8 V,
IOUT = 10 mA, f = 1 kHz
Vn
Output noise voltage
BW = 100 Hz to 100 kHz,
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
tSTR
Start-up time (2)
COUT = 1 μF, IOUT = 300 mA
VEN(high)
Enable pin high (enabled)
0.9
VIN
VEN(low)
Enable pin low (disabled)
0
0.4
IEN
Enable pin current
VIN = VEN = 5.5 V
UVLO
Undervoltage lockout
VIN rising
1.9
V
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
145
°C
Tsd
(1)
(2)
6
Thermal shutdown temperature
68
dB
48
μVRMS
100
μs
0.04
V
V
μA
VDO is measured for devices with VOUT(nom) ≥ 2.35 V.
Start-up time = time from EN assertion to 0.98 × VOUT(nom).
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6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1.90
1.90
VOUT = 1.8 V
IOUT = 10 mA
1.88
1.86
1.84
1.84
1.82
1.82
VOUT (V)
VOUT (V)
1.86
1.80
1.78
1.76
1.72
1.80
1.78
1.76
+125°C
+85°C
+25°C
-40°C
1.74
VOUT = 1.8 V
IOUT = 300 mA
1.88
+125°C
+85°C
+25°C
-40°C
1.74
1.72
1.70
1.70
2.1
2.6
3.1
3.6
4.1
VIN (V)
4.6
5.1
2.3
5.6
2.7
3.1
Figure 1. Line Regulation
3.5
3.9
VIN (V)
4.3
4.7
5.5
5.1
Figure 2. Line Regulation
350
1.90
IOUT = 300 mA
VOUT = 1.8 V
1.88
300
1.86
250
VDO (mV)
VOUT (V)
1.84
1.82
1.80
1.78
1.76
1.72
50
100
150
200
250
+125°C
+85°C
+25°C
–40°C
50
0
2.25
1.70
0
150
100
+125°C
+85°C
+25°C
-40°C
1.74
200
300
2.75
3.25
IOUT (mA)
4.75
4.25
Figure 4. Dropout Voltage vs Input Voltage
Figure 3. Load Regulation
300
1.90
VOUT = 4.8 V
VOUT = 1.8 V
1.88
250
1.86
1.84
VOUT (V)
200
VDO (mV)
3.75
VIN (V)
150
100
+125°C
+85°C
+25°C
-40°C
50
0
1.82
1.80
1.78
1.76
10mA
150mA
200mA
1.74
1.72
1.70
0
50
100
150
200
250
300
-40 -25 -10
IOUT (mA)
Figure 5. Dropout Voltage vs Output Current
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 6. Output Voltage vs Temperature
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
450
50
VOUT = 1.8 V
45
40
350
35
300
30
IGND (mA)
IGND (mA)
VOUT = 1.8 V
400
25
20
15
5
200
150
+125°C
+85°C
+25°C
-40°C
10
250
+125°C
+85°C
+25°C
-40°C
100
50
0
0
2.1
2.6
3.1
3.6
4.1
VIN (V)
4.6
5.1
0
5.6
Figure 7. Ground Pin Current vs Input Voltage
50
200
150
IOUT (mA)
250
300
Figure 8. Ground Pin Current vs Load
2.5
VOUT = 1.8 V
45
100
50
VOUT = 1.8 V
2
40
ISHDN (mA)
IGND (mA)
35
30
25
20
1.5
1
15
+125°C
+85°C
+25°C
-40°C
0.5
10
5
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
2.1
110 125
Figure 9. Ground Pin Current vs Temperature
2.6
3.1
3.6
4.1
VIN (V)
5.6
Figure 10. Shutdown Current vs Input Voltage
VOUT = 1.8 V
IOUT = 10 mA
90
600
80
500
IOUT = 150 mA
70
PSRR (dB)
ILIM (mA)
5.1
100
700
400
300
200
+125°C
+85°C
+25°C
-40°C
100
0
2.3
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
5.5
60
50
40
30
20
10
VIN - VOUT = 0.5 V
0
10
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 11. Current Limit vs Input Voltage
8
4.6
Figure 12. Power-Supply Ripple Rejection vs Frequency
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
60
PSRR (dB)
VOUT = 1.8 V
1 kHz
70
Output Spectral Noise Density (mV/ÖHz)
80
10 kHz
50
100 kHz
40
30
20
10
0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
10
VOUT = 1.8 V
IOUT = 10 mA
CIN = COUT = 1 mF
1
0.1
0.01
0.001
10
2.8
100
1k
Figure 13. Power-Supply Ripple Rejection vs Input Voltage
10 M
0 mA
VOUT
20 mA/div
IOUT
10 mA
0 mA
IOUT
VOUT
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 15. Load Transient Response
Figure 16. Load Transient Response
tR = tF = 1 ms
tR = tF = 1 ms
50 mA
0 mA
200 mA/div
300 mA
IOUT
100 mV/div
50 mA/div
1M
tR = tF = 1 ms
200 mA
VOUT = 1.8 V
20 mV/div
100 k
Figure 14. Output Spectral Noise Density vs Frequency
5 mV/div
50 mV/div
100 mA/div
tR = tF = 1 ms
10 k
Frequency (Hz)
Input Voltage (V)
VOUT
IOUT
0 mA
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 17. Load Transient Response
Figure 18. Load Transient Response
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1 V/div
2.9 V
VIN
Slew Rate = 1 V/ms
2.9 V
2.3 V
VIN
VOUT
VOUT = 1.8 V
IOUT = 300 mA
5 mV/div
2.3 V
5 mV/div
1 V/div
Slew Rate = 1 V/ms
VOUT
VOUT = 1.8 V
IOUT = 1 mA
1 ms/div
1 ms/div
Figure 20. Line Transient Response
Slew Rate = 1 V/ms
VOUT = 1.8 V
IOUT = 300 mA
5.5 V
VIN
10 mV/div
2.1 V
VOUT = 1.8 V
IOUT = 1 mA
VIN
1 V/div
1 V/div
Figure 19. Line Transient Response
VOUT
VOUT
1 ms/div
200 ms/div
Figure 21. Line Transient Response
10
Figure 22. VIN Ramp Up, Ramp Down Response
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7 Detailed Description
7.1 Overview
The TLV702-Q1 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent
line and load transient performance. These LDOs are designed for power-sensitive applications. A precision
bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection
ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld
equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO)
protections.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
LOGIC
TLV702-Q1 Series
GND
Figure 23. TLV702-Q1 Block Diagram
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV702-Q1 internal current limit protection helps to protect the regulator during fault conditions. During
current limit operation, the output sources a fixed amount of current that is largely independent of the output
voltage. In such a case, the output voltage is not regulated, and is VOUT = ICL × RLOAD. The PMOS pass transistor
dissipates (VIN – VOUT) × ICL until thermal shutdown is triggered and the device turns off. As the device cools, the
device is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles
between current limit operation and thermal shutdown. See Thermal Consideration for more details.
The PMOS pass element in the TLV702-Q1 has a built-in body diode that conducts current when the voltage at
the OUT pin exceeds the voltage at IN. This current is not limited; if extended reverse-voltage operation is
anticipated, externally limit the output current to 5% of the rated IOUT specification.
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Feature Description (continued)
7.3.2 Shutdown
The enable pin (EN) is active high. The device is enabled when voltage at EN pin exceeds 0.9 V. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, connect the EN
pin to the IN pin.
7.3.3 Dropout Voltage
The TLV702-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear (triode) region of operation. The input-to-output
resistance is equal to the drain-source on-state resistance (RDS(on)) of the PMOS pass element. VDO scales
approximately with output current because the PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 13.
7.3.4 Undervoltage Lockout
The TLV702-Q1 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The output current is less than the current limit.
The input voltage is greater than the UVLO voltage.
7.4.2 Dropout Operation
If the input voltage is less than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of
the LDO. Line or load transients in dropout may result in large output voltage deviations.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
12
PARAMETER
VIN
IOUT
Normal mode
VIN > VOUT(nom) + VDO
IOUT < ICL
Dropout mode
VIN < VOUT(nom) + VDO
IOUT < ICL
Current limit
VIN > UVLO
IOUT > ICL
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TLV702-Q1
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV702-Q1 belongs to a new family of next-generation value LDO regulators. These devices consume low
quiescent current and deliver excellent line and load transient performance. These characteristics, combined with
low noise and very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for portable
RF applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C
to +125°C.
8.2 Typical Application
VIN
IN
VOUT
OUT
COUT
CIN
1 F
Ceramic
TLV702-Q1
On
Off
EN
GND
Figure 24. Typical Application Circuit
8.2.1 Design Requirements
Table 2 lists the design parameters.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
2.5 V to 3.3 V
Output voltage
1.8 V
Output current
100 mA
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8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
1-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation
in value and equivalent series resistance (ESR) over temperature.
However, the TLV702-Q1 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output.
Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance
under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the
capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance
after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of
lower-cost dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of
smaller footprint capacitors that have higher derating in size- and space-constrained applications.
Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective
capacitance under the specified operating conditions must not be less than 0.1 μF. Maximum ESR should be
less than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary for stability.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,
but increases the duration of the transient response.
8.2.3 Application Curves
50 mA
1 V/div
IOUT
VIN
Slew Rate = 1 V/ms
2.9 V
2.3 V
0 mA
5 mV/div
20 mV/div
50 mA/div
tR = tF = 1 ms
VOUT
VOUT
VOUT = 1.8 V
IOUT = 1 mA
VOUT = 1.8 V
1 ms/div
10 ms/div
Figure 25. Load Transient Response
14
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Figure 26. Line Transient Response
Copyright © 2013–2019, Texas Instruments Incorporated
Product Folder Links: TLV702-Q1
TLV702-Q1
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SLVSC35D – AUGUST 2013 – REVISED JULY 2019
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV702-Q1. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up or
load transient events.
9.1 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air.
Refer to Thermal Information for thermal performance on the TLV702-Q1 evaluation module (EVM). The EVM is
a two-layer board with two ounces of copper per side.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1.
PD = (VIN - VOUT) ´ IOUT
(1)
10 Layout
10.1 Layout Guidelines
Place the input and output capacitors as close to the device pins as possible. To improve ac performance such
as PSRR, output noise, and transient response, design the board with separate ground planes for VIN and VOUT,
with the ground plane connected only at the GND pin of the device. In addition, connect the ground connection
for the output capacitor directly to the GND pin of the device. High-ESR capacitors may degrade PSRR
performance.
10.1.1 Thermal Consideration
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C maximum.
To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry of the TLV702-Q1 is designed to protect against overload conditions but is not
intended to replace proper heatsinking. Continuously running the TLV702-Q1 into thermal shutdown degrades
device reliability.
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Layout Guidelines (continued)
10.1.2 Package Mounting
Solder pad footprint recommendations for the TLV702-Q1 are available from the TI website at www.ti.com. The
recommended layout examples for the DDC and DSE packages are shown in Figure 27 and Figure 28,
respectively.
10.2 Layout Examples
VOUT
VIN
OUT
IN
CIN
COUT
GND
NC
EN
GND PLANE
Represents via used for
application specific connections
Figure 27. Layout Example for the DDC and DBV Packages
VIN
CIN
IN
EN
GND
NC
OUT
NC
VOUT
GND PLANE
COUT
Represents via used for
application specific connections
Figure 28. Layout Example for the DSE Package
16
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TLV702-Q1
www.ti.com
SLVSC35D – AUGUST 2013 – REVISED JULY 2019
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV702 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 3. Ordering Information (1)
PRODUCT
TLV702xx yyyz
(1)
(2)
VOUT
(2)
XX is nominal output voltage (for example, 28 = 2.8 V).
YYY is the package designator.
Z is tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Texas Instruments, Using the TLV700xxEVM-503 user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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Product Folder Links: TLV702-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV702125QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1M57
TLV70212QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B5H
TLV70212QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H9
TLV70213QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H8
TLV70215QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B6H
TLV70215QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HB
TLV70218QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B7H
TLV70218QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HC
TLV70225QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
G7
TLV70227QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B8H
TLV70227QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H7
TLV70228QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1B9H
TLV70228QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SJV
TLV70228QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HD
TLV70229QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1BAH
TLV70229QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H1
TLV70230QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1MQ7
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Jan-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV70230QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HE
TLV70231QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HF
TLV70232QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HG
TLV70233QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1BBH
TLV70233QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H2
TLV70236QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
H3
TLV70245QDSERQ1
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
HH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV702-Q1 :
• Catalog: TLV702
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV702125QDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
TLV70212QDBVRQ1
SOT-23
DBV
5
3000
180.0
TLV70212QDSERQ1
WSON
DSE
6
3000
179.0
TLV70213QDSERQ1
WSON
DSE
6
3000
TLV70215QDBVRQ1
SOT-23
DBV
5
TLV70215QDSERQ1
WSON
DSE
TLV70218QDBVRQ1
SOT-23
DBV
TLV70218QDSERQ1
WSON
TLV70225QDSERQ1
TLV70227QDBVRQ1
TLV70227QDSERQ1
WSON
TLV70228QDBVRQ1
TLV70228QDDCRQ1
3.23
3.17
1.37
4.0
8.0
Q3
8.4
3.23
3.17
1.37
4.0
8.0
Q3
8.4
1.8
1.8
1.0
4.0
8.0
Q2
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SOT23-THIN
DDC
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TLV70228QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70229QDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
TLV70229QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70230QDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
25-May-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV70230QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70231QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70232QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70233QDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
TLV70233QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70236QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TLV70245QDSERQ1
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV702125QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70212QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70212QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70213QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70215QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70215QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70218QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70218QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70225QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70227QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-May-2019
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV70227QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70228QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70228QDDCRQ1
SOT-23-THIN
DDC
5
3000
195.0
200.0
45.0
TLV70228QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70229QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70229QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70230QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70230QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70231QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70232QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70233QDBVRQ1
SOT-23
DBV
5
3000
183.0
183.0
20.0
TLV70233QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70236QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
TLV70245QDSERQ1
WSON
DSE
6
3000
203.0
203.0
35.0
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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