Texas Instruments | LM74202-Q1 40-V, 2.2-A Integrated Ideal Diode with Overvoltage and Overcurrent Protection | Datasheet | Texas Instruments LM74202-Q1 40-V, 2.2-A Integrated Ideal Diode with Overvoltage and Overcurrent Protection Datasheet

Texas Instruments LM74202-Q1 40-V, 2.2-A Integrated Ideal Diode with Overvoltage and Overcurrent Protection Datasheet
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LM74202-Q1
SLVSFD0 – SEPTEMBER 2019
LM74202-Q1 40-V, 2.2-A Integrated Ideal Diode with Overvoltage and Overcurrent
Protection
1 Features
3 Description
•
The LM74202-Q1 device is a compact, feature-rich
40-V integrated ideal diode with a full suite of
protection features. The wide supply input range
allows control of 12-V automotive battery driven
applications. The device withstands and protects the
loads from positive and negative supply voltages up
to ±40 V. Load, source and device protection are
provided with many programmable features including
overcurrent, inrush current control, overvoltage and
undervoltage thresholds. The internal robust
protection control blocks along with the 40-V rating of
the device simplifies the system design for ISO
standard pulse tesing.
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C ≤ TA ≤ +125°C
– AEC-Q100-012 short circuit reliability Grade A
– HBM ESD classification level 2
– CDM ESD classification level C6
4.2-V to 40-V operating voltage, 42-V maximum
Integrated reverse input polarity protection down
to –40 V
Integrated back-to-back MOSFETs with 150 mΩ
total RON
Transient immunity up-to 55 V
0.1-A to 2.23-A adjustable current limit
(±5% accuracy at 1 A)
Load protection during ISO7637 and ISO16750-2
testing
Short to battery and short to ground protection
Reverse current blocking for protection from
output short to battery
IMON current indicator output (±8.5% accuracy)
Low quiescent current (285 µA in operating, 16 µA
in shutdown)
Adjustable UVLO, OVP cut off, inrush current
control
Selectable current-limiting fault response options
(auto-retry, latch off, CB modes)
Available in easy to use 16-Pin HTSSOP package
1
•
•
•
•
•
•
•
•
•
•
•
•
•
A shutdown pin provides external control for enabling
and disabling the internal FETs and places the device
in a low current shutdown mode. For system status
monitoring and downstream load control, the device
provides fault output and precise current monitor
output. The MODE pin allows flexibility to configure
the device between the three current-limiting fault
responses (circuit breaker, latch off, and auto-retry
modes). The device monitors V(IN) and V(OUT) to
provide reverse current blocking when V(IN) <
(V(OUT)-10mV). This function protects system bus
from overvoltages during output short to battery faults
and also helps in voltage holdup requirements during
power fail and brownout conditions.
The device is available in a 5 mm × 4.4 mm 16-pin
HTSSOP and is fully specified over a –40°C to
+125°C temperature range.
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
LM74202-Q1
Front camera, Rear camera
Drive assist ECU
Telematics control unit
Cellular module asset tracking
CIN
ISO16750-2 Load Dump Pulse 5b Performance at
12 V
+
±
UVLO
OVP
VIN
TVS
VOUT
OUT
COUT
150 PŸ
R1
LM74202-Q1
RFLTb
FLT
SHDN
Health Monitor
ON/OFF Control
dVdT
R2
RTN
CdVdT
Load Monitor
IMON
MODE
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
IN
PACKAGE
HTSSOP (16)
ILIM
GND
RILIM
RIMON
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM74202-Q1
SLVSFD0 – SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
10 Power Supply Recommendations ..................... 29
10.1 Transient Protection .............................................. 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
2
DATE
REVISION
NOTES
September 2019
*
Initial release
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5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With Exposed Thermal Pad
Top View
IN
1
16
OUT
IN
2
15
OUT
UVLO
3
14
FLT
NC
4
13
NC
OVP
5
12
dVdT
MODE
6
11
ILIM
7
10
IMON
9
GND
SHDN
RTN
3RZHU3$'Œ
Integrated Circuit
Package
8
Pin Functions
PIN
NO.
NAME
1, 2
IN
3
4, 13
UVLO
NC
TYPE
DESCRIPTION
P
Input supply voltage. See IN, OUT, RTN and GND Pins section.
I
Input for setting the programmable Undervoltage Lockout threshold. An undervoltage event
turns off the internal FET and asserts FLT to indicate power failure. If the Undervoltage
Lockout function is not needed, the UVLO terminal must be connected to the IN terminal.
See Undervoltage Lockout (UVLO) section.
—
No internal connection. These pins can be connected to RTN for enhanced thermal
performance.
5
OVP
I
Input for setting the programmable Overvoltage Protection threshold. An overvoltage event
turns off the internal FET and asserts FLT to indicate the overvoltage fault. See Overvoltage
Protection (OVP) section.
6
MODE
I
Mode selection pin for overload fault response. See the Device Functional Modes section.
7
SHDN
I
Shutdown pin. Pulling SHDN low enters the device into low-power shutdown mode. Cycling
SHDN pin voltage resets the device that has latched off due to a fault condition. See Low
Current Shutdown Control (SHDN) section.
8
RTN
—
Reference for device internal control circuits. If reverse input polarity protection is not
required, this pin can be connected to GND. See IN, OUT, RTN and GND Pins section.
9
GND
—
Connect GND to system ground. See IN, OUT, RTN and GND Pins section.
10
IMON
O
Analog current monitor output. This pin sources a scaled down ratio of current through the
internal FET. A resistor from this pin to RTN converts current to proportional voltage. If pin is
unused, leave pin floating. See Current Monitoring section.
11
ILIM
I/O
A resistor from this pin to RTN sets the overload and short-circuit current limit. See the
Overload and Short Circuit Protection section.
12
dVdT
I/O
A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In and InRush Current Control section.
14
FLT
O
Fault event indicator. Indicator is an open drain output. If indicator is unused, leave indicator
floating. See FAULT Response section.
15,16
OUT
P
Power output of the device. See IN, OUT, RTN and GND Pins section.
—
PowerPAD integrated circuit package must be connected to RTN plane on PCB using
multiple vias for enhanced thermal performance. PowerPAD is not internally connected to
RTN. Do not use the PowerPAD as the only electrical connection to RTN.
PowerPAD
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted) (1)
MIN
MAX
-42
42
IN, IN-OUT (350ms transient), TA = 25°C
-55
55
[IN, OUT, FLT, UVLO, SHDN] to RTN
-0.3
42
[OVP, dVdT, ILIM, IMON, MODE] to RTN
-0.3
5
-42
0.3
IN, IN-OUT
RTN
IFLT, IdVdT, ISHDN
Sink current
IdVdT, IILIM, IIMON
Tstg
(1)
V
10
mA
Internally
limited
Source Current
TJ
UNIT
Internally
limited
Operating junction temperature
-40
150
°C
Transient junction temperature
-65
T(TSD)
°C
Storage Temperature
-65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model
(CDM), per AEC Q100-011
±1000
All pins
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
IN
UVLO, OUT, FLT
Input voltage range
OVP, dVdT, ILIM, IMON, SHDN
ILIM
Resistance
IMON
IN, OUT
External capacitance
dVdT
TJ
Operating junction temperature range
NOM
MAX
-40
40
0
40
0
4
5.36
120
1
0.1
1
V
kΩ
µF
10
-40
UNIT
nF
25
125
°C
6.4 Thermal Information
LM74202-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
38.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.7
°C/W
RθJB
Junction-to-board thermal resistance
18.2
°C/W
ΨJT
Junction-to-top characterization parameter
0.5
°C/W
YJB
Junction-to-board characterization parameter
18
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.89
4
4.14
V
55
275
305
mV
285
390
µA
16
32
µA
50
µA
V
SUPPLY VOLTAGE
V(IN)
Operating input voltage
VPORR
Internal POR Threshold, Rising
4.2
VPORHys
Internal POR Hysteresis
IQON
Supply Current with device enabled
VIN = 12V
Enabled: V(SHDN) = 2 V,
IQOFF
Supply Current with device disabled
VIN = 12V, V(SHDN) = 0 V
IVINR
Reverse Input supply current
V(IN) = -40 V, V(OUT) = 0 V
40
V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(UVLOR)
UVLO Threshold Voltage, Rising
V(UVLOR)
UVLO Threshold Voltage, Falling
I(UVLO)
UVLO Input leakage current
0 V ≤ V(UVLO) ≤ 40 V
1.175
1.19
1.25
1.08
1.1
1.126
V
100
nA
3.4
V
–100
LOW IQ SHUTDOWN (SHDNb) INPUT
V(SHDN)
Output voltage
I(SHDN) = 0.1µA
V(SHUTF)
SHDN Threshold Voltage for Low
IQ Shutdown, Falling
V(SHUTFR)
SHDN Threshold, Rising
I(SHDN)
Input current
2
2.7
0.45
V
0.96
V(SHDN) = 0.4 V
-10
V
µA
OVER VOLTAGE PROTECTION (OVP) INPUT
V(SEL_OVP)
Factory Set OV Clamp Select
Threshold
V(OVPR)
180
200
240
Over-Voltage Threshold Voltage,
Rising
1.175
1.19
1.225
V(OVPF)
Over-Voltage Threshold Voltage,
Falling
1.085
I(OVP)
OVP Input Leakage Current
0V ≤ V(OVP) ≤ 4V
mV
V
1.125
–100
0
100
nA
4
4.7
5.82
µA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT Charging Current
V(dVdT) = 0 V
R(dVdT)
dVdT Discharging Resistance
SHDN = 0 V, with I(dVdT) = 10mA
sinking
GAIN(dVdT)
dVdT to OUT Gain
△V(OUT) /△V(dVdT)
23.75
24.63
R(ILIM) = 120 kΩ, V(IN)-V(OUT)=1V
0.085
0.1
0.115
R(ILIM) = 12 kΩ, V(IN)-V(OUT)=1V
0.95
1
1.05
R(ILIM) = 8 kΩ, V(IN)-V(OUT)=1V
1.425
1.5
1.575
2.11
2.23
2.35
A
0.11
A
28
Ω
25.5
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V(ILIM)
ILIM Bias Voltage
1
I(OL)
R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=1V
Overload Current Limit
I(OL_R-OPEN)
R(ILIM)= OPEN, Open Resistor Current
Limit
0.055
I(OL_R-SHORT)
R(ILIM)= SHORT, Shorted Resistor
Current Limit
0.095
I(CB)
Circuit breaker detection threshold
R(ILIM) = 120 kΩ, MODE = open
I(CB)
Circuit breaker detection threshold
I(SCL)
Short-Circuit Current Limit
V
0.045
0.073
R(ILIM) = 5.36 kΩ, MODE = open
2
2.21
2.4
A
R(ILIM) = 120 kΩ, V(IN)-V(OUT)=5V
0.08
0.1
0.12
A
1.425
1.5
1.575
A
2.11
2.23
2.35
A
R(ILIM) = 8 kΩ, V(IN)-V(OUT)=5V
R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=5V
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Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
I(FASTRIP)
TEST CONDITIONS
MIN
TYP
MAX
1.87 x
I(OL) +
0.015
Fast-trip comparator threshold
UNIT
A
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON)
0.1A ≤ I(OUT) ≤ 2A
Gain Factor I(IMON):I(OUT)
72
78.28
85
130
150
168
150
220
150
265
µA/A
PASS FET OUTPUT (OUT)
0.1A ≤ I(OUT) ≤ 2A,TJ = 25°C
RON
0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 85°C
IN to OUT Total ON Resistance
0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 125°C
Ilkg(OUT)
OUT Leakage Current in Off State
Ilkg(OUT)
OUT Leakage Current in Off State
78
V(IN) = 40 V, V(SHDN)= 0 V, V(OUT) = 0
V, Sourcing
12
V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24
V, Sinking
-11
V(IN) = -40 V, V(SHDN)= 0 V, V(OUT) = 0
V, Sinking
-40
-18
50
mΩ
µA
11
µA
V(REVTH)
V(IN)-V(OUT) Threshold for Reverse
Protection Comparator, Falling
-16.2
-10
-5
mV
V(FWDTH)
V(IN)-V(OUT) Threshold for Reverse
Protection Comparator, Rising
85
96
110
mV
200
nA
FAULT FLAG (FLTb): ACTIVE LOW
R(FLT)
FLT Pull-Down Resistance
V(OVP) = 2 V, I(FLT) = 5mA sinking
I(FLT)
FLT Input Leakage Current
0 V ≤ V(FLT) ≤ 40 V
350
–200
Ω
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD Threshold, rising
157
°C
TSD hysteresis
10.1
°C
MODE
MODE_SEL
Thermal fault mode selection
MODE = 402 kΩ to RTN
Current limiting with latch
MODE = Open
Circuit breaker mode with
auto-retry
MODE = Short to RTN
Current limiting with autoretry
6.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
UVLO INPUT
UVLO_tON(dly)
UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV,
C(dvdt) = Open
80
UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV,
C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
80+14.
5x
C(dvdt)
µs
UVLO_tON(dly)
UVLO_toff(dly)
UVLO↓ (100mV below V(UVLOF)) to FLT ↓
9
µs
UVLO Turn On Delay
UVLO Turn-Off delay
SHUTDOWN INPUT
6
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Timing Requirements (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF,
C(dVdT) = OPEN.
(All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
SHDN_ton(dly)
SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV,
C(dvdt) ≥ 10 nF, [C(dvdt) in nF]
SHDN_ton(dly)
SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt)=
Open
SHDN_toff(dly)
SHDN ↓ (below V(SHUTF) to FLT ↓
OVP Exit delay
tOVP(dly)
OVP ↓(20mV below V(OVPF)) to V(OUT) = 100mV
OVP Disable delay
tOVP(dly)
OVP↑ (20mV above V(OVPR)) to FLT ↓
tFASTTRIP(dly)
I(OUT) = 1.5x I(FASTRIP)
SHUTDOWN Exit delay
SHUTDOWN Entry delay
MIN
NOM
MAX
350+14
.5 x
C(dvdt)
UNIT
µs
355
10
µs
205
µs
2
µs
170
ns
1.29
µs
(V(IN)-V(OUT)) ↓ (10mV overdrive below V(REVTH)) to
FLT ↓
40
µs
(V(IN)-V(OUT)) ↑ (10mV overdrive above V(FWDTH)) to
FLT ↑
60
µs
540
ms
SHDN↑ to V(OUT) = V(IN)
1.6
ms
SHDN↑ to V(OUT) = V(IN), with C(dVdT) = 47nF
10
ms
4
ms
540
ms
OVP INPUT
CURRENT LIMIT
Fast-Trip Comparator
Delay
REVERSE CURRENT BLOCKING COMPARATOR
tREV(dly)
RCB comparator delay
tFWD(dly)
(V(IN)-V(OUT)) ↓ (100mV overdrive below V(REVTH)) to
internal FET OFF
THERMAL SHUTDOWN
Retry Delay in TSD
tretry
OUTPUT RAMP TIME
Output Ramp Time
tdVdT
FAULT FLAG
FLT assertion delay in
circuit breaker mode
tCB(dly)
MODE = OPEN,Delay from I(out)>I(lim) to FLT ↓(and
internal FET turned off)
Retry Delay in circuit
breaker mode
tCBretry(dly)
MODE= OPEN, C(dVdT) = Open. I(out)>I(lim). Delay
from FLT ↓ to V(dVdT) = 50mV (Rising)
tPGOODR
Delay for rising FLT edge
1.8
ms
tPGOODF
Delay for falling FLT edge
900
µs
PGOOD delay time
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6.7 Typical Characteristics
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
4.2
294
POR Threshold Rising (V)
POR Threshold Falling (V)
291
288
285
3.9
IQ(ON) (µA)
POR Threshold (V)
4.05
3.75
282
279
276
273
3.6
270
267
3.45
-60
-30
0
30
60
Temperature (°C)
90
120
150
264
D001
Figure 1. POR Threshold (VPOR) vs Temperature
0
10
15
20
25
Supply Voltage (V)
30
35
40
D002
Figure 2. Supply Current ON (IQON) vs Supply Voltage (VIN)
1.3
20
UVLO Threshold Rising (V)
UVLO Threshold Falling (V)
1.25
UVLO Threshold (V)
18
16
IQ(OFF) (µA)
5
14
12
1.2
1.15
1.1
1.05
10
1
-40
8
0
5
10
15
20
25
Supply Voltage (V)
30
35
120
160
D004
Figure 4. UVLO Thresholds (VUVLOR, VUVLOF) vs Temperature
24.52
1.28
OVP Threshold Rising (V)
OVP Threshold Falling (V)
1.24
24.54
1.2
GaindVdT
OVP Threshold (V)
40
80
Temperature (°C)
D003
Figure 3. Supply Current OFF (IQOFF) vs Supply Voltage
(VIN)
1.16
24.56
24.58
1.12
24.6
1.08
1.04
-40
0
40
80
Temperature (°C)
120
160
24.62
-50
D005
Figure 5. OVP Thresholds (VOVPR, VOVPF) vs Temperature
8
0
40
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-25
0
25
50
Temperature (°C)
75
100
125
D006
Figure 6. GAIN(dVdT) vs Temperature
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Typical Characteristics (continued)
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
2.5
10
8
ILIM Accuracy (%)
ILIM (A)
2
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
1.5
1
6
4
0.5
2
0
0
25
50
75
RILIM (kOhm)
100
125
0
D007
0
6
12
18
24
VIN (V)
30
36
42
D008
TA = -40 to 125 °C
Figure 7. ILIM vs RILIM
Figure 8. ILIM Accuracy vs Supply Voltage
4.5
79.25
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
4
79
78.75
78.5
3
GIMON (µA/A)
ILIM Accuracy (%)
3.5
2.5
2
1.5
78.25
78
77.75
77.5
1
77.25
0.5
77
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
76.75
-40
140
-20
0
20
D009
Figure 9. ILIM Accuracy vs Temperature with VIN = 12 V
40
60
80
Temperature (°C)
100
120
140
D010
Figure 10. GAIN(IMON) vs Temperature
180
240
160
220
140
200
RON (m:)
IMON (PA)
120
100
80
180
160
60
140
40
120
20
0
0
0.25
0.5
0.75
1
1.25
IOUT (A)
1.5
1.75
2
2.25
100
-40
D011
Figure 11. IMON vs IOUT
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D012
Figure 12. RON vs Temperature
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Typical Characteristics (continued)
TA = 25 °C, V(IN) = 12 V, V(SHDN)= 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN.
(Unless otherwise noted)
-4
-5
-4.5
-5.5
-6
-5
-6.5
Ilkg(OUT) (PA)
Ilkg(OUT) (PA)
-5.5
-6
-6.5
-7
-7
-7.5
-8
-8.5
-7.5
-9
-8
-9.5
-8.5
-9
-40
-10
-20
0
20
40
60
80
Temperature (°C)
V(OUT) = 24 V
100
120
-10.5
-40
140
V(IN) = 0 V
VSHDN = 0 V
11.4
95.2
11.2
95
11
10.8
10.6
94
100
120
93.8
-40
140
Figure 15. VREVTH vs Temperature
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D016
Figure 16. VFWDTH vs Temperature
Thermal Shutdown Time (ms)
RILIM = 120k
RILIM = 12k
RILIM = 5.37k
3.5
ILIM Accuracy (%)
VSHDN = 0 V
100000
4
3
2.5
2
1.5
1
TA = -40 qC
TA = 25 qC
TA = 85 qC
TA = 105 qC
TA = 125 qC
10000
1000
100
10
1
0.5
0.2
-20
0
20
40
60
80
Temperature (°C)
100
120
140
1
D017
Figure 17. ILIM Accuracy vs Temperature with VIN = 24 V
10
140
D014
V(IN) = –24 V
D015
4.5
0
-40
120
94.4
10.2
40
60
80
Temperature (°C)
100
94.6
94.2
20
40
60
80
Temperature (°C)
94.8
10.4
0
20
Figure 14. Ilkg(OUT) vs Temperature with VIN = –24 V
95.4
VFWDTH (mV)
VREVTH (mV)
Figure 13. Ilkg(OUT) vs Temperature with VIN = 0 V
-20
0
V(OUT) = 0 V
11.6
10
-40
-20
D013
2
3
4 5 6 7 8 10
20
Power Dissipation (W)
30 40 50 70 100
D018
Taken on 2-layer PCB with 0.07-mm thick copper and copper area of
10.5 cm2 connected to PowerPAD.
Figure 18. Thermal Shutdown Time vs Power Dissipation
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7 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.1 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
0
10%
time
0
time
UVLO_tON(dly)
UVLO_toff(dly)
-20 mV
V(IN) -V(OUT)
110 mV
V(IN) -V(OUT)
FLT
90%
FLT
10%
0
time
tREV(dly)
I(FASTRIP)
0
tFWD(dly)
time
V(OVPR)+0.1V
V(OVP)
I(SCL)
I(OUT)
FLT
10%
0
time
tFASTRIP(dly)
0
tOVP(dly)
time
Figure 19. Timing Waveforms
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8 Detailed Description
8.1 Overview
LM74202-Q1 is an ideal diode with integrated back-to-back FETs and enhanced built-in protection circuitry. It
provides robust protection for all systems and applications powered from 4.2 V to 40 V. The device integrates
reverse battery input, reverse current, overvoltage, undervoltage, overcurrent and short circuit protection. The
precision overcurrent limit (±5% at 1A) helps to minimize over design of the input power supply, while the fast
response short circuit protection immediately isolates the load from input when a short circuit is detected. The
device allows the user to program the overcurrent limit threshold between 0.1 A and 2.23 A with an external
resistor. The device monitors the bus voltage for brown-out and overvoltage protection, asserting the FLTb pin to
notify downstream systems.
The device is designed to protect systems such as ADAS camera supplies against sudden output short to battery
events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when output short to
battery fault condition or input power fail condition is detected. The internal robust protection control blocks of the
LM74202-Q1 device along with its ±40 V rating helps to simplify the system designs for the various ISO and
LV124 compliance ensuring complete protection of the load and the device.
The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input
power failure condition is detected. The LM74202-Q1 device is also designed to control redundant power supply
systems.
Additional features of the LM74202-Q1 device include:
• Reverse input battery protection
• Reverse current blocking
• Current monitor output for health monitoring of the system
• Electronic circuit breaker operation with overload timeout using MODE pin
• A choice of latch off or automatic restart mode response during current limit fault using MODE pin
• Over temperature protection to safely shutdown in the event of an overcurrent event
• De-glitched fault reporting for brown-out and overvoltage faults
• Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)
12
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8.2 Functional Block Diagram
OUT
IN
150 PŸ
+
-10 mV
PORb
Charge
Pump
+100 mV
4V
3.72 V
+
+
Current
Sense
CP
X78.2 µ
UVLOb
1.19 V
UVLO
REVERSE
1.1 V
SWEN
Gate Control Logic
IMON
TSD
Thermal
Shutdown
+
1.19 V
Current Limit Amp
Fast-Trip Comp
(Threshold=1.8 x IOL)
OVP
1.1 V
1V
OLR
SHDNb
ILIM
OVP
Short detect
Ramp Control
24.6 x
SWEN
Avdd
I(LOAD) • ,(CB)
OLR
5 µA
Timeout
4 msec
timer
FLT
* Only for Latch Mode
S
SET
Q
dVdT
85 Ÿ
UVLOb
RdVdT
RTN
R
PORb
PORb
TSD
CLR
Q
1.8 msec
Fault Latch
900 µs
Avdd
SHDNb
OLR
Gate Enhanced (tPGOOD)
400 NŸ
Avdd
Overload fault response
select detection
VSHUTx
SHDNb
Reverse Input Polarity
Protection circuit
GND
RTN
+
LM74202-Q1
SHDN
MODE
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
This section describes the undervoltage comparator input. When the voltage at UVLO pin falls below V(UVLOF)
during input power fail or input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The
UVLO comparator has a hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider
network from IN supply to UVLO terminal to RTN as shown in Figure 20.
V(IN)
IN
LM74202-Q1
R1
UVLO
+
UVLOb
1.19 V
R2
1.1 V
OVP
+
OVP
1.19 V
R3
RTN
1.1 V
GND
Figure 20. UVLO and OVP Thresholds Set by R1, R2 and R3
If the undervoltage lockout (UVLO) function is not needed, the UVLO terminal must be connected to the IN
terminal. UVLO terminal must not be left floating.
The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables
the internal circuitry when the IN terminal voltage falls below internal POR threshold V(PORF). The internal POR
threshold has a hysteresis of 275 mV.
8.3.2 Overvoltage Protection (OVP)
The device incorporates circuitry to protect the system during overvoltage conditions. This device features an
overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects
the downstream load. To program the OVP threshold, connect a resistor divider from IN supply to OVP terminal
to RTN as shown in Figure 21. OVP Overvoltage Cut-off response is shown in Figure 22. OVP pin must not be
left floating. If OVP pin could be floating due to dry soldering, an additional zener diode at the output will be
required for protection from over voltage.
14
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Feature Description (continued)
V(IN)
IN
LM74202-Q1
R1
UVLO
+
UVLOb
1.19 V
R2
1.1 V
OVP
+
OVP
1.19 V
R3
RTN
1.1 V
GND
Figure 21. OVP Threshold Setting
Figure 22. OVP Overvoltage Cut-Off
Programmable overvoltage clamp can also be achieved using LM74202-Q1 by connecting the resistor ladder
from Vout to OVP to RTN as shown in Figure 23 . This results in clamping of output voltage close to OVP setpoint by resistors R1 and R2. as shown in Figure 24. This scheme will also help in achieving minimal system Iq
during off state. For this OVP configurataion, use R1 > 90 kΩ.
V(IN)
IN
V(OUT)
LM74202-Q1
UVLO
+
UVLOb
R1
(>90 k
)
1.19 V
OVP
1.1 V
OVP
+
R2
OVP
1.19 V
1.1 V
RTN
GND
Figure 24. Programmable Overvoltage Clamp Response
Figure 23. Programmable OV Clamp
If the OVP pin is connected to GND, the device will clamp the output voltage to 37.5 V (typical).
8.3.3 Reverse Battery Protection
To protect the electronic systems from reverse battery voltage due to miswiring, often a power component like a
schottky diode is added in series with the supply line as shown in Figure 25. These additional discretes result in
a lossy and bulky protection solution. The LM74202-Q1 devices feature fully integrated reverse input supply
protection and does not need an additional diode. These devices can withstand a reverse voltage of –40 V
without damage. Figure 26 illustrates the reverse input polarity protection functionality.
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Feature Description (continued)
INPUT
OUTPUT
OUTPUT
INPUT
LM74202-Q1
Hot-Swap Controller
GND
GND
Figure 25. Reverse Battery Protection Circuits - Discrete vs LM74202-Q1
Figure 26. Reverse Input Supply Protection at –40 V
8.3.4 Hot Plug-In and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the supply voltage and prevents unintended resets of the system
power. The controlled start-up also helps to eliminate conductive and radiative interferences. An external
capacitor connected from the dVdT pin to RTN defines the slew rate of the output voltage at power-on as shown
in Figure 27 and Figure 28.
16
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Feature Description (continued)
LM74202-Q1
4V
5 µA
dVdT
RdVdT
SWENb
C(dVdT)
RTN
GND
Figure 27. Output Ramp Up Time tdVdT is Set by C(dVdT)
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When the terminal is
left floating, the devices set an internal output voltage ramp rate of 23.9 V / 1.6 ms. A capacitor can be
connected from dVdT pin to RTN to program the output voltage slew rate slower than 23.9 V / 1.6 ms. Use
Equation 1 and Equation 2 to calculate the external C(dVdT) capacitance.
Equation 1 governs slew rate at start-up.
æ C(dVdT ) ö æ dV(OUT ) ö
÷´ç
I(dVdT) = ç
÷
ç Gain(dVdT ) ÷ ç dt ÷
ø
è
ø è
where
•
I(dVdT) = 4.7 µA (typical)
dV
•
•
OUT
dt
Gain(dVdT) = dVdT to VOUT gain = 24.6
(1)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 8.7 × 103 × V(IN) × C(dVdT)
(2)
The inrush current can be calculated by Equation 3
IINRUSH = COUT/[8.7 x 103 x CdVdT]
(3)
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Feature Description (continued)
VIN
CdVdT = 22 nF
COUT = 47 µF
RILIM = 5.36 kΩ
Figure 28. Hot Plug-In and In-Rush Current Control at 24-V Input
8.3.5 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
8.3.5.1 Overload Protection
The device offers following choices for the overload protection fault response:
• Active current limiting (Auto-retry and Latch-off modes)
• Electronic Circuit Breaker with overload timeout (Auto-retry mode)
See the configurations in Table 1 to select a specific overload fault response.
Table 1. Overload Fault Response Configuration
MODE Pin Configuration
Overload Protection Type
Open
Electronic circuit breaker with auto-retry
Shorted to RTN
Active current limiting with auto-retry
A 402-kΩ resistor across MODE pin to RTN
pin
Active current limiting with latch-off
8.3.5.1.1 Active Current Limiting
When the active current limiting mode is selected, during overload events, the device continuously regulates the
load current to the overcurrent limit I(OL) programmed by the R(ILIM) resistor as shown in Equation 4.
12
IOL
R ILIM
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(4)
During an overload condition, the internal current-limit amplifier regulates the output current to I(LIM). The FLT
signal assert after a delay of tPGOODF. The output voltage droops during the current regulation, resulting in
increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown
threshold (T(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is
reset by either of the following conditions:
18
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•
•
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Cycling V(IN) below V(PORF)
Toggling SHDN
When the device is configured in auto-retry mode, it commences an auto-retry cycle tCBretry(dly) ms after TJ <
[T(TSD) – 10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes
normal operation. Figure 29 and Figure 30 illustrates the behavior of the system during current limiting with autoretry functionality.
IMON
V_OUT
FLTb
I_IN
Load transition from 22 Ω to
12 Ω
RILIM = 8 kΩ
MODE pin connected to RTN
Figure 29. Auto-Retry MODE Fault Behavior
RILIM = 5.36 kΩ
Figure 30. Response During Coming Out of Overload Fault
8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
In this mode, during overload events, the device allows the overload current to flow through the device until
I(LOAD) < I(FASTRIP). The circuit breaker threshold I(CB) can be programmed using the R(ILIM) resistor, as shown in
Equation 5.
12
R ILIM
I(CB)
0.03A
where
•
•
I(CB) is circuit breaker current threshold in A
R(ILIM) is the current limit resistor in kΩ
(5)
The device commences an auto-retry cycle after a delay of tCBretry(dly). The FLT signal remains asserted until the
fault condition is removed and the device resumes normal operation. Figure 31 and Figure 32 illustrate behavior
of the system during electronic circuit breaker with auto-retry functionality.
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IMON
V_OUT
FLTb
I_IN
MODE left floating
RILIM = 8 kΩ
Load Transition from 22 Ω to 12 Ω
Figure 31. Circuit Breaker Functionality
Load Transition from 22 Ω to 12 Ω , RILIM = 8 kΩ
Figure 32. Zoomed at the Instance of Load Step
8.3.5.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases very rapidly. As the currentlimit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). The fast-trip comparator turns off the internal FET after a duration of
tFASTTRIP(dly), when the current through the FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid
short-circuit peak current. The fast-trip threshold is internally set to 87% higher than the programmed overload
current limit (I(FASTRIP) = 1.87 × I(OL) + 0.015). The fast-trip circuit holds the internal FET off for only a few
microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output
current to I(OL). Then the device behaves similar to overload condition. Figure 33 and Figure 34 illustrate the
behavior of the system when the current exceeds the fast-trip threshold.
VIN = 24 V, RILIM = 5.36 kΩ
Figure 33. Output Hot Short Functionality at 24-V Input
20
Figure 34. Zoomed at the Instance of Output Short
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8.3.5.2.1 Start-Up With Short-Circuit On Output
When the device is started with a short-circuit on the output end, it limits the load current to the current limit I(OL),
and behaves similarly to the overload condition. Figure 35 illustrates the behavior of the device in this condition.
This feature helps in quick isolation of the fault and hence ensures stability of the DC bus.
V_IN
V_OUT
FLTb
I_IN
MODE pin connected to RTN
VIN = 24 V RILIM = 5.36 kΩ
Figure 35. Start-Up With Short on Output
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8.3.5.3 FAULT Response
The FLT open-drain output asserts (active low) under following conditions:
• Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions
• When the device enters low current shutdown mode when SHDN is pulled low
• During start-up when the internal FET GATE is not fully enhanced (for example: VOUT has not reached VIN).
The FLT output does not assert in the event of reverse voltage on Input.
The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions
without the need for an external circuitry.
The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An
internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in
dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the
internal FET is fully enhanced and VOUT has reached VIN. The PGOOD signal has deglitch time incorporated to
ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising
deglitch delay is determined by tPGOOD(degl) = Maximum {(900 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and
tPGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) resets
FLT.
8.3.5.3.1 Look Ahead Overload Current Fault Indicator
With the device configured in current limit operation and when the overload condition exists for more than
tPGOODF, the FLT asserts to warn of impending turnoff of the internal FETs due to the subsequent thermal
shutdown event. Figure 36 and Figure 37 depict this behavior. The FLT signal remains asserted until the fault
condition is removed and the device resumes normal operation.
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
Figure 36. Look Ahead Overload Current Fault Indication
RILIM = 12 kΩ
MODE pin connected
to RTN
Load transient event
from 37 Ω to 15 Ω
Figure 37. Output Turnoff Due to Thermal Shutdown With
FLT Asserted in Advance
8.3.5.4 Current Monitoring
The current source at IMON terminal is internally configured to be proportional to the current flowing from IN to
OUT. This current can be converted into a voltage using a resistor R(IMON) from IMON terminal to RTN terminal.
The IMON voltage can be used as a means of monitoring current flow through the system. The maximum voltage
range (V(IMONmax) for monitoring the current is limited to minimum of ([V(IN) – 1.5 V, 4 V]) to ensure linear output.
This puts a limitation on maximum value of R(IMON) resistor and is determined by Equation 6.
R
22
IMONmax
Min [(V(IN) - 1.5), 4 V]
1.8 u I LIM u GAIN IMON
(6)
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The output voltage at IMON terminal is calculated using Equation 7 and Equation 8.
For IOUT > 50 mA,
V
IMON
>I OUT
u GAIN
IMON
@ u R IMON
Where,
•
•
•
GAIN(IMON) is the gain factor I(IMON):I(OUT)
I(OUT) is the load current
I(MON_OS) = 2 µA (Typical)
(7)
For IOUT < 50 mA (typical), IMON output current is close to I(MON_OS) and Equation 8 provides the voltage output
with RIMON.
V
IMON
(I(IMON _ OS)) u R(IMON)
(8)
This pin must not have a bypass capacitor to avoid delay in the current monitoring information.
In case of reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC
input to limit the current through the ESD protection structures of the ADC.
8.3.5.5 IN, OUT, RTN and GND Pins
The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the
power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus
transients. The recommended input operating voltage range is 4.2 V to 40 V. Similarly all OUT pins must be
connected together and to the load. V(OUT), in the ON condition, is calculated using Equation 9.
V
OUT
V
IN
RON u I
OUT
Where,
•
RON is the total ON resistance of the internal FETs.
(9)
The GND pin must be connected to the system ground. RTN is the device ground reference for all the internal
control blocks. Connect the device support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO
and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between
RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection
feature. if negative input voltage is applied on IN pins with RTN pin connected to GND, the device can get
damaged.
8.3.5.6 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction
temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the
device either latches off or commences an auto-retry cycle 540 ms after TJ < [T(TSD) – 10°C]. During the thermal
shutdown, the fault pin FLT pulls low to indicate a fault condition.
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8.3.5.7 Low Current Shutdown Control (SHDN)
The internal FETs and hence the load current can be switched off by pulling the SHDN pin below V(SHUTF)
threshold with a micro-controller GPIO pin as shown in Figure 38. The device quiescent current reduces to 16 μA
(typical) in shutdown state. To assert SHDN low, the pull down must sink at least 10 µA at 400 mV. To enable
the device, SHDN must be pulled up to V(SHUTR) threshold. Once the device is enabled, the internal FETs turns
on with dVdT mode.
LM74202-Q1
AVdd
Rpu
SHDN
from µC
GPIO
+
SHDNb
VSHUTx
OFF
ON
GND
Figure 38. Shutdown Control
8.4 Device Functional Modes
The device responds differently to overload and short circuit conditions. The operational differences are
explained in Table 2.
Table 2. Device Operational Differences Under Different MODE Configurations
Mode Pin Configuration
Mode Connected To RTN
(Current Limit With Auto-Retry)
Start-up
A 402-KΩ Resistor Connected
Between Mode And RTN Pins
(Current Limit With Latchoff)
Mode Pin = Open
Inrush current controlled by dVdT
Inrush limited to I(OL) level as set
by R(ILIM)
Inrush limited to I(OL) level as set
by R(ILIM)
Inrush limited to I(OL) level as set
by R(ILIM)
Fault timer runs when current is
limited to I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
Overcurrent response
If TJ > T(TSD), device turns off
If TJ > T(TSD), device turns off
Device turns off if TJ > T(TSD)
before timer expires
Current is limited to I(OL) level as
set by R(ILIM)
Current is limited to I(OL) level as
set by R(ILIM)
Current is allowed through the
device if I(LOAD) < I(FASTTRIP)
Power dissipation increases as
V(IN) – V(OUT) increases
Power dissipation increases as
V(IN) – V(OUT) increases
Fault timer runs when the current
increases above I(OL)
Fault timer expires after tCB(dly)
causing the FETs to turnoff
Device turns off when TJ > T(TSD)
Device turns off when TJ > T(TSD)
Device turns off if TJ > T(TSD)
before timer expires
Device attempts restart 540 ms
after TJ < [T(TSD) – 10°C]
Device remains off
Device attempts restart 540 ms
after TJ < [T(TSD) – 10°C].
Short-circuit response
Fast turnoff when I(LOAD) > I(FASTRIP)
Quick restart and current limited to I(OL), follows standard start-up
24
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is an automotive ideal diode, typically used for load protection in automotive applications. It can
operate from 12-V battery with programmable current limit, overvoltage, undervoltage and reverse polarity
protections. The device provides robust protection against reverse current and transients (such as ISO 7637-2
Pulse 1 and ISO 16750-2 Pulse 5b) due to cables and switches in different automotive systems such as an ECU.
The device also provides robust protection for output short to battery, output short to GND, reverse battery and
input overvoltage.
The Detailed Design Procedure section can be used to select component values for the device.
9.2 Typical Application
IN
VIN: 4.2 V - 32 V
R1
97.6 k
150 PŸ
UVLO
OVP
SMBJ28CA
LM74202-Q1
(1)
FLT
Health Monitor
D2
R3
ON/OFF Control
Load
Monitor
IMON
MODE
CdVdT
12 nF
COUT
47 µF
RFLTb
100 k
SHDN
dVdT
R2
5.11 k
OUT
OUT
CIN
1 µF
(1)
OVP
ILIM
RTN
GND
RILIM
5.36 k
RIMON
20 k
R4
OVP connection for Programmable over voltage clamp. See Overvoltage Protection (OVP).
Figure 39. 12-V, 2-A Ideal Diode Load Protection Circuit for Automotive ECU
9.2.1 Design Requirements
Table 3 shows the Design Requirements for LM74202-Q1. In addition to below requirements, the circuit is
designed to provide protection for transients as per ISO 7637-2 Pulse 1 and ISO 16750-2 Pulse 5b.
Table 3. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
V(IN)
Typical input voltage
4.2 to 32 V
V(UV)
Undervoltage lockout set point
4V
V(OV)
Overvoltage cutoff set point
24 V
I(LIM)
Current limit
2.23 A
C(OUT)
Load capacitance
47 µF
I(LOAD)
Load current
2A
9.2.2 Detailed Design Procedure
9.2.2.1 Step by Step Design Procedure
To begin the design process, the designer must know the following parameters:
• Operating voltage range
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•
•
•
•
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Maximum output capacitance
Start-up time
Maximum current limit
Transient voltage levels
9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range
To provide operation in cold crank conditions for automotive batteries, the UVLO is set to POR value (4 V) by
connecting UVLO to IN pin and OVP threshold is set from resistors connected from IN pins to provide protection
from transient during ISO 16750 Pulse 5b. During the ISO 16750 5b transient, output voltage is cut-off at 24 V
and provides protection to load from high input voltage during the transient. The overvoltage threshold is
calculated by Equation 10.
VOVPR = R2/(R1 + R2) × VOV
where
•
•
Overvoltage threshold rising, VOVPR = 1.19 V
VOV is overvoltage protection voltage (= 24 V)
(10)
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R23) must be chosen to be 20x greater than the leakage
current of OVP pin.
9.2.2.3 Programming the Current-Limit Threshold—R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
R(ILIM) = 5.36 kΩ was selected to set ILIM to 2.23 A.
9.2.2.4 Programming Current Monitoring Resistor—RIMON
The voltage at IMON pin V(IMON) represents the voltage proportional to the load current. This can be connected to
an ADC of the downstream system for health monitoring of the system. The R(IMON) must be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using Equation 11.
R(IMON)
V (IMON max)
I(LIM) u 75 u 10
6
(11)
For current monitoring up-to a current of 2.2 A, and considering the operating input voltage range of ADC from 0
V to 4 V, V(IMONmax) is 4 V and R(IMON) is selected as 20 kΩ.
9.2.2.5 Limiting the Inrush Current
To limit the inrush current and power dissipation during start-up, an appropriate value of CdVdT must be selected.
The inrush current during start-up is estimated by Equation 12. A 12nF capacitance is selected for CdVdT to keep
inrush current less than 0.5 A.
IINRUSH = COUT / [8.7 × 103 × CdVdt]
(12)
9.2.2.5.1 Selection of Input TVS for Transient Protection
To protect the device and the load from input transients exceeding the absolute maximum ratings of the device, a
TVS diode is required at input of the device. To meet the requirements of protection for ISO 16750 pulse 5b and
ISO 7637 pulse 1 as per Table 4, SMBJ28CA is selected for protection from transients.
Table 4. Input TVS Selection for Transients
Parameter
ISO 16750 Pulse 5b
ISO 7637 Pulse 1
and Reverse Battery
Maximum Transient Voltage of Pulse
(VT)
35 V
-150V
A bidirectional TVS is required to protect
from positive and negative transients
Pulse Current through TVS (IPulse)
(VT - VC)/(Ri)
(VT - VC)/(Ri)
Ri = Source impedance.
For ISO 16750 Pulse 5b; Ri = 0.5 Ω
For ISO 7637 Pulse 1;Ri = 10 Ω
26
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Table 4. Input TVS Selection for Transients (continued)
Parameter
ISO 16750 Pulse 5b
ISO 7637 Pulse 1
and Reverse Battery
Clamping voltage of TVS (VC) at Pulse
current IPulse
< 55 V
> –(55 - VOUT-Max) V
To keep input voltage below absolute
maximum rating of the device. See
Equation 13 for VC
Breakdown voltage of TVS (VBR)
> 32V
> 14V
To operate with maximum operating input
voltage and to protect from maximum
reverse battery voltage
VC = VBR + IPulse × [VClamp-max - VBR]/[IPP - IT]
where
•
•
•
•
VC is the clamping voltage of TVS at IPulse current through it.
VBR is break down voltage of TVS with IT test current through it.
VClamp-max is maximum clamping voltage of TVS at peak pulse current IPP
VBR, IT, VClamp-max and IPP are the specifications of the TVS diode.
(13)
9.2.3 Application Curves
Figure 40. Protection from Output Short to GND [VIN = 12
V, ILIM = 2.23 A, MODE = RTN]
Figure 41. Protection from Output short to Battery [VIN =
Floating, VOUT = 12 V, ILIM = 2.23 A, MODE = RTN ]
Figure 42. Protection from ISO 7637-2 Pulse 1 [12 V
Battery, Transient Voltage = –150 V , RLOAD = 14 Ω]
Figure 43. Protection from ISO 16750-2 Pulse 5b [12 V
Battery, Transient Voltage = 35 V , RLOAD = 14 Ω]
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Figure 44. Protection from Reverse Battery [VIN = -12 V,
VOUT = 0 V, ILIM = 2.23 A ]
28
Figure 45. Protection from overvoltage at Input [VIN = 36 V,
RLOAD = 14 Ω, ILIM = 2.23 A ]
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10 Power Supply Recommendations
The device is designed for the supply voltage range of 4.2 V ≤ VIN ≤ 40 V. Power supply must be rated higher
than the current limit set to avoid voltage droops during overcurrent and short circuit conditions.
10.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A ceramic capacitor at input (C(IN)) with value more than 1µF to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 14.
Vspike(Absolute ) = V(IN) + I(Load) ´
L(IN)
C(IN)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(14)
Automotive applications could require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients include ISO 7637 Pulse 1, Output
short to battery, Output short to GND and reverse battery at input.
The circuit implementation with optional protection components (TVS Diode at Input and schottky diode at
output) is shown in Figure 46. For protection from automotive transients similar to ISO 7637 Pulse 1, Output
short to battery , output short to GND and reverse battery, use CIN ≥ 1 µF and COUT ≥ 3.3 µF. For selection of
TVS diode and other components, see Application Information.
INPUT
IN
R1
CIN
UVLO
R2
OVP
MODE
dVdT
R3
RTN
(• 3.3 µF)
FLT
LM74202-Q1
*
SHDN
IMON
ILIM
GND
RILIM
CdVdT
*
COUT
R4
150 m
(• 1 µF)
*
OUTPUT
OUT
RIMON
Optional components needed for suppression of transients
Figure 46. Circuit Implementation for Automotive Transient Protection
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
30
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND. Use CIN ≥ 1 µF for automotive transient protection. See Transient Protection.
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the device. See Figure 47 for PCB layout example with HTSSOP package.
High current carrying power path connections must be as short as possible and must be sized to carry atleast
twice the full-load current.
RTN, which is the reference ground for the device must be a copper plane or island.
Locate all the device support components R(ILIM), C(dVdT), R(IMON), and MODE, UVLO, OVP resistors close to
their connection pin. Connect the other end of the component to the RTN with shortest trace length.
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications. Designs that do not need reverse input polarity protection can
have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the
PCB ground plane.
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11.2 Layout Example
Top Layer
Bottom layer GND plane
Via to Bottom Layer
Top Layer RTN Plane
Track in bottom layer
Bottom Layer RTN Plane
BOTTOM Layer GND Plane
Top Layer
Power GND Plane
High
Frequency
Bypass cap
VIN PLANE
IN
OUT
IN
OUT
VOUT PLANE
FLT
UVLO
N.C
N.C
PWP
OVP
dVdT
MODE
ILIM
IMON
SHDN
EP Blue
RTN
GND
TOP Layer
RTN Plane
BOTTOM Layer RTN Plane
Figure 47. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• LM76202-Q1 EVM User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
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7-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM74202QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
M74202Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM74202QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM74202QPWPRQ1
HTSSOP
PWP
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016H
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.600
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
PIN 1 INDEX
AREA
A
SEATING
PLANE
0.1 C
16
1
14X 0.65
2X
5.1
4.9
NOTE 3
4.55
8
9
B
16X
4.5
4.3
0.30
0.19
0.1
C A B
SEE DETAIL A
(0.15) TYP
0.25
GAGE PLANE
1.2 MAX
2X 1.15 MAX
NOTE 5
8
9
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 15
TYPICAL
2.46
2.16
2X 0.3 MAX
NOTE 5
17
THERMAL
PAD
16
1
2.66
2.36
4223630/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0016H
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.66)
16X (1.5)
METAL COVERED
BY SOLDER MASK
SYMM
1
16
(0.6) TYP
16X (0.45)
(R0.05) TYP
17
SYMM
(5)
NOTE 9
(1.2)
TYP
(2.46)
14X (0.65)
9
8
( 0.2) TYP
VIA
(1.2) TYP
SEE DETAILS
(5.8)
SOLDER MASK
DEFINED PAD
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MAX
ALL AROUND
EXPOSED METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223630/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0016H
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.66)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
METAL COVERED
BY SOLDER MASK
1
16
16X (0.45)
(R0.05) TYP
SYMM
(2.46)
BASED ON
0.125 THICK
STENCIL
17
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.97 X 2.75
2.66 X 2.46 (SHOWN)
2.43 X 2.25
2.25 X 2.08
4223630/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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