Texas Instruments | LM26420-Q1 Dual 2-A, Automotive-Qualified, High-Efficiency Synchronous DC/DC Converter (Rev. A) | Datasheet | Texas Instruments LM26420-Q1 Dual 2-A, Automotive-Qualified, High-Efficiency Synchronous DC/DC Converter (Rev. A) Datasheet

Texas Instruments LM26420-Q1 Dual 2-A, Automotive-Qualified, High-Efficiency Synchronous DC/DC Converter (Rev. A) Datasheet
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LM26420-Q1
SNVSB35A – MAY 2018 – REVISED JULY 2019
LM26420-Q1 Dual 2-A, Automotive-Qualified, High-Efficiency Synchronous
DC/DC Converter
1 Features
3 Description
•
•
The LM26420-Q1 regulator is a monolithic, highefficiency dual PWM step-down DC/DC converter.
This device has the ability to drive two 2-A loads with
an internal 75-mΩ PMOS top switch and an internal
50-mΩ NMOS bottom switch using state-of-the-art
BICMOS technology results in the best power density
available. The world-class control circuitry allow on
times as low as 30 ns, thus supporting exceptionally
high-frequency conversion over the entire 3-V to 5.5V input operating range down to the minimum output
voltage of 0.8 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC Q100-Qualified With the Following Results:
– Device Temperature Grade 0 (Q0): –40°C to
+150°C Ambient Operating Temperature
– Device Temperature Grade 1 (Q1): –40°C to
+125°C Ambient Operating Temperature
Compliant with CISPR25 Class 5 conducted
emissions
Input voltage range of 3 V to 5.5 V
Output voltage range of 0.8 V to 4.5 V
2-A Output current per regulator
Fixed 2.2-MHz switching frequency
0.8 V, 1.5% Internal voltage reference
Internal soft start
Independent power good and precision enable for
each output
Current mode, PWM operation
Thermal shutdown
Overvoltage protection
Start-up into prebiased output loads
Regulators are 180° out of phase
Create a custom design using the LM26420-Q1
with the WEBENCH® Power Designer
Although the operating frequency is high, efficiencies
up to 93% are easy to achieve. External shutdown is
included, featuring an ultra-low standby current. The
LM26420-Q1 utilizes current-mode control and
internal compensation to provide high performance
regulation over a wide range of operating conditions.
Because its switching frequency is ensured to be
greater than 2 MHz, the LM26420-Q1 can be used in
automotive applications without causing interference
in the AM frequency band.
Device Information(1)
PART NUMBER
LM26420-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (20)
6.50 mm × 4.40 mm
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Automotive Head Unit and Cluster
ADAS camera systems
Automotive radar systems
Highly integrated POL power
LM26420 Dual Buck DC/DC Converter
LM26420 Efficiency (Up to 93%)
VIN
3 V to 5.5 V
VIN
VOUT1
2.5 V/2 A
PG2
EN1
SW1
LM26420
Buck 1
PG1
EN2
Buck 2
VOUT2
1.2 V/2 A
SW2
FB2
FB1
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM26420-Q1
SNVSB35A – MAY 2018 – REVISED JULY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics Per Buck ...........................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
13
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ............................................... 18
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
10.3 Thermal Considerations ........................................ 29
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2018) to Revision A
•
2
Page
Updated Power Supply Recommendations ......................................................................................................................... 28
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SNVSB35A – MAY 2018 – REVISED JULY 2019
5 Pin Configuration and Functions
RUM Package
16-Pin WQFN
Top View
4
3
2
PWP Package
20-Pin HTSSOP
Top View
1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
16
5
15
6
DAP
7
14
8
13
9
10
11
12
Pin Functions: 16-Pin WQFN
PIN
NUMBER
NAME
1,2
TYPE
DESCRIPTION
VIND1
P
Power input supply for Buck 1.
3
SW1
P
Output switch for Buck 1. Connect to the inductor.
4
PGND1
G
Power ground pin for Buck 1.
5
FB1
A
Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.
6
PG1
G
Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply
(open drain output).
7
PG2
G
Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply
(open drain output).
8
FB2
A
Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.
9
PGND2
G
Power ground pin for Buck 2.
10
SW2
P
Output switch for Buck 2. Connect to the inductor.
VIND2
A
Power Input supply for Buck 2.
13
EN2
A
Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or
be greater than VIN + 0.3 V.
14
AGND
G
Signal ground pin. Place the bottom resistor of the feedback network as close as possible to
pin.
15
VINC
A
Input supply for control circuitry.
16
EN1
A
Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or
be greater than VIN + 0.3 V.
Die Attach Pad
—
Connect to system ground for low thermal impedance and as a primary electrical GND
connection.
11, 12
DAP
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Pin Functions 20-Pin HTSSOP
PIN
TYPE
DESCRIPTION
NUMBER
NAME
1
VINC
A
Input supply for control circuitry.
2
EN1
A
Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float or
be greater than VIN + 0.3 V.
VIND1
A
Power Input supply for Buck 1.
SW1
P
Output switch for Buck 1. Connect to the inductor.
PGND1
G
Power ground pin for Buck 1.
3, 4
5
6,7
8
FB1
A
Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.
9
PG1
G
Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply
(open drain output).
Die Attach Pad
—
Connect to system ground for low thermal impedance, but it cannot be used as a primary
GND connection.
PG2
G
Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply
(open drain output).
10, 11, DAP
12
13
14, 15
16
17, 18
FB2
A
Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.
PGND2
G
Power ground pin for Buck 2.
SW2
P
Output switch for Buck 2. Connect to the inductor.
VIND2
A
Power Input supply for Buck 2.
19
EN2
A
Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float or
be greater than VIN + 0.3 V.
20
AGND
G
Signal ground pin. Place the bottom resistor of the feedback network as close as possible to
pin.
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.5
7
FB
–0.5
3
EN
–0.5
7
Output voltages
SW
–0.5
7
V
Infrared or convection reflow (15 sec)
Soldering Information
220
°C
150
°C
Input voltages
Storage temperature Tstg
(1)
–65
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
Other pins
±750
Corner pins 1, 10, 11, and 20
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
VIN
MAX
3
5.5
Junction temperature (Q1)
–40
125
Junction temperature (Q0)
–40
150
UNIT
V
°C
6.4 Thermal Information
LM26420-Q1
THERMAL METRIC
(1)
PWP (HTSSOP)
RUM (WQFN)
20 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
38.5
36.2
°C/W
RθJC(top)
Junction-to-case thermal resistance
21.0
32.7
°C/W
RθJB
Junction-to-board thermal resistance
19.9
14.1
°C/W
ψJT
Junction-to-top characterization parameter
0.7
0.3
°C/W
ψJB
Junction-to-board characterization parameter
19.7
14.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
4.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics Per Buck
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
VFB
Feedback Voltage
ΔVFB/VIN
Feedback Voltage Line Regulation
IB
Feedback Input Bias Current
TEST CONDITIONS
0.788
VIN = 3 V to 5.5 V
VIN Falling
TYP
MAX
0.8
0.812
0.05
VIN Rising
Undervoltage Lockout
UVLO
MIN
2
UVLO Hysteresis
UNIT
V
%/V
0.4
100
nA
2.628
2.9
V
2.3
V
330
mV
FSW
Switching Frequency
FFB
Frequency Foldback
DMAX
Maximum Duty Cycle
RDSON_TOP
TOP Switch On Resistance
RDSON_BOT
BOTTOM Switch On Resistance
ICL_TOP
TOP Switch Current Limit
VIN = 3.3 V
2.4
3.3
A
ICL_BOT
BOTTOM Switch Reverse Current
Limit
VIN = 3.3 V
0.4
0.75
A
ΔΦ
Phase Shift Between SW1 and SW2
160
180
200
Enable Threshold Voltage
0.97
1.04
1.12
VEN_TH
2.01
2.2
86%
91.5%
300
75
135
HTSSOP-20 Package
70
135
WQFN-16 Package
55
100
TSSOP-20 Package
45
80
0.15
ISW_TOP
Switch Leakage
IEN
Enable Pin Current
Sink/Source
VPG-TH-U
Upper Power Good Threshold
FB Pin Voltage Rising
848
Upper Power Good Hysteresis
FB Pin Voltage Rising
Lower Power Good Hysteresis
656
V
nA
925
1,008
710
mV
mV
791
40
mV
mV
3.3
5
VINC Quiescent Current (switching)
with both outputs on
VFB = 0.7 V
4.7
6.2
VINC Quiescent Current (shutdown)
VEN = 0 V
VIND Quiescent Current (nonswitching)
VFB = 0.9 V
0.9
1.5
VIND Quiescent Current (switching)
VFB = 0.7 V
11
15
IQVIND
VIND Quiescent Current (switching)
LM26420Q0 VFB = 0.7 V
11
18
IQVIND
VIND Quiescent Current (shutdown)
VEN = 0 V
TSD
Thermal Shutdown Temperature
6
°
µA
VFB = 0.9 V
IQVIND
mΩ
5
VINC Quiescent Current (nonswitching) with both outputs on
IQVINC
mΩ
–0.7
40
Lower Power Good Threshold
MHz
kHz
WQFN-16 Package
Enable Threshold Hysteresis
VPG-TH-L
2.65
0.05
mA
µA
mA
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mA
0.1
µA
165
°C
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6.6 Typical Characteristics
All curves taken at VIN = 5 V with configuration in typical application circuits shown in Application and Implementation. TJ =
25°C, unless otherwise specified.
Figure 1. Efficiency vs Load
Figure 2. Efficiency vs Load
Figure 3. Efficiency vs Load
Figure 4. Efficiency vs Load
1.808
1.807
OUTPUT (V)
1.806
1.805
1.804
1.803
1.802
1.801
0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0
LOAD (A)
VIN = 5 V
VOUT = 1.8 V
Figure 6. Load Regulation
Figure 5. Efficiency vs Load
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Typical Characteristics (continued)
All curves taken at VIN = 5 V with configuration in typical application circuits shown in Application and Implementation. TJ =
25°C, unless otherwise specified.
1.808
1.798
1.807
1.797
OUTPUT (V)
OUTPUT (V)
1.806
1.805
1.804
1.796
1.795
1.794
1.803
1.793
1.802
1.792
1.801
0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0
3.0
3.5
VIN = 3 V
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
LOAD (A)
VOUT = 1.8 V
VOUT = 1.8 V
IOUT = 1000 mA
Figure 8. Line Regulation
Figure 7. Load Regulation
WQFN - TOP FET - R DSON (mΩ)
110
100
90
80
70
60
50
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 9. Oscillator Frequency vs Temperature,
Figure 10. RDSON Top Vs Temperature (WQFN-16 Package)
110
TSSOP - TOP FET - R DSON (mΩ)
WQFN - BOTTOM FET - R DSON (mΩ)
80
70
60
50
40
30
-50
-25
0
25
50
75
100
90
80
70
60
50
-50
125
TEMPERATURE (°C)
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 11. RDSON Bottom Vs Temperature
(WQFN-16 Package)
8
100
Figure 12. RDSON Top Vs Temperature (TSSOP-20 Package)
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Typical Characteristics (continued)
All curves taken at VIN = 5 V with configuration in typical application circuits shown in Application and Implementation. TJ =
25°C, unless otherwise specified.
11.6
X Version
70
IQ SWITCHING - VIND (mA)
TSSOP - BOTTOM FET - R DSON (mΩ)
80
60
50
40
30
20
-50
-25
0
25
50
75
100
125
11.4
11.2
11.0
10.8
10.6
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. RDSON Bottom vs Temperature
(TSSOP-20 Package)
Figure 14. IQ (Quiescent Current Switching)
3.50
CURRENT LIMIT (A)
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
VIN = 5 V and 3.3 V
Figure 16. Current Limit vs Temperature
Figure 15. VFB vs Temperature
REVERSE CURRENT LIMIT (A)
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.70
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 17. Reverse Current Limit vs Temperature
Figure 18. Short Circuit Waveforms
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Typical Characteristics (continued)
All curves taken at VIN = 5 V with configuration in typical application circuits shown in Application and Implementation. TJ =
25°C, unless otherwise specified.
0.8002
FEEDBACK VOLTAGE (V)
IQ SWITCHING - VIND (mA)
12.50
12.00
11.50
11.00
10.50
0.8000
0.7998
0.7996
0.7994
0.7992
IQ SWITCHING - VIND (mA)
FEEDBACK VOLTAGE (V)
10.00
0.7990
±50
0
50
100
150
TEMPERATURE (öC)
±50
3.350
0.735
REVERSE CURENT LIMIT (A)
0.740
3.250
3.200
3.150
3.100
3.050
C004
0.725
0.720
0.715
0.710
REVERSE CURRENT LIMIT (A)
3.000
0.705
-50
0
50
100
150
TEMPERATURE (ö •
-50
0
Figure 21. Current Limit vs Temperature (Q0 Grade)
50
100
150
TEMPERATURE (|C)
C005
C006
Figure 22. Reverse Current Limit vs Temperature (Q0 Grade)
110.0
65.0
TSSOP - BOTTOM FET - RDSON (m
105.0
TSSOP - TOP FET - RDSON (m
150
0.730
CURRENT LIMIT (A)
100.0
95.0
90.0
85.0
80.0
75.0
70.0
65.0
TSSOP - TOP FET - RDSON (m
60.0
-50
0
50
TEMPERATURE (|C)
100
150
60.0
55.0
50.0
45.0
40.0
TSSOP - BOTTOM FET - RDSON (m
35.0
-50
0
50
TEMPERATURE (|C)
C007
Figure 23. RDSON Top vs Temperature (Q0 Grade)
10
100
Figure 20. VFB vs Temperature (Q0 Grade)
3.400
3.300
50
TEMPERATURE (|C)
Figure 19. IQ (Quiescent Current) vs Temperature
(Q0 Grade)
CURRENT LIMIT (A)
0
C002
100
150
C008
Figure 24. RDSON Bottom vs Temperature (Q0 Grade)
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Typical Characteristics (continued)
All curves taken at VIN = 5 V with configuration in typical application circuits shown in Application and Implementation. TJ =
25°C, unless otherwise specified.
OSCILLATOR FREQUENCY (MHz)
2.110
2.105
2.100
2.095
2.090
OSCILLATOR FREQUENCY (MHz)
2.085
-50.0
0.0
50.0
100.0
TEMPERATURE (|C)
150.0
C009
Figure 25. Oscillator Frequency vs Temperature (Q0 Grade)
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7 Detailed Description
7.1 Overview
The LM26420-Q1 is a constant frequency dual PWM buck synchronous regulator device that can supply two
loads at up to 2 A each. The regulator has a preset switching frequency of 2.2 MHz. This high frequency allows
the LM26420-Q1 to operate with small surface mount capacitors and inductors, resulting in a DC/DC converter
that requires a minimum amount of board space. The LM26420-Q1 is internally compensated, so it is simple to
use and requires few external components. The LM26420-Q1 uses current-mode control to regulate the output
voltage. The following operating description of the LM26420-Q1 refers to the Functional Block Diagram, which
depicts the functional blocks for one of the two channels, and to the waveforms in Figure 26. The LM26420-Q1
supplies a regulated output voltage by switching the internal PMOS and NMOS switches at constant frequency
and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal
clock. When this pulse goes low, the output control logic turns on the internal PMOS control switch (TOP Switch).
During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL)
increases with a linear slope. IL is measured by the current sense amplifier, which generates an output
proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and
compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage
and VREF. When the PWM comparator output goes high, the TOP Switch turns off and the NMOS switch
(BOTTOM Switch) turns on after a short delay, which is controlled by the Dead-Time-Control Logic, until the next
switching cycle begins. During the top switch off-time, inductor current discharges through the BOTTOM Switch,
which forces the SW pin to swing to ground. The regulator loop adjusts the duty cycle (D) to maintain a constant
output voltage.
VSW
D = TON/TSW
VIN
SW
Voltage
TOFF
TON
0
IL
t
TSW
IPK
Inductor
Current
0
t
Figure 26. LM26420-Q1 Basic Operation of the PWM Comparator
12
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7.2 Functional Block Diagram
VIN
EN
ThermalSHDN
+
+
-
ILIMIT
ENABLE and
UVLO
VREF x 1.15
+
OVPSHDN
+
ISENSE
Control
Logic
RAMPArtificial
Clock
2.2 MHz
ISENSE
S
FB
+
-
+
R
R
Q
P-FET
DeadTimeControl
Logic
SW
DRIVERS
N-FET
InternalComp
Q
VREF = 0.8 V
R
Internal - LDO
S
+
-
SOFT-START
IREVERSE-LIMIT
Pgood
880 mV
720 mV
+
-
+
-
GND
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7.3 Feature Description
7.3.1 Soft Start
This function forces VOUT to increase at a controlled rate during start-up in a controlled fashion, which helps
reduce inrush current and eliminate overshoot on VOUT. During soft start, reference voltage of the error amplifier
ramps from 0 V to its nominal value of 0.8 V in approximately 600 µs. If the converter is turned on into a prebiased load, then the feedback begins ramping from the prebias voltage but at the same rate as if it had started
from 0 V. The two outputs start up ratiometrically if enabled at the same time, see Figure 27 below.
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Feature Description (continued)
RATIOMETRIC START UP
VOUT1
VOLTAGE
VOUT2
VEN1,2
TIME
Figure 27. LM26420 Soft-Start
7.3.2 Power Good
The LM26420-Q1 features an open drain power good (PG) pin to sequence external supplies or loads and to
provide fault detection. This pin requires an external resistor (RPG) to pull PG high when the output is within the
PG tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.
7.3.3 Precision Enable
The LM26420-Q1 features independent precision enables that allow the converter to be controlled by an external
signal. This feature allows the device to be sequenced either by a external control signal or the output of another
converter in conjunction with a resistor divider network. It can also be set to turn on at a specific input voltage
when used in conjunction with a resistor divider network connected to the input voltage. The device is enabled
when the EN pin exceeds 1.04 V and has a 150-mV hysteresis.
7.4 Device Functional Modes
7.4.1 Output Overvoltage Protection
The overvoltage comparator compares the FB pin voltage to a voltage that is approximately 15% greater than the
internal reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS
switch is turned off, which allows the output voltage to decrease toward regulation.
7.4.2 Undervoltage Lockout
Undervoltage lockout (UVLO) prevents the LM26420-Q1 from operating until the input voltage exceeds 2.628 V
(typical). The UVLO threshold has approximately 330 mV of hysteresis, so the device operates until VIN drops
below 2.3 V (typical). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic.
7.4.3 Current Limit
The LM26420-Q1 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a
current limit comparator detects if the output switch current exceeds 3.3 A (typical), and turns off the switch until
the next switching cycle begins.
7.4.4 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the output switch when the device junction
temperature exceeds 165°C. After thermal shutdown occurs, the output switch does not turn on until the junction
temperature drops to approximately 150°C.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Programming Output Voltage
The output voltage is set using Equation 1 where R2 is connected between the FB pin and GND, and R1 is
connected between VOUT and the FB pin. A good value for R2 is 10 kΩ. When designing a unity gain converter
(VOUT = 0.8 V), R1 must be between 0 Ω and 100 Ω, and R2 must be on the order of 5 kΩ to 50 kΩ. 10 kΩ is the
suggested value where R1 is the top feedback resistor and R2 is the bottom feedback resistor.
VOUT
R1 =
VREF
- 1 x R2
(1)
(2)
VREF = 0.80V
LOUT
LM26420
VIND
VINC
EN
VOUT
SW
R1
COUT
FB
AGND PGND
R2
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Programming VOUT
To determine the maximum allowed resistor tolerance, use Equation 3:
1
V=
VFB
1
1 + 2x
VOUT
TOL
I
where
•
TOL is the set point accuracy of the regulator, is the tolerance of VFB.
(3)
Example:
VOUT = 2.5 V, with a setpoint accuracy of ±3.5%.
1
V=
0.8V
2.5V
1 + 2x
3.5% 1.5%
1
= 1.4%
(4)
Choose 1% resistors. If R2 = 10 kΩ, then R1 is 21.25 kΩ.
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Application Information (continued)
8.1.2 VINC Filtering Components
Additional filtering is required between VINC and AGND in order to prevent high frequency noise on VIN from
disturbing the sensitive circuitry connected to VINC. A small RC filter can be used on the VINC pin as shown in
Figure 29.
VIN
LM26420
VIND1,2
SW
VINC
RF
CIN
CF
FB
EN
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
Figure 29. RC Filter On VINC
In general, RF is typically between 1 Ω and 10 Ω so that the steady state voltage drop across the resistor due to
the VINC bias current does not affect the UVLO level. CF can range from 0.22 µF to 1 µF in X7R or X5R
dielectric, where the RC time constant should be at least 2 µs. CF must be placed as close to the device as
possiblewith a direct connection from VINC and AGND.
8.1.3 Using Precision Enable and Power Good
The LM26420-Q1 device precision EN and PG pins address many of the sequencing requirements required in
today's challenging applications. Each output can be controlled independently and have independent power
good. This allows for a multitude of ways to control each output. Typically, the enables to each output are tied
together to the input voltage and the outputs ratiometrically ramp up when the input voltage reaches above
UVLO rising threshold. There may be instances where it is desired that the second output (VOUT2) does not turn
on until the first output (VOUT1) has reached 90% of the desired setpoint. This is easily achieved with an external
resistor divider attached from VOUT1 to EN2, see Figure 30.
Figure 30. VOUT1 Controlling VOUT2 with Resistor Divider
If it is not desired to have a resistor divider to control VOUT2 with VOUT1, then the PG1 can be connected to the
EN2 pin to control VOUT2, see Figure 31. RPG1 is a pullup resistor on the range of 10 kΩ to 100 kΩ, 50 kΩ is the
suggested value. This turns on VOUT2 when VOUT1 is approximately 90% of the programmed output.
NOTE
This also turns off VOUT2 when VOUT1 is outside the ±10% of the programmed output.
16
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Application Information (continued)
Figure 31. PG1 Controlling VOUT2
Another example might be that the output is not to be turned on until the input voltage reaches 90% of desired
voltage setpoint. This verifies that the input supply is stable before turning on the output. Select REN1 and REN2
such that the voltage at the EN pin is greater than 1.12 V when reaching the 90% desired set-point.
VIN
LM26420
VIND
SW
REN1
VINC
RF
CIN
REN2
EN
FB
CF
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
Figure 32. VOUT Controlling VIN
The power good feature of the LM26420-Q1 is designed with hysteresis in order to ensure no false power good
flags are asserted during large transient. Once power good is asserted high, it is not pulled low until the output
voltage exceeds ±14% of the setpoint for a during of approximately 7.5 µs (typical), see Figure 33.
VOUT
+14%
+10%
-10%
-14%
~7.5 Ps
t
VPG
t
Figure 33. Power Good Hysteresis Operation
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Application Information (continued)
8.1.4 Overcurrent Protection
When the switch current reaches the current limit value, it is turned off immediately. This effectively reduces the
duty cycle and therefore the output voltage dips and continues to droop until the output load matches the peak
current limit inductor current. As the FB voltage drops below 480 mV the operating frequency begins to decrease
until it hits full on frequency foldback, which is set to approximately 300 kHz. Frequency foldback helps reduce
the thermal stress in the device by reducing the switching losses and to prevent runaway of the inductor current
when the output is shorted to ground.
It is important to note that when recovering from a overcurrent condition the converter does not go through the
soft-start process. There may be an overshoot due to the sudden removal of the overcurrent fault. The reference
voltage at the non-inverting input of the error amplifier always sits at 0.8 V during the overcurrent condition,
therefore when the fault is removed the converter bring the FB voltage back to 0.8 V as quickly as possible. The
overshoot depend on whether there is a load on the output after the removal of the overcurrent fault, the size of
the inductor, and the amount of capacitance on the output. The smaller the inductor and the larger the
capacitance on the output the smaller the overshoot.
NOTE
Overcurrent protection for each output is independent.
8.2 Typical Applications
8.2.1
2.2-MHz, 0.8-V Typical High-Efficiency Application Circuit
VIN
3 V to 5.5 V
R7
C3
C5
C4
R5
R6
VIN1
VINc
VIN2
PG1
PG2
LM26420
EN1
VOUT1
1.8 V/2 A
EN2
VOUT2
L1
0.8 V/2 A
L2
SW1
SW2
FB1
FB2
R2
R1
C1
R3
PGND1, PGND2,
AGND, DAP
C2
C6
R4
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Figure 34. LM26420-Q1 (2.2 MHz): VIN = 5 V, VOUT1 = 1.8 V at 2 A and VOUT2 = 0.8 V at 2 A
18
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Typical Applications (continued)
8.2.1.1 Design Requirements
Example requirements for typical synchronous DC/DC converter applications:
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
VOUT
Output voltage
VIN (minimum)
Maximum input voltage
VIN (maximum)
Minimum input voltage
IOUT (maximum)
Maximum output current
ƒSW
Switching frequency
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM26420-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
Table 2. Bill Of Materials
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
U1
2-A buck regulator
TI
LM26420-Q1
C3, C4
15 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J156M
C1
33 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J336M
C2, C6
22 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J226M
C5
0.47 µF, 10 V, 0805, X7R
Vishay
VJ0805Y474KXQCW1BC
L1
1.0 µH, 7.9 A
TDK
RLF7030T-1R0M6R4
L2
0.7 µH, 3.7 A
Coilcraft
LPS4414-701ML
R3, R4
10.0 kΩ, 0603, 1%
Vishay
CRCW060310K0F
R5, R6
49.9 kΩ, 0603, 1%
Vishay
CRCW060649K9F
R1
12.7 kΩ, 0603, 1%
Vishay
CRCW060312K7F
R7, R2
4.99 Ω, 0603, 1%
Vishay
CRCW06034R99F
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8.2.1.2.2 Inductor Selection
The duty cycle (D) can be approximated as the ratio of output voltage (VOUT) to input voltage (VIN):
D=
VOUT
VIN
(5)
The voltage drop across the internal NMOS (SW_BOT) and PMOS (SW_TOP) must be included to calculate a
more accurate duty cycle. Calculate D by using the following formulas:
D=
VOUT + VSW_BOT
VIN + VSW_BOT ± VSW_TOP
(6)
VSW_TOP and VSW_BOT can be approximated by:
VSW_TOP = IOUT × RDSON_TOP
VSW_BOT = IOUT × RDSON_BOT
(7)
(8)
The inductor value determines the output ripple voltage. Smaller inductor values decrease the size of the
inductor, but increase the output ripple voltage. An increase in the inductor value decreases the output ripple
current.
One must ensure that the minimum current limit (2.4 A) is not exceeded, so the peak current in the inductor must
be calculated. The peak current (ILPK) in the inductor is calculated by:
ILPK = IOUT + ΔiL
(9)
'i L
I OUT
VIN - VOUT
VOUT
L
L
DTS
TS
t
Figure 35. Inductor Current
VIN - VOUT
L
=
2'iL
DTS
(10)
In general,
ΔiL = 0.1 × (IOUT) → 0.2 × (IOUT)
(11)
If ΔiL = 20% of 2 A, the peak current in the inductor is 2.4 A. The minimum ensured current limit over all
operating conditions is 2.4 A. One can either reduce ΔiL, or make the engineering judgment that zero margin is
safe enough. The typical current limit is 3.3 A.
The LM26420-Q1 operates at frequencies allowing the use of ceramic output capacitors without compromising
transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple
voltage. See Output Capacitor section for more details on calculating output voltage ripple. Now that the ripple
current is determined, the inductance is calculated by:
L=
DTS
x (VIN - VOUT)
2'iL
(12)
Where
TS =
20
1
fS
(13)
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When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating.
Inductor saturation results in a sudden reduction in inductance and prevent the regulator from operating correctly.
The peak current of the inductor is used to specify the maximum output current of the inductor and saturation is
not a concern due to the exceptionally small delay of the internal current limit signal. Ferrite based inductors are
preferred to minimize core losses when operating with the frequencies used by the LM26420-Q1. This presents
little restriction because the variety of ferrite-based inductors is huge. Lastly, inductors with lower series
resistance (RDCR) provides better operating efficiency. For recommended inductors see Table 2.
8.2.1.2.3 Input Capacitor Selection
The input capacitors provide the AC current needed by the nearby power switch so that current provided by the
upstream power supply does not carry a lot of AC content, generating less EMI. To the buck regulator in
question, the input capacitor also prevents the drain voltage of the FET switch from dipping when the FET is
turned on, therefore providing a healthy line rail for the LM26420-Q1 to work with. Because typically most of the
AC current is provided by the local input capacitors, the power loss in those capacitors can be a concern. In the
case of the LM26420-Q1 regulator, because the two channels operate 180° out of phase, the AC stress in the
input capacitors is less than if they operated in phase. The measure for the AC stress is called input ripple RMS
current. It is strongly recommended that at least one 10µF ceramic capacitor be placed next to each of the VIND
pins. Bulk capacitors such as electrolytic capacitors or OSCON capacitors can be added to help stabilize the
local line voltage, especially during large load transient events. As for the ceramic capacitors, use X7R or X5R
types. They maintain most of their capacitance over a wide temperature range. Try to avoid sizes smaller than
0805. Otherwise significant drop in capacitance may be caused by the DC bias voltage. See Output Capacitor
section for more information. The DC voltage rating of the ceramic capacitor should be higher than the highest
input voltage.
Capacitor temperature is a major concern in board designs. While using a 10-µF or higher MLCC as the input
capacitor is a good starting point, it is a good idea to check the temperature in the real thermal environment to
make sure the capacitors are not overheated. Capacitor vendors may provide curves of ripple RMS current vs.
temperature rise, based on a designated thermal impedance. In reality, the thermal impedance may be very
different. So it is always a good idea to check the capacitor temperature on the board.
Because the duty cycles of the two channels may overlap, calculation of the input ripple RMS current is a little
tedious — use Equation 14:
Iirrms = (I1 - Iav )2 d1+ (I2 - Iav )2 d 2 + (I1 + I2 - Iav )2 d3
where
•
•
•
•
•
•
I1 is Channel 1's maximum output current
I2 is Channel 2's maximum output current
d1 is the non-overlapping portion of Channel 1's duty cycle D1
d2 is the non-overlapping portion of Channel 2's duty cycle D2
d3 is the overlapping portion of the two duty cycles.
Iav is the average input current
(14)
Iav= I1 × D1 + I2 × D2. To quickly determine the values of d1, d2 and d3, refer to the decision tree in Figure 36. To
determine the duty cycle of each channel, use D = VOUT/VIN for a quick result or use the following equation for a
more accurate result.
D=
VOUT + VSW_BOT + IOUT x RDC
VIN + VSW_BOT - VSW_TOP
where
•
RDC is the winding resistance of the inductor.
(15)
Example:
VIN = 5 V, VOUT1 = 3.3 V, IOUT1 = 2 A, VOUT2 = 1.2 V, IOUT2 = 1.5 A, RDS = 170 mΩ, RDC = 30 mΩ. (IOUT1 is the
same as I1 in the input ripple RMS current equation, IOUT2 is the same as I2).
First, find out the duty cycles. Plug the numbers into the duty cycle equation and we get D1 = 0.75, and D2 =
0.33. Next, follow the decision tree in Figure 36 to find out the values of d1, d2 and d3. In this case, d1 = 0.5, d2
= D2 + 0.5 – D1 = 0.08, and d3 = D1 – 0.5 = 0.25. Iav = IOUT1 × D1 + IOUT2 × D2 = 1.995 A. Plug all the numbers
into the input ripple RMS current equation and the result is IIR(rms) = 0.77 A.
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Figure 36. Determining D1, D2, And D3
8.2.1.2.4 Output Capacitor
The output capacitor is selected based upon the desired output ripple and transient response. The initial current
of a load transient is provided mainly by the output capacitor. The output ripple of the converter is approximately:
'VOUT = 'IL RESR +
1
8 x FSW x COUT
(16)
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple is approximately sinusoidal and 90° phase shifted from the switching action. Given the availability
and quality of MLCCs and the expected output voltage of designs using the LM26420-Q1, there is really no need
to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high
frequency noise. A certain amount of switching edge noise couples through parasitic capacitances in the inductor
to the output. A ceramic capacitor bypasss this noise while a tantalum capacitor does not. Because the output
capacitor is one of the two external components that control the stability of the regulator control loop, most
applications require a minimum of 22 µF of output capacitance. Capacitance often, but not always, can be
increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended
multilayer ceramic capacitors are X7R or X5R types.
8.2.1.2.5 Calculating Efficiency and Junction Temperature
The complete LM26420-Q1 DC/DC converter efficiency can be estimated in the following manner.
K=
POUT
PIN
(17)
Or
K=
POUT
POUT + PLOSS
(18)
Calculations for determining the most significant power losses follow here. Other losses totaling less than 2% are
not discussed.
Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction.
Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and
dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D):
D=
VOUT + VSW_BOT
VIN + VSW_BOT ± VSW_TOP
(19)
VSW_TOP is the voltage drop across the internal PFET when it is on, and is equal to:
VSW_TOP = IOUT × RDSON_TOP
22
(20)
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VSW_BOT is the voltage drop across the internal NFET when it is on, and is equal to:
VSW_BOT = IOUT × RDSON_BOT
(21)
If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes:
D=
VOUT + VSW_BOT + VDCR
VIN + VSW_BOT + VDCR ± VSW_TOP
(22)
Another significant external power loss is the conduction loss in the output inductor. The equation can be
simplified to:
PIND = IOUT2 × RDCR
(23)
The LM26420-Q1 conduction loss is mainly associated with the two internal FETs:
2
PCOND_TOP = (IOUT x D) 1 +
2
'iL
1
x
3
IOUT
PCOND_BOT = (IOUT x (1-D)) 1 +
2
'iL
1
x
3
IOUT
RDSON_TOP
2
RDSON_BOT
(24)
If the inductor ripple current is fairly small, the conduction losses can be simplified to:
PCOND_TOP = (IOUT2 × RDSON_TOP × D)
PCOND_BOT = (IOUT2 × RDSON_BOT × (1-D))
PCOND = PCOND_TOP + PCOND_BOT
(25)
(26)
(27)
Switching losses are also associated with the internal FETs. They occur during the switch on and off transition
periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss
is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node.
Switching Power Loss is calculated as follows:
PSWR = 1/2(VIN × IOUT × FSW × TRISE)
PSWF = 1/2(VIN × IOUT × FSW × TFALL)
PSW = PSWR + PSWF
(28)
(29)
(30)
Another loss is the power required for operation of the internal circuitry:
PQ = IQ × VIN
(31)
IQ is the quiescent operating current, and is typically around 8.4 mA (IQVINC = 4.7 mA + IQVIND = 3.7 mA) for the
550-kHz frequency option.
Due to Dead-Time-Control Logic in the converter, there is a small delay (~4 nsec) between the turn ON and OFF
of the TOP and BOTTOM FET. During this time, the body diode of the BOTTOM FET is conducting with a
voltage drop of VBDIODE (~0.65 V). This allows the inductor current to circulate to the output, until the BOTTOM
FET is turned ON and the inductor current passes through the FET. There is a small amount of power loss due
to this body diode conducting and it can be calculated as follows:
PBDIODE = 2 × (VBDIODE × IOUT × FSW × TBDIODE)
(32)
Typical Application power losses are:
PLOSS = ΣPCOND + PSW + PBDIODE + PIND + PQ
PINTERNAL = ΣPCOND + PSW+ PBDIODE + PQ
(33)
(34)
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Table 3. Power Loss Tabulation
DESIGN PARAMETER
VALUE
DESIGN PARAMETER
VALUE
VIN
5V
VOUT
1.2 V
IOUT
2A
POUT
2.4 W
FSW
550 kHz
VBDIODE
0.65 V
PBDIODE
5.7 mW
IQ
8.4 mA
PQ
42 mW
TRISE
1.5 nsec
PSWR
4.1 mW
TFALL
1.5 nsec
PSWF
4.1 mW
RDSON_TOP
75 mΩ
PCOND_TOP
81 mW
RDSON_BOT
55 mΩ
PCOND_BOT
167 mW
INDDCR
20 mΩ
PIND
80 mW
D
0.262
PLOSS
384 mW
η
86.2%
PINTERNAL
304 mW
These calculations assume a junction temperature of 25°C. The RDSON values are larger due to internal heating;
therefore, the internal power loss (PINTERNAL) must be first calculated to estimate the rise in junction temperature.
24
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8.2.1.3 Application Curves
VOUT = 1.2 V
25-100% Load Transient
VIN = 5 V
Figure 37. Load Transient Response
VIN = 5 V
VOUT = 1.8 V at 1 A
Figure 38. Start-Up (Soft Start)
VOUT = 1.8 V at 1 A
Figure 39. Enable - Disable
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8.2.2 2.2-MHz, 1.8-V Typical High-Efficiency Application Circuit
Vin
4.5 V to 5.5 V
C3
R7
C4
C5
R5
R6
VIN1
VINc
VIN2
PG1
PG2
LM26420
EN1
VOUT1
EN2
VOUT2
L1
3.3 V/2 A
1.8 V/2 A
L2
SW1
SW2
FB1
FB2
R1
R2
C1
PGND1, PGND2,
AGND, DAP
R3
C2
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 40. LM26420-Q1 (2.2 MHz): VIN = 5 V, VOUT1 = 3.3 V at 2 A and VOUT2 = 1.8 V at 2 A
8.2.2.1 Design Requirements
See Design Requirements above.
8.2.2.2 Detailed Design Procedure
Table 4. Bill Of Materials
26
PART ID
PART VALUE
MANUFACTURER
U1
2-A Buck Regulator
TI
LM26420-Q1
C3, C4
15 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J156M
C1
22 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J226M
C2
33 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J336M
C5
0.47 µF, 10 V, 0805, X7R
Vishay
VJ0805Y474KXQCW1BC
L1, L2
1.0 µH, 7.9 A
TDK
RLF7030T-1R0M6R4
R3, R4
10.0 kΩ, 0603, 1%
Vishay
CRCW060310K0F
R2
12.7 kΩ, 0603, 1%
Vishay
CRCW060312K7F
R5, R6
49.9 kΩ, 0603, 1%
Vishay
CRCW060649K9F
R1
31.6 kΩ, 0603, 1%
Vishay
CRCW060331K6F
R7
4.99 Ω, 0603, 1%
Vishay
CRCW06034R99F
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Also see Detailed Design Procedure above.
8.2.2.3 Application Curves
See Application Curves above.
8.2.3 LM26420-Q12.2-MHz, 2.5-V Typical High-Efficiency Application Circuit
Vin
3 V to 5.5 V
C3
R7
C4
C5
R5
R6
VIN1
VINc
VIN2
PG1
PG2
LM26420
EN1
VOUT1
EN2
VOUT2
L1
1.2 V/2 A
L2
SW1
SW2
FB1
FB2
R1
2.5 V/2 A
R2
C1
PGND1, PGND2,
AGND, DAP
R3
C2
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 41. LM26420-Q1 (2.2 MHz): VIN = 5 V, VOUT1 = 1.2 V at 2 A and VOUT2 = 2.5 V at 2 A
8.2.3.1 Design Requirements
See Design Requirements above.
8.2.3.2 Detailed Design Procedure
Table 5. Bill Of Materials
PART ID
PART VALUE
MANUFACTURER
U1
2-A buck regulator
TI
PART NUMBER
LM26420-Q1
C3, C4
15 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J156M
C1
33 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J336M
C2
22 µF, 6.3 V, 1206, X5R
TDK
C3216X5R0J226M
C5
0.47 µF, 10 V, 0805, X7R
Vishay
VJ0805Y474KXQCW1BC
L1
1.0 µH, 7.9A
TDK
RLF7030T-1R0M6R4
L2
1.5 µH, 6.5A
TDK
RLF7030T-1R5M6R1
R3, R4
10.0 kΩ, 0603, 1%
Vishay
CRCW060310K0F
R1
4.99 kΩ, 0603, 1%
Vishay
CRCW06034K99F
R5, R6
49.9 kΩ, 0603, 1%
Vishay
CRCW060649K9F
R2
21.5 kΩ, 0603, 1%
Vishay
CRCW060321K5F
R7
4.99 Ω, 0603, 1%
Vishay
CRCW06034R99F
Also see Detailed Design Procedure above.
8.2.3.3 Application Curves
See Application Curves above.
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9 Power Supply Recommendations
The LM26420-Q1 is designed to operate from an input voltage supply range between 3 V and 5.5 V. This input
supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LM26420-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is located more than a few inches from the LM26420-Q1, additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF
or 100-μF electrolytic capacitor is a typical choice.
LM26420-Q1 contains a high side PMOS FET and a low side NMOS FET as shown in Figure 42. The source
nodes of the high side PMOS FETs are connected to VIND1 and VIND2 respectively. VINC is the power source
for the high and low side gate drivers. Ideally, VINC is connected to VIND1 and VIND2 by an RC filter as detailed
in VINC Filtering Components . If VINC is allowed to be lower than VIND1 or VIND2, the high side PMOS FETs
may be turned on regardless of the state of the respective gate drivers. Under this condition, shoot through will
occur when the low side NMOS FET is turned on and permanent damage may result. When applying input
voltage to VINC, VIND1 and VIND2, VINC must not be less than VIND1,2 – VTH to avoid shoot through and FET
damage.
VIND1 or VIND2
VINC
UVLO
-
PMOS
+
+
High-side
Driver
Control
Circuit
NMOS
Low-side
Driver
Figure 42. VINC, VIND1 and VIND2 Connection
10 Layout
10.1 Layout Guidelines
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration is the close coupling of the GND connections of the input capacitor and the PGND
pin. These ground ends must be close to one another and be connected to the GND plane with at least two
through-holes. Place these components as close to the device as possible. Next in importance is the location of
the GND connection of the output capacitor, which must be near the GND connections of VIND and PGND.
There must be a continuous ground plane on the bottom layer of a two-layer board except under the switching
node island. The FB pin is a high impedance node, and care must be taken to make the FB trace short to avoid
noise pickup and inaccurate regulation. The feedback resistors must be placed as close to the device as
possible, with the GND of R1 placed as close to the GND of the device as possible. The VOUT trace to R2 must
be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN,
SW, and VOUT traces, so they must be as short and wide as possible. However, making the traces wide
increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by
choosing a shielded inductor. The remaining components must also be placed as close as possible to the device.
See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines for further considerations, and the LM26420-Q1
demo board as an example of a four-layer layout.
28
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Layout Guidelines (continued)
Figure 43. Internal Connection
For certain high power applications, the PCB land may be modified to a dog bone shape (see Figure 44). By
increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced.
10.2 Layout Example
VIN
CINC
RINC
L1
Place bypass cap close
to VINC and DAP
VINC
1
20
AGND
EN1
2
19
EN2
VIND1
3
18
VIND1
4
17
SW1
5
16
Place ceramic
VIND2 bypass caps close to
VIND and PGND pins
VIND2
L2
CIN2
SW2
PGND1
6
15
PGND2
PGND1
7
14
PGND2
FB1
8
13
FB2
PG1
9
12
PG2
CIN1
COUT1
COUT2
VOUT2
VOUT1
RFBT1
VOUT distribution
point is away
from inductor
and past COUT
RFBB1
Thermal Vias under DAP
DAP
10
RFBT2
RFBB2
11
DAP
GND
GND
As much copper area as possible for GND, for better thermal performance
Figure 44. Typical Layout For DC/DC Converter
10.3 Thermal Considerations
TJ = Chip junction temperature
TA = Ambient temperature
RθJC = Thermal resistance from chip junction to device case
RθJA = Thermal resistance from chip junction to ambient air
Heat in the LM26420-Q1 due to internal power dissipation is removed through conduction and/or convection.
Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the
transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs conductor).
Heat Transfer goes as:
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Thermal Considerations (continued)
Silicon → package → lead frame → PCB
Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural
convection occurs when air currents rise from the hot device to cooler air.
Thermal impedance is defined as:
RT =
'T
Power
(35)
Thermal impedance from the silicon junction to the ambient air is defined as:
RTJA =
TJ - TA
PINTERNAL
(36)
The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can
greatly affect RθJA. The type and number of thermal vias can also make a large difference in the thermal
impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to
the ground plane. Five to eight thermal vias must be placed under the exposed pad to the ground plane if the
WQFN package is used. Up to 12 thermal vias must be used in the HTSSOP-20 package for optimum heat
transfer from the device to the ground plane.
Thermal impedance also depends on the thermal properties of the application's operating conditions (VIN, VOUT,
IOUT, etc.), and the surrounding circuitry.
10.3.1 Method 1: Silicon Junction Temperature Determination
To accurately measure the silicon temperature for a given application, two methods can be used. The first
method requires the user to know the thermal impedance of the silicon junction to top case temperature.
Some clarification needs to be made before we go any further.
RθJC is the thermal impedance from silicon junction to the exposed pad.
RθJT is the thermal impedance from top case to the silicon junction.
In this data sheet RθJT is used so that it allows the user to measure top case temperature with a small
thermocouple attached to the top case.
RθJT is approximately 20°C/W for the 16-pin WQFN package with the exposed pad. Knowing the internal
dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically
measured on the bench we have:
RTJT =
TJ - TT
PINTERNAL
(37)
Therefore:
TJ = (RθJT × PINTERNAL) + TC
(38)
From the previous example:
TJ = 20°C/W × 0.304W + TC
(39)
10.3.2 Thermal Shutdown Temperature Determination
The second method, although more complicated, can give a very accurate silicon junction temperature.
The first step is to determine RθJA of the application. The LM26420-Q1 has over-temperature protection circuitry.
When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a
hysteresis of about 15°C. Once the silicon junction temperature has decreased to approximately 150°C, the
device starts to switch again. Knowing this, the RθJA for any application can be characterized during the early
stages of the design one may calculate the RθJA by placing the PCB circuit into a thermal chamber. Raise the
ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW pin is
monitored, it is obvious when the internal FETs stop switching, indicating a junction temperature of 165°C.
Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient
temperature RθJA can be determined.
30
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Thermal Considerations (continued)
RTJA =
165° - T A
PINTERNAL
(40)
Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be
found.
An example of calculating RθJA for an application using the LM26420-Q1 WQFN demonstration board is shown
below.
The four layer PCB is constructed using FR4 with 1 oz copper traces. The copper ground plane is on the bottom
layer. The ground plane is accessed by eight vias. The board measures 3 cm × 3 cm. It was placed in an oven
with no forced airflow. The ambient temperature was raised to 152°C, and at that temperature, the device went
into thermal shutdown.
From the previous example:
PINTERNAL = 304 mW
RTJA =
(41)
165oC - 152oC
= 42.8o C/W
304 mW
(42)
If the junction temperature was to be kept below 125°C, then the ambient temperature could not go above
112°C.
TJ – (RθJA × PINTERNAL) = TA
125°C – (42.8°C/W × 304 mW) = 112.0°C
(43)
(44)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM26420-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
32
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11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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33
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM26420Q0XMH/NOPB
ACTIVE
HTSSOP
PWP
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM26420
Q0XMH
LM26420Q0XMHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM26420
Q0XMH
LM26420Q1XMH/NOPB
ACTIVE
HTSSOP
PWP
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM26420
Q1XMH
LM26420Q1XMHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM26420
Q1XMH
LM26420Q1XSQ/NOPB
ACTIVE
WQFN
RUM
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
L26420Q
LM26420Q1XSQX/NOPB
ACTIVE
WQFN
RUM
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
L26420Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM26420-Q1 :
• Catalog: LM26420
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM26420Q0XMHX/NOPB HTSSOP
PWP
20
2500
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
LM26420Q1XMHX/NOPB HTSSOP
PWP
20
2500
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
LM26420Q1XSQ/NOPB
WQFN
RUM
16
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM26420Q1XSQX/NOPB
WQFN
RUM
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM26420Q0XMHX/NOPB
HTSSOP
PWP
20
2500
367.0
367.0
35.0
LM26420Q1XMHX/NOPB
HTSSOP
PWP
20
2500
367.0
367.0
35.0
LM26420Q1XSQ/NOPB
WQFN
RUM
16
1000
210.0
185.0
35.0
LM26420Q1XSQX/NOPB
WQFN
RUM
16
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RUM0016A
SQB16A (Rev A)
www.ti.com
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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