Texas Instruments | TPS25982 2.7 V to 24 V, 15-A, 2.7-mΩ Smart eFuse With 1.5% Accurate Load Current Monitoring and Adjustable Transient Fault Management (Rev. A) | Datasheet | Texas Instruments TPS25982 2.7 V to 24 V, 15-A, 2.7-mΩ Smart eFuse With 1.5% Accurate Load Current Monitoring and Adjustable Transient Fault Management (Rev. A) Datasheet

Texas Instruments TPS25982 2.7 V to 24 V, 15-A, 2.7-mΩ Smart eFuse With 1.5% Accurate Load Current Monitoring and Adjustable Transient Fault Management (Rev. A) Datasheet
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TPS25982
SLVSEI3A – OCTOBER 2018 – REVISED JUNE 2019
TPS25982 2.7 V to 24 V, 15-A, 2.7-mΩ Smart eFuse With 1.5% Accurate Load Current
Monitoring and Adjustable Transient Fault Management
1 Features
3 Description
•
The TPS25982 family of eFuses is a highly integrated
circuit protection and power management solution in
a small package. The devices are operational over a
wide input voltage range. A single part caters to lowvoltage systems needing minimal I*R voltage drop as
well as higher voltage, high current systems needing
low power dissipation. They are a robust defense
against overloads, short-circuits, voltage surges and
excessive inrush current.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide input voltage range: 2.7 V to 24 V
– 30-V Absolute maximum
Low On-Resistance: RON = 2.7-mΩ typical
Adjustable current limit threshold
– Range: 2 A to 15 A
– Accuracy: ± 8% (typical for ILIM > 5 A)
Circuit breaker and current limiter options
Adjustable overcurrent blanking timer
– Handles load transients without tripping
Accurate current monitor output
– ± 1.5% (typical at 25 °C for IOUT > 3 A)
User configurable fault response
– Latch-off or auto-retry
– Number of retries (Finite or indefinite)
– Delay between retries
Robust short-circuit protection
– Fast-trip response time < 400-ns typical
– Tested against 1 million power-into-short
events
– Immune to line transients - no nuisance
tripping
Adjustable output slew rate (dVdt) control
Adjustable undervoltage lockout
Overvoltage lockout (Fixed 3.7-V, 7.6-V, 16.9-V
and no-OVLO options)
Integrated overtemperature protection
Power good indication
Adjustable load detect and handshake timer
UL 2367 Recognition (pending)
IEC 62368 CB Certification (pending)
Small footprint: 4-mm × 4-mm QFN package
2 Applications
•
•
•
•
•
Hot-Swap, hot-plug
Server standby rail, PCIe riser, add-on card and
fan module protection
Routers and switches optical module protection
Industrial PC
Digital TV
Overvoltage events are limited by internal cutoff
circuits, with multiple device options to choose the
overvoltage threshold.
Multiple device options exist to choose between the
response to overcurrent conditions, circuit breaker or
active current limiter. The overcurrent limit and fasttrip (short-circuit) threshold can be set with a single
external resistor. The devices intelligently manage the
overcurrent response by distinguishing between
transient events and actual faults, thereby allowing
the system to function uninterrupted during line and
load transients without compromising on the
robustness of the protection against faults. The
device can be configured to stay latched off or retry
automatically after a fault shutdown. The number of
auto-retries as well as the retry delay are configurable
with capacitors. This enables remote systems to
automatically recover from temporary faults while
ensuring that power supplies are not stressed
indefinitely due to a persistent fault.
The TPS25982 devices are available in a small 4 mm
× 4 mm QFN package. The devices are characterized
for operation over a junction temperature range of
–40˚C to 125˚C.
Device Information(1)
PART NUMBER
TPS25982
PACKAGE
QFN (24)
BODY SIZE (NOM)
4.0 mm × 4.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematics
TPS25982
Power
Supply
IN
OUT
CIN
RPG
EN/UVLO
PG
NRETRY
IMON
RETRY_DLY
RVL2
VPG
LDSTRT
RVL1
C*
NRETRY
C*
LDSTRT
C*
RETRY_DLY
ILIM
CL
dVdt
CdVdt
RILIM
RL
GND ITIMER
C*
ITIMER
RIMON
* Optional components for extended functionality
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25982
SLVSEI3A – OCTOBER 2018 – REVISED JUNE 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements ................................................ 8
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Fault Response ......................................................
17
17
18
27
8.5 Device Functional Modes........................................ 29
9
Application and Implementation ........................ 31
9.1 Application Information............................................ 31
9.2 Typical Application: Standby Power Rail Protection in
Datacenter Servers ................................................. 31
9.3 System Examples ................................................... 38
10 Power Supply Recommendations ..................... 42
10.1 Transient Protection .............................................. 42
10.2 Output Short-Circuit Measurements ..................... 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 45
12 Device and Documentation Support ................. 46
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
47
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
4 Revision History
Changes from Original (October 2018) to Revision A
•
2
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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5 Device Comparison Table
PART NUMBER
OVERVOLTAGE LOCKOUT
THRESHOLD
OVER CURRENT RESPONSE
TYPICAL (V)
TPS259822LNRGE
3.7
Active Current Limiter
TPS259823LNRGE
7.6
Active Current Limiter
TPS259824LNRGE
16.9
Active Current Limiter
TPS259827LNRGE
No OVLO
Active Current Limiter
TPS259822ONRGE
3.7
Circuit Breaker
TPS259823ONRGE
7.6
Circuit Breaker
TPS259824ONRGE
16.9
Circuit Breaker
TPS259827ONRGE
No OVLO
Circuit Breaker
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6 Pin Configuration and Functions
RGE
24-Pin QFN
Top View
20
OUT 19
OUT
21
23
OUT
OUT
24
OUT 22
OUT
18 OUT
IN
1
IN
2
IN
3
16 IN
GND
4
15 dVdt
GND
5
EN/UVLO
6
17 OUT
IN
Thermal Pad 1
14 GND
GND
Thermal Pad 2
13 PG
12
LDSTRT
11 NRETRY
IMON
10 RETRY_DLY
9
ILIM
ITIMER
8
7
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
OUT
17, 18, 19,
20, 21, 22,
23, 24
Power
IN
1, 2, 3, 16,
Pad 1
Thermal /
Power
4, 5, 14,
Pad 2
Ground
6
Analog Input
ITIMER
7
Analog
Output
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
output current can temporarily exceed set current limit (but lower than fast-trip threshold)
before the device overcurrent response takes action. Leave this pin open for fastest
response to overcurrent events. Refer to ITIMER Functional Mode Summary for more
details.
ILIM
8
Analog
Output
An external resistor from this pin to GND sets the output current limit threshold and fast trip
threshold. Do not leave floating.
IMON
9
Analog
Output
Analog output load current monitor. This pin sources a current proportional to the load
current. This can be converted to a voltage signal by connecting an appropriate resistor from
this pin to GND.
RETRY_DLY
10
Analog
Output
A capacitor from this pin to GND sets the time period that has to elapse after a fault
shutdown before the device attempts to restart automatically. Connect this pin to GND for
latch-off operation (no auto-retries) after a fault. Refer to Fault Response section for more
details.
NRETRY
11
Analog
Output
A capacitor from this pin to GND sets the number of times the part attempts to restart
automatically after shutdown due to fault. Connect this pin to GND if the part should retry
indefinitely. Refer to Fault Response section for more details.
GND
EN/UVLO
4
Power Output
Power Input. The exposed pad must be soldered to input power plane uniformly to ensure
proper heat dissipation and to maintain optimal current distribution through the device.
Connect to System Ground
Active High Enable for the device. A resistor divider on this pin from input supply to GND can
be used to adjust the Undervoltage Lockout threshold. Do not leave floating.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
Load Detect/Handshake Signal. A capacitor from this pin to GND sets the time period after
PG assertion within which the pin has to be pulled low for the device to remain ON. Connect
to GND if the load detect/handshake feature is not used. Refer to Load Detect/Handshake
(LDSTRT) section for more details. Do not leave floating.
LDSTRT
12
Analog Input
PG
13
Active High Power Good Indication. This pin is asserted when the FET is fully enhanced and
Digital Output output has reached maximum voltage. It is an open drain output that requires an external
pull-up resistor to an external supply. This pin remains logic low when VIN < VUVP.
dVdt
15
Analog
Output
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for
the fastest slew rate during start up.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Parameter
Pin
MIN
MAX UNIT
VIN
Maximum Input Voltage Range
IN
–0.3
30
V
VOUT
Maximum Output Voltage Range
OUT
–0.8
min (30V, VIN + 0.3)
V
VEN/UVLO
Maximum Enable Pin Voltage Range
EN/UVLO
–0.3
7
V
VLDSTRT
Maximum LDSTRT Pin Voltage Range
LDSTRT
7
V
VdVdt
Maximum dVdt Pin Voltage Range
dVdt
VPG
Maximum PG Pin Voltage Range
PG
VITIMER
Maximum ITIMER Pin Voltage Range
ITIMER
Internally Limited
V
VNRETRY
Maximum NRETRY Pin Voltage Range
NRETRY
Internally Limited
V
VRETRY_DLY
Maximum RETRY_DLY Pin Voltage Range
RETRY_DLY
Internally Limited
V
IMAX
Maximum Continuous Switch Current
IN to OUT
Internally Limited
A
TJ
Junction temperature
TLEAD
Maximum Soldering Temperature
Tstg
Storage temperature
(1)
Internally Limited
V
–0.3
7
V
Internally Limited
°C
–65
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
± 2000
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins (2)
± 1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
UNIT
VIN
Input Voltage Range
IN
VOUT
Output Voltage Range
OUT
VEN/UVLO
Enable Pin Voltage Range
EN/UVLO
VLDSTRT
LDSTRT Pin Capacitor Voltage Rating
LDSTRT
VdVdT
dVdT Pin Capacitor Voltage Rating
dVdt
VPG
PG Pin Voltage Range
PG
VITIMER
ITIMER Pin Capacitor Voltage Rating
ITIMER
4
V
VNRETRY
NRETRY Pin Capacitor Voltage Rating
NRETRY
4
V
VRETRY_DLY
RETRY_DLY Pin Capacitor Voltage Rating
RETRY_DLY
4
RILIM
ILIM Pin Resistor
ILIM
IMAX
Continuous Switch Current
IN to OUT
TJ
Junction temperature
(1)
(2)
2.7
MAX
24
V
VIN + 0.3
V
6 (1)
V
4
V
VIN + 4
V
6 (2)
V
V
Ω
82
1650
15
A
–40
125
°C
For supply voltages below 6V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 6V, it is recommended
to use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits.
For supply voltages below 6V, it is okay to pull up the PG pin to IN/OUT through a resistor. For supply voltages greater than 6V, it is
recommended to use a stepped down power supply to ensure the voltage at the PG pin is within the specified limits.
7.4 Thermal Information
TPS25982X
THERMAL METRIC (1)
(2)
RGE (QFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.7
°C/W
RθJB
Junction-to-board thermal resistance
11.2
°C/W
ΨJT
Junction-to-top characterization parameter
3
°C/W
ΨJB
Junction-to-board characterization parameter
11.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.6
°C/W
(1)
(2)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with minimum recommended pad size (2 oz
Cu) and 3x2 via array.
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7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for
TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
24
V
800
1200
µA
VSD < VEN < VUVLO
204
300
µA
VEN < VSD
3.67
20
µA
INPUT SUPPLY (IN)
VIN
Input Voltage Range
IQ
IN Quiescent Current
ISD
IN Shutdown Current
VUVP
IN Undervoltage Protection
Threshold
2.7
VEN ≥ VUVLO(R)
VIN Rising
2.46
2.53
2.6
V
VIN Falling
2.35
2.42
2.49
V
TPS259822x, VIN Rising
3.62
3.7
3.76
V
TPS259823x, VIN Rising
7.39
7.6
7.76
V
TPS259824x, VIN Rising
16.32
16.9
17.31
V
TPS259822x, VIN Falling
3.52
3.6
3.66
V
TPS259823x, VIN Falling
7.22
7.4
7.55
V
TPS259824x, VIN Falling
15.80
16.4
16.81
V
3 A ≤ IOUT ≤ min(15 A, ILIM), –40 °C ≤
TA ≤ 75 °C
238.6
246
253.4
µA/A
RILIM = 773 Ω, TJ = 25 ℃
1.76
2
2.17
A
RILIM = 773 Ω, TJ = -40 to 125 ℃
1.53
2
2.43
A
RILIM = 300 Ω, TJ = 25 ℃
4.75
4.98
5.23
A
RILIM = 300 Ω, TJ = -40 to 125 ℃
4.36
4.98
5.66
A
RILIM = 182 Ω, TJ = 25 ℃
7.77
8.13
8.54
A
RILIM = 182 Ω, TJ = -40 to 125 ℃
7.23
8.13
9.07
A
RILIM = 100 Ω, TJ = 25 ℃
13.56
14.71
15.66
A
RILIM = 100 Ω, TJ = -40 to 125 ℃
12.85
14.71
15.99
A
OVERVOLTAGE PROTECTION (IN)
VOVP(R)
Overvoltage Protection Threshold
VOVP(F)
OUTPUT CURRENT MONITOR (IMON)
GIMON
Current Monitor Gain (IIMON:IOUT)
OUTPUT CURRENT LIMIT (ILIM)
ILIM
IOUT Current Limit Threshold
RILIM = Open
ICB
IOUT Circuit Breaker Threshold
During ILIM pin Short to GND
Condition (Single point failure)
ISC
Short-circuit Fast Trip Threshold
0
RILIM = Short to GND, TJ = 25 ℃
A
20
210
A
% ILIM
ON-RESISTANCE (IN - OUT)
RON
TJ = 25 ℃, IOUT = 2 A
ON State Resistance
2.7
TJ = -40 to 125 ℃, IOUT = 2 A
3.2
mΩ
4.5
mΩ
ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VEN Rising
1.18
1.2
1.23
V
VEN Falling
1.08
1.1
1.13
V
VSD
EN/UVLO Pin Voltage Threshold for
VEN Falling
Lowest Shutdown Current
0.59
0.8
IENLKG
EN/UVLO Pin Leakage Current
VUVLO(F)
EN/UVLO Pin Voltage Threshold
V
0.1
µA
786
mV
POWER GOOD INDICATION (PG)
VPGD
PG Pin Low Voltage (PG deasserted)
IPGLKG
PG Pin Leakage Current (PG
asserted)
RON(PGA)
RON When PG is asserted
VIN < VUVP, VEN < VSD, IPG = 26 µA
651
VIN = 3.3V, IPG ≤ 5 mA
320
mV
VIN ≥ 5V, IPG ≤ 5 mA
100
mV
PG pulled up to 5 V through 10 kΩ
1.7
4.2
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Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS259824x/7x, 5 V for TPS259823x, 3.3 V for
TPS259822x, VEN/UVLO = 2 V, RILIM = 1650 Ω , CdVdT = Open, OUT = Open. All voltages referenced to GND.
PARAMETER
TEST CONDITIONS
VIN - VOUT Threshold when PG is
de-asserted
VPGTHD
MIN
TYP
MAX
UNIT
0.224
0.326
0.450
V
AUTO-RETRY DELAY INTERVAL (RETRY_DLY)
VRETRY_DLY(R)
VRETRY_DLY(F)
RETRY_DLY Oscillator Comparator
Threshold
VRETRY_DLY_HY
RETRY_DLY Oscillator Hysteresis
1.1
V
0.35
V
0.65
0.75
0.85
V
1.7
2.05
2.5
µA
S
IRETRY_DLY
RETRY_DLY Pin Bias Current
NUMBER OF AUTO-RETRIES (NRETRY)
VNRETRY(R)
VNRETRY(F)
NRETRY Oscillator Comparator
Threshold
VNRETRY_HYS
NRETRY Oscillator Hysteresis
INRETRY
NRETRY Pin Bias Current
1.1
V
0.35
V
0.65
0.75
0.85
V
1.7
2.05
2.5
µA
1.4
2.1
2.8
µA
CURRENT FAULT TIMER (ITIMER)
IITIMER
ITIMER Discharge Current
ISC > IOUT > ILIM
RITIMER
ITIMER Internal Pull-up Resistance
IOUT < ILIM
23
kΩ
VINT
ITIMER Pin Default Voltage
IOUT < ILIM
2.5
V
VITIMER
ITIMER Comparator Falling
Threshold
ISC > IOUT > ILIM, ITIMER Voltage Rising
1.53
V
ΔVITIMER
ITIMER Comparator Voltage
Threshold Delta
ISC > IOUT > ILIM, ITIMER Voltage Falling
0.7
0.98
1.3
VLDSTRT
LDSTRT Rising Threshold
LDSTRT voltage rising
1.1
1.21
1.3
V
ILDSTRT
LDSTRT Charging Current
PG asserted
1.7
2.05
2.4
µA
RLDSTRT
LDSTRT Internal Pull-down
Resistance
V
LDSTRT
31
Ω
OVERTEMPERATURE PROTECTION
TSD
Thermal Shutdown Threshold
TJ Rising
150
°C
TSDHys
Thermal Shutdown Hysteresis
TJ Falling
10
°C
dVdt
IdVdt
dVdt Pin Charging Current
3.88
4.6
6.33
µA
7.6 Timing Requirements
PARAMETER
tOVP
Overvoltage Protection Response Time
tLIM
Current Limit Response Time
tSC
Short Circuit Response Time
tPGD
(1)
(2)
(3)
8
TEST CONDITIONS
(2)
PG Assertion/De-assertion De-glitch
(3)
(1)
MIN
TYP MAX
UNIT
VIN > VOVLO(R) to VOUT↓, TPS259822x
1.5
µs
VIN > VOVLO(R) to VOUT↓, TPS259823x
5
µs
VIN > VOVLO(R) to VOUT↓, TPS259824x
5
µs
IOUT > ILIM + 30% and ITIMER expired to
IOUT ≤ ILIM
270
µs
IOUT > 3 x ILIM to VOUT turned OFF
400
ns
VG > (VIN + 3.6V) to PG↑ or (VIN - VOUT)>
VPGTHD to PG↓
120
µs
Please refer to Fig. 43
Please refer to Fig. 45
Please refer to Fig. 47
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7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section
for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance
(COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is
available in steady state condition and the load voltage is completely discharged before the device is enabled.Typical Values
are taken at TJ = 25°C unless specifically noted otherwise. RL = 3.6 Ω, COUT = 1 mF
PARAMETER
SRON
tD,ON
tR
tON
tD,OFF
VIN
Output Rising slew rate
Turn on delay
Rise time
Turn on time
Turn off delay
CdVdt = Open
CdVdt = 3300pF
CdVdt =
6800pF
2.7 V
6.26
1.39
0.68
12 V
7.35
1.4
0.68
24 V
7.4
1.4
0.68
2.7 V
1.3
1.49
1.7
12 V
1.24
2.1
3.01
24 V
1.2
2.91
4.74
2.7 V
0.67
1.63
3.35
12 V
1.35
6.99
14.41
24 V
2.66
13.77
28.41
2.7 V
1.97
3.12
5.05
12 V
2.59
9.09
17.42
24 V
3.86
16.68
33.15
2.7 V
151
152
152
12 V
212
212
212
24 V
262
262
262
UNIT
V/ms
ms
ms
ms
µs
VEN/UVLO
VUVLO(R)
EN/UVLO
VUVLO(F)
0
tD,OFF
tON
VIN
90%
SRON
OUT
10%
0V
tR
tD,ON
tF
Time
Figure 1. TPS25982 Switching Times
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7.8 Typical Characteristics
4
3.6
RON (m:)
3.4
3.2
2.56
VIN
2.7 V
3.3 V
5V
12 V
24 V
2.54
2.52
2.5
VUVP (V)
3.8
3
2.8
2.48
Rising
Falling
2.46
2.6
2.44
2.4
2.42
2.2
2
-40
-20
0
20
40
60
TJ (qC)
80
100
120
2.4
-40
140
-20
0
20
D006
Figure 2. ON Resistance vs Temperature
40
60
TJ (qC)
80
100
120
140
D007
Figure 3. Supply UVP Threshold vs Temperature
3.7
7.625
7.6
3.68
7.575
Rising
Falling
Rising
Falling
7.55
VOVP (V)
VOVP (V)
3.66
3.64
7.525
7.5
7.475
3.62
7.45
7.425
3.6
7.4
3.58
-40
-20
0
20
40
60
TJ (qC)
80
100
120
7.375
-40
140
-20
0
20
D001
40
60
TJ (qC)
80
Figure 5. Supply OVP Threshold vs Temperature
1.21
16.85
1.2
16.8
1.19
16.75
Rising
Falling
1.18
1.17
VUVLO (V)
16.7
VOVP (V)
140
TPS259823x Variants
16.9
16.65
16.6
16.55
1.16
Rising
Falling
1.15
1.14
16.5
16.45
1.13
16.4
1.12
16.35
1.11
16.3
-40
120
D003
TPS259822x Variants
Figure 4. Supply OVP Threshold vs Temperature
100
-20
0
20
40
60
TJ (qC)
80
100
120
1.1
-40
140
-20
0
20
D009
40
60
TJ (qC)
80
100
120
140
D008
TPS259824x Variants
Figure 6. Supply OVP Threshold vs Temperature
Figure 7. EN/UVLO Threshold vs Temperature
0.875
900
875
0.85
0.825
825
0.8
800
0.775
VSD(F) (V)
Iq (PA)
850
VIN
2.7 V
12 V
24 V
775
750
0.75
0.725
725
0.7
700
0.675
0.65
675
650
-40
VIN
3.3 V
12 V
24 V
-20
0
20
40
60
TJ (qC)
80
100
120
140
0.625
-40
D002
-20
0
20
40
60
TJ (qC)
80
100
120
140
D014
VENUVLO = 2 V, OUT = Open
Figure 8. Quiescent Current vs Temperature
10
Figure 9. EN/UVLO Falling Threshold for Lowest Current
Consumption
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240
235
230
225
220
215
210
205
200
195
190
185
180
175
170
165
160
-40
12
VIN
2.7 V
12 V
24 V
VIN
2.7 V
12 V
24 V
10
8
Isd (PA)
Isd (PA)
Typical Characteristics (continued)
6
4
2
-20
0
20
40
60
TJ(qC)
80
100
120
0
-40
140
-20
0
20
40
60
TJ (qC)
D004
VENUVLO = 1 V, OUT = Open
25
18
20
16
15
14
10
10
8
6
120
140
D005
Figure 11. Deep Shut-Down Current vs Temperature
20
12
100
VENUVLO = 0 V, OUT = Open
ILIM Accuracy (%)
ILIM (A)
Figure 10. Shut-Down Current vs Temperature
80
MIN
MAX
5
0
-5
-10
4
-15
2
-20
-25
0
0
200
400
600
0
800 1000 1200 1400 1600 1800
RILIM (:)
D010
2
4
6
8
ILIM (A)
10
12
14
16
D011
Across Process, Voltage, Temperature Corners
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
Figure 13. Output Current Limit (ILIM) Accuracy
900
IPG
26uA
242uA
850
800
VPG (mV)
IMON Accuracy (%)
Figure 12. Output Current Limit (ILIM) vs RILIM
MIN
MAX
750
700
650
600
550
0
2
4
6
8
IOUT (A)
10
12
14
500
-40
16
-20
0
20
D012
40
60
TJ (qC)
80
100
120
140
D015
VIN = 0 V
Figure 14. Output Current Monitor Gain (GIMON) Accuracy
Figure 15. Power Good Output Voltage (De-asserted State)
vs Temperature
1.0025
2.2
1
2.18
0.9975
2.16
0.995
2.14
0.9925
2.12
IITIMER (PA)
'VITIMER (V)
Across Process, Voltage, Temperature Corners, Normalized to
mean value of 246 μA/A
0.99
0.9875
0.985
0.9825
0.9775
0.975
-40
-20
0
20
40
60
TJ (qC)
80
100
120
2.06
2.04
VIN
2.7 V
12 V
24 V
0.98
2.1
2.08
VIN
2.7 V
12 V
24 V
2.02
2
1.98
-40
140
D016
Figure 16. ITIMER Voltage Threshold Delta vs Temperature
-20
0
20
40
60
TJ (qC)
80
100
120
140
D019
Figure 17. ITIMER Discharge Current vs Temperature
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Typical Characteristics (continued)
1.215
2.16
VIN
2.7 V
12 V
24 V
2.14
1.213
2.1
VLDSTRT (V)
ILDSTRT (PA)
2.12
2.08
2.06
1.211
1.209
2.04
VIN
2.7 V
12 V
24 V
2.02
2
1.98
-40
-20
0
20
40
60
TJ (qC)
80
100
120
1.207
1.205
-40
140
Figure 18. LDSTRT Charging Current vs Temperature
IRETRY_DLY (PA)
IDVDT (PA)
2.12
4.6
4.4
VIN
2.7 V
12 V
24 V
4.2
-20
0
20
40
60
TJ (qC)
80
100
120
140
D021
120
2.1
2.06
2.04
2
140
-20
0
20
D022
40
60
TJ (qC)
80
100
120
140
D024
Figure 21. RETRY_DLY Bias Current vs Temperature
2.14
VIN
2.7 V
12 V
24 V
0.758
0.756
2.12
2.1
0.754
INRETRY (PA)
VRETRY_DLY_HYS (V)
100
2.08
1.98
-40
0.76
0.752
0.75
0.748
2.08
2.06
2.04
2.02
0.746
0.744
2
0.742
1.98
-20
0
20
40
60
TJ (qC)
80
100
120
VIN
2.7 V
12 V
24 V
1.96
-40
140
-20
0
D025
Figure 22. RETRY_DLY Oscillator Hysteresis vs
Temperature
20
40
60
TJ (qC)
80
100
120
140
D027
Figure 23. NRETRY Bias Current vs Temperature
0.76
1000
0.75
Time to Thermal Shutdown (ms)
VIN
3.3 V
12 V
24 V
0.755
VNRETRY_HYS (V)
80
2.02
Figure 20. DVDT Charging Current vs Temperature
0.745
0.74
0.735
0.73
0.725
TA
-40 qC
27 qC
85 qC
125 qC
500
300
200
100
50
30
20
10
5
3
2
1
-20
0
20
40
60
TJ (qC)
80
100
120
140
0
D026
Figure 24. NRETRY Oscillator Hysteresis vs Temperature
12
40
60
TJ (qC)
VIN
2.7 V
12 V
24 V
2.14
0.72
-40
20
2.16
4.8
0.74
-40
0
Figure 19. LDSTRT Threshold Voltage vs Temperature
5
4
-40
-20
D020
4
8
12
16
20
24
28
Power Dissipation (W)
32
36
40
D023
Figure 25. Thermal Shutdown Plot - Steady State
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Typical Characteristics (continued)
Time to Thermal Shutdown (ms)
200
TPS259827x
TPS259822x/23x/24x
100
50
30
20
10
5
3
2
1
0.5
2
3
4 5 6 7 8 10
20
30 40 50
Power Dissipation (W)
70
100
D002
Figure 26. Thermal Shutdown Plot - Inrush/Overload
CIN = 1 μF
COUT = 220 μF
CdVdt = 3.3 nF
Figure 27. Hotplug
COUT = 220 μF
CdVdt = 3.3 nF
COUT = 220 μF
CdVdt = 10 nF
ROUT = Open
Figure 28. Startup With EN - dVdt Limited
ROUT = 6 Ω
TPS259824x (16.7-V OVP variant)
Figure 29. Startup With EN Into Resistive Load - dVdt
Limited
Figure 30. Overvoltage Protection
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Typical Characteristics (continued)
RILIM = 100 Ω
CITIMER = Open
RILIM = 100 Ω
Figure 31. Current Limit Without Transient Overcurrent
Blanking
RILIM = 100 Ω
CITIMER = 4.7 nF
RETRY_DLY =
Short to GND
Figure 33. Current Limit Followed By Thermal Shutdown Latch-off
14
CITIMER = 4.7 nF
Figure 32. Current Limit With Transient Overcurrent
Blanking
RILIM = 100 Ω
CITIMER = 4.7 nF
CRETRY_DLY = 1 nF,
CNRETRY = Open
Figure 34. Current Limit Followed By Thermal Shutdown Auto-Retry
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Typical Characteristics (continued)
RILIM = 100 Ω
CITIMER = 4.7 nF
RILIM = 100 Ω
CRETRY_DLY = Open,
CNRETRY = Open
Figure 36. Circuit Breaker - Auto-Retry
Figure 35. Circuit Breaker With Transient Overcurrent
Blanking
RILIM = 100 Ω
CITIMER = 4.7 nF
RILIM = 100 Ω
Figure 37. Power Up Into Output Short-Circuit
Figure 38. Output Hard Short-Circuit While ON
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Typical Characteristics (continued)
RILIM = 100 Ω
RILIM = 332 Ω
Figure 39. Output Hard Short-Circuit While ON (Zoomed In)
Figure 40. Supply Line Transient Immunity - Input Voltage
Step
RILIM = 511 Ω
Figure 41. Supply Line Transient Immunity - Adjacent Load Hot Unplug
16
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8 Detailed Description
8.1 Overview
The TPS25982 device is a smart eFuse with integrated power switch that is used to manage load voltage and
load current. The device starts its operation by monitoring the IN bus. When VIN is above the Undervoltage
Protection threshold (VUVP) and below the Overvoltage Protection threshold (VOVP), the device samples the
EN/UVLO pin. A high level on this pin enables the internal MOSFET to start conducting and allow current to flow
from IN to OUT. When EN/UVLO is held low, the internal MOSFET is turned off. After a successful start-up
sequence, the device now actively monitors its load current, input voltage and protects the load from harmful
overcurrent and overvoltage conditions. The device also relies on a built-in thermal sense circuit to shut down
and protect itself in case the device internal temperature (Tj) exceeds the safe operating conditions.
8.2 Functional Block Diagram
TPS25982
PG
120 µs
GHI
R
/Q
S
Q
120 µs
TSD
FET Temperature Sense &
Overtemperature Protection
GND
PG_int
326 mV
OUT
IN
UVPb
Charge
Pump
GHI
2.53 V
2.42 V
x 246
µA/A
GHI
IMON
4.6 µA
dVdt
3.6 V
OVPb#
3.7 V/7.6 V/16.9 V
Gate control
3.6 V/7.4 V/16.4 V
EN/UVLO
ILIM
SWEN
OC
GHI
UVLOb
1x
1.2 V
1.1 V
SCPb
VIN transient
detect
2.1x
LDSTRT_FLT
S
Q
Q
2.5V
RETRY
FLTb
FLT
1.5 V
PG_int
Retry Logic
23 kO
CB**
TSD
ITIMER pin fault
ILIM pin fault
R
FLT
UVLOb
UVPb
OVPb#
SD
UVPb
RETRY
ILIM pin fault
CL* or CB**
SD
0.6 V
Short
detect
Current Limit Amplifier*
CL*
S
R
Q
Q
ITIMER
Short
detect
1.2 V
2.5V
2 µA
OC
2.1 µA
ITIMER pin fault
* TPS25982xL (CL variants) only
RETRY_DLY
** TPS25982xO (CB variants) only
#
Not applicable for TPS259827x (no-OVLO variant)
NRETRY
LDSTRT
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8.3 Feature Description
The TPS25982 eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Undervoltage Protection (UVLO and UVP)
The TPS25982 implements Undervoltage Protection on IN to turn off the output in case the applied voltage
becomes too low for the downstream load or the device to operate correctly. The Undervoltage Protection has a
default internal threshold of VUVP. If needed, it is also possible to set a user defined Undervoltage Protection
threshold higher than VUVP using the UVLO comparator on the EN/UVLO pin. Figure 42 and Equation 1 show
how a resistor divider from supply to GND can be used to set the UVLO set point for a given voltage supply level.
Power
Supply
IN
RVL1
EN/UVLO
RVL2
GND
Figure 42. Adjustable Supply UVLO Threshold
VINUVLO =
VUVLO(R) x (RVL1 RVL2)
RVL2
(1)
The resistors must be sized large enough to minimize the constant leakage from supply to ground through the
resistor divider network. At the same time, keep the current through the resistor network sufficiently larger (20x)
than the leakage current on the EN/UVLO pin to minimize the error in the resistor divider ratio.
8.3.2 Overvoltage Protection (OVP)
The TPS25982 implements Overvoltage Lock-Out (OVLO) on IN to protect the output load in the event of input
overvoltage. When the input exceeds the Overvoltage Protection threshold (VOVP(R)) the device turns off the
output within tOVP. As long as an overvoltage condition is present on the input, the device stays disabled and the
output will be turned off. Once the input voltage returns to the normal operating range, the device attempts to
start up normally.
18
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Feature Description (continued)
Input Overvoltage Event
IN
Input Overvoltage Removed
VOVP(R)
VOVP(F)
0
tOVP
OUT
dVdt Limited
0
VPG
PG
0
Time
Figure 43. Overvoltage Response
There are multiple device options with different fixed overvoltage thresholds to choose from, including one
without internal overvoltage protection. See the Device Comparison Table for a list of available options.
8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
TPS25982 devices incorporate three levels of protection against overcurrent:
• Adjustable slew rate (dVdt) for inrush current control
• Adjustable overcurrent protection (with adjustable blanking timer) - Circuit Breaker or Active Current Limiter to
protect against soft overload conditions
• Adjustable fast-trip response to quickly protect against severe overcurrent (short-circuit) faults
8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
During hot-plug events or while trying to charge a large output capacitance, there can be a large inrush current. If
the inrush current is not controlled, it can damage the input connectors and/or cause the system power supply to
droop leading to unexpected restarts elsewhere in the system. The TPS25982 provides integrated output slew
rate (dVdt) control to manage the inrush current during start-up. The inrush current is directly proportional to the
load capacitance and rising slew rate. The following equation can be used to calculate the slew rate (SR)
required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
SR V / ms
IINRUSH mA
COUT PF
(2)
An external capacitance can be connected to the dVdt pin to control the rising slew rate and lower the inrush
current during turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using the
following formula:
CdVdt pF
4600
SR V / ms
(3)
The fastest output slew rate is achieved by leaving the dVdt pin open.
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Feature Description (continued)
8.3.3.2 Circuit Breaker
The TPS25982xO (Circuit Breaker) variants respond to output overcurrent conditions by turning off the output
after a user adjustable transient fault blanking interval. When the load current exceeds the programmed current
limit threshold (ILIM set by the ILIM pin resistor RILIM), but lower than the fast-trip threshold (2.1 x ILIM), the device
starts discharging the ITIMER pin capacitor using an internal pull-down current (IITIMER). If the load current drops
below the current limit threshold before the ITIMER capacitor drops by ΔVITIMER, the circuit breaker action is not
engaged and the ITIMER is reset by pulling it up to VINT internally. This allows short transient overcurrent pulses
to pass through the device without tripping the circuit. If the overcurrent condition persists, the ITIMER capacitor
continues to discharge and once it falls by ΔVITIMER, the circuit breaker action turns off the FET immediately. The
following equation can be used to calculate the RILIM value for a desired current limit threshold.
RILIM :
1460
ILIM A 0.11
(4)
NOTE
Leaving the ILIM pin Open sets the current limit to zero and causes the FET to shut off as
soon as any load current is detected. Shorting the ILIM pin to ground at any point during
normal operation is detected as a fault and the part shuts down. The ILIM pin Short to
GND fault detection circuit requires a minimum amount of load current (ICB) to flow through
the device. This ensures robust eFuse behavior even under single point failure conditions.
Refer to the Fault Response section for details on the device behavior after a fault.
Transient Output Overload
2.1 x ILIM
IOUT
Persistent Output Overload
ITIMER expired
Overload Removed
ILIM
Circuit Breaker
operation
0
tITIMER
VINT
4VITIMER
ITIMER
0
VIN
OUT
0
VPG
PG
0
TSD
TSDHYS
TJ
TJ
Time
Figure 44. Circuit Breaker Response
20
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Feature Description (continued)
The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from
ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using Equation 5.
tITIMER (ms) =
CITIMER (nF) u 'VITIMER (V)
IITIMER (PA)
(5)
Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
Table 1. Device ITIMER Functional Mode Summary
ITIMER Pin Connection
Timer Delay before Overcurrent response
OPEN
0s
Capacitor to ground
As per Equation 5
Short to GND
ITIMER Pin Fault - Part Shuts Off
NOTE
1. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This
ensures robust eFuse behavior even in case of single point failure conditions. Refer to the
Fault Response section for details on the device behavior after a fault.
2. Larger ITIMER capacitors take longer to charge during start-up and may lead to
incorrect fault assertion if the ITIMER voltage is still below the pin short detection
threshold after the device has reached steady state. To avoid this, it is recommended to
limit the maximum ITIMER capacitor to the value suggested by the equation below.
CITIMER <
tGHI
53000
§ VIN + 3.6V ·
tGHI = tD,ON + Cdvdt u ¨
¸
Idvdt
©
¹
Where
• tGHI is the time taken by the device to reach steady state
• tD,ON is the device turn-on delay
• Cdvdt is the dVdt capacitance
• Idvdt is the dVdt charging current
It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER
intervals if needed by increasing the dVdt capacitor value accordingly, but at the expense
of higher start-up time.
Once the part shuts down due to a Circuit Breaker fault, it can be configured to either stay latched off or restart
automatically. Refer to the Fault Response section for details.
8.3.3.3 Active Current Limiting
The TPS25982xL (Current Limiter) variants respond to output overcurrent conditions by actively regulating the
current to a set limit after a user adjustable fault blanking interval. When the load current exceeds the
programmed current limit threshold (ILIM set by the ILIM pin resistor RILIM), but lower than the fast-trip threshold
(2.1 x ILIM), the device starts discharging the ITIMER pin capacitor using an internal pull-down current (IITIMER). If
the load current drops below the current limit threshold before the ITIMER capacitor voltage drops by ΔVITIMER,
the current limit action is not engaged and the ITIMER is reset by pulling it up to VINT internally. This allows short
transient overcurrent pulses to pass through the device without limiting the current. If the overcurrent condition
persists, the ITIMER capacitor continues to discharge and once it falls by ΔVITIMER, the device regulates the FET
gate voltage to actively limit the output current to the set ILIM level. The device will exit current limiting when the
load current falls below ILIM. Equation 6 can be used to calculate the RILIM value for a desired current limit.
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1460
ILIM A 0.11
(6)
NOTE
Leaving the ILIM pin Open sets the current limit to zero and causes the FET to shut off as
soon as any load current is detected. Shorting the ILIM pin to ground at any point during
normal operation is detected as a fault and the part shuts down. The ILIM pin Short to
GND fault detection circuit requires a minimum amount of load current (ICB) to flow through
the device. This ensures robust eFuse behavior even under single point failure conditions.
Refer to the Fault Response section for details on the device behavior after a fault.
Transient Output Overload
2.1 x ILIM
IOUT
Persistent Output Overload
ITIMER expired
tLIM
Overload Removed
Thermal shutdown
ILIM
Current limiting
operation
0
tITIMER
VINT
4VITIMER
ITIMER
0
VIN
VIN - VPGTHD
OUT
0
VPG
PG
0
TSD
TSDHYS
TJ
TJ
Time
Figure 45. Active Current Limiter Response
The duration for which load transients are allowed can be adjusted using an appropriate capacitor value from
ITIMER pin to ground. The transient overcurrent blanking interval can be calculated using Equation 7.
tITIMER (ms) =
CITIMER (nF) u 'VITIMER (V)
IITIMER (PA)
(7)
Leave the ITIMER pin open to allow the part to activate the current limit with the minimum possible delay. Refer
to ITIMER Functional Mode Summary for more details.
22
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NOTE
1. Current limiting based on RILIM is active during startup for both Current Limit and Circuit
Breaker variants. In case the startup current exceeds ILIM, the device regulates the current
to the set limit. However, during startup the current limit is engaged without waiting for the
ITIMER delay.
2. Shorting the ITIMER pin to ground is detected as a fault and the part shuts down. This
ensures robust eFuse behavior even in case of single point failure conditions. Refer to the
Fault Response section for details on the device behavior after a fault.
3. Larger ITIMER capacitors take longer to charge during start-up and may lead to
incorrect fault assertion if the ITIMER voltage is still below the pin short detection
threshold after the device has reached steady state. To avoid this, it is recommended to
limit the maximum ITIMER capacitor to the value suggested by the equation below.
CITIMER <
tGHI
53000
§ VIN + 3.6V ·
tGHI = tD,ON + Cdvdt u ¨
¸
Idvdt
©
¹
Where
• tGHI is the time taken by the device to reach steady state
• tD,ON is the device turn-on delay
• Cdvdt is the dVdt capacitance
• Idvdt is the dVdt charging current
It is possible to avoid incorrect ITIMER pin fault assertion and achieve higher ITIMER
intervals if needed by increasing the dVdt capacitor value accordingly, but at the expense
of higher start-up time.
During current regulation, the output voltage will drop resulting in increased device power dissipation across the
FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET is turned
off. See Overtemperature Protection (OTP) for more details on device response to overtemperature.
8.3.3.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When an output shortcircuit is detected, the internal fast-trip comparator turns off the output within the tSC. The comparator employs a
scalable threshold which is equal to 2.1 × ILIM. This enables the user to adjust the fast-trip threshold as per
system needs rather than using a fixed threshold which may not be suitable for all systems. After a fast trip
event, the device restarts in a current limited mode to try and restore power to the load quickly in case the fast
trip was triggered by a transient event. However, if the fault is persistent, the device will stay in current limit
causing the junction temperature to rise and eventually enter thermal shutdown. See Overtemperature Protection
(OTP) section for details on the device response to overtemperature.
In some of the systems, for example servers or telecom equipment which house multiple hot-pluggable cards
connected to a common supply backplane, there can be transients on the supply due to switching of large
currents through the inductive backplane. This can result in current spikes on adjacent cards which could be
potentially large enough to inadvertently trigger the fast-trip comparator of the eFuse. The TPS25982 uses a
proprietary algorithm to avoid nuisance tripping in such cases thereby facilitating un-interrupted system
operation.
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Input Line
Transient
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Persistent Output Short-Circuit
Thermal Shutdown
Temporary Output
Short-Circuit
Output Short-Circuit Removed
Retry Timer Elapsed
IN
0
tSC
tSC
2.1 x ILIM
IOUT
ILIM
0
No Fast-trip
Fast-trip
Fast-trip
VIN
OUT
dVdt Limited
Start-up
Current Limited
Start-up
0
VPG
PG
tRETRY_DLY
0
TSD
TSDHYS
TJ
Time
Figure 46. Input Line Transient and Output Short-Circuit Response
NOTE
To prevent the current limit/circuit breaker loop from interfering with the input line transient
detection logic, TI recommends to set the ITIMER interval higher than 100 μs. Refer to
Table 1 for more details on ITIMER.
8.3.4 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the die cools down sufficiently, that is the die temperature falls below (TSD - TSDHys).
Thereafter, the part can be configured to either remain latched off or restart automatically. Refer to the Fault
Response section for details.
8.3.5 Analog Load Current Monitor (IMON)
The device allows the system to monitor the output load current accurately by providing an analog current on the
IMON pin which is proportional to the current through the FET. The user can connect a resistor from IMON to
ground to convert this signal to a voltage which can be fed to the input of an Analog-to-Digital Converter. The
internal amplifier on the IMON employs chopper based offset cancellation techniques to provide accurate
measurement even at lower currents over time and temperature.
VIMON V
24
G IMON PA / A u I OUT A u R IMON :
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It is recommended to limit the maximum IMON voltage to the values mentioned in VIMON(Max) Recommended
Values . This is to ensure the IMON pin internal amplifier has sufficient headroom to operate linearly.
Table 2. VIMON(MAX) Recommended Values
VIN
Recommended VIMON(MAX)
2.7 V
1V
3.3 V
1.8 V
>5V
3.3 V
It is recommended to add a RC low pass filter on the IMON output to filter out any glitches and get a smooth
average current measurement. TI recommends a series resistance of 10 kΩ or higher.
8.3.6 Power Good (PG)
PG is an active high open drain output which indicates whether the FET is fully turned ON and the output voltage
has reached the maximum value. After power-up, PG is pulled low initially. The gate driver circuit starts charging
the gate capacitance from the internal charge pump. When the FET gate voltage reaches (VIN + 3.6V), PG is
asserted after a de-glitch time (tPGD). During normal operation, if at any time VOUT falls below (VIN - VPGTHD), PG
is de-asserted after a de-glitch time (tPGD).
Device Enabled
EN/UVLO
Overcurrent Removed
Overcurrent Event
VUVLO(R)
0
IN
0
Slew rate (dVdt) controlled
startup/Inrush current limiting
VIN
VPGTHD
Current limiting
operation
OUT
0
VPG
PG
120 µs
120 µs
120 µs
0
VIN
dVdT
0
VIN + 3.6V
VGate
tITIMER
0
ILIM
IINRUSH
IOUT
0
Time
Figure 47. Power Good Assertion and De-assertion
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NOTE
1. When there is no supply to the device, the PG pin is expected to stay low. However,
there is no active pull-down in this condition to drive this pin all the way down to 0 V. If the
PG pin is pulled up to an independent supply which is present even if the TPS25982 is
unpowered, there can be a small voltage seen on this pin depending on the pin sink
current, which in turn is a function of the pull-up supply voltage and resistor. Minimize the
sink current to keep this pin voltage low enough not to be detected as a logic HIGH by
associated external circuits in this condition.
2. The PG pin provides a mechanism to detect a possible failed MOSFET condition during
start-up. If the PG does not get asserted for an extended period of time after the device is
powered up and enabled, it might be an indication of internal MOSFET failure.
8.3.7 Load Detect/Handshake (LDSTRT)
The LDSTRT pin provides a mechanism for the downstream load circuit to indicate to the TPS25982 that the
load is present and has powered up successfully. This allows the system to have additional control over the
conditions in which power is presented to the load and disconnect the power when the load is not present or
unable to provide a valid handshake signal after an expected boot-up time.
Once the TPS25982 completes the startup sequence and the output reaches the full voltage, it asserts the PG
signal. At the same time, it also starts charging the capacitor on the LDSTRT pin (CLDSTRT) with an internal
current source (ILDSTRT). If the LDSTRT pin voltage rises above VLDSTRT before the load circuit pulls it low, the
TPS25982 detects the condition as a LDSTRT fault and turns off the FET to power down the load. The time to
trigger the LDSTRT fault can be calculated from the following equation:
tLDSTRT (ms) =
CLDSTRT (nF) u VLDSTRT (V)
ILDSTRT (PA)
(9)
During normal operation, if at any time the load circuit releases the active pull-down on the LDSTRT pin, the
capacitor CLDSTRT would start charging up again and eventually trigger a shutdown due to LDSTRT fault once the
capacitor charges up to VLDSTRT.
Once the TPS25982 turns off due to LDSTRT fault, it can be turned ON again in 3 ways:
• LDSTRT pin is driven low
• Input supply voltage is driven low (< VUVP(F)) and then driven high (> VUVP(R))
• EN/UVLO voltage is driven low (< VSD) and then driven high (> VUVLO(R))
Tie the LDSTRT pin to ground if this functionality is not needed.
IN
IN
0
0
EN/UVLO
EN/UVLO
0
VIN
0
VIN
OUT
OUT
0
0
VPG
VPG
PG
PG
0
0
tLDSTRT
tLDSTRT
1.2 V
LDSTRT
LDSTRT pulled low by MCU
0
2.5 V
LDSTRT
1.2 V
0
Figure 48. Successful LDSTRT Handshake
26
No Handshake Signal from System MCU
Time
Time
Figure 49. Unsuccessful LDSTRT Handshake
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The LDSTRT pin can also be used to implement a load or module detect function wherein the output power is
presented only when the load or module is plugged in. A typical use case for this function is on optical module
power supply rails in Switches/Routers or similar networking end equipment. The LDSTRT pin should be tied to a
corresponding pin on the module connector which gets pulled low by the module when it is plugged in. An
example of such a signal is ModPrsL on QSFP-DD modules.
In this scheme, initially when the TPS25982 is powered up or enabled, the output charges up and PG is
asserted. If the module is not plugged in, there is no external pull-down on the LDSTRT pin and the pin voltage
starts rising due to internal pull-up . Once the LDSTRT pin voltage exceeds VLDSTRT, the TPS25982 turns off the
output power. If the module is plugged in later, the LDSTRT pin is pulled low by the module and the TPS25982
turns on the output power.
IN
0
EN/UVLO
0
VIN
OUT
dVdt limited
0
VPG
PG
0
2.5 V
LDSTRT
1.2 V
0
Optical module not present
Optical module plugged in
Time
Figure 50. Optical Module Plug-In Detection Using LDSTRT
8.4 Fault Response
The following events trigger an internal fault which causes the device to shut down:
• Overtemperature Protection
• Circuit Breaker Operation
• ITIMER pin Short to GND
• ILIM pin Short to GND
Once the device shuts down due to a fault, even if the associated external fault is subsequently cleared, the fault
stays latched internally and the output cannot turn on again until the latch is reset. The fault latch can be
externally reset by one of the following methods:
• Input supply voltage is driven low (< VUVP(F))
• EN/UVLO voltage is driven low (< VSD)
The fault latch can also be reset by an internal auto-retry logic. The user can either disable the auto-retry
behavior completely (latch-off behavior) or configure the device to auto-retry indefinitely or for a limited number of
times before latching off. The auto-retry behavior is controlled by the connections on the RETRY_DLY and
NRETRY pins.
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Fault Response (continued)
Table 3. Pin Configurable Fault Response
EN/UVLO
RETRY_DLY
NRETRY
L
X
X
DEVICE STATE
Disabled
H
Short to GND
X
No auto-retry (Latch-off)
H
Open
Open
Auto-retry 4 times with minimum delay between retries and
then latch-off
H
Open
Short to GND
Auto-retry indefinitely with minimum delay between retries
H
Capacitor to GND
Capacitor to GND
H
Capacitor to GND
Open
H
Capacitor to GND
Short to GND
Auto-retry delay and count as per Equation 10 and
Equation 11
Auto-retry 4 times with finite delay between retries as per
Equation 10 and then latch-off
Auto-retry indefinitely with finite delay between retries as per
Equation 10
To configure the part for a finite number of auto-retries with a finite auto-retry delay, first choose the capacitor
value on RETRY_DLY pin using the following equation.
tRETRY_DLY (Ps) =
128 u CRETRY_DLY (pF) + 4 pF u VRETRY_DLY_HYS (V)
IRETRY_DLY (PA)
(10)
Next, choose the capacitor value on the NRETRY pin using the following equation.
NRETRY =
4 u IRETRY_DLY (PA) u CNRETRY (pF)
INRETRY (PA) u CRETRY_DLY (pF) + 4 pF
(11)
The number of auto-retries is quantized to certain discrete levels as shown in Table 4 .
Table 4. NRETRY Quantization Levels
NRETRY Calculated From Equation 11
NRETRY Actual
0<N<4
4
4 < N < 16
16
16 < N < 64
64
64 < N < 256
256
256 < N < 1024
1024
Table 5. NRETRY and RETRY_DLY Combination Examples
Auto Retry Delay
915 ms
416 ms
RETRY_DLY Capacitor
22 nF
10 nF
No. of Auto Retries
9.3 ms
3 ms
2.2 nF
220 pF
68 pF
4.7 nF
1 nF
220 pF
NRETRY Capacitor
4
Open
16
47 nF
22 nF
64
0.22 μF
0.1 μF
22 nF
2.2 nF
1 nF
256
1 μF
0.47 μF
0.1 μF
10 nF
4.7 nF
1024
3.3 μF
1.5 μF
0.47 μF
33 nF
10 nF
Infinite
28
91.7 ms
Short to GND
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A spreadsheet design tool TPS25982xx Design Calculator is also available for simplified calculations.
Output overload followed by Thermal Shutdown
Retry Timer starts once device cools down
1st Retry
IN
0
Nth Retry
tRETRY_DLY
Thermal Shutdown
IOUT
Thermal Shutdown
ILIM
0
VIN
Programmed number of retries over,
Device Latches Off
OUT
0
TSD
TSDHYS
TJ
TJ
Time
Figure 51. Auto-Retry After Fault
The auto-retry logic has a mechanism to reset the count to zero if two consecutive faults occur far apart in time.
This ensures that the auto-retry response to any later fault is handled as a fresh sequence and not as a
continuation of the previous fault. If the fault which triggered the shutdown and subsequent auto-retry cycle is
cleared eventually and does not occur again for a duration equal to 7 retry delay timer periods starting from the
last fault, the auto-retry logic resets the internal auto-retry count to zero.
8.5 Device Functional Modes
The TPS25982 can be pin strapped to support various configurable functional modes.
Table 6. LDSTRT Handshake Functional Modes
EN/UVLO
LDSTRT
DEVICE STATE
L
X
Disabled
H
L
ON
H
H
OFF
Refer to Load Detect/Handshake (LDSTRT) section for more details.
Table 7. Fault Response Functional Modes
EN/UVLO
RETRY_DLY
NRETRY
L
X
X
DEVICE STATE
Disabled
H
Short to GND
X
No auto-retry (Latch-off)
H
Open
Open
Auto-retry 4 times with minimum delay between retries and
then latch-off
H
Open
Short to GND
Auto-retry indefinitely with minimum delay between retries
H
Capacitor to GND
Capacitor to GND
Auto-retry delay and count as per Equation 10 and
Equation 11
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Table 7. Fault Response Functional Modes (continued)
EN/UVLO
RETRY_DLY
NRETRY
H
Capacitor to GND
Open
H
Capacitor to GND
Short to GND
DEVICE STATE
Auto-retry 4 times with finite delay between retries as per
Equation 10 and then latch-off
Auto-retry indefinitely with finite delay between retries as per
Equation 10
Refer to Fault Response section for more details.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25982 device is an integrated 15-A eFuse that is typically used for hot-swap and power rail protection
applications. It operates from 2.7 V to 24 V with adjustable overcurrent and undervoltage protection. It also
provides optional overvoltage with various fixed internal thresholds. The device aids in controlling the inrush
current and has the flexibility to configure the number of auto-retries and retry delay. The adjustable overcurrent
blanking timer provides the functionality to allow transient overcurrent pulses without limiting or tripping. These
devices protect source, load and internal MOSFET from potentially damaging events in systems such as Server
standby rails, PCIe cards, SSDs, HDDs, Optical Modules, Routers and Switches.
The following design procedure can be used to select the supporting component values based on the application
requirement. Additionally, a spreadsheet design tool TPS25982xx Design Calculator is available in the web
product folder.
9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
VIN
12 V
TPS259824O
IN
LDSTRT
RVL1
10Ÿ
CIN
SMCJ12A
CNRETRY
2.2nF
0.1µF
VOUT
OUT
EN/UVLO
PG
NRETRY
IMON
RETRY_DLY
CLDSTRT
0.1µF
RVL2
125.Ÿ
CRETRY_DLY
2.2nF
ILIM
3.3V
RPG
100.Ÿ
CL
1.4mF
dVdt
B520C-13-F
GND ITIMER
RILIM
100Ÿ
CITIMER
4.7nF
RL
CdVdt
10nF
RIMON
887Ÿ
Figure 52. Typical Application Schematic - Protection for Server Standby Rail
9.2.1 Design Requirements
Table 8 shows the design parameters for this application example.
Table 8. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, VIN
12 V
Undervoltage lockout set point, VINUVLO
10.8 V
Maximum load current, IOUT
12 A
Current limit, ILIM
15 A
Transient overcurrent blanking interval (tITIMER)
2 ms
Load capacitance, COUT
1.4 mF
Load at start-up, RL(SU)
10 Ω
Output voltage ramp time, TdVdt
20 ms
Maximum ambient temperature, TA
70 °C
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Typical Application: Standby Power Rail Protection in Datacenter Servers (continued)
Table 8. Design Parameters (continued)
LDSTRT handshake delay, tLDSTRT
60 ms
Retry delay, tRETRY_DLY
100 ms
No. of retries, NRETRY
4
9.2.2 Detailed Design Procedure
9.2.2.1 Device Selection
This design example considers a 12-V system operating voltage with a tolerance of ±10 %. The rated load
current is 12 A. If the current exceeds 15 A, then the device must allow overload current for 2-ms interval before
breaking the circuit and then restart. Accordingly, the TPS259824O variant is chosen. (Refer to Device
Comparison Table for device options.) Ambient temperatures may range from 20 °C to 70 °C. The load has a
minimum input capacitance of 1.4 mF and start-up resistive load of 10 Ω. The downstream load is turned on only
after the PG signal is asserted.
9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the overload current limit, whose value can be calculated using
Equation 12.
RILIM :
1460
ILIM A 0.11
(12)
For ILIM = 15 A, RILIM value is calculated to be 98.05 Ω. Choose the closest available standard value: 100 Ω, 1%.
Refering to the Electrical Characteristics table, it can be verified that the minimum current limit across
temperature for RILIM value of 100 Ω is 12.85 A, which is higher than the nominal rated load current (12 A),
thereby ensuring stable operation under normal conditions.
9.2.2.3 Setting the Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of RVL1 and
RVL2 connected between IN, EN/UVLO and GND pins of the device. The resistor values required for setting the
undervoltage are calculated using Equation 13.
VINUVLO =
VUVLO(R) x (RVL1 RVL2)
RVL2
(13)
For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance
for RVL1 and RVL2. However, leakage currents due to external active components connected to the resistor string
can add error to these calculations. So, the resistor string current, IRVL12 must be 20 times greater than the
leakage current (IENLKG).
From the device electrical specifications, UVLO rising threshold VUVLO(R) = 1.2 V. From design requirements,
VINUVLO = 10.8 V. First choose the value of RVL1 = 1 MΩ and use Equation 13 to calculate RVL2 = 125 kΩ.
Use the closest standard 1% resistor values: RVL1 = 1 MΩ, and RVL2 = 125 kΩ
9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the
downstream system for monitoring the operating condition and health of the system. The RIMON must be selected
based on the maximum load current and the maximum IMON pin voltage at full-scale load current. The maximum
IMON pin voltage must be selected based on the input voltage range of the ADC used or the value suggested in
VIMON(Max) Recommended Values, whichever is lower. RIMON is set using Equation 14.
RIMON(:)
VIMONmax(V)
IOUTmax(A) u 246 u 10 6
(14)
For ILIM = 15 A and considering the operating range of ADC to be 0 V to 3.3 V, RIMON can be calculated as
32
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3.3
15 u 246 u 10 6
894
(15)
Selecting RIMON value less than shown in Equation 15 ensures that ADC limits are not exceeded for maximum
value of load current. Choose closest available standard value: 887 Ω, 1 %.
9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The required ramp-up capacitor CdVdt is calculated considering the two possible cases (see Case 1: Start-Up
Without Load: Only Output Capacitance COUT Draws Current and Case 2: Start-Up With Load: Output
Capacitance COUT and Load Draw Current)
9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
During start-up, as the output capacitor charges, the voltage drop as well as the power dissipated across the
internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 16
PD(INRUSH) = 0.5 x VIN x IINRUSH
(16)
Where IINRUSH is the inrush current and is determined by Equation 17
IINRUSH = COUT u
VIN
TdVdt
(17)
Equation 16 assumes that the load does not draw any current (apart from the capacitor charging current) until
the output voltage has reached its final value.
9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
When the load draws current during the turn-on sequence, there is additional power dissipated. Considering a
resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during
TdVdt time. Equation 18 shows the average power dissipation in the internal FET during charging time due to
resistive load.
PD(LOAD)
2
§ 1 · VIN
=¨ ¸×
© 6 ¹ RL(SU)
(18)
Equation 19 gives the total power dissipated in the device during start-up
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
(19)
The power dissipation, with and without load, for selected start-up time must not exceed the start-up thermal
shutdown limits as shown in Thermal Shutdown Plot During Start-up
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Time to Thermal Shutdown (ms)
200
TPS259827x
TPS259822x/23x/24x
100
50
30
20
10
5
3
2
1
0.5
2
3
4 5 6 7 8 10
20
30 40 50
Power Dissipation (W)
70
100
D002
Figure 53. Thermal Shutdown Plot During Start-up
For the design example under discussion, the output voltage has to be ramped up in 20 ms, which mandates a
slew-rate of 0.6 V/ms for a 12 V rail.
The required CdVdt capacitance on dVdt pin to set 0.6 V/ms slew rate can be calculated using Equation 20
CdVdt pF
4600
SR V / ms
7666 pF
(20)
The dVdt capacitor is subjected to typically VIN+ 4 V during startup. The high voltage bias leads to a drop in the
effective capacitor value. So, it is suggested to choose 20% higher than the calculated value, which gives 9.2 nF.
Choose closest 10% standard value: 10 nF
The 10 nF CdVdt capacitance sets a slew-rate of 0.46 V/ms and output ramp time TdVdt of 26 ms.
The inrush current drawn by the load capacitance COUT during ramp-up can be calculated using Equation 21
IINRUSH = 1.4 mF u
12 V
26 ms
0.65 A
(21)
The inrush power dissipation can be calculated using Equation 22
PD(INRUSH) = 0.5 x 12 x 0.65 = 3.9 W
(22)
For 3.9 W of power loss, the thermal shutdown time of the device must be greater than the ramp-up time TdVdt to
ensure a successful start-up. Figure 53 shows the start-up thermal shutdown limit. For 3.9 W of power, the
shutdown time is approximately 100 ms. So it is safe to use 26 ms as the start-up time without any load on the
output.
The additional power dissipation when a 10-Ω load is present during start-up is calculated using Equation 23
2
PD(LOAD)
§ 1 · 12
¨ 6 ¸ u 10
© ¹
2.4W
(23)
The total device power dissipation during start-up can be calculated using Equation 24
PD(STARTUP)
3.9
2.4
6.3 W
(24)
From Thermal Shutdown Plot During Start-up, the thermal shutdown time for 6.3 W is approximately 40 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 10 nF for CdVdt capacitor with start-up load of 10 Ω.
When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by
increasing the value of the CdVdt capacitor. A spreadsheet tool TPS25982xx Design Calculator available on the
web can be used for iterative calculations.
34
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9.2.2.6 Setting the Load Handshake (LDSTRT) Delay
To indicate a successful start-up, the load circuit must provide a handshake signal to TPS25982 by pulling down
the LDSTRT pin within the time set by the capacitor CLDSTRT on the LDSTRT pin. Once the PG asserts, the
device sources 2-μA current into CLDSTRT. For a successful handshake, the load circuit must pull-down the
LDSTRT pin before CLDSTRT charges up to 1.2 V.
For the design requirement of 60-ms handshake delay, use Equation 25 to calculate CLDSTRT
CLDSTRT
ILDSTRT u
tLDSTRT
VLDSTRT
2PA u
60ms
1.2V
0.1PF
(25)
Choose closest available standard value: 0.1 µF, 10 %.
9.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
For the design example under discussion, overcurrent transients are allowed for 2-ms duration. This blanking
interval can be set by selecting appropriate capacitor CITIMER from ITIMER pin to ground. The value of CITIMER to
set 2 ms for tITIMER can be calculated using Equation 26.
CITIMER (nF) =
tITIMER (ms)
= 4.255 nF
0.47
(26)
Choose closest available standard value: 4.7 nF, 10 %.
9.2.2.8 Setting the Auto-Retry Delay and Number of Retries
The time delay between retries can be programmed by selecting capacitor CRETRY_DLY on RETRY_DLY pin. The
value of CRETRY_DLY to set a 100-ms auto-retry delay can be calculated using Equation 27.
CRETRY_DLY (pF) =
tRETRY_DLY (Ps)
46.83
4 pF = 2131.38 pF
(27)
Choose closest available standard value: 2.2 nF, 10 %.
The number of auto-retry attempts can be set by a capacitor CNRETRY on the NRETRY pin using Equation 28
NRETRY =
4 u CNRETRY (pF)
CRETRY_DLY (pF) + 4 pF
(28)
For this design example, the requirement is to retry 4 times after the device shuts down due to a fault. Since, the
number of auto-retries can be adjusted in discrete steps as explained in Fault Response , choose CNRETRY such
that NRETRY is less than 4. Use Equation 29 to calculate CNRETRY.
CNRETRY (pF) <
NRETRY u CRETRY_DLY (pF) + 4 pF
4
< 2204 pF
(29)
Choose closest available standard value: 2.2 nF, 10 %.
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9.2.3 Application Curves
COUT = 1.4 mF
CdVdt = 10 nF
RL(SU) = Open
Figure 54. Hot-Plug Start-Up Without Load on Output dVdt Limited
RILIM = 100 Ω
CITIMER = 4.7 nF
CdVdt = 10 nF
RL(SU) = 10 Ω
Figure 55. Hot-Plug Start-Up With Load on Output - dVdt
Limited
RILIM = 100 Ω
Figure 56. Circuit Breaker With Transient Overcurrent
Blanking Interval of 2 ms
36
COUT = 1.4 mF
CITIMER = 4.7 nF
CRETRY_DLY = 2.2 nF,
CNRETRY = 2.2 nF
Figure 57. Circuit Breaker - Auto-Retry 4 Times With Retry
Delay of 100 ms
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RILIM = 100 Ω
RILIM = 100 Ω
Figure 58. Output Hard Short-Circuit While ON
Figure 59. Output Hard Short-Circuit While ON (Zoomed In)
Figure 60. Power-Up With Short-Circuit on Output
Figure 61. Power-Up With Short-Circuit on Output - AutoRetry 4 Times With Retry Delay of 100 ms
CLDSTRT = 0.1 μF
CLDSTRT = 0.1 μF
Figure 62. Successful Load Handshake (LDSTRT)
Figure 63. Unsuccessful Load Handshake (LDSTRT)
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9.3 System Examples
9.3.1 Optical Module Power Rail Path Protection
Optical modules are commonly used in high-bandwidth data communication systems such as Optical Networking
equipment, Enterprise/Data-Center Switches and Routers. Several variants of optical modules are available in
the market, which differ in the form-factor and the data speed support (Gbit/s). Of these, the popular variant
Double Dense Quad Small Form-factor Pluggable (QSFP-DD) module supports speeds up to 400 Gbit/s. In
addition to the system protection during hot-plug events, the other key requirement for optical module is the tight
voltage regulation. The optical module uses 3.3 V supply and requires voltage regulation within ±5 % for proper
operation.
A typical power tree of such system is shown in Figure 64. The optical line card consists of DC-DC converter,
protection device (eFuse) and power supply filters. The DC-DC converter steps-down the 12 V to 3.3 V and
maintains the 3.3 V rail within ±2 %. The power supply filtering network uses ‘LC’ components to reduce high
frequency noise injection into the optical module. The DC resistance of the inductor ‘L’ causes voltage drop of
around 1.5 % which leaves us with a voltage drop budget of just 1.5 % (3.3 V * 1.5% = 50 mV) across the
protection device. Considering a maximum load current of 5.5 A per module, the maximum ON-resistance of the
protection device should be less than 9 mΩ. TPS25982 eFuse offers ultra-low ON-resistance of 2.7 mΩ (typical)
and 4.5 mΩ (maximum, across temperature), thereby meeting the target specification with additional margin to
spare and simplifying the overall system design.
VIN
12V
3.3V
DC-DC
VOUT
IN
OUT
VccTx
eFuse
LDSTRT
VccRx
Hot Plug / Unplug
QSFP
Module
Vcc
GND
ModPrsL
Optical Line Card
Figure 64. Power Tree Block Diagram of a Typical Optical Line Card
As shown in Figure 64, ModPrsL signal acts as a handshake signal between the line card and the optical
module. ModPrsL is always pulled to ground inside the module. When the module is hot-plugged into the host
“Optical Line Card” connector, the ModPrsL signal pulls down the LDSTRT pin and enables the TPS25982
eFuse to power the module. This ensures that power is applied on the port only when a module is plugged in and
disconnected when there is no module present.
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System Examples (continued)
TPS259822O
VIN
IN
VOUT
OUT
LDSTRT
CIN
0.1µF
CNRETRY
OPEN
EN/UVLO
PG
NRETRY
IMON
RETRY_DLY
CLDSTRT
0.1µF
CRETRY_DLY
OPEN
3.3V
RPG
100.Ÿ
CL
dVdt
B520C-13-F
ILIM
10µF
RL
GND ITIMER
RILIM
210Ÿ
CITIMER
15nF
CdVdt
3.3nF
RIMON
1910Ÿ
Figure 65. TPS259822O Configured for a 3.3-V Power Rail Path Protection in Optical Module
9.3.1.1 Design Requirements
Table 9 shows the design parameters for this example.
Table 9. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, VIN
3.3 V
Overvoltage lockout, VOVP
3.7 V
Maximum voltage drop in the path
±5%
Maximum load current, IOUT
5.5 A
Current limit, ILIM
7A
Transient overcurrent blanking interval (tITIMER)
6 ms
Load capacitance, COUT
10 µF
Maximum ambient temperature, TA
85 °C
Module present detection, ModPrsL
Yes
Retry delay, tRETRY_DLY
200 µs
No. of retries, NRETRY
4
9.3.1.2 Device Selection
Optical modules are very sensitive to supply voltage variations and thus require input overvoltage protection.
TPS259822O variant from TPS25982 family is selected to set overvoltage protection at 3.7 V. TPS259822O
allows overcurrents for a user specified blanking interval tITIMER before breaking the circuit path. In this use case,
tITIMER is set for 6 ms interval.
9.3.1.3 External Component Settings
By following similar design procedure as outlined in Detailed Design Procedure, the external component values
are calculated as below
• RILIM = 210 Ω to set 7-A current limit
• CITIMER = 15 nF to set fault blanking time of 6 ms
• RIMON = 1910 Ω to set maximum IMON pin voltage VIMON within ADC range of 3.3 V
• CdVdt capacitance is chosen as 3.3 nF
• Leave RETRY_DLY and NRETRY pins OPEN to set minimum auto-retry delay of 200 μs and number of
retries to 4
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9.3.1.4 Voltage Drop
Table 10 shows the power path voltage drop (%) due to the eFuse in QSFP modules of different power classes.
Table 10. Voltage Drop across TPS25982 on QSFP Module Power Rail
POWER CLASS
MAXIMUM POWER
CONSUMPTION PER MODULE
(W)
MAXIMUM LOAD CURRENT (A)
TYPICAL VOLTAGE DROP (%)
1
1.5
0.454
0.037
2
3.5
1.06
0.087
3
7
2.12
0.174
4
8
2.42
0.2
5
10
3.03
0.248
6
12
3.63
0.3
7
14
4.24
0.347
8
18
5.45
0.446
9.3.1.5 Application Curves
Figure 66. Output Voltage Profile When Optical Module is
Inserted
40
Figure 67. Output Voltage Profile When Optical Module is
Plugged Out
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Figure 68. Circuit Breaker With Transient Overcurrent
Blanking Interval of 6 ms; Device Restarts in Current Limit
Mode
Figure 69. Overload Response and Recovery
Figure 70. Overvoltage Cut-off at 3.7 V with TPS259822O
Device
Figure 71. Overvoltage Protection Response and Recovery
with TPS259822O Device
9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
TPS25982 eFuse provides inrush current management and also protects the system from most common faults
such as undervoltage, overvoltage and overcurrents. The combination of high current support along with low ONresistance makes TPS25982 eFuse an ideal protection solution for PCIe cards, Storage Interfaces and DC Fan
loads. The external component values can be calculated by following the design procedure outlined in Detailed
Design Procedure. Alternatively, a spreadsheet design tool TPS25982xx Design Calculator is available for
simplified design efforts.
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10 Power Supply Recommendations
The TPS25982 devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 24 V. TI recommends an input
ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Use a Schottky diode across the output to absorb negative spikes.
• Use a low value ceramic capacitor CIN = 0.001 μF to 0.1 μF to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated using Equation 30.
VSPIKE(Absolute) = VIN + ILOAD x
LIN
CIN
where
•
•
•
•
VIN is the nominal supply voltage
ILOAD is the load current
LIN equals the effective inductance seen looking into the source
CIN is the capacitance present at the input
(30)
Some of the applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. A typical circuit implementation with optional
protection components (a ceramic capacitor, TVS and Schottky diode) is shown in Figure 72.
TPS25982
IN
12V
OUT
1MO
100kO
100O
0.1uF
EN/UVLO
PG
NRETRY
IMON
RETRY_DLY
137kO
3.3V
LDSTRT
56pF
1uF
ILIM
220uF
dVdt
GND ITIMER
56pF
3.3nF
100O
511O
4.7nF
Figure 72. Typical Circuit Implementation With Optional Protection Components
42
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10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
• Source bypassing
• Input leads
• Board layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results.
NOTE
Do not expect to see waveforms exactly like the waveforms in this data sheet because
every setup is different.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
44
The IN Exposed Thermal Pad is used for Heat Dissipation. Connect to as much copper area as possible
using an array of thermal vias. The via array also helps to minimize the voltage gradient across the VIN pad
and facilitates uniform current distribution through the internal FET, which improves the current sensing and
monitoring accuracy.
For all applications, TI recommends a ceramic decoupling capacitor of 0.01 μF or greater between IN and
GND terminals. For hot-plug applications, where input power-path inductance is negligible, this capacitor can
be eliminated or minimized.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current. It is recommended to use a minimum trace width of 50 mil for the OUT power
connection.
The GND terminal is the reference for all internal signals and must be isolated from any bounce due to large
switching currents in the system power ground plane. It is recommended to connect the device GND to a
signal ground island on the board, which in turn is connected to the system power GND plane at one point.
Locate the support components for the following signals close to their respective connection pins - ILIM,
IMON, ITIMER, RETRY_DLY, NRETRY and dVdT with the shortest possible trace routing to reduce parasitic
effects on the respective associated functions. These traces must not have any coupling to switching signals
on the board.
The ILIM pin is highly sensitive to capacitance and TI recommends to pay special attention to the layout to
maintain the parasitic capacitance below 30 pF for stable operation.
Use short traces on the RETRY_DLY and NRETRY pins to ensure the auto-retry timer delay and number of
auto-retries is not altered by the additional parasitic capacitance on these pins.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
Use proper layout and thermal management techniques to ensure there is no significant steady state thermal
gradient between the two thermal pads on the IC. This is necessary for proper functioning of the device
overtemperature protection mechanism and successful startup under all conditions.
Obtaining acceptable performance with alternate layout schemes is possible; the Layout Example is intended
as a guideline and shown to produce good results from electrical and thermal standpoint.
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11.2 Layout Example
Blind PCB via to Inner Layer
PCB via to Bottom Layer
VIN Plane (Top Layer)
VOUT Plane (Top Layer)
> 50 mils
*
*
*
*
Signal GND (Top Layer)
Power GND Plane (Top Layer)
* Optional components for suppressing transients induced while
switching current through inductive elements at input/output
Figure 73. TPS25982 Example PCB Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• TPS259824OEVM eFuse Evaluation Board
• TPS259827LEVM eFuse Evaluation Board
• TPS25982xx Design Calculator
12.1.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS259822L
Click here
Click here
Click here
Click here
Click here
TPS259823L
Click here
Click here
Click here
Click here
Click here
TPS259824L
Click here
Click here
Click here
Click here
Click here
TPS259827L
Click here
Click here
Click here
Click here
Click here
TPS259822O
Click here
Click here
Click here
Click here
Click here
TPS259823O
Click here
Click here
Click here
Click here
Click here
TPS259824O
Click here
Click here
Click here
Click here
Click here
TPS259827O
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
46
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12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS259822LNRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
22LN
TPS259822LNRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
22LN
TPS259822ONRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
22ON
TPS259822ONRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
22ON
TPS259823LNRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
23LN
TPS259823LNRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
23LN
TPS259823ONRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
23ON
TPS259823ONRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
23ON
TPS259824LNRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
24LN
TPS259824LNRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
24LN
TPS259824ONRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
24ON
TPS259824ONRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
24ON
TPS259827LNRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
27LN
TPS259827LNRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
27LN
TPS259827ONRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
27ON
TPS259827ONRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TP2598
27ON
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2019
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS259822LNRGER
VQFN
RGE
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259822LNRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259822ONRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259822ONRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259823LNRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259823LNRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259823ONRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259823ONRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259824LNRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259824LNRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259824ONRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259824ONRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259827LNRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259827LNRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
TPS259827ONRGER
VQFN
RGE
24
3000
330.0
12.4
4.35
4.35
1.1
8.0
12.0
Q2
TPS259827ONRGET
VQFN
RGE
24
250
180.0
12.5
4.35
4.35
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS259822LNRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259822LNRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259822ONRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259822ONRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259823LNRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259823LNRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259823ONRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259823ONRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259824LNRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259824LNRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259824ONRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259824ONRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259827LNRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259827LNRGET
VQFN
RGE
24
250
205.0
200.0
33.0
TPS259827ONRGER
VQFN
RGE
24
3000
338.0
355.0
50.0
TPS259827ONRGET
VQFN
RGE
24
250
205.0
200.0
33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024M
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
0.475
0.275
PIN 1 INDEX AREA
4.1
3.9
0.29
0.19
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 2.7 0.1
4X 2.5
(0.2) TYP
7
SEE TERMINAL
DETAIL
6
12
13
26
0.85 0.1
EXPOSED
THERMAL PAD
(0.925)
SYMM
(0.625)
25
1.45 0.1
1
18
0.29
0.19
0.1
C A B
0.05
24X
24
PIN 1 ID
(OPTIONAL)
2X 0.5
19
SYMM
24X
0.475
0.275
4223975/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024M
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.7)
SYMM
19
24
24X (0.575)
1
18
(1.45)
24X (0.24)
(0.625)
25
(1.1)
TYP
(R0.05)
TYP
SYMM
(0.15)
TYP
26
(0.85)
(3.825)
(0.925)
TYP
20X (0.5)
13
6
( 0.2) TYP
VIA
12
7
6X (1.1)
(3.825)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223975/B 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024M
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.188)
4X (0.694)
24
19
24X (0.575)
1
25
18
24X (0.24)
2X
(1.3)
(R0.05) TYP
2X
(0.625)
SYMM
(3.825)
26
2X
(0.925)
2X
(0.76) 20X (0.5)
13
6
METAL
TYP
12
7
SYMM
(3.825)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223975/B 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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