Texas Instruments | BQ25886 Standalone 2-Cell, 2-A Boost-Mode Battery Charger With PowerPath, USB BC1.2 Detection, and USB On-The-Go Boost (OTG) (Rev. A) | Datasheet | Texas Instruments BQ25886 Standalone 2-Cell, 2-A Boost-Mode Battery Charger With PowerPath, USB BC1.2 Detection, and USB On-The-Go Boost (OTG) (Rev. A) Datasheet

Texas Instruments BQ25886 Standalone 2-Cell, 2-A Boost-Mode Battery Charger With PowerPath, USB BC1.2 Detection, and USB On-The-Go Boost (OTG) (Rev. A) Datasheet
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BQ25886
SLUSD88A – MARCH 2019 – REVISED JUNE 2019
BQ25886 Standalone 2-Cell, 2-A Boost-Mode Battery Charger With PowerPath, USB BC1.2
Detection, and USB On-The-Go Boost (OTG)
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
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High-efficiency 2-A, 1.5-MHz switch mode boost
charger
– 93.4% Charge efficiency at 5-V adapter, 7.6-V
battery, 1-A charge
– Optimized for USB input and 2-cell Li-Ion
battery
Single input to support USB input adapters
– Supports 4.3-V to 6.2-V input voltage range
with 20-V absolute maximum input voltage
rating
– Input current limit (500 mA to 3.3 A) to support
USB2.0, USB3.0 standard adapters
– Integrated USB D+/D- auto-detect USB SDP,
CDP, DCP, and non-standard adapters
Standalone function with PowerPath management
– Highest battery discharge efficiency with 17mΩ battery discharge MOSFET
– Narrow VDC (NVDC) PowerPath management
– Instant-on works with no battery or deeply
discharged battery
– Ideal diode operation in battery supplement
mode
– Adjustable charge voltage with VSET pin
supports 8.2 V, 8.4 V, 8.7 V, and 8.8 V
– Adjustable charge current with ICHGSET pin
supports 100 to 2200 mA
– Adjustable input current limit with ILIM pin
Input current optimizer (ICO) to maximize input
power without overloading adapters
High integration includes all MOSFETs, current
sensing and loop compensation
High accuracy
– ±0.5% Charge voltage regulation
– ±5% Charge current regulation
– ±7.5% Input current regulation
Safety
– Battery temperature sensing in charge
– Thermal regulation and thermal shutdown
Wireless speaker
Smart Speaker
EPOS Printer
Portable POS
IP network camera
3 Description
The BQ25886 is a highly-integrated 2-A boost switchmode battery charge management and system
PowerPath management which enables instant power
on and provides accurate termination control device
for 2-cell (2s) Li-Ion and Li-polymer battery. The
BQ25886 is a standalone solution with PowerPath
and OTG.
Device Information(1)
PART NUMBER
BQ25886
PACKAGE
BODY SIZE (NOM)
VQFN (24)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
5V @ 3A
VREF
STAT
VBUS
/PG
PMID
6.0V to 8.8V
SYSTEM
LOAD
SYS
SW
ICHG=2A
BAT
BTST
REGN
D+
Host
D-
VREGN
OTG
TS
/CE
ILIM
2s Battery
1
BQ25886
`
VSET
ICHGSET
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25886
SLUSD88A – MARCH 2019 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
Changes from Original (March 2019) to Revision A
•
2
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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5 Device Comparison Table
Table 1. Device Comparison
PART NUMBER
BQ25882
BQ25883
BQ25886
BQ25887
VBUS Operating Range
3.9 to 6.2 V
3.9 to 6.2 V
4.3 to 6.2 V
3.9 to 6.2 V
USB Detection
D+/D-
D+/D-
D+/D-
PSEL
PowerPath
Yes
Yes
Yes
No
Cell Balancing
No
No
No
Yes
OTG
Up to 2 A
Up to 2 A
Up to 2 A
No OTG
16 bit ADC
Yes
Yes
No
Yes
Control Interface
I2C
I2C
Standalone
I2C
Status Pin
/PG
STAT, /PG
STAT, /PG
STAT, /PG
Package
2.1x2.1 WCSP-25
4x4 QFN-24
4x4 QFN-24
4x4 QFN-24
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6 Pin Configuration and Functions
RGE Package (Standalone)
24-Pin VQFN
Top View
D+
VBUS
PMID
PMID
GND
GND
24
23
22
21
20
19
D-
1
18
SW
STAT
2
17
SW
/CE
3
16
SYS
GND
4
15
SYS
OTG
5
14
BAT
VSET
6
13
BAT
BQ25886
RGE, 4x4
8
9
10
11
TS
ILIM
/PG
ICHGSET
REGN
12
BTST
7
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
D+
24
AIO
Positive USB data line – D+/D– based USB host/charging port detection. The detection includes
data contact detection (DCD) and secondary detection in BC1.2.
D–
1
AIO
Negative USB data line – D+/D– based USB host/charging port detection. The detection includes
data contact detection (DCD) and secondary detection in BC1.2.
STAT
2
DO
Open drain charge status indicator – Connect to the pull-up rail via 10-kΩ resistor. LOW indicates
charge in progress. HIGH indicates charge complete or charge disabled. When any fault occurs, the
STAT pin blinks at 1Hz.
CE
3
DI
Active Low Charge Enable Pin – Battery charging is enabled when CE pin is LOW. CE pin is
internally pulled low with 900k-Ω resistor.
OTG
5
DI
OTG – USB On-The-Go Enable input. Pull high to enable OTG function. Pull low to disable OTG
function.
VSET
6
AI
Battery Charge Voltage Limit – VSET pin sets battery charge voltage. Program battery regulation
voltage with a resistor pull-down from VSET to GND as follows:
RVSET< 18kΩ (short to GND) = 8.2 V
RVSET= 39kΩ (±10%) = 8.8 V
RVSET= 75kΩ (±10%) = 8.7 V
RVSET> 150kΩ (floating) = 8.4 V
TS
7
AI
Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor.
Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends
when TS pin is out of range. Recommend 103AT-2 thermistor.
AI
Input Current Limit (IINDPM) – ILIM pin sets the maximum input current and can be used to
monitor input current. IINDPM loop regulates ILIM pin voltage at 0.8V. When ILIM pin is less than
0.8V, the input current can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8V). A resistor
connected from ILIM pin to ground sets the input current limit as maximum (IINMAX = KILIM /
RILIM). When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. Input
current limit less than 500mA is not supported on ILIM pin. Do not float this pin.
ILIM
4
8
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Pin Functions (continued)
PIN
NAME
PG
NO.
9
I/O
DESCRIPTION
DO
Open drain active low power good indicator – Connect to the pull up rail via 10-kΩ resistor. LOW
indicates a good input source if the input voltage is within VVBUS_OP (3.9 V), and can provide more
than IPOORSRC (30 mA).
ICHGSET
10
AI
Charge Current Limit – A resistor from ICHGSET to GND is used to program the charge current.
The acceptable programming range on ICHGSET pin is 30mA (114Ω) – 2.2A (8kΩ). Pre-charge and
termination current is 1/10 of the fast charge current. The minimum pre-charge current is clamped at
30mA (typ). Minimum termination current is clamped at 10mA (typ). ICHGSET short to GND clamps
charge current to minimum setting 30mA (typ). Floating ICHGSET disables charge.
REGN
11
P
Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a
4.7-µF ceramic capacitor. REGN current limit is 50 mA.
BTST
12
P
PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap
diode. Connect a 47nF bootstrap capacitor from SW to BTST.
BAT
13, 14
P
Battery Power Connection – Connect minimum recommended 10-µF capacitance after derating
closely to the BAT pin and GND.
SYS
15, 16
P
System Connection – The internal BATFET is connected between SYS and BAT. When the battery
falls below the minimum system voltage, the switch-mode converter keeps SYS above the minimum
system voltage. Connect a 2x22-µF capacitance after derating closely to the SYS pin and PGND.
SW
17, 18
P
Inductor Connection – Connect to the switched side of the external inductor.
GND
19, 20, 4
–
Ground Return
PMID
21, 22
P
Blocking MOSFET Connection – The minimum recommended total input low-ESR capacitance on
VBUS and PMID, after applied derating, is 10 uF. At least 1-uF is recommended at VBUS with the
remainder at PMID. Typical value for PMID is 10 uF.
VBUS
23
P
Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1µF ceramic capacitor, placed as close to the IC as possible.
NC
1
–
No Connect – Leave these pins floating or tie to ground.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
VBUS (converter not switching)
-0.3
20
V
PMID (converter not switching)
-0.3
8.5
V
BAT, SYS (converter not switching)
-0.3
12
V
(2)
13
V
BTST
-0.3
19
V
REGN, STAT, /PG, TS
-0.3
6
V
ILIM
-0.3
5
V
BTST to SW
-0.3
6
V
D+, D-, ICHGSET, VSET, /CE
-0.3
6
V
6
mA
SW
Voltage Range (with respect to GND unless otherwise
specified)
Output Sink Current
-0.3
STAT, /PG
UNIT
Junction Temperature, TJ
–40
150
°C
Storage temperature, Tstg
–40
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
-2V for 50ns
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VVBUS
Input Voltage
IVBUS
NOM
MAX
UNIT
6.2
V
Average input current (VBUS)
3.3
A
IBAT
Average charge current (IBAT)
2.2
A
IBAT_RMS
RMS discharging current with internal MOSFET
5
A
IBAT_PK
Peak discharging current with internal MOSFET
9 (up to
1us)
A
VBAT
Battery Voltage
TA
Operating free-air temperature range
(1)
6
4.3
-40
9.2 (1)
V
85
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on SW pin. A tight layout minimizes
switching noise.
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7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
BQ25886
THERMAL METRIC
(1)
RGE (VQFN)
UNIT
24-PIN
RΘJA
Junction-to-ambient thermal resistance (EVM (2))
18
°C/W
RΘJA
Junction-to-ambient thermal resistance (JEDEC (1))
32.4
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
26.7
°C/W
RΘJB
Junction-to-board thermal resistance
10.7
°C/W
ΨJT
Junction-to-top characterization parameter
0.4
°C/W
ΨJB
Junction-to-board characterization parameter
10.6
°C/W
RΘ JC(bot)
Junction-to-case (bottom) thermal resistance
3.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Measured on 35µm thick copper, 4-layer board
7.5 Electrical Characteristics
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
IBAT
IVBUS_HIZ
IVBUS
Battery discharge current (BAT)
Input supply current (VBUS) in HIZ
Input supply current (VBUS)
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ=25C, ADC Disabled
12
14
µA
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ < 85C, ADC Disabled
12
20
µA
VBUS = 5 V, High-Z Mode, no battery,
25℃
30
48
µA
VBUS = 5 V, High-Z Mode, no battery,
<85℃
30
55.2
µA
VBUS = 5 V, VBAT = 7.6 V, converter not
switching
1.5
3
mA
VBUS = 5 V, VBAT = 7.6 V, converter
switching, ISYS = 0A
3
mA
VBUS/VBAT POWER UP
VVBUS_OP
VBUS operating range
VVBUS_UVLO_RISING
VBUS rising, no battery
VBUS rising
VBUS over-voltage rising threshold
VBUS rising
6.2
VBUS over-voltage falling threshold
VBUS falling
5.9
VPOORSRC_FALLING
Bad adapter detection threshold
VBUS falling below VPOORSRC_FALLING
IPOORSRC
Bad adapter detection current source
VVBUS_OV
4.3
3.3
6.2
V
3.68
V
6.6
V
6.4
V
3.7
V
15
mA
ISYS = 0A, VBAT = 8.80 V > SYS_MIN,
Charge Disabled
100
mV
ISYS = 0A, VBAT < SYS_MIN, Charge
Disabled
200
mV
6.2
6.4
V
POWER-PATH
VSYS
VSYS_MIN
Typical System Regulation Voltage
System Regulation Voltage
VBAT < SYS_MIN, Charge Disabled
BATTERY CHARGER
VREG_ACC
Charge voltage
RVSET < 18 kΩ, VREG = 8.20 V, TJ =
-40℃ - 85℃
8.159
8.2
8.241
V
VREG_ACC
Charge voltage
RVSET = 39 kΩ (±10%), VREG = 8.80 V,
TJ = -40℃ - 85℃
8.756
8.8
8.844
V
VREG_ACC
Charge voltage
RVSET = 75 kΩ (±10%), VREG = 8.70 V,
TJ = -40℃ - 85℃
8.656
8.7
8.744
V
VREG_ACC
Charge voltage
RSET > 150kΩ,VREG = 8.40 V, TJ =
-40℃ to 85℃
8.358
8.4
8.442
V
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Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
ICHG = RICHGSET/KICHGSET. ICHG = 1000
mA
TYP
MAX UNIT
KICHGSET
Charge current regulation setting
ratio
ICHG_RANGE
Charge current regulation range
30
2200
mA
ICHG_ACC
Fast Charge current regulation
accuracy
ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
-7.5
7.5
%
ICHG_ACC
Fast Charge current regulation
accuracy
ICHG = 500mA, VBAT = 6.2 V or 7.6 V, TJ
= 0°C to 85°C
-15
15
%
ICHG_ACC
Fast Charge current regulation
accuracy
ICHG = 250 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
-25
25
%
IPRECHG_RANGE
Precharge current range
Ω/A
3810
30
800
mA
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
25°C
170
237
mA
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
0°C to 85°C
150
245
mA
10
800
mA
ITERM_ACC
ICHG = 1.5A, ITERM = 150 mA, TJ = 25°C
143
159
mA
ITERM_ACC
ICHG = 1.5A, ITERM = 150 mA, TJ = 0°C
to 85°C
120
180
mA
ICHG = 1.5A, ITERM = 50 mA, TJ = 25°C
42
60
mA
ICHG = 1.5A, ITERM = 50 mA, TJ = 0°C to
85°C
18
75
mA
IPRECHG_ACC
ITERM_RANGE
ITERM_ACC
Precharge current accuracy
Termination current range
Termination current accuracy
ITERM_ACC
VBAT_SHORT_RISING
Short Battery Voltage rising threshold
VBAT rising
to start pre-charging
4.1
4.4
4.7
V
VBAT_SHORT_FALLIN
Short Battery Voltage falling
threshold to stop pre-charging
VBAT falling
3.7
4
4.3
V
IBAT_SHORT
Low Battery Voltage trickle charging
current
VBAT < 4.4 V
VBAT_LOWV_RISING
VBAT LOWV Rising threshold to
start fast-charging
VBAT rising, VBATLOWV = 6.0 V
5.7
6
6.3
V
VBAT_LOWV_FALLING
VBAT LOWV Falling threshold to
stop fast-charging
VBAT falling, VBATLOWV = 6.0 V
5.3
5.6
5.9
V
VRECHG
Recharge threshold below VREG
VBAT falling
TJ = 25°C
32
35
mΩ
RON_QHS (Q2)
High-side switching MOSFET onresistance between SW and
SYS (Q2)
TJ = – 40°C to 125°C
32
47
mΩ
Low-side switching MOSFET onresistance between SW and GND
(Q3)
TJ = 25°C
42
46
mΩ
RON_QLS (Q3)
TJ = – 40°C to 125°C
42
63
mΩ
RON_QBAT (Q4)
MOSFET on-resistance between
SYS and BAT (Q4)
TJ = 25°C
18
19
mΩ
RON_QBAT (Q4)
MOSFET on-resistance between
SYS and BAT (Q4)
TJ = – 40°C - 85°C
18
23
mΩ
IBAT_DISCHG
BAT Discharge current source
VBAT = 8V, EN_BAT_DISCHG = 1
8
11.5
16
mA
4.171
4.3
4.429
G
100
mA
200
mV
INPUT VOLTAGE / CURRENT REGULATION
VINDPM
Input voltage regulation range
KILIM
IINMAX = KILIM/RILIM
IINDPM
Input Current regulation by ILIM pin = 0.5A
Input current regulation limit, IINMAX =
Input Current regulation by ILIM pin = 0.9A
KILIM/RILIM
Input Current regulation by ILIM pin = 1.5A
RON_QBLK (Q1)
8
Input Current regulation by ILIM pin
Blocking MOSFET on-resistance
between VBUS and PMID (QBLK)
Ax
Ω
1110
457
505
V
553
mA
mA
839
909
980
1413
1518
1624
mA
TJ = 25°C
33
37
mΩ
TJ = – 40°C to 125°C
33
51
mΩ
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Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
500
600
700
mV
7
10
14
µA
50
100
150
µA
250
400
mV
14.25
24.8
kΩ
800
mV
D + /D- DETECTION
VD+D-_600MVSRC
D+/D- Voltage Source (600 mV)
ID+_10UASRC
D+ Current Source (10 µA)
ID+D-_100UASNK
D+/D- Current Sink (100 µA)
VD+D-_0P325
D+/D- Comparator Threshold for
Secondary Detection
RD-_19K
D- Resistor to Ground (19 kΩ)
VD+_0P8
D+ Comparator Threshold for Data
Contact Detection
VD+D-_1P2
D+/D- Threshold for Non-standard
adapter
1.05
1.35
V
VD+D-_2P0
D+/D- Comparator Threshold for
Non-standard adapter
1.85
2.15
V
VD+D-_2P8
D+/D- Threshold for Non-standard
adapter
2.55
2.85
V
ID+D-_LKG
D+/D- Leakage Current
-1
1
µA
HiZ
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP_RISING
Battery over-voltage rising threshold
VBAT rising, as percentage of VREG
102.5
104
105
%
VBAT_OVP_FALLING
Battery over-voltage falling threshold
VBAT falling, as percentage of VREG
101
102
103.3
%
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG
TSHUT_RISING
Junction temperature regulation
accuracy
TREG = 120°C
120
°C
Thermal Shutdown Rising threshold
Temperature Increasing
150
°C
Thermal Shutdown Falling threshold
Temperature Decreasing
120
°C
JEITA THERMISTOR COMPARATOR (BOOST MODE)
VT1
TS pin voltage rising. T1 (0°C)
threshold, Charge suspended below
this temperature.
As Percentage to REGN
VT1_HYS
TS pin voltage falling. Charge reenabled to ICHG/2 and VREG above
this temperature
As Percentage to REGN
VT2
TS pin voltage rising. T2 (10°C)
threshold, charge set to ICHG/2 and
VREG below this temperature
As Percentage to REGN
VT2_HYS
TS pin voltage falling. Charge set to
ICHG and VREG above this
temperature
As Percentage to REGN
VT3
TS pin voltage falling. T3 (45°C)
threshold, charge set to ICHG and
8.1 V above this temperature.
As Percentage to REGN
VT3_HYS
TS pin voltage rising. Charge set to
ICHG and VREG below this
temperature
As Percentage to REGN
VT5
TS pin voltage falling. T5 (60°C)
threshold, charge suspended above
this temperature.
As Percentage to REGN
VT5_HYS
TS pin voltage rising. Charge set to
ICHG and 8.1 V below this
temperature
As Percentage to REGN
72.75
73.25
73.75
1.3
67.75
68.25
%
68.75
1.2
44.25
44.75
34.375
%
%
45.25
1
33.875
%
%
%
34.875
1.35
%
%
COLD/HOT THERMISTOR COMPARATOR (OTG BUCK MODE)
VBCOLD0
Cold Temperature Threshold, TS pin
Voltage Rising Threshold
As Percentage to REGN (Approx. – 10°C
w/ 103AT)
VBCOLD0_HYS
Cold Temperature Threshold, TS pin
Voltage Falling Threshold
As Percentage to REGN
76.5
77
77.5
1
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Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBHOT1
Hot Temperature Threshold, TS pin
Voltage falling Threshold
As Percentage to REGN (Approx. 60°C w/
103AT)
VBHOT1_HYS
Hot Temperature Threshold, TS pin
Voltage rising Threshold
As Percentage to REGN
MIN
TYP
33.875
34.375
MAX UNIT
34.875
3
%
%
BOOST MODE CONVERTER
FSW
PWM switching frequency
Oscillator frequency
1.35
1.5
5.1
1.65 MHz
OTG BUCK MODE CONVERTER
VOTG_ACC
OTG Buck mode voltage regulation
accuracy
IVBUS = 0A, OTG_VLIM = 5.1V
4.947
VOTG_ACC
OTG Buck mode voltage regulation
accuracy
IVBUS = 0A, OTG_VLIM = 5.1 V
-3
IOTG_ACC
OTG Buck mode current regulation
accuracy
OTG_ILIM = 2A
VOTG_OVP
OTG Buck mode over-voltage
threshold
-15
-7.5
5.8
6
4.8
5.253
V
3
%
0
%
V
REGN LDO
VREGN
REGN LDO output voltage
VVBUS = 5 V, IREGN = 20 mA
4.7
IREGN
REGN LDO current limit
VVBUS = 5 V, VREGN = 3.8 V
50
5.15
V
mA
LOGIC I/O PIN (/CE)
VIH_CEZ
Input high threshold level, /CE
VIL_CEZ
Input low threshold level, /CE
IIN_BIAS_CEZ
High level leakage current, /CE
1.3
V
0.4
V
Pull-up rail 1.8 V
2.5
uA
0.4
V
1
µA
LOGIC O PIN (/INT, /PG, STAT)
VOL
Output low threshold level
Sink current = 5 mA
IOUT_BIAS
High level leakage current
Pull-up rail 1.8 V
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
tVBUS_OV
VBUS OVP reaction time
tPOORSRC
Bad adapter detection duration
VBUS rising above VBUS_OV threshold to
converter turn off
200
ns
30
ms
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge termination
Charge current falling below ITERM
250
ms
tRECGH_DGL
Deglitch time for recharge threshold
BAT voltage falling below VRECHG = 100
mV
250
ms
tBAT_OVP_DGL
Deglitch time for battery over-voltage
to disable charge
1
µs
tSAFETY
Charge Safety Timer Accuracy
CHG_TIMER = 12 hours
10.8
12
13.2
hr
DIGITAL CLOCK AND WATCHDOG TIMER
fLPDIG
Digital low power clock
REGN LDO disabled
18
30
fDIG
Digital clock
REGN LDO enabled
1.35
1.5
10
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kHZ
1.65 MHz
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7.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSYS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
95
95
VBAT = 7.6 V
VBAT = 8.0 V
93
93
92
92
91
90
89
91
90
89
88
88
87
87
86
86
85
85
0
0.2
0.4
0.6
0.8
1
1.2 1.4
Charge Current (A)
1.6
1.8
VBAT = 7.6 V
VBAT = 8.0 V
94
Efficiency (%)
Efficiency (%)
94
2
0
VBUS = 5V
0.4
VBUS = 5V
Figure 1. Charge Efficiency vs. Charge Current
0.6
0.8
1
1.2 1.4
Charge Current (A)
95
90
90
85
85
80
75
70
65
60
1.8
2
D001
L = 1µH (IHLP2525CZER1R0k01)
80
75
70
65
60
PFM En, OOA En
55
0.01
0.02 0.03
VBUS = 5V
0.050.07 0.1
0.2 0.3
System Current (A)
0.5 0.7
PFM En, OOA En
55
0.01
1
0.02 0.03
D016
VBAT = 8.4V
VBUS = 5V
Figure 3. System Efficiency vs. System Current
0.050.07 0.1
0.2 0.3
System Current (A)
VBAT = 8.4V
0.5 0.7
1
D017
L = 1µH (IHLP2525CZER1R0k01)
Figure 4. System Efficiency vs. System Current
95
96
90
91
85
86
Efficiency (%)
Efficiency (%)
1.6
Figure 2. Charge Efficiency vs. Charge Current
95
System Efficiency (%)
System Efficiency (%)
0.2
D001
80
75
70
65
81
76
71
66
60
61
PFM En, OOA En
55
0.01
0.02 0.03
VBUS = 5V
0.050.07 0.1
IBUS (A)
0.2 0.3
0.5 0.7
PFM En, OOA En
1
56
0.01
D018
VBAT = 7.6V
VBUS = 5V
Figure 5. OTG Efficiency vs. VBUS Output Current
0.02 0.03
0.050.07 0.1
IBUS (A)
VBAT = 7.6V
0.2 0.3
0.5 0.7
1
D019
L = 1µH (IHLP2525CZER1R0k01)
Figure 6. OTG Efficiency vs. VBUS Output Current
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Typical Characteristics (continued)
CVBUS = 1µF, CPMID= 10µF, CSYS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
10
10
VBAT = 6.6 V
VBAT = 7.6 V
7.5
5
Accuracy (%)
Accuracy (%)
5
2.5
0
-2.5
2.5
0
-2.5
-5
-5
-7.5
-7.5
-10
-10
0
0.2
0.4
0.6
0.8
1
1.2 1.4
ICHG Setting (A)
1.6
1.8
2
0
0.4
0.6
VBUS = 5V
Figure 7. Charge Current Accuracy vs. ICHG Setting
0.8
1
1.2 1.4
ICHG Setting (A)
1.6
1.8
2
D004
L = 1µH (IHLP2525CZER1R0k01)
Figure 8. Charge Current Accuracy vs. ICHG Setting
225
8.56
200
8.55
8.54
175
System Voltage (V)
Offset from SYS_MIN (mV)
0.2
D004
VBUS = 5V
150
125
100
75
50
8.53
8.52
8.51
8.5
8.49
8.48
8.47
25
8.46
0
0.8
1.0
VBUS = 5V
1.2
1.4
System Current (A)
1.6
8.45
0.3
1.8
0.4
0.5
D006
VBAT = 6V, EN_CHG = 0
SYSMIN = 7V
VBUS = 5V
Figure 9. SYSMIN Load Regulation
0.6
0.7
0.8
System Current (A)
0.9
1
D007
VBAT = 8.4V
EN_CHG = 0
Figure 10. System Load Regulation After Charge Done
2.0
3.0
-40°C
0°C
25°C
85°C
2.5
2.0
ICHG = 0.5A
ICHG = 1.0A
ICHG = 1.4A
1.8
1.6
Charge Current (A)
1.5
Accuracy (%)
VBAT = 6.6 V
VBAT = 7.6 V
7.5
1.0
0.5
0.0
-0.5
-1.0
1.4
1.2
1.0
0.8
0.6
-1.5
0.4
-2.0
-2.5
0.2
-3.0
0.0
90
6
6.3
6.6
VBUS = 5.1V
6.9
7.2
7.5
7.8
VBAT Voltage (V)
8.1
8.4
8.7
IBUS = 1A
100
105
110
115
Die Temperature (°C)
120
125
130
D015
VBUS = 5V
VBAT = 7.6V
ICHG = 0.5A, 1.0A, 1.4A
Measured on 35-µm thick copper, 4-layer board
Figure 11. OTG Voltage Regulation vs. VBAT Voltage
12
95
D010
Figure 12. Max Current Temperature Profile
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8 Detailed Description
8.1 Overview
The BQ25886 device is a highly integrated 2-A switch-mode battery charger for 2s Li-Ion and Li-polymer battery.
It integrates the input blocking FET (Q1, QBLK), high-side switching FET (Q2, QHS), low-side switching FET
(Q3, QLS), and battery FET (Q4, QBAT). The device also integrates the boot-strap diode for high-side gate drive.
8.2 Functional Block Diagram
PMID
VBUS
VVBUS_UVLO_RISING
+
UVLO
QBLK
CONTROL
REGN
REGN
REGN
LDO
EN_HIZ
+
QBLK
(Q1)
BTST
VBUS_OVP
VVBUS_OV
VOREF
VVBUS
VOTG_OVP
VVBUS
IIN
+
+
+
VINDPM
+
+
IC_TJ
+
TREG
QHS
(Q2)
(1)
IQ2 OTG_Q2_OCP
+
SNS
6.2V
IHSOCP
BAT
BAT_OVP
BAT
+
VBAT_OVP
VBAT_REG
IINDPM
SYS
OTG_OVP(1)
+
SW
DC-DC
CONTROL
QLS
(Q3)
REGN
ICHG
GND
ICHG_REG
EN_CHARGE
GND
Q3_OCP
EN_HIZ
EN_OTG
ILIM
REF
DAC
CONVERTER
CONTROL
STATE
MACHINE
POORSRC
TSHUT
+
REFRESH
VBTST ± VSW
VBTST_REFRESH
SYS
TSHUT
ICHG
QBAT
(Q4)
VBAT_REG
ICHGSET
ICHG_REG
D-
+
IC_TJ
VSET
D+
ILSOCP
VPOORSRC
VVBUS
+
+
IQ3
QBAT
CONTROL
BAT
USB
DETECTION
RECHRG
+
/PG
TERMINATION
+
VREG - VRECHG
BAT
ICHG
ITERM
CHARGE
CONTROL
STATE
MACHINE
STAT
BATLOWV
BATUVLO
+
+
VBAT_LOWV
BAT
VBAT_UVLO_RISING
BAT
TS_SUSPEND
OTG
VTS
BATTERY
SENSING
THERMISTOR
TS
/CE
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8.3 Feature Description
8.3.1 Device Power-On-Reset
The internal bias circuits are powered from either VBAT or VBUS when it rises above VVBUS_UVLO_RISING or
VBAT_UVLO_RISING. When VBUS rises above VVBUS_UVLO_RISING or BAT rises above VBAT_UVLO_RISING, the BATFET
driver is active.
8.3.2 Device Power Up from Battery without Input Source
If only the battery is present and the voltage is above UVLO threshold (VBAT_UVLO_RISING), the BATFET turns on
and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
8.3.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the boost converter is started. The power up
sequence from input source is as listed:
1. Poor Source Qualification
2. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINDPM) and input source
type
3. Power Up REGN LDO
4. Converter Power-up
8.3.3.1 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the boost converter.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC (typical 15mA)
If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage fault
goes away. If a poor source is detected (condition 2 above), the device repeats poor source qualification routine
every 2 seconds. After 7 consecutive failures, the device goes to HIZ mode. The battery powers up the system
when the device is in HIZ. On BQ25886, adapter re-plugin is required to restart device operation. If the fault is
not removed, the part will enter HIZ mode again after the 7 consecutive failures.
8.3.3.2 Input Source Type Detection
After input source is qualified, the charger device runs input source type detection.
The BQ25886 sets input current limit through D+/D- pin. After input source type detection, /PG pin is pulled LOW.
The charger input current is always limited by the lower of ILIM pin or input source detection (500mA or 900mA),
Input Current Optimizer (ICO) setting if a DCP is detected.
8.3.3.2.1 D+/D– Detection Sets Input Current Limit
The BQ25886 contains a D+/D- based input source detection to program the input current limit. The D+/Ddetection has three major steps: Data Contact Detect (DCD), Primary Detection, and Secondary Detection.
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Feature Description (continued)
Unknown/500mA
Divider 3/1A
Divider 1/2.1A
Divider 4/2.4A
Non-Standard
Adapter
Adapter Plug-in
or
FORCE_INDET
Data Detection
Contact
(DCD)
VBUS Detection
Primary
Detection
Secondary
Detection
SDP
(500mA)
CDP
(1500mA)
DCP
(3000mA)
USB BC1.2 Standard
Figure 13. D+/D- Detection Flow
Table 2. Non-Standard Adapter Detection
NON-STANDARD
ADAPTER
D+ THRESHOLD
D– THRESHOLD
INPUT CURRENT LIMIT
Divider 1
VD+ within V2P8_VTH
VD– within V2P0_VTH
2.1 A
Divider 3
VD+ within V2P0_VTH
VD– within V2P8_VTH
1A
Divider 4
VD+ within V2P8_VTH
VD– within V2P8_VTH
2.4 A
Table 3. Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION
INPUT CURRENT LIMIT (IINDPM)
USB SDP (USB500)
500 mA
USB CDP
1.5 A
USB DCP
3.0 A
Divider 3
1A
Divider 1
2.1 A
Divider 4
2.4 A
Unknown 5V Adapter
500 mA
8.3.3.3 Power Up REGN Regulator (LDO)
The REGN LDO supplies internal bias circuits as well as the QHS and QLS gate drive. The LDO also provides
bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLO_RISING in boost mode or VBUS below VVBUS_UVLO_RISING in buck mode
2. Poor Source Qualification detects a valid input source
3. Input Source Type Detection completes and sets appropriate input current limit
4. After 220-ms delay is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
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8.3.3.4 Converter Power Up
After the input current limit is set, the PG pin is pulled LOW, and the converter is enabled, allowing the QHS and
QLS to start switching.Before charging begins, the battery discharge source (IBAT_DISCHG) is enabled
automatically to detect the presence of battery. BATFET stays on to charge the battery. The device provides softstart when system rail is ramped up.
As a battery charger, the device deploys a highly efficient 1.5-MHz boost switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current and temperature, simplifying output filter design.
In order to improve light-load efficiency, the device switches to PFM (Pulse Frequency Modulation) control at light
load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation,
the switching duty cycle is set by the ratio of SYS and VBUS.
8.3.4 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without
overloading the input source. The algorithm automatically identifies maximum input current limit of a power
source without staying in VINDPM to avoid input source overload.
On BQ25886, ICO starts automatically when DCP type of input source is detected. When other input source typs
are detected, ICO is disabled. The actual input current limit used by the Dynamic Power Management circuitry is
limited by the lower value of current limit identified by the ICO algorithm or the current limit set by the ILIM pin.
When the algorithm is enabled, it runs continuously to adjust input current limit of Dynamic Power Management
(IINDPM) using ICO algorithm. When optimal input current is identified, the input current limit set by ICO will not
be changed until the algorithm is forced to run by the following event:
1. A new input source is plugged-in
2. VINDPM is entered
3. VBUS_OVP event
Table 4. Input Current Optimizer Automatic Operation
DEVICE
BQ25886 (D+/D–)
INPUT SOURCE
INPUT CURRENT LIMIT
(IINDPM)
AUTOMATIC START ICO
ALGORITHM
USB SDP (USB500)
500 mA
Disable
USB CDP
1.5 A
Disable
USB DCP
3.0 A
Enable
Divider 3
1A
Disable
Divider 1
2.1 A
Disable
Divider 4
2.4 A
Disable
Unknown 5V Adapter
500 mA
Disable
8.3.5 Buck Mode Operation from Battery (OTG)
The device supports buck converter operation to deliver power from the battery to other portable devices through
USB port. The buck mode output current rating meets the USB On-The-Go 500-mA output requirement. The
maximum output is 2.0 A. The buck operation is enabled when the following conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than VVBUS_PRESENT
3. Buck mode operation is enabled (OTG pin is pulled high)
4. Voltage at TS (thermistor) pin is within range BHOT and BCOLD
5. After 30-ms delay from buck mode enable
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8.3.6 PowerPath Management
The device accommodates a wide range of input sources from USB, to wall adapter, to power bank. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. Even with a
fully depleted battery, the system is regulated above the minimum system voltage (fixed 6.2 V (typ)).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 200 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, the BATFET is fully on and the voltage difference between the system and
battery is the the BATFET's drain to source voltage drop.
When the battery charging is disabled and VBAT is above minimum system voltage setting or charging is
terminated, the system is always regulated at typically 50mV above battery voltage.
9.0
8.6
Charge Enabled
SYS (V)
8.2
7.8
Charge Disabled
7.4
7.0
Minimum System Voltage
6.6
6.2
5.4
5.8
6.2
6.6
7.0 7.4
BAT (V)
7.8
8.2
8.6
Figure 14. System Voltage vs. Battery Voltage
8.3.6.2 Dynamic Power Management
To meet the maximum current limit in the USB spec and avoid over loading the adapter, the device features
Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. As the
charger's system load plus charge current increases with constant input voltage, the charger's input current must
increase. If this current exceeds the charger's preset input current limit or causes the input source voltage to
droop near the input voltage limit (VINDPM fixed at 4.3 V typical), the device then reduces the charge current
until the input current is regulated to the input current limit or the input voltage is regulated to the VINDPM
threshold.Note that if the D+/D- algorithm detected a DCP port and VINDPM triggered, the ICO algorithm lowers
the input current limit.
If the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop.
Once the system voltage falls below the battery voltage, the device automatically enters the Supplement Mode
where the BATFET turns on and battery starts discharging so that the system is supported from both the input
source and battery.
The figure shows the DPM response with 5-V/3-A adapter, 6.4-V battery, 1.5-A charge current and 6.8 V
minimum system voltage setting.
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VSYS
7.0V
6.8V
6.4V
6.0V
VBAT
VBUS
5.0V
4.0V
3A
IBUS
2A
IBAT
1A
ISYS
0A
-1A
CC
DPM
DPM
CC
Supplement
Figure 15. DPM Response
8.3.6.3 Supplement Mode
When the voltage falls below the battery voltage, the BATFET turns on.
VBAT - VSYS (mV)
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the
BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current.
The figure shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit Supplement
Mode when the battery is below battery depletion threshold (VBAT_UVLO_RISING).
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0
0.5
1
1.5
2
2.5
3
IBAT(A)
3.5
4
4.5
5
D001
Figure 16. BATFET I-V Curve
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8.3.7 Battery Charging Management
The BQ25886 charges 2-cell Li-Ion battery with up to 2.2-A charge current for high capacity battery. The low
RDS(ON) BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.3.7.1 Autonomous Charging Cycle
When battery charging is enabled (CE pin is LOW), the device autonomously completes a charging cycle without
host involvement. The device default charging parameters are listed in Table 5 below.
Table 5. Charging Parameter Default Settings
DEFAULT MODE
BQ25886
Charging Voltage
Set by VSET
Charging Current
Set by ICHGSET
Pre-Charge Current
1/10 of ICHG
Termination Current
1/10 of ICHG
Temperature Profile
JEITA
Safety Timer
12 hours
A new charge cycle starts when the following conditions are valid:
1. Converter starts
2. No thermistor fault on TS
3. No safety timer fault
The charger automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device is not in DPM mode or thermal regulation.
When a full battery voltage is discharged below recharge threshold (threshold fixed at 200 mV for BQ25886), the
device automatically starts a new charging cycle. After the charge is done, toggle CE pin can initiate a new
charging cycle.
The STAT output indicates the charging status of: charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). If no battery is connected, the STAT pin blinks as capacitance connected at BAT
charges, discharges, then recharges.
8.3.7.2 Battery Charging Profile
The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off timer charging. At the beginning of a charging cycle, the device checks the battery voltage and regulates
current/voltage accordingly.
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate, as explained in the Charging Safety Timer section.
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VREG
Battery Voltage
ICHG
Charge Current
VBATLOWV
VBAT_SHORT
IPRECHG
ITERM
Figure 17. Battery Charging Profile
8.3.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the STAT pin goes HIGH. Termination is temporarily disabled when the charger device
is in input current, voltage or thermal regulation. On the BQ25886, termination threshold is 1/10 of the fast
charge current setting.
8.3.7.4 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.7.4.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge
current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V / cell.
On the BQ25886, at cool temperature (T1-T2), the charge current is reduced to 20% of the fast charge current,
ICHG. At warm temperature (T3 - T5), the charge voltage is set to 8.0 V. Whenever the charger detectes "warm"
or "cool" temperature, termination is automatically disabled.
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RT1
REGN
2s Battery
10K
RT2
TS
BQ2588x
Figure 18. TS Resistor Network
100
%
Percentage of
ICHG
Charging Voltage
VREG
80%
60%
40%
8.3V
8.0V
20%
T1
0°C
T2
10°
C
TS Temperature
T3
45°
C
T5
60°
C
T1
0°C
T2
10°
C
TS Temperature
T3
45°
C
T5
60°
C
Figure 19. TS Charging Values
Assuming a 103AT NTC (Negative Temperature Coefficient) thermistor on the battery pack as shown above, the
value of RT1 and RT2 can be determined by:
RT 2
RT 1
§ 1
1 ·
RNTC ,T 1 u RNTC ,T 5 u ¨
¸
© VT 5 VT 1 ¹
§ 1
·
§ 1
·
1¸ RNTC ,T 5 u ¨
1¸
RNTC ,T 1 u ¨
© VT 1 ¹
© VT 5 ¹
1
1
VT 1
1
1
RT 2 RNTC ,T 1
(1)
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
RNTC,T1 = 27.28 kΩ
RNTC,T5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ
8.3.7.5 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions.
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During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the setting. For example, if the charger is in input current regulation throughout the
whole charging cycle, and the safety timer is set to 12 hours, then the timer will expire in 24 hours.
During faults which disable charging, or supplement mode, timer is suspended. Once the fault goes away, safety
timer resumes. If the charging cycle is stopped and started again, the timer gets reset.
The safety timer is reset for the following events:
1. Charging cycle stop and restart (toggle CE pin, or charged battery falls below recharge threshold).
2. BAT voltage changes from pre-charge to fast-charge or vice versa.
The precharge safety timer (fixed 2hr counter that runs when VBAT < VBAT_LOWV), follows the same rules as the
fast-charge safety timer in terms of getting suspended, reset, and counting at half-rate.
8.3.8 Status Outputs
8.3.8.1 Power Good Indicator (PG)
The open drain PG pin goes low to indicate a good input source when:
1. VBUS above VVBUS_UVLO_RISING
2. VBUS below VVBUS_OV threshold
3. VBUS above VPOORSRC (typ. 3.7 V) when IPOORSRC (typ. 30 mA) current is applied (not a poor source)
4. Input Source Type Detection is completed
8.3.8.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.
Table 6. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including trickle charge, pre-charge, fastcharge, recharge)
LOW
Charging complete
HIGH
Sleep mode, charge disable
HIGH
Charge suspend (Input over-voltage, TS fault, timer fault or battery
over-voltage) OTG Buck Mode suspend (due to TS fault)
Blinking at 1Hz
8.3.9 Input Current Limit on ILIM Pin
For safe operation, the BQ2588x has an additional hardware pin on ILIM to limit maximum input current. The
maximum input current is set by a resistor from ILIM pin to ground as:
K
IINMAX = ILIM
RILIM
(3)
The actual input current limit is the lower value between ILIM pin setting and current limit set by D+/D- detection.
The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters input current regulation
(refer to Dynamic Power Management section).
The ILIM pin can also be used to monitor input current. The voltage on ILIM pin is proportional to the input
current. ILIM can be used to monitor input current with the following relationship:
I IN
K ILIM u VILIM
RILIM u 0.8V
(4)
For example, if ILIM pin is set with 820-Ω resistor, and the ILIM voltage 0.5V, the actual input current is 0.795 A
to 0.973 A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 0.8 V.
8.3.10 Voltage and Current Monitoring
The device closely monitors the input voltage, as well as internal FET currents for safe boost and buck mode
operation.
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8.3.10.1 Voltage and Current Monitoring in Boost Mode
8.3.10.1.1 Input Over-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage exceeds VVBUS_OV, the
device stops switching immediately to protect the power FETs. The device automatically starts switching again
when the over-voltage condition goes away.
8.3.10.1.2 Input Under-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage falls below VPOORSRC during
operation, the device stops switching. The device automatically attempts to restart switching when the undervoltage condition goes away.
8.3.10.1.3 System Over-Voltage Protection
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above system regulation voltage.
Upon SYSOVP, converter stops immediately to clamp the overshoot.
8.3.10.1.4 System Over-Current Protection
The charger device continually monitors and compares VBUS to VSYS to protect against a system short-circuit
event. In the event that VSYS drops to within 250 mV of VBUS during operation, a short circuit event is flagged
and the converter stops switching. The device attempts to recover from this condition automatically.
8.3.10.2 Voltage and Current Monitoring in OTG Buck Mode
The device closely monitors the VBUS voltage, as well as RBFET (Q1, QBLK) and LSFET (Q3, QLS) current to
ensure safe buck mode operation.
8.3.10.2.1 VBUS Over-voltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters over-voltage
protection which stops switching, and exits buck mode.
8.3.10.2.2 VBUS Over-Current Protection
The device monitors output current to provide output short protection. The OTG buck mode has built-in constant
current regulation to allow OTG to adapt to various types of loads. If short circuit is detected on VBUS, the OTG
turns off and retries 7 times. If the retries are not successful, OTG is disabled.
8.3.11 Thermal Regulation and Thermal Shutdown
8.3.11.1 Thermal Protection in Boost Mode
The device monitors internal junction temperature, TJ, to avoid overheating and limits the IC surface temperature
in boost mode. When the internal junction temperature exceeds the thermal regulation limit (120°C), the device
reduces charge current.
During thermal regulation, the actual charging current is usually below the programmed value. Therefore,
termination is disabled, and the safety timer runs at half the clock rate.
Additionally, the device has thermal shutdown to turn off the converter when IC surface temperature exceeds
TSHUT. The converter turns back on when IC temperature is below TSHUT_HYS.
8.3.11.2 Thermal Protection in OTG Buck Mode
The BQ2588x monitors the internal junction temperature to provide thermal shutdown during OTG buck mode.
8.3.12 Battery Protection
8.3.12.1 Battery Over-Voltage Protection (BATOVP)
The battery over-voltage limit is clamped at 4% above the battery regulation voltage while charging. When
battery over-voltage occurs, the charger device immediately disables charge.
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8.4 Device Functional Modes
The BQ25886 is a standalone device and therefore does not include any functional modes for I2C operations.
24
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the BQ25886 configured as a standalone device and a 2s battery charger for LiIon and Li-Polymer batteries used in a wide range of portable devices. It integrates an input blocking FET (QBLK,
Q1), high-side switching FET (QHS, Q2), and low-side switching FET (QLS, Q3). The device also integrates a
bootstrap diode for the high-side gate drive.
9.2 Typical Application
5V @ 3A
VBUS
1 F
1 H
10 F
VREF
2.2K
Q1
30 F
2.2K
STAT
/PG
PMID
(optional)
Q2
SYS
SW
SYSTEM
LOAD
6.4V
47nF
44 F
BTST
ICHG=2A
Q4
10 F
4.7 F
BAT
REGN
Q3
2s Battery
D+
DVREGN
5.23K
OTG
/CE
TS
ILIM
150NŸ
30.1K
383Ÿ
BQ25886
VSET
10K
Host
`
5.7NŸ
ICHGSET
GND
Figure 20. BQ25886 (Stand-Alone) Typical Application Diagram
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 7 below.
Table 7. Design Parameters
PARAMETER
VALUE
VBUS voltage range
4.3 V to 6.2 V
Input current limit (ILIM)
2.4 A
Fast charge current limit (ICHGSET)
1.5 A
Minimum System Voltage
6.2 V
Battery Regulation Voltage (VSET)
8.4 V
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The
inductor saturation current should be higher than the input current (IIN) plus half the ripple current (IRIPPLE):
ISAT t IIN
IRIPPLE
2
(5)
The inductor ripple current (IRIPPLE) depends on input voltage (VVBUS), duty cycle (D = VBAT/VBUS), switching
frequency (fSW) and inductance (L):
VBUS u (VSYS VBUS )
VSYS u fSW u L
IRIPPLE
(6)
The maximum inductor ripple current happens in the vicinity of D = 0.5. Usually inductor ripple is designed in the
range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical
design.
9.2.2.2 Input (VBUS / PMID) Capacitor
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then
the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated
by
IPMID
IRIPPLE
| 0.29 u IRIPPLE
2u 3
(7)
A low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed close to the PMID and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
input voltage level. 25-V rating or higher capacitor is preferred for up to 5-V input voltage. A minimum 10-μF
capacitor is suggested for up to 3.3-A input current. Keep in mind, long impedance cable would cause significant
voltage drop with higher inrush current. For optimal performance, 44-uF cap on PMID is recommended. In
addition, a minimum 1-μF capacitor is suggested at VBUS pin.
9.2.2.3 Output (VSYS) Capacitor
The SYS capacitor is the boost converter output capacitor and should also have enough ripple current rating to
absorb output switching ripple current. The output capacitor RMS current ICOUT is given:
ICSYS , rms
IOUT u
D
1 D
(8)
The output capacitor voltage ripple is a function of the boost output current (IOUT), and can be calculated as
follows:
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IOUT u D
fSW u CSYS
(9)
A low ESR ceramic capacitor such as X7R or X5R is preferred for SYS decoupling capacitor and should be
placed close to the SYS and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
output voltage level. 16-V rating or higher capacitor is preferred. Minimum 44-μF capacitor is suggested for up to
2.2-A boost converter output current.
9.2.2.4 ILIM resistor
The ILIM resistor sets the maximum input current limit and can be used to monitor input current. The maximum
input current is set by a resistor from ILIM pin to ground as:
K
IINMAX = ILIM
RILIM
(10)
Using maximum input current limit 900mA as an example. The KLIM is 1110. If the maximum input current limit
cannot exceed 900mA, then IINMAX used in the calculation should be 819.9mA as regulation accuracy at
900mA (typ) setting is around +/-8.9%. Resistor accuracy should also be taken into consideration when setting
input current limit. When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. Input current
limit less than 500mA is not supported on ILIM pin. Do not float this pin.
9.2.2.5 ICHGSET resistor
A resistor from ICHGSET to GND is used to program the charge current. Pre-charge and termination current is
1/10 of the fast charge current. The minimum pre-charge current is clamped at 30mA (typ). Minimum termination
current is clamped at 10mA (typ). ICHGSET short to GND clamps charge current to minimum setting 30mA (typ).
Floating ICHGSET disables charge. RICHGSET can be calculated as:
ICHGSET
RICHGSET
KICHGSET
(11)
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9.2.3 Application Curves
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
VBUS = 5 V
VBAT = 6.0 V
ICHG = 1 A
VBUS = 5 V
Figure 21. Adapter Power Up with Charge Enabled
VBUS = 5 V
VBAT = 7.4 V
ICHG = 1 A
Figure 23. Charge Disabled
VBAT = 7.6 V
VBUS = 5.1 V
ICHG = 1 A
Figure 22. Charge Enable
VBUS = 5 V
VBAT = Open
Charge enabled
Figure 24. Adapter Plug-in with No Battery
No IBUS load
Figure 25. Buck Mode (OTG) Startup
28
VBAT = 7.4 V
VBAT = 7.6 V
Adapter removed
with OTG = HIGH
RBUS = 25 Ω
Figure 26. Buck Mode Startup After Adapter Removal
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CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
VBAT = 7.6 V
VBUS = 5.1 V
IBUS = 1 A
Figure 27. Buck Mode (OTG) PWM Switching
VBUS = 5 V
VBAT = 7.6 V
ICHG = 1 A
VBAT = 7.6 V
VBAT = 8.4 V
Charge disabled
IBUS = 0 mA
Figure 28. Buck Mode (OTG) PFM Switching
VBUS = 5 V
Figure 29. Boost Mode PWM Switching
VBUS = 5 V
VBUS = 5.1 V
VBAT = 8.4 V
Charge disabled
Figure 30. Boost Mode PFM Switching
DCP Adapter
Figure 31. System Load Transient Response
VBAT = 8.0 V
Charge enabled
Figure 32. VINDPM Transient Response
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CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
DCP Adapter
VBAT = 8.0 V
Charge enabled
Figure 33. IINDPM Transient Response
30
VBAT = 7.6 V
VBUS = 5.1 V
Figure 34. Buck Mode (OTG) Load Transient Response
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10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9-V and 6.2-V input
with at least 500-mA current rating connected to VBUS or a 2-cell Li-Ion battery with voltage > VBAT_UVLO
connected to BAT. The source current rating needs to be at least 3-A in order for the boost converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loops is important to prevent electrical and magnetic field
radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB
according to this specific order is essential.
1. Put SYS output capacitor as close to SYS and GND pins as possible. Ground connections need to be tied to
the IC ground with a short copper trace connection or GND plane.
2. Place PMID input capacitor as close as possible to PMID pins and PGND pins and use shortest copper trace
connection or GND plane.
3. Place inductor input terminal to SW pins as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the input current. Minimize
parasitic capacitance from this area to any other trace or plane.
4. Decoupling capacitors should be placed on the same side of and next to the IC and make trace connection
as short as possible.
5. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
6. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
7. Via size and number should be enough for a given current path.
Refer to the EVM design and the Layout Example below for the recommended component placement with trace
and via locations.
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11.2 Layout Example
Figure 35. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• BQ2588x Boosting Battery Chargers Evaluation Module User's Guide
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ25886RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ25886
BQ25886RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BQ25886
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ25886RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ25886RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ25886RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ25886RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
2.5
SYMM
1
PIN 1 ID
(OPTIONAL)
18
24X 0.30
0.18
24
19
SYMM
24X 0.48
0.28
0.1
0.05
C A B
C
4219016 / A 08/2017
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
(
2.7)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
TYP
6
13
(R0.05)
12
7
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
19
24
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.694)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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