Texas Instruments | TPS54010 3-V to 4-V Input, 14-A Synchronous Step-Down Converter (Rev. C) | Datasheet | Texas Instruments TPS54010 3-V to 4-V Input, 14-A Synchronous Step-Down Converter (Rev. C) Datasheet

Texas Instruments TPS54010 3-V to 4-V Input, 14-A Synchronous Step-Down Converter (Rev. C) Datasheet
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TPS54010
SLVS509C – MAY 2004 – REVISED JUNE 2019
TPS54010 3-V to 4-V Input, 14-A Synchronous Step-Down Converter
1 Features
3 Description
•
•
The TPS54010 low-input voltage, high-output current
synchronous buck PWM converter in a dc/dc
regulator integrating all required active components.
Included on the substrate with the listed features are
a true, high- performance, voltage error amplifier that
enables maximum performance under transient
conditions and flexibility in choosing the output filter L
and C components; an undervoltage-lockout circuit to
prevent start-up until the VIN input voltage reaches 3
V; an internally and externally set slowstart circuit to
limit in-rush currents; and a power-good output useful
for processor/logic reset, fault signaling, and supply
sequencing.
1
•
•
•
•
•
•
Separate Low-Voltage Power Bus
8-mΩ MOSFET Switches for High Efficiency at
14-A Continuous Output
Adjustable Output Voltage Down to 0.9 V
Externally Compensated With 1% Internal
Reference Accuracy
Fast Transient Response
Wide PWM Frequency:
Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
The TPS54010 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heat sinks.
2 Applications
•
•
•
Device Information(1)
Low-Voltage, High-Density Systems With Power
Distributed at 2.5 V, 3.3 V Available
Point of Load Regulation for HighPerformance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking, and Optical
Communications Infrastructure
PART NUMBER
PACKAGE
TPS54010
BODY SIZE (NOM)
HTSSOP (28)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Typical Application and Efficiency Curve
SIMPLIFIED SCHEMATIC
2.5 V or 3.3 V
Input1
EFFICIENCY
vs
OUTPUT CURRENT
0.68 mH
PVIN
350 mF
PH
TPS54010
BOOT
PGND
Output
100
0.047 mF
200 mF
0.1 mF
95
90
3.3 V
VIN
1 mF
COMP
VBIAS
AGND VSENSE
85
120 pF
4.64 kW
10 kW
3300 pF
422 W
1 mF
Efficiency − %
Input2
80
75
70
65
14.7 kW
1500 pF
Compensation
Network
VIN = 3.3 V,
PVIN = 2.5 V,
VO = 1.5 V,
fs= 700 kHz
60
55
50
0
2
4
6
8
10
12
14
16
IO − Output Current − A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54010
SLVS509C – MAY 2004 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Dissipation Ratings ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9
Layout ................................................................... 26
9.1 PCB Layout ............................................................. 26
9.2 Layout Example ...................................................... 28
10 Device and Documentation Support ................. 29
10.1
10.2
10.3
10.4
10.5
10.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
11 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2005) to Revision C
Page
•
Editorial changes only, no technical revisions; ...................................................................................................................... 1
•
remove Ordering Information table; information in POA ....................................................................................................... 1
2
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SLVS509C – MAY 2004 – REVISED JUNE 2019
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP
Top View
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
Pin Functions
PIN
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and
RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for
details.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating
drive for the high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
15, 16, 17, 18,
19
PH
6-14
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large
copper areas to the input and output supply returns, and negative terminals of the input and output
capacitors. A single point connection to AGND is recommended.
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
20, 21, 22, 23
Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the
PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor.
PWRGD
4
Power-good open-drain output. High when VSENSE > 90% Vref, otherwise PWRGD is low. Note that
output is low when SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device
operation and capacitor input to externally set the start-up time.
SYNC
27
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator
or pin select between two internally set switching frequencies. When used to synchronize to an external
signal, a resistor must be connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND
pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
24
Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package
with a high-quality, low-ESR 1-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage compensation network/output divider.
PVIN
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Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MINIMUM to MAXIMUM
VI
Input voltage range
VO
Output voltage range
VO
Source current
IS
Sink current
SS/ENA, SYNC
–0.3 to 7
RT
–0.3 to 6
VSENSE
–0.3 to 4
PVIN, VIN
–0.3 to 4.5
BOOT
–0.3 to 10
VBIAS, COMP, PWRGD
–0.3 to 7
PH
–0.6 to 6
V
V
PH
Internally limited
COMP, VBIAS
6
PH
25
A
COMP
6
mA
SS/ENA, PWRGD
Voltage differential
UNIT
mA
10
AGND to PGND
±0.3
V
TJ
Operating junction temperature range
–40 to 125
°C
Tstg
Storage temperature range
–65 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VI
TJ
Input voltage, VIN
3
(3)
4
MAX
UNIT
4
V
Power Input voltage, PVIN
2.2
4
V
Operating junction temperature
–40
125
°C
6.4 Dissipation Ratings (1)
(1)
(2)
NOM
(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28-Pin PWP with solder
14.4°C/W
6.94 W (3)
3.81 W
2.77 W
28-Pin PWP without solder
27.9°C/W
3.58 W
1.97 W
1.43 W
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
(a) 3 inch × 3 inch, 4 layers, thickness: 0.062 inch
(b) 1.5-oz. copper traces located on the top of the PCB
(c) 1.5-oz. copper ground plane on the bottom of the PCB
(d) 0.5-oz. copper ground planes on the 2 internal layers
(e) 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
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6.5
SLVS509C – MAY 2004 – REVISED JUNE 2019
Electrical Characteristics
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
VI
Input voltage, VIN
Supply voltage range, PVIN
3
4
V
2.2
4
V
6.3
10
mA
8.3
13
mA
SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V
1
1.4
mA
fs = 350 kHz, RT open, PH pin open, PVIN = 3.3 V,
SYNC = 0 V
6
8
mA
fs = 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V,
PVIN = 2.5 V, VIN = 3.3 V
6
9
mA
Output = 1.8 V
fs = 350 kHz, RT open, PH pin open, PVIN = 2.5 V,
SYNC = 0 V
VIN
IQ
Quiescent current
PVIN
fs = 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V,
PVIN = 2.5 V
SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V
<140
µA
UNDERVOLTAGE LOCKOUT (VIN)
Start threshold voltage, UVLO
2.95
Stop threshold voltage, UVLO
2.7
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO (1)
3
2.8
V
V
0.11
V
2.5
µs
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.7
2.8
Output current, VBIAS (2)
2.9
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (1) (3)
Load regulation
IL = 7 A, fs = 350 kHz, TJ = 85°C
IL = 0 A to 14 A, fs = 350 kHz, TJ = 85°C
PVIN = 2.5 V, VIN = 3.3 V
(1) (3)
0.05
%/V
0.013
%/A
OSCILLATOR
Internally set—free running frequency
Externally set—free running frequency range
RT open (1), SYNC ≤ 0.8 V
280
350
420
RT open (1), SYNC ≥ 2.5 V
440
550
660
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 68 kΩ (1% resistor to AGND) (1)
663
700
762
High-level threshold voltage, SYNC
2.5
Pulse duration, SYNC
V
700
kHz
ns
300
Ramp valley (1)
0.75
Ramp amplitude (peak-to-peak) (1)
V
1
Minimum controllable on time (1)
V
200
Maximum duty cycle (1)
(1)
(2)
(3)
0.8
50
Frequency range, SYNC
kHz
V
Low-level threshold voltage, SYNC
(1)
kHz
ns
90%
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 11
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open-loop voltage gain
1 kΩ COMP to AGND (1)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (1)
3
5
Error amplifier common mode input voltage
range
Powered by internal LDO (1)
0
Input bias current, VSENSE
VSENSE = Vref
VBIAS
60
Output voltage slew rate (symmetric), COMP
1
dB
MHz
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding
deadtime)
10-mV overdrive (1)
70
85
ns
1.2
1.4
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA (1)
Falling edge deglitch, SS/ENA (1)
Internal slow-start time
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V
0.03
V
2.5
µs
2.6
3.35
4.1
2
5
8
ms
µA
1.3
2.3
4
mA
POWER GOOD
Power-good threshold voltage
VSENSE falling
Power-good hysteresis voltage (1)
Power-good falling edge deglitch (1)
93
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VIN = 3.3 V, PVIN = 2.5 V
0.18
µs
0.3
V
1
µA
CURRENT LIMIT
Current limit
VIN = 3.3 V, PVIN = 2.5 V
(1)
21
A
Current limit leading edge blanking time (1)
, Output shorted
14.5
100
ns
Current limit total response time (1)
200
ns
165
°C
10
°C
THERMAL SHUTDOWN
Thermal shutdown trip point (1)
135
Thermal shutdown hysteresis (1)
OUTPUT POWER MOSFETS
rDS(on)
6
Power MOSFET switches
VIN = 3 V, PVIN = 2.5 V
8
21
VIN = 3.6 V, PVIN = 2.5 V
8
18
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6.6 Typical Characteristics
10
12
VIN = 3.6 V,
PVIN = 2.5 V,
IO = 9 A
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
12
8
6
4
2
0
−40 −20
VIN = 3.3 V,
PVIN = 2.5 V,
IO = 9 A
10
8
6
4
2
0
100 125
−40 −20 0
20 40 60 80 100 125
TJ − Junction Temperature − °C
Figure 1. Drain-Source On-State Resistance vs Junction
Temperature
Figure 2. Drain-Source On-State Resistance vs Junction
Temperature
20
40
60
80
f − Externally Set Oscillator Frequency − kHz
f − Internally Set Oscillator Frequency − kHz
TJ − Junction Temperature − °C
0
750
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
0
25
85
125
800
700
RT = 68 kΩ
600
500
RT = 100 kΩ
400
300
RT = 180 kΩ
200
−40
TJ − Junction Temperature − °C
Figure 3. Internally Set Oscillator Frequency vs Junction
Temperature
25
85
125
Figure 4. Externally Set Oscillator Frequency vs Junction
Temperature
0.895
8
VO = 1.5 V,
VI = PVIN = 3.3 V,
TJ = 125°C
Device Power Dissipation − W
7
V ref − Voltage Reference − V
0
TJ − Junction Temperature − °C
0.893
0.891
0.889
0.887
6
5
4
3
2
1
0.885
0
−40
0
25
85
TJ − Junction Temperature − °C
125
0
5
10
15
20
IO − Output Current − A
Figure 5. Voltage Reference vs Junction Temperature
Figure 6. Device Power Dissipation vs Output Current
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Typical Characteristics (continued)
0
140
PVIN = 2.5 V
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
−20
−40
−60
0.891
80
0.889
Phase
−80
−100
60
−120
40
Gain
20
−140
Phase − Degrees
100
Gain − dB
VO − Output Voltage Regulation − V
0.895
−160
0.887
0
0.885
−180
−20
3
3.1
3.2
3.3
3.4
VI − Input Voltage − V
3.5
1
3.6
10
100
−200
1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 7. Reference Voltage vs Input Voltage
Figure 8. Error Amplifier Open-Loop Response
Internal Slow-Start Time − ms
3.80
VIN = 3.3 V,
PVIN = 2.5 V
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
125
TJ − Junction Temperature − °C
Figure 9. Internal Slow-Start Time vs Junction Temperature
8
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7 Detailed Description
7.1 Overview
The TPS54010 low-input voltage, high-output current synchronous buck PWM converter in a dc/dc regulator
integrating all required active components. Included on the substrate with the listed features are a true, highperformance, voltage error amplifier that enables maximum performance under transient conditions and flexibility
in choosing the output filter L and C components; an undervoltage-lockout circuit to prevent start-up until the VIN
input voltage reaches 3 V; an internally and externally set slowstart circuit to limit in-rush currents; and a powergood output useful for processor/logic reset, fault signaling, and supply sequencing.
7.2 Functional Block Diagram
VBIAS
AGND
VIN
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.11 V
VIN
REG
VBIAS
Enable
Comparator
3.0 − 4.0 V
SHUTDOWN
PVIN
ILIM
Comparator
Thermal
Shutdown
150°C
2.2 − 4.0 V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
8 mΩ
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
S
Error
Amplifier
Reference
VREF = 0.891 V
PWM
Comparator
LOUT
VO
CO
Adaptive Dead-Time
and
Control Logic
VIN
8 mΩ
OSC
PGND
Power-Good
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54010
Hysteresis: 0.03 Vref
VSENSE
COMP
SHUTDOWN
35 µs
RT SYNC
7.3 Feature Description
7.3.1 Operating With Separate Pvin
The TPS54010 is designed to operate with the power stage (high-side and low-side MOSFETs) and the PVIN
input connected to a separate power source from VIN. The primary intended application has VIN connected to a
3.3-V bus and PVIN connected to a 2.5-V bus. The TPS54010 cannot be damaged by any sequencing of these
voltages. However, the UVLO (see Undervoltage Lockout (UVLO)) is referenced to the VIN input. Some
conditions may cause undesirable operation.
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Feature Description (continued)
If PVIN is absent when the VIN input is high, the slow-start is released, and the PWM circuit goes to maximum
duty factor. When the PVIN input ramps up, the output of the TPS54010 follows the PVIN input until enough
voltage is present to regulate to the proper output value.
NOTE
If the PVIN input is controlled via a fast bus switch, it results in a hard-start condition and may damage the load
(that is, whatever is connected to the regulated output of the TPS54010). If a power-good signal is not available
from the 2.5-V power supply, one can be generated using a comparator and hold the SS/ENA pin low until the
2.5-V bus power is good. An example of this is shown in Figure 10. This circuit can also be used to prevent the
TPS54010 output from following the PVIN input while the PVIN power supply is ramping up.
100 kΩ
VIN
10 kΩ
+
−
PVIN
VBIAS
10 kΩ
27.4 kΩ
SS/ENA
1/2 LM293
Figure 10. Undervoltage Lockout Circuit For Pvin Using Open-Collector or Open-Drain Comparator
PVIN and VIN can be tied together for 3.3-V bus operation.
7.3.2 Maximum Output Voltage
The maximum attainable output voltage is limited by the minimum voltage at the PVIN pin. Nominal maximum
duty cycle is limited to 90% in the TPS54010; so, maximum output voltage is:
V
+ PVIN
0.9
O(max)
(min)
(1)
Care must be taken while operating when nominal conditions cause duty cycles near 90%. Load transients can
require momentary increases in duty cycle. If the required duty cycle exceeds 90%, the output may fall out of
regulation.
7.3.3 Grounding and PowerPAD Layout
The TPS54010 has two internal grounds (analog and power). Inside the TPS54010, the analog ground ties to all
of the noise-sensitive signals, whereas the power ground ties to the noisier power signals. The PowerPAD must
be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the
TPS54010, particularly at higher output currents. However, ground noise on an analog ground plane can also
cause problems with some of the control and bias signals. For these reasons, separate analog and power ground
planes are recommended. These two planes must tie together directly at the IC to reduce noise between the two
grounds. The only components that must tie directly to the power ground plane are the input capacitor, the output
capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54010.
7.3.4 Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-ms falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a lowvalue capacitor connected between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:
10
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Feature Description (continued)
t +C
d
(SS)
1.2 V
5 mA
(2)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t
+C
(SS)
(SS)
5 mA
(3)
The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the
internal rate.
7.3.5 Undervoltage Lockout (UVLO)
The TPS54010 incorporates an undervoltage-lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-ms rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to
noise on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section.
7.3.6 VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital-switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin; see the functional block
diagram of this data sheet.
7.3.7 Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high-precision regulation of the TPS54010, because it cancels offset errors in the scale and error amplifier
circuits.
7.3.8 Oscillator and PWM Ramp
The oscillator frequency is set to an internally fixed value of 350 kHz. The oscillator frequency can be externally
adjusted from 280 to 700 kHz by connecting a resistor between the RT pin to ground. The switching frequency is
approximated by the following equation, where R is the resistance from RT to AGND:
Switching Frequency + 100 kW 500 [kHz]
R
(4)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to 80% of the synchronization signal. The following table
summarizes the frequency selection configurations:
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Feature Description (continued)
SWITCHING
FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 180 kΩ to 68 kΩ
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external
synchronization frequency
7.3.9 Error Amplifier
The high-performance, wide bandwidth, voltage error amplifier sets the TPS54010 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the
particular application needs. Type-2 or Type-3 compensation can be employed using external compensation
components.
7.3.10 PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control-logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET
remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET
on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point,
setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch
is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54010 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
7.3.11 Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver
does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.
The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied from VIN, whereas the high-side driver is supplied from
the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and
reduces external component count.
7.3.12 Overcurrent Protection
The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading-edge blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter.
Load protection during current sink operation is provided by thermal shutdown.
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7.3.13 Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously; starting up by control of the slow-start circuit, heating
up due to the fault condition, and then shutting down on reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
7.3.14 Power-Good (PWRGD)
The power-good circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low. When VIN, UVLO threshold, SS/ENA, enable threshold, and
VSENSE > 90% of Vref, the open-drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of
Vref and a 35-µs falling-edge deglitch circuit prevent tripping of the power-good comparator due to high-frequency
noise.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following design procedure can be used to select component values for the TPS54010. This section
presents a simplified discussion of the design process.
8.2 Typical Application
Figure 11 shows the schematic for a typical
TPS54010 application. The TPS54010 can provide
up to 14-A output current at a nominal output voltage
of 1.5 V. Nominal input voltages are 2.5 V for PVIN
and 3.3 V for VIN. For proper thermal performance,
the exposed PowerPAD underneath the device must
be soldered down to the printed-circuit board.
µF
µF
µF
kΩ
µF
8.2.1 Design Requirements
To begin the design process, a few parameters must
be decided:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
kΩ
For this design example, use the following as the
input parameters:
µF
µF
Table 1. Design Parameters
kΩ
µ
µF
µF
kΩ
kΩ
kΩ
Figure 11. Application Circuit, 2.5 V to 1.5 V
µF
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage (VIN)
3.3 V
Input voltage range (PVIN)
2.2 to 3.5 V
Output voltage
1.5 V
Input ripple voltage
300 mV
Output ripple voltage
50 mV
Output current rating
14 A
Operating frequency
700 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Switching Frequency
The switching frequency can be set to either one of two internally programmed frequencies or set to a externally
programmed frequency. With the RT pin open, setting the SYNC pin at or above 2.5 V selects 550-kHz
operation, whereas grounding or leaving the SYNC pin open selects 350-kHz operation. For this design, the
switching frequency is externally programmed using the RT pin. By connecting a resistor (R4) from RT to AGND,
any frequency in the range of 250 to 700 kHz can be set. Use Equation 5 to determine the proper value of RT.
R4(kW) + 500 kHz 100 kW
ƒs(kHz)
(5)
In this example circuit, R4 is calculated to be 71.5 kΩ and the switching frequency is set at 700 kHz.
14
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8.2.2.2 Input Capacitors
The TPS54010 requires an input de-coupling capacitor and, depending on the application, a bulk input capacitor.
The minimum value for the de-coupling capacitor, C9, is 10 µF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. Additionally, some bulk
capacitance may be needed, especially if the TPS54010 circuit is not located within about 2 inches from the input
voltage source. The value for this capacitor is not critical but it also should be rated to handle the maximum input
voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable.
This input ripple voltage can be approximated by Equation 6:
I
0.25
OUT(MAX)
DV
+
) I
ESR
PVIN
OUT(MAX)
MAX
C
ƒ sw
BULK
ǒ
Ǔ
(6)
Where IOUT(MAX) is the maximum load current.
The TPS54010 requires an input de-coupling capacitor and, depending on the application, a bulk input capacitor.
ƒsw is the switching frequency, C(BULK) is the bulk capacitor value and ESRMAX is the maximum series resistance
of the bulk capacitor.
The maximum RMS ripple current also must be checked. For worst-case conditions, this can be approximated by
Equation 7:
I
OUT(MAX)
I
+
CIN
2
(7)
In this case, the input ripple voltage would be 155 mV and the RMS ripple current would be 7 A. The maximum
voltage across the input capacitors would be Vin max plus delta Vin/2. The chosen bulk capacitor, a Sanyo
POSCAP 6TPD330M is rated for 6.3 V and 4.4 A of ripple current; two bypass capacitors, TDK
C3225X5R1C106M are each rated for 16 V, and the ripple current capacity is greater than 3 A at the operating
frequency of 700 kHz. Total ripple current handling is in excess of 10.4 A. It is important that the maximum
ratings for voltage and current are not exceeded under any circumstance.
8.2.2.3 Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Because the TPS54010 is an externally
compensated device, a wide range of filter component types and values can be supported.
8.2.2.3.1 Inductor Selection
To calculate the minimum value of the output inductor, use Equation 8
V
L
MIN
+
V
ǒVin(MAX) * VOUTǓ
OUT
IN(MAX)
K
IND
I
F sw
OUT
(8)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
For designs using low ESR output capacitors such as ceramics, use KIND = 0.3. When using higher ESR output
capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.2 to keep the inductor ripple current small. The minimum inductor value is
calculated to be 0.44 µH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 9:
I
L(RMS)
+
Ǹ
I2
) 1
OUT(MAX) 12
ȡ
ȧVOUT
Ȣ
ǒVin(MAX) * VOUTǓ
V
IN(MAX)
L
OUT
F sw
2
ȣ
0.8ȧ
Ȥ
(9)
and the peak inductor current can be found from Equation 10
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ǒVin(MAX) * VOUTǓ
V
I
L(PK)
+I
OUT(MAX)
)
OUT
1.6 V
IN(MAX)
L
OUT
F sw
(10)
For this design, the RMS inductor current is 15.4 A, and the peak inductor current is 15.1 A. For this design, a
Vishay IHLP2525CZ-01 style output inductor is specified. The largest value greater than 0.44 µH that meets
these current requirements is 0.68 µH. Increasing the inductor value decreases the ripple current and the
corresponding output ripple voltage. The inductor value can be decreased if more margin in the RMS current is
required. In general, inductor values for use with the TPS54010 falls in the range of 0.47 to 2.2 µH.
8.2.2.3.2 Capacitor Requirements
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired
closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is
desirable to keep the closed-loop crossover frequency at less than 1/5 of the switching frequency. With high
switching frequencies such as the 500 kHz frequency of this design, internal circuit limitations of the TPS54010
limit the practical maximum crossover frequency to about 70 kHz. To allow for adequate phase gain in the
compensation network, the LC corner frequency should be about one decade or so below the closed-loop
crossover frequency. This limits the minimum capacitor value for the output filter to:
C
OUT(MIN)
+
1
L
OUT
ǒ
K
2p ƒ
CO
Ǔ
2
(11)
Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically
10 for one decade difference. For a desired crossover of 100-kHz and a 0.68-µH inductor, the minimum value for
the output capacitor is 93 µF using a minimum K factor of 5. Increasing the K factor would require using a larger
capacitance as 100 kHz is approaching the maximum practical closed-loop crossover frequency for this device.
The selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half
the ripple voltage. Any de-rating amount must also be included. The maximum RMS ripple current in the output
capacitors is given by Equation 12:
I
+ 1
COUT(RMS)
Ǹ12
ȡVOUT ǒVPVIN(MAX) * VOUTǓȣ
ȧ V
L
F sw ȧ
PVIN(MAX)
OUT
Ȣ
Ȥ
(12)
The calculated RMS ripple current is 780 mA in the output capacitors.
The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in
the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output
filter; therefore, the maximum specified ESR as listed in the capacitor data sheet is given by Equation 13 :
ESR
MAX
+N
C
ȡVIN(MAX) LOUT F sw 0.8ȣ
ȧ
ȧ
Ǔ
ǒ
V
V
*V
IN(MAX)
OUT Ȥ
Ȣ OUT
DV
P*P(MAX)
(13)
and the maximum ESR required is 22.2 mΩ. A capacitor that meets these requirements is a Cornell Dubilier
Special Polymer (SP) ESRD101M06 rated at 6.3 V with a maximum ESR of 0.015 Ω and a ripple current rating of
2 A. An additional small 0.1-µF ceramic bypass capacitor C13 is a also used.
Other capacitor types work well with the TPS54010, depending on the needs of the application.
16
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8.2.2.3.3 Compensation Components
The external compensation used with the TPS54010 allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are supported. The design example uses Type-3
compensation consisting of R1, R3, R5, C6, C7, and C8. Additionally, R2 along with R1 forms a voltage divider
network that sets the output voltage. These component reference designators are the same as those used in the
SWIFT Designer Software. There are a number of different ways to design a compensation network. This
procedure outlines a relatively simple procedure that produces good results with most output filter combinations.
Use the SWIFT Designer Software for designs with unusually high closed-loop crossover frequencies, low value,
low ESR output capacitors such as ceramics or if you are unsure about the design procedure.
When designing compensation networks for the TPS54010, a number of factors must be considered. The gain of
the compensated error amplifier should not be limited by the open-loop amplifier gain characteristics and should
not produce excessive gain at the switching frequency. Also, the closed-loop crossover frequency should be set
less than one-fifth of the switching frequency, and the phase margin at crossover must be greater than 45
degrees. The general procedure outlined here produces results consistent with these requirements without going
into great detail about the theory of loop compensation.
First, calculate the output filter LC corner frequency using Equation 14:
1
ƒ
+
LC
2p L
C
OUT OUT
Ǹ
(14)
For the design example, fLC = 19.3 kHz.
Choose the closed-loop crossover frequency to be greater than fLC and less than one-fifth of the switching
frequency. Also, the crossover frequency should not exceed 150 kHz, as the error amplifier may not provide the
desired gain. For this design, a crossover frequency of 100 kHz was chosen. This value is chosen for
comparatively wide loop bandwidth while still allowing for adequate phase boost to insure stability.
Next, calculate the R2 resistor value for the output voltage of 1.5 V using Equation 15:
R2 + R1 0.891
V
* 0.891
OUT
(15)
For any TPS54010 design, start with an R1 value of 10 kΩ. R2 is 14.7 kΩ.
Now, the values for the compensation components that set the poles and zeros of the compensation network can
be calculated. Assuming that R1 >> than R5 and C6 >> C7, the pole and zero locations are given by Equation 16
through Equation 22:
1
ƒ +
Z1
2pR3C6
(16)
1
ƒ +
Z2
2pR1C8
(17)
1
ƒ
+
P1
2pR5C8
(18)
1
ƒ
+
P2
2pR3C7
(19)
Additionally, there is a pole at the origin, which has unity gain at a frequency:
1
ƒ
+
INT
2pR1C6
(20)
This pole is used to set the overall gain of the compensated error amplifier and determines the closed-loop
crossover frequency. Because R1 is given as 1 kΩ and the crossover frequency is selected as 100 kHz, the
desired fINT can be calculated from Equation 21:
ƒ
CO
ƒ
+
INT
V
2
IN(MAX)
(21)
And the value for C6 is given by Equation 22:
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C6 +
1
2pR1 ƒ
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INT
(22)
The first zero, fZ1 is located at one-half the output filter LC corner frequency; so, R3 can be calculated from:
1
R3 +
pC6 ƒ
LC
(23)
The second zero, fZ2 is located at the output filter LC corner frequency; so, C8 can be calculated from:
1
C8 +
2pR1 ƒ
LC
(24)
The first pole, fP1 is located to coincide with output filter ESR zero frequency. This frequency is given by:
1
ƒ
+
ESR0
2pR
C
ESR OUT
(25)
where RESR is the equivalent series resistance of the output capacitor.
In this case, the ESR zero frequency is 88.4 kHz, and R5 can be calculated from:
1
R5 +
2pC8 ƒ
ESR
(26)
The final pole is placed at a frequency above the closed-loop crossover frequency high enough to not cause the
phase to decrease too much at the crossover frequency while still providing enough attenuation so that there is
little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 3.5 times the closed-loop
crossover frequency and the last compensation component value C7 can be derived:
1
C7 +
7pR3 ƒ
CO
(27)
Note that capacitors are only available in a limited range of standard values, so the nearest standard value has
been chosen for each capacitor. The measured closed-loop response for this design is shown in Figure 5.
8.2.2.4 Bias and Bootstrap Capacitors
Every TPS54010 design requires a bootstrap capacitor, C3, and a bias capacitor, C4. The bootstrap capacitor
must be a 0.1 µF. The bootstrap capacitor is located between the PH pins and BOOT. The bias capacitor is
connected between the VBIAS pin and AGND. The value should be 1.0 µF. Both capacitors should be highquality ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close
to the device connection pins as possible.
8.2.2.5 Power Good
The TPS54010 is provided with a power-good output pin PWRGD. This output is an open-drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A 10-kΩ pullup works well in this application.
8.2.2.6 Snubber Circuit
R10 and C11 of the application schematic comprise a snubber circuit. The snubber is included to reduce
overshoot and ringing on the phase node when the internal high-side FET turns on. Because the frequency and
amplitude of the ringing depends to a large degree on parasitic effects, it is best to choose these component
values based on actual measurements of any design layout. See literature number SLUP100 for more detailed
information on snubber design.
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µ
µ
µ
kΩ
µ
71.5 kΩ
µF
µF
kΩ
µ
µF
µF
Ω
14.7 kΩ
µF
10 kΩ
The following part numbers are used for test purposes:
C1 = T520D337M0O4ASE015 (Kemet)
C2 = TDK C3225X5R0J107M ceramic 6.3 V X5R
L1 = IHLP2525CZ−01 0.68 µH (Vishay Dale)
Figure 12. 1.5-V Power Supply With Ceramic Output Capacitors
Figure 12 shows an application where all ceramic capacitors, including the main output filter capacitor, are used.
The compensation network components were calculated using SWIFT Designer Software. See Figure 21 through
Figure 29 for loop response, performance graphs, and switching waveforms for this circuit.
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µF
µF
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µF
kΩ
µF
µ
µF
10 kΩ
µF
µF
µF
20 kΩ
10 kΩ
10 kΩ
2 kΩ
10 kΩ
14.7 kΩ
10 kΩ
49.9 Ω
10 kΩ
49.9 Ω
µF
Figure 13. 1.5-V Power Supply With Remote Sense
With an output current of 14 A, if the load is located far from the dc/dc converter circuit, it may be beneficial to
include a remote sense capability. Figure 13 is an example of a power supply incorporating active differential
remote sensing. As the TPS54010 only has a positive VSENSE input, this circuit compensates for voltage drops
in both the output voltage rail and the return (GND). The difference amplifier of U2 forces the output of the
TPS54010 to generate an output voltage that maintains a constant 1.5-V difference between
+1.5V_REMOTE_SENSE and –1.5V_REMOTE_SENSE.
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3.6 V
100 nF
330 µF
10 µF
10 µF
C17
1 µF
100 nF
0.047 µF
1 µF
10 kΩ
0.68 µH
0.047 µF
2.4 kΩ
100 µF
100 µF
0.1 µF
422 Ω
14.7 kΩ
10 kΩ
Figure 14. 2.5 V To 1.5 V Power Supply With Charge Pump
If a suitable 3-V to 4-V source is not available for the VIN supply, a charge pump may be used to boost the PVIN
voltage. In this circuit, the charge pump is used to boost a 2.5-V source to a nominal 3.6 V.
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8.2.3 Application Curves: Circuit in Figure 11
The performance data for Figure 15 through Figure 23 are for the circuit in Figure 11. Conditions are PVIN = 2.5 V, VIN = 3.3 V,
VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified.
60
180
0.5
Phase
20
60
Phase - Degrees
120
Gain - dB
Gain
0
0
-20
-60
-40
-120
Output Voltage Variation - %
0.4
40
0.3
3.3 V
0.2
2.5 V
0.1
0
2.2 V
-0.1
-0.2
4.0 V
-0.3
-0.4
-60
100
1k
-180
1M
10 k
100 k
f - Frequency - Hz
Figure 15. Measured Loop Response vs Frequency
-0.5
0.3
4
6
8
10
IO - Output - A
12
14
16
100
2.2 V
95
0.2
IO = 0A
3.3 V
90
0.15
2.5 V
85
0.1
Efficiency - %
Output Voltage Deviation - %
2
Figure 16. Load Regulation vs Output Current
0.25
IO = 7A
0.05
0
-0.05
IO = 14A
-0.1
80
75
4.0 V
70
65
-0.15
60
-0.2
55
-0.25
-0.3
2
2.5
3
PVIN - V
50
3.5
4
Figure 17. Line Regulation vs Input Voltage
IO = 14 A
0
2
4
6
8
10
IO - Output - A
12
14
16
Figure 18. Efficiency vs Output Current
VO(RIPPLE) = 20 mV/div (ac coupled)
PVIN(RIPPLE) = 100 mV/div (ac coupled)
IO = 14 A
V(PH) = 1 V/div
V(PH ) = 1 V/div
Time = 500 nsec/div
Time = 500 nsec/div
Figure 19. Input Ripple Voltage
22
0
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Figure 20. Output Voltage Ripple
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The performance data for Figure 15 through Figure 23 are for the circuit in Figure 11. Conditions are PVIN = 2.5 V, VIN = 3.3 V,
VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified.
V(SS/ENA) = 1 V/div
VO = 50 mV/div (ac coupled)
IO = 5 A/div
VO = 1 V/div
Time = 10 msec/div
Time = 200 sec/div
Figure 22. Start-Up Waveform Output Voltage Relative To
Enable
Figure 21. Load Transient Response
VIN = 1 V/div
VO = 1 V/div
Time = 10 msec/div
Figure 23. Start-Up Waveform Output Voltage Relative To VIN
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The performance data for Figure 15 through Figure 23 are for the circuit in Figure 11. Conditions are PVIN = 2.5 V, VIN = 3.3 V,
VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified.
8.2.4 Application Curves: Circuit in Figure 12
The performance data for Figure 24 through Figure 33 are for the circuit in Figure 12. Conditions are PVIN = 2.5 V, VIN = 3.3 V,
VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified.
60
125
VO = 1.5 V,
PVIN = VI = 3.3 V,
TJ = 125°C
TA − Free-Air Temperature − ° C
115
105
180
Phase
40
120
95
20
75
65
55
60
Phase - Degrees
Gain - dB
85
Gain
0
0
-20
-60
-40
-120
45
Safe Operating Area
35
25
15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IO − Output Current − A
Note: Figure 25 applies to the application circuit
(Figure 13) installed on a 3 inch x 3 inch x 0.062 inch
four-layer PCB.
-60
100
1k
-180
1M
10 k
100 k
f - Frequency - Hz
Figure 25. Measured Loop Response vs Frequency
0.5
0.3
0.4
0.25
0.3
Output Voltage Deviation - %
Output Voltage Variation - %
Figure 24. Free-Air Temperature vs Maximum Output
Current
3.3 V
0.2
2.5 V
0.1
0
2.2 V
-0.1
-0.2
4.0 V
-0.3
-0.4
0.2
IO = 0A
0.15
0.1
0.05
IO = 7A
0
-0.05
IO = 14A
-0.1
-0.15
-0.2
-0.25
-0.3
-0.5
0
2
4
6
8
10 12
IO - Output Current - A
14
16
Figure 26. Load Regulation vs Output Current
100
2
2.5
3
PVIN - V
3.5
4
Figure 27. Line Regulation vs Pvin
PVIN(RIPPLE) = 100 mV/div (ac coupled)
2.2 V
95
3.3 V
90
2.5 V
Efficiency - %
85
80
75
4.0 V
70
65
60
55
50
IO = 14 A
0
2
4
6
8
10 12
IO - Output Current - A
14
16
V(PH) = 1 V/div
Time = 500 nsec/div
Figure 29. Input Ripple Voltage
Figure 28. Efficiency vs Output Current
24
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The performance data for Figure 24 through Figure 33 are for the circuit in Figure 12. Conditions are PVIN = 2.5 V, VIN = 3.3 V,
VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified.
VO = 100 mV/div (ac coupled)
VO(RIPPLE) = 10 mV/div (ac coupled)
IO = 5 A/div
IO = 14 A
V(PH ) = 1 V/div
Time = 500 nsec/div
Time = 200 msec/div
Figure 30. Output Voltage Ripple
Figure 31. Load Transient Response
V(SS/ENA) = 1 V/div
VIN = 1 V/div
VO = 1 V/div
VO = 1 V/div
Time = 10 msec/div
Time = 10 msec/div
Figure 32. Start-Up Waveform Output Voltage Relative to
Enable
Figure 33. Start-Up Waveform Output Voltage Relative to
Enable
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9 Layout
9.1 PCB Layout
The PVIN pins are connected together on the printed- circuit board (PCB) and bypassed with a low ESR ceramic
bypass capacitor. Take care to minimize the loop area formed by the bypass capacitor connections, the PVIN
pins, and the TPS54010 ground pins. The minimum recommended bypass capacitance is a 10-µF ceramic
capacitor with a X5R or X7R dielectric. The optimum placement is as close as possible to the PVIN pins, the
AGND, and PGND pins. See Figure 35 for an example of a board layout. If the VIN is connected to a separate
source supply, it is bypassed with its own capacitor. There is an area of ground on the top layer of the PCB,
directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground
area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors.
The AGND and PGND pins are tied to the PCB ground by connecting them to the ground area under the device
as shown in Figure 35. Use a separate wide trace for the analog ground signal path. This analog ground is used
for the voltage set point divider, timing resistor RT, slow-start capacitor, and bias capacitor grounds. The PH pins
are tied together and routed to the output inductor. Because the PH connection is the switching node, an inductor
is located close to the PH pins, and the area of the PCB conductor is minimized to prevent excessive capacitive
coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown in Figure 35. Keep
the boot capacitor close to the IC, and minimize the conductor trace lengths. Connect the output filter
capacitor(s) between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout,
Cout, and PGND as small as is practical. Place the compensation components from the VOUT trace to the
VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC
package and the device pinout, they must be routed close, but maintain as much separation as possible while
keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated
analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz
operating frequency, connect them to this trace.
For operation at full rated load current, the analog ground plane must provide an adequate heat-dissipating area.
A 3-inch by 3-inch plane of 1-ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available must be used when 6-A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer must be made using 0.013-inch
diameter vias to avoid solder wicking through the vias.
Eight vias must be in the PowerPAD area with four additional vias located under the device package. The size of
the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias
beyond the twelve recommended that enhance thermal performance must be included in areas not under the
device package.
26
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8 PL Ø 0.0130
4 PL
Ø 0.0180
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
PowerPAD Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Exposed
Copper Area for PowerPAD. 5mm
Stencils May Require 10 Percent
Larger Area
0.0630
0.0400
Figure 34. Recommended Land Pattern for 28-Pin PWP PowerPAD
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9.2 Layout Example
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
VSENSE
COMPENSATION
NETWORK
COMP
SYNC
INPUT
BYPASS
CAPACITOR
SLOW-START
CAPACITOR
SS/ENA
BIAS CAPACITOR
PWRGD
BOOT
CAPACITOR
VBIAS
BOOT
PH
PH
PVIN
PH
PVIN
PH
PGND
PH
VOUT
PH
VIN
EXPOSED
POWERPAD PVIN
AREA
PVIN
PVIN
OUTPUT INDUCTOR
PGND
OUTPUT
FILTER
CAPACITOR
PGND
PGND
PGND
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to GROUND PLANE
Figure 35. TPS54010 Layout
28
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SLVS509C – MAY 2004 – REVISED JUNE 2019
10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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8-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54010PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54010
TPS54010PWPG4
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54010
TPS54010PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54010
TPS54010PWPRG4
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54010
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54010 :
• Enhanced Product: TPS54010-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54010PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54010PWPR
HTSSOP
PWP
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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