Texas Instruments | TPS1H000-Q1 40-V, 1-Ω, Single-Channel Smart High-Side Switch (Rev. C) | Datasheet | Texas Instruments TPS1H000-Q1 40-V, 1-Ω, Single-Channel Smart High-Side Switch (Rev. C) Datasheet

Texas Instruments TPS1H000-Q1 40-V, 1-Ω, Single-Channel Smart High-Side Switch (Rev. C) Datasheet
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TPS1H000-Q1
SLVSDO6C – AUGUST 2017 – REVISED JUNE 2019
TPS1H000-Q1 40-V, 1-Ω, Single-Channel Smart High-Side Switch
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Single-Channel 1000-mΩ Smart High-Side Switch
Wide Operating Voltage: 3.4 V to 40 V
Low Standby Current: <500 nA
Adjustable Current Limit With External Resistor
– ±15% When ≥150 mA
– ±10% When ≥300 mA
Configurable Behavior After Current Limit
– Holding Mode
– Latch-Off Mode With Adjustable Delay Time
– Auto-Retry Mode
Supports Standalone Operation Without an MCU
Protection:
– Short-to-GND and Overload
– Thermal Shutdown and Thermal Swing
– Negative Voltage Clamp for Inductive Loads
– Loss-of-GND and Loss-of-Battery
Diagnostics:
– Overload and Short-to-GND Detection
– Open-Load and Short-to-Battery Detection in
ON or OFF State
– Thermal Shutdown and Thermal Swing
Typical Block Diagram
•
Single-Channel LED Driver
Single-Channel High-Side Relay Driver
Body Lighting
Advanced Driver Assistance Systems (ADAS)
Sensors
General Resistive, Inductive and Capacitive Loads
3 Description
The TPS1H000-Q1 device is a fully protected singlechannel high-side power switch with an integrated
1000-mΩ NMOS power FET.
An adjustable current limit improves system reliability
by limiting the inrush or overload current. The high
accuracy of the current limit improves overload
protection, simplifying the front-stage power design.
Configurable features besides current limit provide
design flexibility in the areas of functionality, cost, and
thermal dissipation.
The device supports full diagnostics with the digital
status output. Open-load detection is available in both
the ON- and OFF-states. The device supports
operation with or without an MCU. Standalone mode
allows use of the device in isolated systems.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS1H000-Q1
HVSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Current-Limit Protection in Auto-Retry Mode
3.4 V to 40 V
Supply Voltage
Up to 40 V
Up to 40 V
VS
LED Strings
IN
DIAG_EN
Relays
FAULT
OUT
Sub Module:
Cameras, Sensors
CL
General Resistive, Capacitive,
Inductive Loads
DELAY
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS1H000-Q1
SLVSDO6C – AUGUST 2017 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Revision B (March 2018) to Revision C
•
Page
Changed IN is high and DIAG_EN is high to IN is low and DIAG_EN is low in the Standby Mode section ....................... 21
Changes from Revision A (August 2017) to Revision B
Page
•
Added Footnote 2 to the Electrical Characteristics table........................................................................................................ 6
•
Added reverse current protection information to the Reverse-Current Protection section................................................... 19
Changes from Original (August 2017) to Revision A
Page
•
Changed numerous locations in the Features, Applications, and Description sections......................................................... 1
•
Added typical characteristic graphs........................................................................................................................................ 8
•
Changed text in the second paragraph of the Overview section ........................................................................................ 10
•
Changed the links for references to Table 2 and Table 3. .................................................................................................. 14
•
Added a row to Table 3 ....................................................................................................................................................... 15
•
Changed text references to Figure 24 and Figure 25 .......................................................................................................... 17
•
Added application curves and explanatory text.................................................................................................................... 23
•
Changed "ground pad" to "thermal pad" in Layout Guidelines ............................................................................................ 24
2
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5 Pin Configuration and Functions
DGN PowerPAD™ Package
8-Pin HVSSOP With Exposed Thermal Pad
Top View
IN
1
DIAG_EN
2
8
VS
7
OUT
6
GND
5
DELAY
Thermal
FAULT
3
CL
4
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CL
4
O
Adjustable current limit. Connect to device GND if external current limit is not used.
DELAY
5
I/O
Function configuration when in current limit; internal pullup
DIAG_EN
2
I
Enable the diagnostic function
FAULT
3
O
Open-drain diagnostic status output. Leave floating if not used
GND
6
—
Ground pin
IN
1
I
Input control for output activation; internal pulldown
OUT
7
O
Output, source of the high-side switch, connected to the load
Power supply, drain for the high-side switch.
VS
8
I
Thermal pad
—
—
Thermal pad. Connect to device GND or leave floating.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1) (2)
Supply voltage VS pin
Reverse polarity voltage
t < 400 ms
(3)
MIN
MAX
UNIT
—
42
V
t < 1 minute
–36
—
V
t < 2 minutes
–100
250
mA
–0.3
VS
V
Current on IN and DIAG_EN pins
–10
—
mA
Voltage on DELAY pin
–0.3
7
V
Current on DELAY pin
–60
—
mA
Voltage on FAULT pin
–0.3
7
V
Current on FAULT pin
–30
10
mA
Voltage on CL pin
–0.3
7
V
Current on CL pin
—
6
mA
Voltage on OUT pin
—
42
V
Inductive load switch-off energy dissipation
single pulse (4)
—
40
mJ
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Current on GND
Voltage on IN and DIAG_EN pins
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground.
Reverse polarity condition: VIN = 0 V, reverse current < IR(2), GND pin 1-kΩ resistor in parallel with diode.
Test condition: VVS = 13.5 V, L = 300 mH, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 × 35-μm Cu. 600 mm2 thermal pad copper
area.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002 (1)
All pins except VS, OUT,
and GND
±2000
Pins VS, OUT, and GND
±3000
Charged-device model (CDM), per AEC Q100-011
(1)
UNIT
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
VS
MAX
UNIT
4
40
V
Voltage on IN and DIAG_EN pins
0
40
V
Voltage on FAULT pin
0
5
V
Io,nom
Nominal dc load current
TJ
Operating junction temperature
4
NOM
Operating voltage
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0
1
A
–40
150
°C
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6.4 Thermal Information
TPS1H000-Q1
THERMAL METRIC (1)
DGN (HVSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
49.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50.2
°C/W
RθJB
Junction-to-board thermal resistance
21.4
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
21.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.1
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Electrical Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VVS(nom)
Nominal operating voltage
4
VVS(uvr)
Undervoltage restart
VVS rising
3.5
VVS(uvf)
Undervoltage shutdown
VVS falling
3
V(uv,hys)
Undervoltage shutdown, hysteresis
40
V
3.7
4
V
3.2
3.4
V
0.5
V
OPERATING CURRENT
I(op)
Nominal operating current
I(off)
Standby current
VVS = 13.5 V, VIN = 5 V, VDIAG_EN =
0 V, IOUT = 0.1 A, ICL = 0.5 A.
5
VVS = 13.5 V, VIN = VDIAG_EN = VCL =
VOUT = 0 V, TJ = 25 °C
0.5
VVS = 13.5 V, VIN = VDIAG_EN = VCL =
VOUT = 0 V, TJ = 125 °C
3
3
I(off,diag)
Standby current with diagnostics
enabled
VVS = 13.5 V, VIN = 0 V, VDIAG_EN =
5V
t(off,deg)
Standby-mode deglitch time (1)
IN from high to low, if deglitch time≥
t(off,deg), the device enters into
standby mode.
Ilkg(out)
Output leakage current in off-state
VVS = 13.5 V, VIN = VDIAG_EN = VOUT
=0V
mA
µA
12.5
mA
ms
3
µA
POWER STAGE
rDS(on)
On-state resistance
ICL(int)
Internal current limit
ICL(TSD)
Current-limit value percentage during
thermal shutdown
VDS(clamp)
Drain−to−source voltage internally
clamped
VVS ≥ 3.5 V, TJ = 25°C
1000
VVS ≥ 3.5 V, TJ = 150°C
CL pin connected to GND
2000
1
mΩ
1.8
A
65
V
1
V
60%
45
OUTPUT DIODE CHARACTERISTICS
VF
Drain−to-source diode voltage
IN = 0, IOUT = −0.15 A
IR(1)
Continuous reverse current from
source to drain during a short-tobattery condition (1)
t < 60 s, VIN= 0 V, TJ = 25°C.
1
A
IR(2)
Continuous reverse current from
source to drain during a reversepolarity condition (1)
t < 60 s, VIN= 0 V, TJ = 25°C. GND
pin 1-kΩ resistor in parallel with
diode.
1
A
0.3
0.7
LOGIC INPUT (IN, DIAG_EN)
VIH
(1)
Logic high-level voltage
2
V
Value specified by design, not subject to production test
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Electrical Characteristics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
VIL
TEST CONDITIONS
MIN
TYP
Logic low-level voltage
Rpd,in
MAX
0.8
Logic-pin pulldown resistor
IN. VIN = 5 V
150
400
DIAG_EN. VVS = VDIAG_EN = 5 V
350
850
UNIT
V
kΩ
DIAGNOSTICS
Ilkg(loss,GND)
Loss of ground output leakage
current
td(ol,on)
Open-load deglitch time in on-state
VIN = 5 V, VDIAG_EN = 5 V, when IOUT
< I(ol,on), duration longer than td(ol,on),
open load is detected.
200
I(ol,on)
Open-load detection threshold in onstate
VIN = 5 V, VDIAG_EN = 5 V, when IOUT
< I(ol,on), duration longer than td(ol,on),
open load is detected.
1
V(ol,off)
Open-load detection threshold in offstate
VIN = 0 V, VDIAG_EN = 5 V, when
VVS – VOUT < V(ol,off), duration longer
than td(ol,off), open load is detected.
1.4
td(ol,off)
Open-load deglitch time in off-state
VIN = 0 V, VDIAG_EN = 5 V, when
VVS – VOUT < V(ol,off), duration longer
than td(ol,off), open load is detected.
200
I(ol,off)
Off-state output sink current
VIN = 0 V, VDIAG_EN = 5 V, VVS =
VOUT = 13.5 V
–70
VFAULT
FAULT low output voltage
IFAULT = 2 mA
tFAULT
FAULT signal holding time (1)
8.5
ms
T(SD)
Thermal shutdown threshold (1)
175
°C
T(SD,rst)
Thermal shutdown status reset (1)
155
°C
T(sw)
Thermal swing shutdown threshold (1)
60
°C
T(hys)
Hysterisis for resetting the thermal
shutdown and swing (1)
10
°C
100
µA
300
450
µs
5
8
mA
300
2.6
V
450
µs
µA
0.2
V
CURRENT LIMIT AND DELAY CONFIGURATION
K(CL)
Current-limit current ratio (1)
600
VCL(th)
Current-limit internal threshold
voltage (1)
0.8
dK(CL)/K(CL)
External current limit accuracy (2)
(IOUT – ICL × K(CL)) × 100 / (ICL ×
K(CL))
Idl(chg)
Delay pin charging current in latch-off
mode (1)
Vdl(th)
Pulling up threshold in auto-retry
mode
Vdl(ref)
Internal reference voltage in latch-off
mode
Internal fixed delay time
tdl2
Adjustable delay time by external
capacitor on DELAY pin (1)
tCL(deg)
Ilimit ≥ 0.05 A, VVS – VOUT ≥ 2.5V
–20%
20%
Ilimit ≥ 0.15 A , VVS – VOUT ≥ 2.5V
–15%
15%
Ilimit ≥ 0.3 A, Ilimit < 1 A, VVS – VOUT
≥ 2.5V
–10%
10%
4.5
Deglitch time when current limit
V
1.45
300
(1)
µA
2.7
(1)
tdl1
V
400
Connect with 3.3 uF capacitor as the
maximum value.
IN low to high, VDIAG_EN = 5 V, the
deglitch time from IN rising edge to
FAULT reporting out.
300
IN keeps high, VDIAG_EN = 5 V, the
deglitch time from CL start-point to
FAULT reporting out.
80
V
500
µs
1000
ms
500
µs
180
thic(on)
On-time when in auto-retry mode (1)
35
40
45
ms
thic(off)
Off-time when in auto-retry mode (1)
0.8
1
1.2
s
(2)
6
External current limit accuracy is only applicable to overload conditions greater than 1.5 x the current limit setting
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6.6 Switching Characteristics
MIN
NOM
MAX
td(on)
Turnon delay time, IN rising edge to
10% of VOUT
PARAMETER
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
= 0.1 A
TEST CONDITIONS
UNIT
20
50
90
µs
td(off)
Turnoff delay time, IN falling edge to VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
90% of VOUT
= 0.1 A
20
50
90
µs
dV/dt(on)
Slew rate on, VOUT from 10% to
90%
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
= 0.1 A
0.1
0.6
V/µs
dV/dt(off)
Slew rate off, VOUTfrom 90% to 10%
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
= 0.1 A
0.3
0.9
V/µs
VIN
90%
90%
VOUT
dV/dt(off)
dV/dt(on)
10%
10%
td(on)
td(off)
Figure 1. Output Delay Characteristics
Open Load
Open Load
IN
FAULT
td(ol,on)
td(ol,off)
Figure 2. Open-Load Blanking-Time Characteristic
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6.7 Typical Characteristics
1.7
4
VVS Rising
VVS Falling
3.9
1.5
IN Voltage (V)
UVLO Voltage (V)
3.8
3.7
3.6
3.5
1.4
1.3
1.2
3.4
1.1
3.3
3.2
-40
IN High
IN Low
1.6
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
1
-40
110 125
-25
-10
Figure 3. UVLO Voltage Threshold
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D002
Figure 4. IN Voltage Threshold
1.7
1
DIAG_EN High
DIAG_EN Low
1.6
0.9
1.5
Diode Voltage (V)
DIAG_EN Voltage (V)
5
D001
1.4
1.3
1.2
0.8
0.7
1.1
1
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
0.6
-40
110 125
-25
-10
5
D003
Figure 5. DIAG_EN Voltage Threshold
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D004
Figure 6. Body-Diode Forward Voltage
2
55
rDS(on)_3.5V
rDS(on)_13.5V
rDS(on)_40V
1.9
1.8
54
On-Resistance (:)
Clamp Voltage (V)
1.7
53
52
1.6
1.5
1.4
1.3
1.2
1.1
51
1
0.9
50
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
0.8
-40
-25
D005
Figure 7. Drain-to-Source Clamp Voltage
8
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-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D006
Figure 8. FET On-Resistance
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Typical Characteristics (continued)
-1.5
3.5
150mA CL Accuracy (%)
50mA CL Accuracy (%)
-2
-2.5
-3
-3.5
-4
3
2.5
2
1.5
-4.5
-5
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
1
-40
110 125
IOUT = 50 mA
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D008
IOUT = 150 mA
Figure 9. Current-Limit Accuracy at 50 mA
Figure 10. Current-Limit Accuracy at 150 mA
3
0
-0.5
2.5
1A CL Accuracy (%)
300mA CL Accuracy (%)
-25
D007
2
1.5
-1
-1.5
-2
1
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
-2.5
-40
-25
-10
D009
IOUT = 300 mA
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
D010
IOUT = 1 A
Figure 11. Current-Limit Accuracy at 300 mA
Figure 12. Current-Limit Accuracy at 1 A
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7 Detailed Description
7.1 Overview
The TPS1H000-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current-limit function greatly improves the reliability of the
whole system. Full diagnostic features enable intelligent control of the load.
The external high-accuracy current limit allows setting the current-limit value for the application. When
overcurrent occurs, the device improves system reliability by clamping the inrush current effectively. The
TPS1H000-Q1 device can also save system cost by reducing the size of PCB traces and connectors, and
the capacity of the preceding power stage. The TPS1H000-Q1 device allows three modes when a current
limit occurs. Through the configuration on the DELAY pin, users can set the output to any of three modes:
hold the current consistently, latch off immediately, or retry automatically. The configurable behaviors during
current limit provide design flexibility that considers functionality, cost, and thermal dissipation.
The TPS1H000-Q1 device supports full diagnostics with the digital status output. High-accuracy and lowthreshold open-load detection enables real-time on-state monitoring. The TPS1H000-Q1 device also
supports operation without an MCU, the standalone mode, which allows the system to implement the full
functionality locally.
The TPS1H000-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including LEDs, relays, and sub-modules.
7.2 Functional Block Diagram
VS
Internal Reference
Gate Driver
IN
DIAG_EN
VDS Clamp
Charge Pump
Diagnostics
& Protection
Thermal Monitor
FAULT
ON/OFF State
Open Load Detection
OUT
Short to GND & Overload
Current Limit
GND
10
CL
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7.3 Feature Description
7.3.1 Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is reached, a closed loop activates immediately. The output current is clamped at
the set value, and a fault is reported out. The device heats up due to the high power dissipation on the power
FET.
The device has two current-limit thresholds.
• Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
• External adjustable current limit – An external resistor is used to set the current-limit threshold. Use
Equation 1 to calculate R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current
and the current-limit set value. K(CL) is constant across temperature and supply voltage. The external
adjustable current limit allows the flexibility to set the current-limit value by application.
RCL
uK
V
CL(th)
(CL)
IOUT
(1)
Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected to the device GND.
For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the output before the current-limit closed loop is
set up. The fast-trip response time is less than 1 µs, typically. With this fast response, the device can achieve
better inrush current-suppression performance.
vs
IOUT/K(CL)
Internal Current Limit
-
+
+
VCL(th)
+
IOUT
OUT
External Current Limit
VCL(th)
+
CL
Figure 13. Current Limit
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Feature Description (continued)
7.3.2 DELAY Pin Configuration
When a current limit occurs, the TPS1H000-Q1 device supports three different behaviors of the output.
Table 1. Current Limit Configurations
MODE
Holding
Latch-off
DELAY
CONFIGURATION
OUTPUT CURRENT BEHAVIOR
FAULT RECOVERY
When hitting a current limit, the output current
FAULT clears when IN turns low for a
holds at the setting current. The device enters into duration longer than tFAULT OR when the
thermal shutdown mode when TJ > T(SD).
current limit is removed when IN is high.
Connect to GND
directly
When hitting a current limit, the output current
holds at the setting current, but latches off after a
preset DELAY time (tdl1+ tdl2). tdl1 is the default
delay time; tdl2 is a capacitor-configurable delay
time.
Connect to GND
through a capacitor
FAULT clears when IN turns low for a
duration longer than tFAULT.
The output stays latched off regardless of whether
the current limit is removed. The output recovers
only when IN is toggling.
Auto-retry
When hitting a current limit, the output current
FAULT clears when IN turns low for a
holds at the setting current, but periodically comes duration longer than tFAULT OR when the
on for thic(on) and turns off for thic(off).
current limit is removed for thic(on)
External pullup
7.3.2.1 Holding Mode
Holding mode is active when the DELAY pin connects to GND directly. When hitting a current limit, the output
current holds at the setting current. The device enters into thermal shutdown mode when TJ > T(SD).
DELAY
TPS1H000-Q1
Figure 14. Holding Mode Connection
IOUT
tCL(deg)
Holding the current
VFAULT
Current Limit
Figure 15. Holding Mode Example
7.3.2.2 Latch-Off Mode
Latch-off mode is active when the DELAY pin connects to GND through a capacitor. When hitting a current limit,
the output current holds at the setting current, but latches off after a preset DELAY time (tdl1+ tdl2). tdl1 is the
default delay time, tdl2 is a configurable delay time set by a capacitor. The output stays latched off regardless of
whether the current limit is removed. The output recovers only when IN is toggling.
tdl2 can be calculated by Equation 2. The Idl(chg)is the device charging current in latch-off mode, Vdl(ref) is the
internal reference voltage in latch off mode, tdl2 is the user-setting delay time, and CDELAY is the capacitor
connected on the DELAY pin.
12
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I dl chg u t dl2
Vdl ref
(2)
DELAY
TPS1H000-Q1
Figure 16. Latch-Off-Mode Connection
IOUT
tdl2
tCL(deg) tdl1
Latch off
VFAULT
Current Limit
Figure 17. Latch-Off-Mode Example
7.3.2.3 Auto-Retry Mode
Auto-retry mode is active when the DELAY pin is externally pulled up. The pullup voltage must be higher than
Vdl(th). When hitting the current limit, the output current holds at the setting current, but periodically comes on for
thic(on) and turns off for thic(off).
DELAY
TPS1H000-Q1
Figure 18. Auto-Retry-Mode Connection
IOUT
tCL(deg)
thic(on)
thic(off)
tCL(deg)
thic(on)
thic(off)
VFAULT
Current Limit
Figure 19. Auto-Retry-Mode Example
7.3.3 Standalone Operation
In a typical application, the TPS1H000-Q1 device is controlled by a microcontroller. The device also supports
standalone operation. IN and DIAG_EN have a 40-V maximum dc rating, and can be connected to the VS pin
directly. In auto-retry mode, the DELAY pin can also be connected to the VS pin through a 100-kΩ resistor.
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3.4V - 40V
IN
DIAG_EN
1
8
2
7
Tab
FAULT
3
6
CL
4
5
VS
OUT
Load
GND
DELAY
Figure 20. Standalone Operation in Latch-Off Mode
3.4V - 40V
IN
DIAG_EN
1
8
2
7
Tab
FAULT
3
6
CL
4
5
VS
OUT
Load
GND
DELAY
Figure 21. Standalone Operation in Auto-Retry Mode
7.3.4 Fault Truth Table
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the microcontroller can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and IN low.
Table 2 applies when the DIAG_EN pin is enabled. Table 3 applies when the DIAG_EN pin is disabled.
14
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Table 2. Fault Truth Table
CONDITION
IN
OUT
CRITERION
FAULT
L
L
—
H
H
H
—
H
H
L
Current limit triggered.
L
See Table 1.
H
H
IOUT < l(ol,on)
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when the open
load is removed.
L (1)
H
VVS – VOUT < V(ol,off)
L
FAULT clears when IN is toggling
OR FAULT clears when the open
load is removed.
Thermal shutdown
H
—
Thermal shutdown
triggered
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when thermal
shutdown quits.
Thermal swing
H
—
Thermal swing triggered
L
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when thermal
swing quits.
Normal
Overload or short to GND
Open load or short to
battery
(1)
FAULT RECOVERY
—
An external pullup is required for open-load detection.
Table 3. DIAG_EN Disabled Condition
DIAG_EN
LOW
IN
PROTECTIONS AND DIAGNOSTICS
ON
Diagnostics disabled, full protections
OFF
Diagnostics disabled, no protection
7.3.5 Full Diagnostics
7.3.5.1 Short-to-GND and Overload Detection
When the output is on, a short to GND or an overload condition causes overcurrent. If the overcurrent triggers
either the internal or external current-limit threshold, a fault condition is reported out as FAULT pin = low.
7.3.5.2 Open-Load Detection
7.3.5.2.1 Output On
When the output is on, if the current flowing through the output IOUT < l(ol,on), the device recognizes an open-load
fault. For open-load detection in output on, no external circuitry is required.
7.3.5.2.2 Output Off
When the output is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUT < V(ol,off)), and the device recognizes an open-load fault.
There is always a leakage current I(ol,off) present on the output due to the internal logic control path or external
humidity, corrosion, and so forth. So an external pullup resistor is recommended to offset the leakage current
when an open load is detected. The recommended pullup resistance is 15 kΩ.
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Open Load Detection in Off-State
R(pullup)
V(ol,off)
Vds
Load
Figure 22. Open-Load Detection in Output Off
7.3.5.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state.
7.3.5.4 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing).
Thermal behaviors after Short to GND
IN
TJ
T(SD)
T(hys)
T(SD,rst)
T(hys)
T(SW)
ICL
ICL(TSD)
IOUT
FAULT
Figure 23. Thermal Behavior Diagram
7.3.5.4.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thermal shutdown occurs, the
output turns off.
16
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7.3.5.4.2 Thermal Swing
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET) –
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). The thermal swing function improves the device reliability when subjected to
repetitive fast thermal variation.
7.3.5.4.3 Fault Report Holding
When using PWM dimming, FAULT is easily cleared by the PWM falling edge. Even if the fault condition remains
all the time, FAULT is discontinuous. To avoid this unexpected fault report behavior, the device implements faultreport holding time. Figure 24 shows a typical issue when PWM dimming, the FAULT is cleared unexpectedly
even when the short-to-GND still exists. The TPS1H000-Q1 device with fault-report holding function allows the
right behavior as shown in Figure 25.
Short-to-GND
IN
Fault cleared
FAULT
Figure 24. Without Fault-Report Holding
Short-to-GND
IN
Fault not cleared
t < tFAULT
FAULT
Figure 25. With Fault-Report Holding
7.3.6 Full Protections
7.3.6.1 UVLO Protection
The device monitors the supply voltage, VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
7.3.6.2 Inductive Load Switching Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp).
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VS
VDS(clamp)
OUT
L
R
GND
+
Figure 26. Drain-to-Source Clamping Structure
IN
VVS
VOUT
VDS(clamp)
IOUT
t(decay)
Figure 27. Inductive-Load Switching-Off Diagram
7.3.6.3 Loss-of-GND Protection
When loss of GND occurs, the output is shut down regardless of whether the IN pin is high or low. The device
can protect against two ground-loss conditions, loss of device GND and loss of module GND.
7.3.6.4 Loss-of-Power-Supply Protection
When loss of supply occurs, the output is shut down regardless of whether the IN pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the logic control pins to maintain the inductance current. To protect the system in this condition, TI
recommends protection with an external free-wheeling diode.
18
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Vs
VS
MCU
IOs
High-side Switch
OUT
D
L
Figure 28. Protection for Loss of Power Supply
7.3.6.5 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
• When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current.
To protect the device, TI recommends two types of external circuitry.
• Adding a blocking diode (method 1). Both the device and load are protected when in reverse polarity.
• Adding a GND network (method 2). The reverse current through the device GND is blocked. The reverse
current through the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a
GND network. The recommended configuration is a 1-kΩ resistor in parallel with a >100-mA diode. The
reverse current protection diode in the GND network forward voltage should be less than 0.6 V in any
circumstances. In addition a minimum resistance of 4.7 K is recommended on the I/O pins.
Load
Figure 29. Reverse-Current External Protection, Method 1
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Load
Figure 30. Reverse-Current External Protection, Method 2
7.3.6.6 MCU I/O Protection
TI recommends series resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
IOs
MCU
TPS1H000-Q1
Load
Figure 31. MCU I/O External Protection
7.4 Device Functional Modes
7.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics, as shown in Figure 32.
20
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Device Functional Modes (continued)
Standby Mode
(IN low, DIAG_EN low)
DIAG_EN high to low
IN low to high
DIAG_EN low
AND
IN high to low
AND
t > t(off,deg)
DIAG_EN low to high
Standby Mode
With DIAG
IN low to high
Normal Mode
(IN high)
(IN low, DIAG_EN high)
IN high to low
AND
DIAG_EN high
AND
t > t(off,deg)
Figure 32. Working Modes
7.4.1.1 Normal Mode
When IN is high, the device enters normal mode.
7.4.1.2 Standby Mode
When IN is low and DIAG_EN is low, the device enters standby mode with ultralow power consumption.
7.4.1.3 Standby Mode With Diagnostics
When IN is low and DIAG_EN is high, the device enters standby mode with diagnostics. The device still supports
open-load and short-to-battery detection even when IN is low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS1H000-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current-limit function greatly improves the reliability of the whole
system. Full diagnostic features enable intelligent control of the load. The TPS1H000-Q1 device can be used for
a wide variety of resistive, inductive, and capacitive loads, including LEDs, relays, and sub-modules.
8.2 Typical Application
Figure 33 shows an example of how to design the external circuitry parameters.
Supply Voltage
R(SER)
VS
IN
R(SER)
DIAG_EN
MCU
R(SER)
General Resistive, Capacitive,
Inductive Loads
OUT
3.3/5V
R(pullup)
FAULT
DELAY
C(DELAY)
CL
GND
R(CL)
Figure 33. Typical Application Circuitry
8.2.1 Design Requirements
• VVS range from 6 V to 18 V
• Nominal current of 100 mA
• Expected current limit value of 500 mA
• Thermal sensitive system, when current limit occurs, the output latches off after 0.2 s. The 0.2 s is to ensure
the safe start-up for a capacitive load, clamping the inrush current but without latch-off during start-up.
• Full diagnostics with 5-V MCU, including on-state open-load detection, short-to-GND or overcurrent detection,
and thermal shutdown detection
8.2.2 Detailed Design Procedure
To set the adjustable current limit value at 500 mA, calculate R(CL) as follows:
22
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Typical Application (continued)
R (CL)
VCL(th) u K (CL)
IOUT
0.8 u 600
0.5
960
(3)
To set the adjustable latch-off delay at 0.2 s, calculate C(DELAY) as follows:
t dl t CL(deg) t dl1 t dl2 0.2 | t dl2
C DELAY
I dl(chg) u t dl2
Vdl(ref)
4.5 u 0.2
u 10
1.45
6
0.62 PF
(4)
TI recommends R(SER) = 10 kΩ for a 5-V MCU, and R(pullup) = 10 kΩ as the pullup resistor.
8.2.3 Application Curves
The following curves are test examples of hard short conditions. The load is 0.1 A and the current limit value is
0.5 A. Figure 34 shows a waveform of the latch-off mode. Figure 35 shows a waveform of the auto-retry mode.
Load = 0.1 A
Current limit = 0.5
A
Load = 0.1 A
Figure 34. Hard-Short Condition in Latch-Off Mode
Current limit = 0.5
A
Figure 35. Hard-Short Condition in Auto-Retry Mode
9 Power Supply Recommendations
The device can be used for both 12-V and 24-V applications. The normal power supply connection is a 12-V or
24-V system.
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10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 175°C. If the output current is very high, the power
dissipation may be large. However, the PCB layout is very important. Good PCB design can optimize heat
transfer, which is absolutely essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heatflow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the board opposite the
package.
• Add as many thermal vias as possible directly under the package thermal pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
10.2 Layout Example
IN
DIAG_EN
1
8
2
7
OUT
6
GND
5
DELAY
3
Thermal Pad
FAULT
CL
4
VS
Figure 36. Layout Example
24
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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6-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS1H000AQDGNRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HVSSOP
DGN
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
17SX
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS1H000AQDGNRQ1 HVSSOP
DGN
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS1H000AQDGNRQ1
HVSSOP
DGN
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SCALE 4.000
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
NOTE 3
1.95
4
5
8X
B
3.1
2.9
NOTE 4
0.38
0.25
0.13
C A B
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
1
0 -8
0.15
0.05
0.7
0.4
DETAIL A
A 20
1.846
1.646
TYPICAL
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
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EXAMPLE BOARD LAYOUT
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.846)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
( 0.2) TYP
VIA
(0.55)
SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
TM
DGN0008G
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8X (0.45)
8
1
SYMM
(2.15)
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
(4.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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