Texas Instruments | TPS54618 2.95-V to 6-V, 6-A, Synchronous Step-Down SWIFT Converter (Rev. F) | Datasheet | Texas Instruments TPS54618 2.95-V to 6-V, 6-A, Synchronous Step-Down SWIFT Converter (Rev. F) Datasheet

Texas Instruments TPS54618 2.95-V to 6-V, 6-A, Synchronous Step-Down SWIFT Converter (Rev. F) Datasheet
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TPS54618
SLVSAE9F – NOVEMBER 2010 – REVISED MAY 2019
TPS54618 2.95-V to 6-V, 6-A,
Synchronous Step-Down SWIFT™ Converter
1 Features
3 Description
•
The TPS54618 device is a full-featured 6-V, 6-A,
synchronous step-down current-mode converter with
two integrated MOSFETs.
1
•
•
•
•
•
•
•
•
•
Two 12-mΩ (typical) MOSFETs for high efficiency
at 6-A loads
300-kHz to 2-MHz switching frequency
0.8-V ±1% Voltage reference over temperature
(–40°C to +150°C)
Synchronizes to external clock
Adjustable slow start and sequencing
UV and OV power-good output
–40°C to 150°C Operating Junction Temperature
Range
Thermally enhanced 3-mm × 3-mm, 16-pin WQFN
package
Pin-Compatible to TPS54418
Create a custom design using the TPS54618 with
the WEBENCH® Power Designer
2 Applications
•
•
•
Low-voltage, high-density power systems
Point-of-load regulation for high-performance
DSPs, FPGAs, ASICs, and microprocessors
Broadband, networking, and optical
communications infrastructure
The TPS54618 enables small designs by integrating
the MOSFETs, implementing current-mode control to
reduce external component count, reducing inductor
size by enabling up to 2-MHz switching frequency,
and minimizing the IC footprint with a small, 3-mm ×
3-mm, thermally-enhanced WQFN package.
The TPS54618 provides accurate regulation for a
variety of loads with an accurate ±1% voltage
reference (VREF) over temperature.
Efficiency is maximized through the integrated
12-mΩ MOSFETs and 515-μA typical supply current.
Using the enable pin, shutdown supply current is
reduced to 5.5-µA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The outputvoltage start-up ramp is controlled by the slow-start
pin. An open-drain power-good signal indicates the
output is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protect the
device during an overcurrent condition.
For more SWIFT™ documentation, see the TI
website at www.ti.com/swift.
Device Information(1)
PART NUMBER
TPS54618
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Efficiency vs Output Current
100
VIN
TPS54618
VIN
3 Vin
95
BOOT
5 Vin
90
EN
PH
PWRGD
VOUT
Efficiency - %
85
80
75
70
65
SS
RT/CLK
COMP
VSENSE
PowerPad
60
fs = 500kHz
55
50
GND
AGND
Vout = 1.8V
0
1
2
3
4
IO - Output Current - A
5
6
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54618
SLVSAE9F – NOVEMBER 2010 – REVISED MAY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
10.3 Power Dissipation Estimate .................................. 32
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2015) to Revision F
•
Editorial changes only, no technical revisions; add links for WEBENCH .............................................................................. 1
Changes from Revision D (November 2013) to Revision E
•
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changes from Revision C (September 2013) to Revision D
Page
•
Changed title of data sheet..................................................................................................................................................... 1
•
Changed EN pin maximum rating from 3.3 V to 4.0 V in Absolute Maximum Ratings .......................................................... 4
•
Changed RT/CLK pin maximum rating from 3.3 V to 4.0 V in Absolute Maximum Ratings .................................................. 4
Changes from Revision B (October 2012) to Revision C
•
Changed all Thermal Information values................................................................................................................................ 4
Changes from Revision A (November 2010) to Revision B
•
2
Page
Changed EN pin maximum rating from 3.3 V to 4.0 V in Absolute Maximum Ratings .......................................................... 4
Changes from Original (November 2010) to Revision A
•
Page
Page
Changed Figure 5 in Typical Characteristics.......................................................................................................................... 7
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SLVSAE9F – NOVEMBER 2010 – REVISED MAY 2019
5 Pin Configuration and Functions
VIN
EN
PWRGD
BOOT
RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
16
15
14
13
VIN 1
12 PH
VIN 2
11 PH
Thermal
Pad
GND 3
10 PH
GND 4
6
7
8
COMP
RT/CLK
AGND
5
VSENSE
9
SS/TR
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
AGND
5
G
Analog ground should be electrically connected to GND close to the device.
BOOT
13
I
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP
7
O
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
EN
15
I
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Can be used to
set the on/off threshold (adjust UVLO) with two additional resistors.
G
Power ground. This pin should be electrically connected directly to the power pad under the device.
O
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
GND
3
4
10
PH
11
12
PWRGD
14
O
An open-drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
over/undervoltage or EN shut down.
RT/CLK
8
I/O
Resistor timing or external clock input pin
SS/TR
9
I/O
Slow-start and tracking. An external capacitor connected to this pin sets the output voltage rise time.
This pin can also be used for tracking.
1
VIN
2
I
Input supply voltage, 2.95 V to 6 V
16
VSENSE
6
I
Inverting node of the transconductance (gm) error amplifier
Thermal
Pad
—
G
GND pin should be connected to the exposed power pad for proper operation. This power pad should
be connected to any internal PCB ground plane using multiple vias for good thermal performance.
(1)
I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
PWRGD, VIN
–0.3
7
EN, RT/CLK
–0.3
4
COMP, SS, VSENSE
–0.3
3
BOOT
7
PH
PH (10-ns transient)
Source current
Sink current
V
VPH+ 7
BOOT-PH
Output voltage
UNIT
–0.6
7
–2
10
V
EN, RT/CLK
100
COMP, SS
100
µA
µA
PWRGD
10
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VVIN
Input voltage
TA
Operating junction temperature
MIN
MAX
3
6
UNIT
V
–40
150
°C
6.4 Thermal Information
TPS54618
THERMAL METRIC
(1) (2)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
44.38
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.09
°C/W
RθJB
Junction-to-board thermal resistance
15.96
°C/W
ψJT
Junction-to-top characterization parameter
0.69
°C/W
ψJB
Junction-to-board characterization parameter
15.91
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.55
°C/W
(1)
(2)
4
Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLVSAE9F – NOVEMBER 2010 – REVISED MAY 2019
6.5 Electrical Characteristics
at TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN UVLO STOP
2.28
2.5
VIN UVLO START
2.45
2.6
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
2.95
6
V
V
Shutdown supply current
EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V
5.5
15
μA
Quiescent current, Iq
VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ
515
650
μA
Rising
1.25
Falling
1.18
Enable threshold + 50 mV
–3.5
Enable threshold – 50 mV
–1.9
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
V
μA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
2.95 V ≤ VIN ≤ 6 V, –40°C <TJ < 150°C
0.791
0.799
0.807
BOOT-PH = 5 V
12
25
BOOT-PH = 2.95 V
16
33
VIN = 5 V
13
25
VIN = 2.95 V
17
33
V
MOSFET
High-side switch resistance
Low-side switch resistance
mΩ
mΩ
ERROR AMPLIFIER
Input current
2
nA
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
245
μmhos
Error amplifier transconductance (gm)
during slow-start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
Vsense = 0.4 V
79
μmhos
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
±20
μA
25
A/V
COMP to Iswitch gm
CURRENT LIMIT
Current limit threshold
VIN = 6 V, 25°C < TJ < 150°C
7.46
10.6
15.3
VIN = 2.95 V, 25°C < TJ < 150°C
7.68
10.2
13.5
A
THERMAL SHUTDOWN
Thermal shutdown
Hysteresis
168
°C
20
°C
BOOT (BOOT PIN)
BOOT charge resistance
VIN = 5 V
16
Ω
BOOT-PH UVLO
VIN = 2.95 V
2.1
V
SLOW-START AND TRACKING (SS/TR PIN)
Charge current
V(SS/TR) = 0.4 V
2
μA
SS/TR to VSENSE matching
V(SS/TR) = 0.4 V
54
mV
SS/TR to reference crossover
98% normal
1.1
V
SS/TR discharge voltage (Overload)
VSENSE = 0 V
61
mV
SS/TR discharge current (Overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
350
µA
SS discharge current (UVLO, EN, Thermal
fault)
VIN = 5 V, V(SS) = 0.5 V
1.9
mA
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Electrical Characteristics (continued)
at TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PWRGD PIN)
VSENSE threshold
VSENSE falling (Fault)
91%
VSENSE rising (Good)
93%
VSENSE rising (Fault)
109%
VSENSE falling (Good)
107%
Hysteresis
VSENSE falling
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V
Vre
2%
ON-resistance
Output low
I(PWRGD) = 3 mA
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
Vref
7
nA
56
100
Ω
0.2
0.3
V
0.65
1.5
V
NOM
MAX
UNIT
2000
kHz
600
kHz
2000
kHz
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
Switching frequency
200
Rt = 400 kΩ
400
Switching frequency range using CLK mode
300
Minimum CLK pulse width
RT/CLK voltage
500
75
R(RT/CLK) = 400 kΩ
ns
0.5
RT/CLK high threshold
1.6
RT/CLK low threshold
0.4
V
2.2
V
0.6
V
RT/CLK falling edge to PH rising edge delay
Measure at 500 kHz with RT resistor in series
90
ns
PLL lock in time
Measure at 500 kHz
42
μs
Measured at 50% points on PH, IOUT = 3 A
75
Measured at 50% points on PH, VIN = 6 V,
IOUT = 0 A
120
PH (PH PIN)
Minimum ON-time
Minimum OFF-time
Prior to skipping off pulses, BOOT-PH = 2.95 V,
IOUT = 3 A
Rise time
VIN = 6 V, 6 A
2.25
Fall time
VIN = 6 V, 6 A
2
6
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60
ns
ns
V/ns
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0.025
525
520
0.023
High Side Rdson Vin = 3.3 V
0.021
Low Side Rdson Vin = 3.3 V
0.019
0.017
0.015
0.013
High Side Rdson Vin = 5 V
0.011
Low Side Rdson Vin = 5 V
0.009
510
505
500
495
490
485
0.007
480
0.005
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
475
-50
150
Figure 1. High-Side and Low-Side ON-Resistance
vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Switching Frequency vs Junction Temperature
12
0.807
Vin = 3.3 V
Vin = 6 V
11.5
0.805
11
0.803
Vref - Voltage Reference - V
High Side Switching Current - A
RT = 400 kW,
Vin = 5 V
515
fs - Switching Frequency - kHz
RDSON - Static Drain-Source On-State Resistance - W
6.7 Typical Characteristics
10.5
Vin = 2.95 V
10
9.5
9
0.801
0.799
0.797
0.795
0.793
8.5
8
25
50
75
100
TJ - Junction Temperature - °C
125
150
0.791
-50
-25
125
150
100
2000
1800
Nominal Switching Frequency - %
Vsense Falling
1600
Frequency (kHz)
25
50
75
100
TJ - Junction Temperature - °C
Figure 4. Voltage Reference vs Junction Temperature
Figure 3. High-Side Current Limit vs Junction Temperature
1400
1200
1000
800
600
400
200
100
0
200
300
400
500
600
700
800
75
Vsense Rising
50
25
0
0
Resistance (kΩ)
0.1
Figure 5. Switching Frequency vs RT Resistance
Low Frequency Range
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vsense - V
G000
Figure 6. Switching Frequency vs Vsense
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Typical Characteristics (continued)
105
310
Vin = 3.3 V
Vin = 3.3 V
100
EA - Transconductance - mA/V
EA - Transconductance - mA/V
290
270
250
230
210
95
90
85
80
75
70
65
190
60
170
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
55
-50
150
-25
Figure 7. Transconductance vs Junction Temperature
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 8. Transconductance (Soft-Start)
vs Junction Temperature
-3
1.3
1.29
Vin = 5 V,
Ven = Threshold +50 mV
-3.1
1.28
Vin = 3.3 V, rising
1.27
-3.2
EN - Pin Current - mA
EN - Threshold - V
1.26
1.25
1.24
1.23
1.22
1.21
1.2
Vin = 3.3 V, falling
1.19
1.18
-3.3
-3.4
-3.5
-3.6
-3.7
-3.8
1.17
1.16
1.15
-50
-3.9
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
-4
-50
150
Figure 9. Enable Pin Voltage vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 10. EN Pin Current vs Junction Temperature
-1
-1.4
Vin = 5 V
Vin = 5 V,
Ven = Threshold -50 mV
-1.2
-1.6
Iss/tr - Charge Current - mA
EN - Pin Current - mA
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-1.8
-2
-2.2
-2.4
-2.6
-2.6
-2.8
-2.8
-3
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 11. EN Pin Current vs Junction Temperature
8
-3
-50
-30
-10
10
30
50
70
90
TJ - Junction Temperature - °C
110
130
150
Figure 12. Charge Current vs Junction Temperature
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Typical Characteristics (continued)
2.8
8
2.7
7
Shutdown Supply Current - mA
Vin = 3.3 V
VI - Input Voltage - V
2.6
UVLO Stop Switching
2.5
2.4
2.3
UVLO Start Switching
2.2
6
5
4
3
2
1
2.1
2
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0
-50
150
-25
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 14. Shutdown Supply Current
vs Junction Temperature
Figure 13. Input Voltage vs Junction Temperature
800
8
TJ = 25°C
Vin = 3.3 V
7
700
6
Ivin - Supply Current - mA
Shutdown Supply Current - mA
0
5
4
3
2
600
500
400
300
1
0
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
200
-50
6
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 16. Supply Current vs Junction Temperature
Figure 15. Shutdown Supply Current vs Input Voltage
800
110
TJ = 25°C
108
700
106
PWRGD Threshold - % Vref
Ivin - Supply Current - mA
-25
600
500
400
Vsense Falling
104
Vsense Rising, Vin = 5 V
102
100
98
96
Vsense Rising
Vsense Falling
94
92
300
90
200
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
Figure 17. Supply Current vs Input Voltage
6
88
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 18. PWRGD Threshold vs Junction Temperature
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100
100
Vin = 3.3 V
90
Vin = 5 V,
SS = 0.4 V
90
80
80
SSTR - Vsense Offset - mV
RDSON - Static Drain-Source On-State Resistance - W
Typical Characteristics (continued)
70
60
50
40
30
70
60
50
40
30
20
20
10
10
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
0
-50
150
-25
Figure 19. PWRGD ON-Resistance
vs Junction Temperature
100
95
95
90
Vout = 1.05 V
Efficiency - %
Efficiency - %
85
80
75
70
Vout = 1.05 V
80
75
70
65
Vin = 5 V,
fs = 1 MHz,
TJ = 25°C
60
55
0
1
Vin = 3.5 V,
fs = 1 MHz,
TJ = 25°C
60
55
2
3
4
5
50
6
1
0
2
3
4
5
Output Current - A
Output Current - A
Figure 21. Efficiency vs Load Current
Figure 22. Efficiency vs Load Current
100
100
95
95
90
6
90
Vout = 3.3 V
Vout = 1.8 V
Vout = 1.8 V
85
Efficiency - %
85
Efficiency - %
150
Vout = 1.8 V
Vout = 1.8 V
65
Vout = 1.05 V
80
75
70
65
Vout = 1.05 V
80
75
70
65
Vin = 5 V,
fs = 500 kHz,
TJ = 25°C
60
55
10
125
90
Vout = 3.3 V
85
50
25
50
75
100
TJ - Junction Temperature - °C
Figure 20. SS/TR to VSENSE Offset
vs Junction Temperature
100
50
0
0
1
Vin = 3.5 V,
fs = 500 kHz,
TJ = 25°C
60
55
2
3
4
5
6
50
0
1
2
3
4
5
Output Current - A
Output Current - A
Figure 23. Efficiency vs Load Current
Figure 24. Efficiency vs Load Current
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7 Detailed Description
7.1 Overview
The TPS54618 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs.
To improve performance during line and load transients, the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the
RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the
power switch turn on to a falling edge of an external system clock.
The TPS54618 has a typical default start up voltage of 2.45 V. The EN pin has an internal pullup current source
that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In addition,
the pullup current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54618 is typically 515 μA when not switching and under no load. When the device
is disabled, the supply current is less than 5.5 μA.
The integrated 12-mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 6 A.
The TPS54618 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot
capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54618 to operate approaching 100%. The output
voltage can be stepped down to as low as the 0.799-V reference.
The TPS54618 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54618 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power
good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the
overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until
the output voltage is lower than 107%.
The SS/TR (slow-start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow-start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault
or disabled condition.
The use of a frequency fold-back circuit reduces the switching frequency during start-up and over current fault
conditions to help limit the inductor current.
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7.2 Functional Block Diagram
PWRGD EN
VIN
i1
93%
iHYS
Logic
Thermal
Shutdown
Enable
Comparator
107%
Shutdown
Logic
Voltage
Reference
VSENSE
UVLO
Enable
Threshold
Boot
Charge
Boot
UVLO
+
+
BOOT
SS
Shutdown
Minimum
COMP Clamp
Logic
PWM
Comparator
COMP
Logic and
PWM Latch
PH
Slope
Compensation
Frequency
Shift
Overload
Recovery
Maximum
Clamp
GND
OSC with
PLL
AGND
PowerPad
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54618 uses an adjustable, fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output
is compared to the high-side power switch current. When the power switch current reaches the COMP voltage
level the high-side power switch is turned off and the low-side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient response performance.
7.3.2 Slope Compensation and Output Current
The TPS54618 adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the full
duty cycle range.
7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
The TPS54618 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
12
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Feature Description (continued)
To improve dropout, the TPS54618 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.2 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the lowside MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current
sourced from the BOOT pin is very low, the high-side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.
7.3.4 Error Amplifier
The TPS54618 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower
of the SS/TR pin voltage or the internal 0.799-V voltage reference. The transconductance of the error amplifier is
245 μA/V during normal operation. When the voltage of VSENSE pin is below 0.799 V and the device is
regulating using the SS/TR voltage, the gm is typically greater than 79 μA/V, but less than 245 μA/V. The
frequency compensation components are placed between the COMP pin and ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.799 V at the noninverting
input of the error amplifier.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using
divider resistors with 1% tolerance or better. Start with 100 kΩ for the R1 resistor and use Equation 1 to calculate
R2. To improve efficiency at very light loads, consider using larger value resistors. If the values are too high, the
regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
æ
ö
0.799 V
R2 = R1 ´ ç
÷
V
0.799
V
è O
ø
(1)
TPS54618
VOUT
R1
VSENSE
+
0.799 V
R2
Figure 25. Voltage Divider Circuit
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Feature Description (continued)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54618 is disabled when the VIN pin voltage falls below 2.28 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 26 to adjust the input voltage UVLO by using
two external resistors. TI recommends using the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6
V. The rising threshold (VSTART) should be set to provide enough hysteresis to allow for any input supply
variations. The EN pin has an internal pullup current source that provides the default condition of the TPS54618
operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 1.6 μA of hysteresis is
added. When the EN pin is pulled below 1.18 V, the 1.6 μA is removed. This additional current facilitates input
voltage hysteresis.
TPS54618
VIN
Ip
1.9 µA
Ih
1.6 µA
R1
EN
+
R2
Figure 26. Adjustable Undervoltage Lockout
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
è VENRISING ø
R1 =
æ V
ö
Ip ç1 - ENFALLING ÷ + Ih
VENRISING ø
è
(2)
vertical spacer
R2 =
VSTOP
R1´ VENFALLING
- VENFALLING + R1(Ip + Ih )
where
•
•
•
•
•
R1 and R2 are in Ω
Ih = 1.6 µA
Ip = 1.9 µA
VENRISING = 1.25 V
VENFALLING = 1.18 V
(3)
7.3.8 Soft-Start Pin
The TPS54618 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the
SS/TR pin to ground implements a slow-start time. The TPS54618 has an internal pullup current source of
2 μA, which charges the external slow-start capacitor. Equation 4 calculates the required slow-start capacitor
value.
vertical spacer
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Feature Description (continued)
Css(nF) =
Tss(mS) ´ Iss(mA)
Vref(V)
where
•
•
•
Tss is the desired slow-start time in ms
Iss is the internal slow-start charging current of 2 μA
Vref is the internal voltage reference of 0.799 V
(4)
If, during normal operation, the VIN goes below the UVLO, the EN pin pulls below 1.2 V, or a thermal shutdown
event occurs, the TPS54618 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or
a thermal shutdown is exited, then SS/TR is discharged to below 40 mV before reinitiating a powering-up
sequence. The VSENSE voltage follows the SS/TR pin voltage with a 54-mV offset up to 85% of the internal
voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset
increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference.
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open-drain or collector output of a power on
reset pin of another device. Figure 27 shows the sequential method. The power good is coupled to the EN pin on
the TPS54618 which enables the second power supply once the primary supply reaches regulation.
Ratio-metric start-up can be accomplished by connecting the SS/TR pins together. The regulator outputs ramp
up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must
be doubled in Equation 4. The ratio-metric method is shown in Figure 29.
SPACER
TPS54618
TPS54618
PWRGD
CSS
EN
EN
SS
SS/TR
PWRGD
CSS
EN1
EN2
VO1
VO2
Figure 27. Sequential Start-Up Sequence
Figure 28. Sequential Start-Up
Using EN and PWRGD
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Feature Description (continued)
TPS54618
EN
EN
SS
CSS
SS
PWRGD
VO1
TPS54618
VO2
EN
SS
PWRGD
Figure 29. Schematic for Ratio-Metric Start-Up
Sequence
space
Figure 30. Ratio-Metric Start-Up
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 31 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and
Vout2. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR
to VSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratio-metric startup in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a
negative number in Equation 5 through Equation 7 for ΔV. Equation 7 results in a positive number for
applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Because the SS/TR
pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of
the tracking resistors is needed to ensure the device restarts after a fault. Make sure the calculated R1 value
from Equation 5 is greater than the value calculated in Equation 8 to ensure the device can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in
Figure 30.
16
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Feature Description (continued)
space
R1 =
Vout2 + D V
Vssoffset
´
Vref
Iss
(5)
Vref ´ R1
Vout2 + DV - Vref
(6)
space
R2 =
space
DV = Vout1 - Vout2
(7)
space
R1 > 2930 ´ Vout1- 145 ´ DV
(8)
space
TPS54618
VOUT(1)
EN
EN1
SS/TR
CSS
PWRGD
SS2
Vout1
TPS54618
VOUT(2)
Vout2
EN
R1
SS/TR
R2
PWRGD
Figure 31. Ratio-Metric and Simultaneous Start-Up
Sequence
Figure 32. Ratio-Metric Start-Up Using Coupled
SS/TR Pins
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54618 is adjustable over a wide range from 300 kHz to 2000 kHz by placing
a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in Equation 9 or
Equation 10.
235892
RT (kW ) =
1.027
fSW (kHz )
(9)
space
fSW (kHz ) =
171032
0.974
RT(kW )
(10)
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage, and minimum controllable ON-time should be considered.
The minimum controllable ON-time is typically 75 ns at full current load and 120 ns at no load, and limits the
maximum operating input voltage or output voltage.
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Feature Description (continued)
7.3.11 Overcurrent Protection
The TPS54618 implements a cycle-by-cycle current limit. During each switching cycle the high-side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
7.3.12 Frequency Shift
To operate at high switching frequencies and provide protection during overcurrent conditions, the TPS54618
implements a frequency shift. If frequency shift was not implemented, during an overcurrent condition the lowside MOSFET may not be turned off long enough to reduce the current in the inductor, causing a current
runaway. With frequency shift, during an overcurrent condition the switching frequency is reduced from 100%,
then 50%, then 25%, as the voltage decreases from 0.799 to 0 V on VSENSE pin to allow the low-side MOSFET
to be off long enough to decrease the current in the inductor. During start-up, the switching frequency increases
as the voltage on VSENSE increases from 0 to 0.799 V.
7.3.13 Reverse Overcurrent Protection
The TPS54618 implements low-side current protection by detecting the voltage across the low-side MOSFET.
When the converter sinks current through its low-side FET, the control circuit turns off the low-side MOSFET if
the reverse current is typically more than 4.5 A. By implementing this additional protection scheme, the converter
is able to protect itself from excessive current during power cycling and start-up into prebiased outputs.
7.3.14 Synchronize Using the RT/CLK Pin
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 33. To implement
the synchronization feature in a system, connect a square wave to the RT/CLK pin with an ON-time of at least
75 ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the
internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set
by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V
typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is
synchronized to the falling edge of RT/CLK pin.
RT/CLK
TPS54618
SYNC Clock
PLL
RRT
PH
Figure 33. Synchronizing to a System Clock
18
Figure 34. Plot of Synchronizing to System Clock
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Feature Description (continued)
7.3.15 Power Good (PWRGD Pin)
The PWRGD pin output is an open-drain MOSFET. The output is pulled low when the VSENSE voltage enters
the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is
a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%
or falls below 107% of the internal voltage reference, the PWRGD output MOSFET is turned off. TI recommends
using a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 6 V or less. The
PWRGD is in a valid state once the VIN input voltage is greater than 1.5 V.
7.3.16 Overvoltage Transient Protection
The TPS54618 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109%
of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side
MOSFET is disabled, preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on the next
clock cycle.
7.3.17 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 168°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 150°C, the device reinitiates the power-up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 20°C.
7.4 Device Functional Modes
7.4.1 Simple Small Signal Model for Peak Current Mode Control
Figure 35 shows an equivalent model for the TPS54618 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gm of 245 μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor R0 and capacitor Co model the open loop gain and frequency response of the amplifier. The
1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency
response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting
a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis.
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Device Functional Modes (continued)
TPS54618
PH
VOUT
Power Stage
25 A/V
a
RESR
b
R1
VSENSE
COMP
RLOAD
COUT
c
+
C2
COUT(ea)
R3
ROUT(ea)
0.799V
gM
245 µA/V
R2
C1
Figure 35. Small Signal Model for Loop Response
Figure 35 is a simple, small-signal model that can be used to understand how to design the frequency
compensation. The TPS54618 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 11 and consists of a DC gain, one dominant pole and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 35) is the power stage
transconductance. The gm for the TPS54618 is 25 A/V. The low frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 12. As the load
current increases and decreases, the low frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but the dominant pole moves with load current. The combined
effect is highlighted by the dashed line in the right half of Figure 37. As the load current decreases, the gain
increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load
conditions which makes it easier to design the frequency compensation.
space
VC
RESR
Adc
RLOAD
COUT
Gain
gm(ps)
Copyright © 2016, Texas Instruments Incorporated
fZ
fP
Frequency
Figure 36. Small Signal Model for Peak Current
Mode Control
20
Figure 37. Frequency Response Model for Peak
Current Mode Control
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Device Functional Modes (continued)
æ
ç 1+
vo
è 2p
= Adc ´
vc
æ
ç 1+
è 2p
ö
s
÷
× ¦z ø
ö
s
÷
× ¦p ø
(11)
Adc = gmps ´ RL
¦p =
(12)
C OUT
1
´ RL ´ 2p
(13)
COUT
1
´ RESR ´ 2p
(14)
space
¦z =
7.4.2 Small Signal Model for Frequency Compensation
The TPS54618 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 38. The Type 2
circuits are most likely implemented in high-bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.
VOUT
R1
TPS54618
VSENSE
COMP
gM(ea)
R2
VREF
+
R3
ROUT(ea)
COUT(ea)
5 pF
C1
Type IIA
R3
C2
C1
Type IIB
Figure 38. Types of Frequency Compensation
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Device Functional Modes (continued)
The design guidelines for TPS54618 loop compensation are as follows:
1. The modulator pole, fpmod, and the esr zero, fz1, must be calculated using Equation 15 and Equation 16.
Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 17
and Equation 18 to estimate a starting point for the crossover frequency, fc. Equation 17 is the geometric
mean of the modulator pole and the esr zero and Equation 18 is the mean of modulator pole and the
switching frequency. Use the lower value of Equation 17 or Equation 18 as the maximum crossover
frequency.
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(15)
1
2 p ´ Resr ´ Cout
(16)
space
¦ z m od =
space
¦C =
¦p mod ´ ¦ z mod
(17)
space
¦C =
¦p mod ´
¦ sw
2
(18)
space
2. R3 can be determined by Equation 19:
2p × ¦ c ´ Vo ´ COUT
R3 =
gmea ´ Vref ´ gmps
where
•
•
the gmea amplifier gain (245 μA/V)
gmps is the power stage gain (25 A/V)
(19)
vertical spacer
3. Place a compensation zero at the dominant pole:
¦p =
1
C OUT ´ R L ´ 2 p
C1 can be determined by Equation 20:
R ´ COUT
C1 = L
R3
(20)
space
4. C2 is optional. It can be used to cancel the zero from the ESR of COUT.
Resr ´ COUT
C2 =
R3
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This design example describes a high-frequency switching regulator design using ceramic output capacitors. This
design is available as the HPA606 evaluation module (EVM).
8.2 Typical Application
This section details a high-frequency, 1.8-V output power supply design application with adjusted UVLO.
16
VIN
1
C1
10 PF
L1
0.75 H
U1
TPS54618
VIN = 3-6V
C2
10 PF
C3
0.1 PF
R1
25.6k
2
15
6
VSNS
R2
20.0k
7
8
R3
7.5k
9
PH 10
11
PH
12
PH
13
BOOT
14
PWRGD
3
GND
4
GND
5
AGND
VIN
VIN
VIN
EN
VSNS
COMP
RT/CLK
SS/TR
VOUT = 1.8V, 6A
VOUT
C7
22 PF
C6
0.1 PF
C8
22 PF
C9
22 PF
C10
22 PF
R6
100k
C11
22 PF
VSNS
VIN
R5
100k
R7
80.6k
PWRGD
PWPD
R4
182k
C4
3300 pF
C5
0.01 PF
17
Figure 39. Typical Application Schematic TPS54618
8.2.1 Design Requirements
The design parameters for the TPS54618 are listed in Table 1.
Table 1. Design Parameters
PARAMETER
CONDITIONS
VIN
Input voltage
Operating
VOUT
Output voltage
ΔVOUT
Transient response
IOUT(max)
Maximum output current
VOUT(ripple)
Output voltage ripple
fSW
Switching frequency
MIN
TYP
MAX
3
3.3
6
1.8
1.5-A to 4.5-A load step
UNIT
V
V
4%
1000
6
A
30
mVP-P
kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54618 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2
Step One: Select the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, you want to choose the highest
switching frequency possible because this produces the smallest solution size. The high-switching frequency
allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a
lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the the
performance of the converter. The converter is capable of running from 300 kHz to 2 MHz. Unless a small
solution size is an ultimate goal, a moderate switching frequency of 1 MHz is selected to achieve both a small
solution size and a high-efficiency operation. Using Equation 9, R4 is calculated to be 180 kΩ. A standard 1%
182-kΩ value was chosen in the design.
8.2.2.3 Step Two: Select the Output Inductor
The inductor selected works for the entire TPS54618 input voltage range. To calculate the value of the output
inductor, use Equation 22. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high
inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use KIND = 0.3 and the inductor value is calculated to be 0.7 μH. For this design, a
nearest standard value was chosen: 0.75 μH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 24 and Equation 25.
For this design, the RMS inductor current is 6.01 A and the peak inductor current is 6.84 A. The chosen inductor
is a Toko FDV0630-R75M. It has a saturation current rating of 10 A and a RMS current rating of 8.9 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
´
L1 =
Io ´ Kind
Vinmax ´ ¦ sw
(22)
space
Iripple =
Vinmax - Vout
Vout
´
L1
Vinmax ´ ¦ sw
(23)
space
ILrms =
Io 2 +
æ Vo ´ (Vinmax - Vo) ö
1
´ ç
÷
12
è Vinmax ´ L1 ´ ¦ sw ø
2
(24)
space
ILpeak = Iout +
24
Iripple
2
(25)
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8.2.2.4 Step Three: Choose the Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning
from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the
change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor
must be sized to supply the extra current to the load until the control loop responds to the load change. The
output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing
a tolerable amount of droop in the output voltage. Equation 26 shows the minimum output capacitance necessary
to accomplish this.
For this example, the transient load response is specified as a 3% change in Vout for a load step from 1.5 A
(25% load) to 4.5 A (75% load). For this example, ΔIout = 4.5 – 1.5 = 3.0 A and ΔVout= 0.04 × 1.8 = 0.072 V.
Using these numbers gives a minimum capacitance of 83 μF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation.
Equation 27 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement,
Equation 27 yields 7 μF.
space
Co >
2 ´ DIout
¦ sw ´ DVout
(26)
space
Co >
1
´
8 ´ ¦ sw
1
Voripple
Iripple
where
•
•
•
ΔIout is the change in output current,
fsw is the regulators switching frequency
and ΔVout is the allowable change in the output voltage.
(27)
space
Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 28 indicates the ESR should be less than 18 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 18 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, five 22-μF, 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. The
estimated capacitance after derating by a factor 0.75 is 82.5 µF.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 29 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 29 yields
520 mA.
Voripple
Resr <
Iripple
(28)
space
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Icorm s =
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Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(29)
8.2.2.5 Step Four: Select the Input Capacitor
The TPS54618 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54618.
The input ripple current can be calculated using Equation 30.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10-V voltage rating is required to support the
maximum input voltage. For this example, two 10-μF and one 0.1-μF 10-V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 31. Using the design example values (Ioutmax = 6 A, Cin = 20 μF, Fsw =
1 MHz) yields an input voltage ripple of 149 mV and an RMS input ripple current of 2.94 A.
Icirms = Iout ´
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
(30)
space
DVin =
Ioutmax ´ 0.25
Cin ´ ¦ sw
(31)
8.2.2.6 Step Five: Choose the Soft-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54618 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start capacitor value can be calculated using Equation 32. For the example circuit, the slow-start time is
not too critical because the output capacitor value is 110 μF which does not require much current to charge to
1.8 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms which requires a 10-nF
capacitor. In TPS54618, Iss is 2.2 μA and Vref is 0.799 V.
Tss(ms) ´ Iss(mA)
Css(nF) =
Vref(V)
(32)
8.2.2.7 Step Six: Select the Bootstrap Capacitor
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. TI
recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
8.2.2.8 Step Eight: Select Output Voltage and Feedback Resistors
For the example design, 100 kΩ was selected for R6. Using Equation 33, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.6 kΩ.
Vref
R7 =
R6
Vo - Vref
(33)
26
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8.2.2.8.1 Output Voltage Limitations
Due to the internal design of the TPS54618, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.799 V. Above 0.799 V, the output
voltage may be limited by the minimum controllable ON-time. The minimum output voltage in this case is given
by Equation 34.
Voutmin = Ontimemin ´ Fsmax ´ (Vinmax - loutmin ´ RDSmin ) - Ioutmin ´ (RL + RDSmin )
where
•
•
•
•
•
•
•
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable ON-time (75 ns typical. 120 ns no load)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDSmin = minimum high-side MOSFET ON-resistance (see Electrical Characteristics)
RL = series resistance of output inductor
(34)
There is also a maximum achievable output voltage which is limited by the minimum OFF-time. The maximum
output voltage is given by Equation 35.
æ Offtimemax ö
æ tdead ö
Voutmax = Vin ´ ç 1 ÷ - Ioutmax ´ (RDSmax + RI) - (0.7 - Ioutmax ´ RDSmax )´ ç ts ÷
ts
è
ø
è
ø
where
•
•
•
•
•
•
•
•
Voutmax = maximum achievable output voltage
Vin = minimum input voltage
Offtimemax = maximum OFF-time (90 ns typical for adequate margin)
ts = 1/Fs
Ioutmax = maximum current
RDSmax = maximum high-side MOSFET ON-resistance (see Electrical Characteristics)
RI = DCR of the inductor
tdead = dead time (60 ns)
(35)
8.2.2.9 Step Nine: Select Loop Compensation Components
There are several industry techniques used to compensate DC–DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54618. Because the slope compensation is ignored, the actual cross over frequency is usually lower than
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and
Equation 37. For COUT, the derated capacitance value is 82.5 µF. Use Equation 38 and Equation 39 to estimate a
starting point for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz.
Equation 38 is the geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of
modulator pole and the switching frequency. Equation 38 yields 64.3 kHz and Equation 39 gives 56.7 kHz. The
lower value of Equation 38 or Equation 39 is the maximum recommended crossover frequency. For this example,
a lower fc value of 40 kHz is specified. Next, the compensation components are calculated. A resistor in series
with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms
the compensating pole (if needed).
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(36)
1
2 p ´ Resr ´ Cout
(37)
space
¦ z m od =
space
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¦C =
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¦p mod ´ ¦ z mod
(38)
space
¦C =
¦p mod ´
¦ sw
2
(39)
space
The compensation design takes the following steps:
1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value of the
compensation network. In this example, the anticipated crossover frequency (fc) is 40 kHz. The power stage
gain (gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
2p × ¦ c ´ Vo ´ Co
R3 =
Gm ´ Vref ´ VIgm
(40)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The capacitor of
the compensation network can be calculated from Equation 41.
Ro ´ Co
C4 =
R3
(41)
3. An additional pole can be added to attenuate high-frequency noise. In this application, it is not necessary to
add it.
From the previously listed procedures, the compensation network includes a 7.50-kΩ resistor and a
3300-pF capacitor.
28
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8.2.3 Application Curves
100
100
90
90
70
Efficiency - %
Efficiency - %
70
60
50
40
60
Vin = 5 V
50
40
30
30
20
20
10
10
0
Vin = 3.3 V
80
Vin = 5 V
Vin = 3 V
80
1
0
2
3
5
4
6
0
0.01
0.1
1
Output Current - A
Output Current - A
Figure 40. Efficiency vs Load Current
Figure 41. Efficiency vs Load Current
Vout = 50 mV / div (ac coupled)
10
Vin = 2 V / div
Iout = 2 A / div (1.5 A to 4.5 A load step)
Vout = 1 V / div
PWRGD = 2 V / div
Time = 2 msec / div
Time = 200 usec / div
1-A Load Step
Figure 43. Power Up, VOUT, VIN
Figure 42. Transient Response
Vout = 10 mV / div (ac coupled)
EN = 2 V / div
PH = 2 V / div
Vout = 1 V / div
PWRGD = 2 V / div
Time = 500 nsec / div
IOUT = 0 A
Time = 2 msec / div
Figure 44. Power Up, VOUT, EN
Figure 45. Output Ripple
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Gain - dB
Vin = 100 mV / div (ac coupled)
PH = 2 V / div
60
180
50
150
40
120
30
90
20
60
10
30
0
0
–10
–30
–20
–60
–30
–90
–40
–50
–60
100
–120
Gain
Phase
1000
Time = 500 nsec / div
0.4
0.4
0.3
0.3
100k
–180
1M
IOUT = 2 A
Iout = 3 A
Vin = 5 V
Output Voltage Deviation - %
Output Voltage Deviation - %
10k
Frequency - Hz
Figure 47. Closed-Loop Response
Figure 46. Input Ripple
0.2
0.1
Vin = 3.3 V
0
-0.1
-0.2
-0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.4
0
30
–150
VIN = 3.3. V
IOUT = 2A
Phase - Degrees
SLVSAE9F – NOVEMBER 2010 – REVISED MAY 2019
1
2
3
4
5
6
3
3.5
4
4.5
5
5.5
Output Current - A
Input Voltage-V
Figure 48. Load Regulation vs Load Current
Figure 49. Regulation vs Input Voltage
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 2.95 V and 6 V. This supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme. See the recommendations in Layout Guidelines.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance.
• Minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 50 for a
PCB layout example.
• The GND pins and AGND pin should be tied directly to the power pad under the TPS54618 device. The
power pad should be connected to any internal PCB ground planes using multiple vias directly under the
device. Additional vias can be used to connect the top-side ground area to the internal planes near the input
and output capacitors. For operation at full rated load, the top-side ground area along with any additional
internal ground planes must provide adequate heat dissipating area.
• Place the input bypass capacitor as close to the device as possible.
• Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output
inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive
coupling.
• The boot capacitor must also be located close to the device.
• The sensitive analog ground connections for the feedback voltage divider, compensation components, softstart capacitor and frequency set resistor should be connected to a separate analog ground trace as shown in
Figure 50.
• The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to
the device and routed with minimal trace lengths.
• The additional external components can be placed approximately as shown. It is possible to obtain
acceptable performance with alternate PCB layouts; however, this layout has been shown to produce good
results and can be used as a guide.
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTRORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
VOUT
OUTPUT
FILTER
CAPACITOR
PH
SLOW START
CAPACITOR
RT/CLK
COMP
VSENSE
AGND
SS
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 50. PCB Layout Example
10.3 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd), and supply current loss (Pq).
Pcon = Io2 × RDS_on_Temp
where
• IO is the output current (A).
• RDS_on_Temp is the ON-resistance of the high-side MOSFET with given temperature (Ω).
Pd = ƒsw × Io × 0.7 × 40 × 10–9
(42)
where
• IO is the output current (A).
• ƒsw is the switching frequency (Hz).
Psw = 1/2 × Vin × Io × ƒsw× 13 × 10–9
(43)
where
•
•
•
32
IO is the output current (A).
Vin is the input voltage (V).
ƒsw is the switching frequency (Hz).
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Power Dissipation Estimate (continued)
Pgd = 2 × Vin × ƒsw× 10 × 10–9
where
• Vin is the input voltage (V).
• ƒsw is the switching frequency (Hz).
Pq = Vin × 515 × 10–6
(45)
where
•
Vin is the input voltage (V).
(46)
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
where
•
Ptot is the total device power dissipation (W).
(47)
For given TA:
TJ = TA + Rth × Ptot
where
•
•
•
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
(48)
For given TJmax = 150°C:
TAmax = TJmax – Rth × Ptot
where
•
•
•
•
Ptot is the total device power dissipation (W).
Rth is the thermal resistance of the package (°C/W).
TJmax is maximum junction temperature (°C).
TAmax is maximum ambient temperature (°C).
(49)
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Developmental Support
For developmental support, see the following:
• Evaluation Module for TPS54618 Synchronous Step-Down SWIFT™ DC/DC Converter, HPA606
• For more SWIFT™ documentation, see the TI website at www.ti.com/swift
11.1.2 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54618 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
SWIFT, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
34
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54618RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54618
TPS54618RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54618
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2019
OTHER QUALIFIED VERSIONS OF TPS54618 :
• Automotive: TPS54618-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54618RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS54618RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54618RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS54618RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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