Texas Instruments | LMZM33604 3.5-V to 36-V Input, 1-V to 20-V Output, 4-A Power Module (Rev. A) | Datasheet | Texas Instruments LMZM33604 3.5-V to 36-V Input, 1-V to 20-V Output, 4-A Power Module (Rev. A) Datasheet

Texas Instruments LMZM33604 3.5-V to 36-V Input, 1-V to 20-V Output, 4-A Power Module (Rev. A) Datasheet
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LMZM33604
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LMZM33604 3.5-V to 36-V Input, 1-V to 20-V Output, 4-A Power Module
1 Features
3 Description
The LMZM33604 power module is an easy-to-use
integrated power solution that combines a 4-A DC/DC
converter with power MOSFETs, a shielded inductor,
and passives in a low-profile package. This power
solution requires as few as four external components
and eliminates the loop compensation and inductor
part selection from the design process.
2
•
Small complete solution size: < 250 mm
– Requires as few as 4 external components
– 16 mm × 10 mm × 4 mm QFN package
Supports 5-V, 12-V, 24-V, 28-V input rails
– 1-V to 20-V Output voltage range
– Pin compatible with 6-A LMZM33606
Meets EN55011 radiated emissions
Configurable as negative output voltage
Adjustable features for design flexibility
– Switching frequency (350 kHz to 2.2 MHz)
– Synchronization to an external clock
– Selectable auto mode or FPWM mode
– Auto: boost efficiency at light loads
– FPWM: Fixed frequency over entire load
– Adjustable soft start and tracking input
– Precision enable to program system UVLO
Protection features
– Hiccup mode current limit
– Overtemperature protection
– Power-good output
Operate in rugged environments
– Up to 50-W output power at 85°C, no airflow
– Operating junction range: –40°C to +125°C
– Operating ambient range: –40°C to +105°C
– Shock and vibration tested to Mil-STD-883D
1
•
•
•
•
•
•
The 16 mm × 10 mm × 4 mm, 41-pin, QFN package
is easy to solder onto a printed circuit board and
allows for a compact, low-profile point-of-load design.
The LMZM33604 feature set includes power good,
adjustable soft start, tracking, synchronization,
programmable UVLO, prebias start-up, selectable
auto or FPWM modes, as well as overcurrent and
overtemperature protection. The LMZM33604 can be
configured as negative output voltage for inverting
applications.
Device Information
DEVICE NUMBER
PACKAGE
LMZM33604
QFN (41)
BODY SIZE (NOM)
16.00 mm × 10.00 mm
space
Minimum Solution Size
2 Applications
•
•
•
Industrial, medical and test equipment
General purpose wide VIN regulation
Inverted output applications
space
Typical Efficiency (Auto Mode)
Simplified Schematic
100
VIN
VIN
PGOOD
EN
VOUT
95
90
LMZM33604
RFBT
SYNC/
MODE
COUT
SS/TRK
RT
FB
85
Efficiency (%)
CIN
VOUT
80
75
70
VOUT = 5 V
PGND
65
AGND
RFBB
fSW = 500 kHz
VIN = 12 V
VIN = 24 V
60
55
50
0
0.5
1
1.5
2
2.5
Output Current (A)
3
3.5
4
DFPE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZM33604
SNVSB57A – OCTOBER 2018 – REVISED MAY 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 8
Typical Characteristics (VIN = 12 V).......................... 9
Typical Characteristics (VIN = 24 V)........................ 11
Typical Characteristics (VIN = 36 V)........................ 13
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
26
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Examples...................................................
Theta JA vs PCB Area ..........................................
Package Specifications .........................................
EMI........................................................................
29
30
31
31
32
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
12.1 Tape and Reel Information ................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2018) to Revision A
•
2
Page
Added information on internal LDO and BIAS_SEL ............................................................................................................. 22
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5 Pin Configuration and Functions
SW
SW
2
SW
3
SW
4
SW
5
PGND
VOUT
1
SW
RLX Package
41-Pin QFN
Top View
31
30
29
32
34
36
SW
PGND
VOUT
33
35
37
SW
PGND
VOUT
28
VOUT
27
VOUT
26
VOUT
25
VOUT
24
VOUT
23
SW
6
38
PGND
DNC
7
PGND
8
VCC
9
PGND
39
41
VIN
21
AGND
20
EN
19
SYNC/MODE
PGOOD_PU
AGND
17 18
PGOOD
16
NC
12 13 14 15
SS/TRK
11
FB
10
RT
PGND
22
VIN
PGND
BIAS_SEL
40
PGND
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Pin Functions
PIN
TYPE
DESCRIPTION
16, 21
G
Analog ground. Zero voltage reference for internal references and logic. These pins are not
connected to one another internal to the device and must be connected to one another externally.
Do not connect these pins to PGND; the AGND to PGND connection is made internal to the device.
See the Layout section of the datasheet for a recommended layout.
BIAS_SEL
10
I
Optional BIAS LDO supply input. An internal 470 nF capacitor is placed between this pin and
PGND. Do not float; tie to PGND if not used. Tie to VOUT if 3.3 V ≤ VOUT ≤ 18 V, or tie to an
external 3.3-V or 5-V rail if available to improve efficiency.
DNC
7
—
EN
20
I
Precision enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to VIN.
Precision enable input allows adjustable system UVLO using external resistor divider.
FB
15
I
Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the
upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the
lower resistor (RFBB) of the feedback divider to AGND.
NC
14
—
Not internally connected.
8, 11, 23, 30,
34, 35, 38,
40, 41
G
Power ground. This is the return current path for the power stage of the device. Connect these pins
to the low side of the input source, load, and bypass capacitors associated with VIN and VOUT
using power ground planes on the PCB. Not all pins are connected to PGND internal to the device;
connections must be made externally. Connect pad 40 and 41 to the ground planes using multiple
vias for good thermal performance.
PGOOD
17
O
Open drain output for power-good flag. Internal to the device, a 100-kΩ pullup resistor is placed
between this pin and the PGOOD_PU pin.
PGOOD_PU
18
I
Power-good pullup supply. Connect to logic rail or other DC voltage no higher than 20 V.
RT
12
I
An external timing resistor connected between this pin and AGND adjusts the switching frequency
of the device. If floating, the default switching frequency is 500 kHz. Do not short to ground.
SS/TRK
13
I
Soft start / tracking control pin. Leave this pin floating to use the 5-ms internal soft-start ramp.To
increase the internal soft start ramp time, simply connect a capacitor between this pin and AGND.
This pin sources 2-μA of current to charge this external capacitor. Connect to external voltage ramp
for tracking. Do not connect to ground.
1, 2, 3, 4, 5,
6, 31, 32, 33
O
Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not
place any external components on these pins or tie them to a pin of another function.
NAME
NO.
AGND
PGND
SW
Do not connect. This pin is connected to internal circuitry. Do not connect this pin to AGND, PGND,
or any other voltage. This pin must be soldered to an isolated pad..
SYNC/MODE
19
I
Synchronization input and Mode setting pin. Do not float; tie to AGND or logic high if not used.
Connect to an external clock to synchronize (see Synchronization (SYNC/MODE)). Connect to
AGND to select Auto mode or connect to logic high to select FPWM mode. (see Mode Select (Auto
or FPWM)).
VCC
9
O
Output of internal bias supply. Used to supply internal control circuits and drivers. Do not place any
external component on this pin or tie it to a pin of another function.
22, 39
I
Input supply voltage. Connect external input capacitors between these pins and PGND.
24, 25, 26,
27, 28, 29,
36, 37
O
Output voltage. These pins are connected to the output of the internal inductor. Connect these pins
to the output load and connect external bypass capacitors between these pins and PGND.
VIN
VOUT
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
VIN to PGND
-0.3
42
V
EN to AGND
-0.3
VIN + 0.3
V
FB, RT, SS/TRK to AGND
-0.3
5
V
PGOOD to AGND
-0.1
20
V
SYNC/MODE to AGND
-0.3
5.5
V
BIAS_SEL to AGND
-0.3
Lower of (VIN+0.3) and 20
V
AGND to PGND
-0.3
0.3
V
VOUT to PGND
-0.3
VIN
V
SW to PGND
-0.3
VIN + 0.3
V
SW to PGND (<10 ns transients)
-3.5
42
V
VCC to PGND
-0.3
5
V
-40
125
°C
-55
150
°C
240
°C
Maximum junction temperature, TJ
Temperature
(2)
Storage temperature, Tstg
Peak Reflow Case Temperature
Maximum Number of Reflows Allowed
1
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine,
mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
(1)
(2)
UNIT
500
G
20
G
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under the
recommended operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the
internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area
(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the
module is never exceeded.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
MAX
(1)
36
V
Output voltage, VOUT
1
20
V
EN voltage, VEN
0
VIN
V
PGOOD pullup voltage, VPGOOD
0
18
V
mA
Input voltage, VIN
3.5
PGOOD sink current
UNIT
0
5
3.3
Lower of VIN and 18
V
0
4
A
Switching frequency, FSW
350
1200
Operating ambient temperature, TA
–40
105
BIAS_SEL
Output current, IOUT
20 (2)
Input Capacitance, CIN
(1)
(2)
(3)
°C
µF
min (3)
Output Capacitance, COUT
kHz
700
µF
For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
A minimum of 20 µF ceramic input capacitance is required for proper operation. An additional 100 µF of bulk capacitance is
recommended for applications with transient load requirements. (see Input Capacitor Selection ).
The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ).
6.4 Thermal Information
LMZM33604
THERMAL METRIC (1)
RLX(B2QFN)
UNIT
41 PINS
(2)
RθJA
Junction-to-ambient thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
TSHDN
(1)
(2)
(3)
(4)
6
13.9
°C/W
1.2
°C/W
6.2
°C/W
Thermal Shutdown Temperature
160
°C
Thermal Shutdown Hysteresis
25
°C
(3)
(4)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75 mm x 75 mm double-sided PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA.
The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
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6.5 Electrical Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 500 kHz, FPWM mode (unless
otherwise noted); CIN1 = 3x 10 µF, 50-V, 1210 ceramic; CIN2 = 2x 4.7 µF, 50-V, 1210 ceramic; COUT = 6x 22 µF, 25-V, 1210
ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most
likely parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE (VIN)
VIN
ISHDN
3.5 (1)
Input voltage range
Over IOUT range, VOUT = 2.5 V, fSW = 350 kHz
VIN turn on
VIN increasing, VOUT = 2.5 V, IOUT = 0 A
3.12
36
VIN turn off
VIN decreasing, VOUT = 2.5 V, IOUT = 0 A
2.62
Shutdown supply current
VIN = 12 V, VEN = 0 V, IOUT = 0 A
0.8
V
V
V
10
µA
INTERNAL LDO (VCC, BIAS_SEL)
PWM operation
3.27
V
PFM operation
3.1
V
BIAS_SEL quiescent
current (non-switching)
VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VBIAS_SEL =
3.3 V
21
50
µA
Feedback voltage (2)
–40°C ≤ TJ = TA ≤ 125°C, IOUT = 0 A, Over VIN
range, VOUT = 2.5 V, fSW = 350 kHz
1.006
1.017
V
Load regulation
Over IOUT range, TA = 25 °C
Feedback leakage current
VFB = 1 V
65
nA
Output current
Natural convection, TA = 25 °C
4
A
VCC
Internal VCC voltage
IBIAS_SEL
FEEDBACK
VFB
IFB
0.987
0.1%
0.2
CURRENT
IOUT
0
Overcurrent threshold
9
A
PERFORMANCE
ƞ
Efficiency
IOUT = 3 A, TA = 25 °C
Internal soft start time
SS pin open
Soft-start charge current
VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VSS/TRK =
0.5 V
91%
SOFT START
TSS
ISSC
5
1.8
ms
2
2.2
1.2
1.25
µA
ENABLE (EN)
VEN-H
EN rising threshold
VEN-HYS
EN hysteresis voltage
IEN
EN Input leakage current
1.14
-100
VIN = 12 V, VFB = 1.5 V, VEN = 2 V
V
mV
1.4
200
nA
POWER GOOD (PGOOD)
VPGOOD
VINPG
(1)
(2)
PGOOD thresholds
Overvoltage
106%
110%
113%
Undervoltage
86%
90%
93%
PGOOD low voltage
0.5-mA pullup, VEN = 0 V
Minimum VIN for valid
PGOOD
50-μA pullup, VEN = 0 V, TJ = TA = 25°C
1.3
0.3
V
2
V
For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
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6.6 Switching Characteristics
Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, FPWM mode (unless otherwise noted);
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm, and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
500
MAX
UNIT
560
kHz
2200
kHz
FREQUENCY (RT) and SYNCHRONIZATION (SYNC)
fSW
VSYNC
TS-MIN
8
Default switching frequency
RT pin = open, IOUT = 0 A
440
Switching frequency range
IOUT = 0 A
350
High Threshold
2
Low Threshold
0.4
Minimum SYNC ON/OFF time
V
80
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6.7 Typical Characteristics (VIN = 12 V)
100
100
95
95
90
90
85
85
80
80
75
75
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
70
65
60
70
65
60
55
55
50
50
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
45
40
35
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
45
40
35
30
30
0
1
2
Output Current (A)
3
0
4
1
2
Output Current (A)
3
4
D013
D011
FPWM Mode
Linear Scale
Auto Mode
Linear Scale
Figure 2. Efficiency vs Output Current
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
Figure 1. Efficiency vs Output Current
100
50
40
30
50
40
30
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
20
10
0
0.001
0.01
0.1
Output Current (A)
1
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
20
10
0
0.001
4
0.01
0.1
Output Current (A)
1
4
D012
FPWM Mode
Log Scale
D014
Auto Mode
Log Scale
Figure 3. Efficiency vs Output Current
Figure 4. Efficiency vs Output Current
30
30
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
25
Output Ripple Voltage (mV)
Output Ripple Voltage (mV)
25
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
20
15
10
5
20
15
10
5
0
0
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D016
FPWM Mode
COUT = 4 × 47 µF ceramic
Figure 5. Voltage Ripple vs Output Current
4
D015
Auto Mode
COUT = 4 × 47 µF ceramic
Figure 6. Voltage Ripple vs Output Current
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Typical Characteristics (VIN = 12 V) (continued)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
115
2.5
VOUT, fSW
5.0V, 500kHz
3.3V, 500kHz
2.5V, 400kHz
1.8V, 400kHz
1.2V, 400kHz
105
95
Ambient Temperature (°C)
Power Dissipation (W)
2
1.5
1
85
75
65
55
45
0.5
Airflow
100LFM
Nat Conv
35
25
0
0
1
2
Output Current (A)
3
0
4
1
2
Output Current (A)
3
4
D020
D017
VOUT = 1.8 V
fSW = 400 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 8. Safe Operating Area
115
105
105
95
95
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 7. Power Dissipation vs Output Current
115
85
75
65
55
45
85
75
65
55
45
Airflow
200LFM
100LFM
Nat Conv
35
Airflow
200LFM
100LFM
Nat Conv
35
25
25
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D019
VOUT = 3.3 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
D018
VOUT = 5 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 9. Safe Operating Area
10
4
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Figure 10. Safe Operating Area
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6.8 Typical Characteristics (VIN = 24 V)
100
100
95
95
90
90
85
85
80
80
75
75
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
70
65
60
70
65
60
55
55
50
50
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
45
40
35
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
45
40
35
30
30
0
1
2
Output Current (A)
3
0
4
1
2
Output Current (A)
3
4
D003
D001
FPWM Mode
Linear Scale
Auto Mode
Figure 12. Efficiency vs Output Current
100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
Figure 11. Efficiency vs Output Current
Linear Scale
50
40
30
50
40
30
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
20
10
0
0.001
0.01
0.1
Output Current (A)
1
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
3.3V, 500kHz
20
10
0
0.001
4
0.01
0.1
Output Current (A)
1
4
D002
FPWM Mode
Log Scale
D004
Auto Mode
Figure 13. Efficiency vs Output Current
Figure 14. Efficiency vs Output Current
80
80
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
60
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
70
60
Output Ripple Voltage (mV)
70
Output Ripple Voltage (mV)
Log Scale
50
40
30
50
40
30
20
20
10
10
0
0
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D006
FPWM Mode
COUT = 4 × 47 µF ceramic
4
D005
Auto Mode
Figure 15. Output Voltage Ripple
COUT = 4 × 47 µF ceramic
Figure 16. Output Voltage Ripple
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Typical Characteristics (VIN = 24 V) (continued)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
115
5
VOUT, fSW
18V, 1MHz
15V, 800kHz
12V, 800kHz
5.0V, 500kHz
3.3V, 500kHz
105
95
Ambient Temperature (°C)
Power Dissipation (W)
4
3
2
85
75
65
55
45
1
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
0
1
2
Output Current (A)
3
0
4
1
2
Output Current (A)
3
4
D010
D007
VOUT = 3.3 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 18. Safe Operating Area
115
105
105
95
95
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 17. Power Dissipation
115
85
75
65
55
45
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
85
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D009
VOUT = 5 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
D008
VOUT = 12 V
fSW = 800 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 19. Safe Operating Area
12
4
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Figure 20. Safe Operating Area
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6.9 Typical Characteristics (VIN = 36 V)
100
100
95
95
90
90
85
85
80
80
75
75
Efficiency (%)
Efficiency (%)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
70
65
60
55
70
65
60
55
50
50
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
45
40
35
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
45
40
35
30
30
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
4
D025
FPWM Mode
Linear Scale
D027
Auto Mode
Figure 22. Efficiency vs Output Current
100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
Figure 21. Efficiency vs Output Current
Linear Scale
50
40
30
50
40
30
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
20
10
0
0.001
0.01
0.1
Output Current (A)
1
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
20
10
0
0.001
4
0.01
0.1
Output Current (A)
1
4
D026
FPWM Mode
Log Scale
D028
Auto Mode
Figure 23. Efficiency vs Output Current
Figure 24. Efficiency vs Output Current
40
40
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
30
Output Ripple Voltage (mV)
30
Output Ripple Voltage (mV)
Log Scale
20
10
20
10
0
0
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D030
FPWM Mode
COUT = 4 × 47 µF ceramic
4
D029
Auto Mode
Figure 25. Output Voltage Ripple
COUT = 4 × 47 µF ceramic
Figure 26. Output Voltage Ripple
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Typical Characteristics (VIN = 36 V) (continued)
The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
device.
115
6
VOUT, fSW
20V, 1MHz
18V, 1MHz
15V, 800kHz
12V, 800kHz
5V, 500kHz
105
95
Ambient Temperature (°C)
Power Dissipation (W)
5
4
3
2
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
1
35
25
0
0
1
2
Output Current (A)
3
0
4
1
2
Output Current (A)
3
4
D032
D031
VOUT = 5 V
fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 28. Safe Operating Area
115
105
105
95
95
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 27. Power Dissipation
115
85
75
65
55
45
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
85
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
1
2
Output Current (A)
3
4
0
1
2
Output Current (A)
3
D033
VOUT = 12 V
fSW = 800 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
D034
VOUT = 20 V
fSW = 1 MHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 29. Safe Operating Area
14
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Figure 30. Safe Operating Area
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7 Detailed Description
7.1 Overview
The LMZM33604 is a full-featured 36-V input, 4-A, synchronous step-down converter with controller, MOSFETs,
shielded inductor, and control circuitry integrated into a low-profile, overmolded package. The device integration
enables small designs, while providing the ability to adjust key parameters to meet specific design requirements.
The LMZM33604 provides an output voltage range of 1 V to 20 V. An external resistor divider is used to adjust
the output voltage to the desired value. The switching frequency can also be adjusted, by either an external
resistor or a sync signal, which allows the LMZM33604 to optimize efficiency for a wide variety of input and
output voltage conditions. The device provides accurate voltage regulation over a wide load range by using a
precision internal voltage reference. The EN pin can be pulled low to put the device into standby mode to reduce
input quiescent current. The system undervoltage lockout can be adjusted using a resistor divider on the EN pin.
A power-good signal is provided to indicate when the output is within its nominal voltage range. Thermal
shutdown and current limit features protect the device during an overload condition. A 41-pin, QFN package that
includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Thermal
Shutdown
Precision
Enable
Shutdown
Logic
EN
VCC
OCP
2µA
Soft
Start
SS/TRK
UVLO
PGND
+
+
+
VREF
VIN
FB
Comp
SW
SYNC/MODE
RT
BIAS_SEL
LDO
MODE
Oscillator
PGOOD_PU
Power
Stage
and
Control
Logic
6.8µH
VOUT
100 kO
PGOOD
PGOOD
Logic
AGND
PGND
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7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 15) programs the output voltage of the LMZM33604. The output
voltage adjustment range is from 1 V to 20 V. Figure 31 shows the feedback resistor connection for setting the
output voltage. The recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using
Equation 1.
Table 1 lists the standard external RFBT values for several standard output voltages along with the recommended
switching frequency (FSW) and the frequency setting resistor (RRT) for each of the output voltages listed. (See
Voltage Dropout for the allowable output voltage as a function of input voltage.)
space
RFBT =
10 x
(V
OUT
- VFB
) (k )
where
•
VFB (typical) = 1.006 V
(1)
VOUT
RFBT
FB
RFBB
10 k
AGND
Figure 31. Setting the Output Voltage
Table 1. Standard Component Values
(1)
16
VOUT (V)
RFBT (kΩ) (1)
fSW (kHz)
RRT (kΩ)
1.2
1.96
400
100
1.8
7.87
400
100
2.5
15.0
400
100
3.3
22.6
500
78.7 or open
5
40.2
500
78.7 or open
7.5
64.9
500
78.7 or open
12
110
800
47.5
15
140
800
47.5
18
169
1000
38.3
20
191
1000
38.3
RFBB = 10 kΩ.
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7.3.2 Input Capacitor Selection
The LMZM33604 requires a minimum of 20 µF of ceramic type input capacitance. Use only high-quality ceramic
type X5R or X7R capacitors with sufficient voltage rating. TI recommends an additional 33 µF of non-ceramic
capacitance for applications with transient load requirements. The voltage rating of input capacitors must be
greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends
a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. At worst case, when
operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must
be at least 2 ARMS. Table 2 includes a preferred list of capacitors by vendor.
Table 2. Recommended Input Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING VOLTAGE (V)
CAPACITANCE
(µF)
(2)
ESR (3)
(mΩ)
TDK
X5R
C3225X5R1H106K
50
10
3
Murata
X7R
GRM32ER71H106K
50
10
2
Murata
X7R
GRM32ER71J106K
63
10
2
Panasonic
ZA
EEHZA1H101P
50
100
28
Panasonic
ZA
EEHZA1J560P
63
56
30
(1)
(2)
(3)
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Specified capacitance values.
Maximum ESR at 100 kHz, 25°C.
7.3.3 Output Capacitor Selection
The minimum amount of required output capacitance for the LMZM33604 varies depending on the output
voltage. Table 3 lists the minimum output capacitance for several output voltage ranges. The required output
capacitance must be comprised of all ceramic capacitors.
When adding additional output capacitance, ceramic capacitors or a combination of ceramic and polymer-type
capacitors can be used. The required capacitance above the minimum is determined by actual transient
deviation requirements. See Table 4 for a preferred list of output capacitors by vendor.
Table 3. Minimum Required Output Capacitance
VOUT RANGE (V)
(1)
MINIMUM REQUIRED COUT
MIN
MAX
CAPACITANCE VALUE
1
1
400 µF
(1)
VOLTAGE RATING
>1
1.8
300 µF
> 1.8
2.5
200 µF
> 2.5
3.3
150 µF
> 3.3
5
100 µF
> 5.0
12
100 µF
≥ 16 V
> 12
20
50 µF
≥ 25 V
≥ 6.3 V
The minimum required output capacitance must be made up of ceramic type capacitors. Additional capacitance above the minimum can
be either ceramic or low-ESR polymer type.
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Table 4. Recommended Output Capacitors (1)
VENDOR
SERIES
PART NUMBER
CAPACITOR CHARACTERISTICS
VOLTAGE (V)
CAPACITANCE (µF) (2)
ESR (mΩ) (3)
TDK
X5R
C3225X5R1C106K
16
10
2
Murata
X5R
GRM32ER61C106K
16
10
2
TDK
X5R
C3225X5R1C226M
16
22
2
Murata
X5R
GRM32ER61C226K
16
22
2
Murata
X6S
GRM31CC81E226K
25
22
2
Murata
X7R
GRM32ER71E226M
25
22
2
TDK
X5R
C3225X5R1A476M
10
47
2
Murata
X5R
GRM32ER61C476K
16
47
2
Murata
X5R
GRM31CR61E476M
25
47
2
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
Murata
X5R
GRM32ER61A107M
10
100
2
Kemet
X5R
C1210C107M4PAC7800
16
100
2
Panasonic
POSCAP
6TPF220M9L
6.3
220
9
Panasonic
POSCAP
6TPE220ML
6.3
220
12
(1)
(2)
(3)
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Specified capacitance values.
Maximum ESR at 100 kHz, 25°C.
7.3.4 Transient Response
Table 5 shows the voltage deviation for several transient conditions.
Table 5. Output Voltage Transient Response
CIN = 2× 10 µF, 50-V Ceramic, 33 µF, 50-V Polymer Electrolytic
VOUT (V)
1.8
3.3
5
12
(1)
18
COUT
VOLTAGE
(1)
DEVIATION (mV)
300 µF
40
500 µF
30
150 µF
45
400 µF
40
100 µF
55
250 µF
45
100 µF
175
200 µF
150
50% load step at 1 A/µs.
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7.3.5 Feed-Forward Capacitor
The LMZM33604 is internally compensated to be stable over the operating range of the device. However,
depending on the output voltage and amount of output capacitance, a feed-forward capacitor, CFF, may be added
for optimum performance. The feed-forward capacitor should be placed in parallel with the top resistor divider,
RFBT as shown in Figure 32. The value for CFF can be calculated using Equation 2. For output voltages < 1.2 V,
CFF is ineffective and is not recommended.
CFF =
4.3 x
VOUT x COUT
(pF)
RFBT
where
•
•
COUT is in µF
RFBT is in kΩ
(2)
VOUT
RFBT
CFF
FB
RFBB
10 k
AGND
Figure 32. Feed-Forward Capacitor
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7.3.6 Switching Frequency (RT)
The recommended switching frequency range of the LMZM33604 is 350 kHz to 1.2 MHz. Table 6 shows the
allowable output voltage range for several switching frequency settings for three common input voltages. Under
some operating conditions, the device can operate at higher switching frequencies (up to 2.2 MHz), however, this
will reduce efficiency and thermal performance. The switching frequency can easily be set by connecting a
resistor (RRT) between the RT pin and AGND. Additionally, the RT pin can be left floating, and the LMZM33604
operates at 500 kHz default switching frequency. Use Equation 3 to calculate the RRT value for a desired
frequency or simply select from Table 6.
The switching frequency must be selected based on the output voltage setting of the device. See Table 6 for RRT
values and the allowable output voltage range for a given switching frequency at several common input voltages.
For the most efficient solution, always select the lowest allowable frequency.
RRT =
1
(kO)
fSW (kHz) × (2.675 × 10-5) t 0.0007
(3)
Table 6. Switching Frequency vs Output Voltage
VIN = 5 V (±10%)
VIN = 12 V (±10%)
VIN = 24 V (±10%)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
SWITCHING
FREQUENCY (kHz)
RRT RESISTOR (kΩ)
MIN
MAX
MIN
MAX
MIN
MAX
350
115
1
4
1
8.2
1
8.4
400
100
1
4
1
8.8
1
9.9
500
78.7 or open
1
4
1
9.9
1.1
13.9
600
64.9
1
4
1
9.9
1.3
15.6
700
54.9
1
3.5
1
9.7
1.5
16.9
800
47.5
1
3.4
1
9.6
1.7
18
1000
38.3
1
3.4
1.1
9.3
2.1
20
1200
31.6
1
3.3
1.3
9.1
2.5
19.1
1500
25.5
1
2.9
1.8
8.1
3.2
18.1
1800
21.0
1.1
2.7
2.1
7.7
3.9
17.2
2000
19.1
1.2
2.5
2.5
7.5
4.4
16.5
2200
17.4
1.3
2.4
2.7
7.2
4.8
15.9
7.3.7 Synchronization (SYNC/MODE)
The LMZM33604 switching frequency can also be synchronized to an external clock from 350 kHz to 2.2 MHz.
Before the external clock is present, the device switches at the frequency programmed by the RRT resistor.
Select RRT to set the frequency to be the same as the external synchronization frequency. Once the external
clock is present, the device transitions to SYNC mode within 1 ms (typical) and overrides the RT mode. If the
external clock is removed, the device continues to switch at the SYNC frequency for 10 µs (typ) before returning
to the switching frequency set by the RT resistor, resulting in minimal disturbance to the output voltage during the
transitions.
Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns.
When synchronizing to an external clock, the device operation mode is FPWM. If synchronization is not needed,
connect this pin to AGND or logic high to select either Auto mode or FPWM mode. Do not leave this pin open.
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. Table 6 and show the allowable frequencies for a given range of output voltages. For the most
efficient solution, always select the lowest allowable frequency.
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7.3.8 Output Enable (EN)
The voltage on the EN pin provides electrical ON/OFF control of the device. Once the EN pin voltage exceeds
the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low quiescent current state.
The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the LMZM33604 is to
connect the EN pin to VIN directly as shown in Figure 33. This allows self-start-up of the LMZM33604 when VIN
reaches the turn-on threshold.
If an application requires controlling the EN pin, an external logic signal can be used to drive EN pin as shown in
Figure 34. Applications using an open drain/collector device to interface with this pin require a pullup resistor to a
voltage above the enable threshold.
VIN
VIN
EN
EN
PGND
PGND
Figure 33. Enabling the Device
Figure 34. Typical Enable Control
7.3.9 Programmable System UVLO (EN)
Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be
used for sequencing, to satify a system timing requirement, or to reduce the occurrence of deep discharge of a
battery power source. Figure 35 shows how to use a resistor divider to set a system UVLO level. An external
logic output can also be used to drive the EN pin for system sequencing.
VIN
VIN
RENT
EN
RENB
PGND
Figure 35. System UVLO
Table 7 lists recommended resistor values for RENT and RENB to adjust the system UVLO voltage. TI
recommends to set the system UVLO turn-on threshold to approximately 80% to 85% of the minimum expected
input voltage.
Table 7. Resistor Values for Setting System UVLO
UVLO (V)
6.5
10
15
20
25
RENT (kΩ)
100
100
100
100
100
RENB (kΩ)
22.6
13.7
8.66
6.34
4.99
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7.3.10 Internal LDO and BIAS_SEL
The LMZM33604 integrates an internal LDO, generating a typical VCC voltage (3.27 V) for control circuitry and
MOSFET drivers. The LDO generates VCC voltage from VIN unless a sufficient bias voltage, VBIAS, is applied to
BIAS_SEL pin. The BIAS_SEL input provides an option to supply the LDO with a lower voltage than VIN to
reduce the LDO power loss. The smaller the difference between the input applied to the LDO, VIN_LDO, and the
LDO output voltage, VCC, the more efficiently the device will perform. The amount of current supplied through the
LDO will change based on operating conditions. Figure 36 demonstrates the typical LDO current, ILDO, for
common input voltages over the recommended switching frequency range.
30
Internal LDO Current (mA)
25
20
15
10
5
36 VIN
24 VIN
12 VIN
0
300
400
500
600
700
800
900
1000
1100
1200
Switching Frequency (kHz)
1300
LMZM
VOUT = 5 V
Figure 36. LDO Current vs Switching Frequency
The amount of power loss in the LDO can be calculated by Equation 4.
PLOSS_LDO = ILDO x (VIN_LDO - VCC)
(4)
For example, when the device is operating at VIN = 24 V, VOUT = 5 V, fsw = 500 kHz, BIAS_SEL = PGND, the ILDO
is typical 11 mA, therefore, the PLOSS_LDO = 11 mA × (24 V – 3.27 V) = 228.03 mW. For the same operating
conditions with BIAS_SEL = 5 V, the power loss is equal to 11 mA × (5 V – 3.27 V) = 19.03 mW. The benefits of
applying a bias voltage to reduce power loss are most notable in applications when VIN » VCC or when the device
is operating at a higher switching frequency. The power savings can be calculated by Equation 5.
Power Savings = ILDO x (VIN ± VBIAS_SEL)
(5)
Figure 37 and Figure 38 show efficiency plots of the LMZM33604 operating with different source voltages applied
to the BIAS_SEL pin. Figure 39 demonstrates the power dissipation of the device with various source voltages at
BIAS_SEL pin. The plots include BIAS_SEL tied to a 3.3 V external bias, 5 V external bias, VOUT (5 V) and no
bias voltage applied. The efficiency improvements are more significant when the device is operating at light loads
because the LDO loss is a higher percentage of the total loss.
22
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100
95
90
85
75
Efficiency (%)
Efficiency (%)
80
70
65
60
55
50
45
3.3V External Bias
5.0V External Bias
VOUT Bias (5V)
No Bias
40
35
30
0
1
2
3
4
Output Current (A)
VIN = 24 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0.001
3.3V External Bias
5.0V External Bias
VOUT Bias (5V)
No Bias
0.01
fSW = 500 kHz
0.1
1
Output Current (A)
LMZM
FPWM Mode
VIN = 24 V
Figure 37. Efficiency Comparison with BIAS_SEL vs
Output Current
fSW = 500 kHz
4
LMZM
FPWM Mode
Figure 38. Efficiency Comparison with BIAS_SEL vs
Output Current
3
Power Dissipation (W)
No Bias
VOUT Bias (5V)
5.0V External Bias
3.3V External Bias
2
1
0
0
1
2
3
4
Output Current (A)
VIN = 24 V
fSW = 500 kHz
LMZM
FPWM Mode
Figure 39. Power Dissipation Comparison with BIAS_SEL
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7.3.11 Power Good (PGOOD) and Power Good Pullup (PGOOD_PU)
The LMZM33604 has a built-in power-good signal (PGOOD) that indicates whether the output voltage is within its
regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage
source of 15 V or less. The maximum recommended PGOOD sink current is 5 mA. A typical pullup resistor value
is between 10 kΩ and 100 kΩ.
Once the output voltage rises above 90% (typical) of the set voltage, the PGOOD pin rises to the pullup voltage
level. The PGOOD pin is pulled low when the output voltage drops lower than 90% (typical) or rises higher than
110% (typ) of the nominal set voltage.
Internal to the device, a 100-kΩ pullup resistor is placed between the PGOOD pin and the PGOOD_PU pin.
Applying a pullup voltage directly to the PGOOD_PU pin, eliminates the need for an external pullup resistor.
7.3.12 Mode Select (Auto or FPWM)
The LMZM33604 has configurable Auto mode or FPWM mode options. To select Auto mode, connect the
SYNC/MODE pin (pin 19) to AGND, or a logic signal lower than 0.3 V. To select FPWM mode, connect the
SYNC/MODE pin to a bias voltage or logic signal greater than 0.6 V. When synchronizing to an external clock,
the device inherently operates in FPWM mode.
In Auto mode, the device operates in discontinuous conduction mode (DCM) at light loads. In DCM, the inductor
current stops flowing when it reaches 0 A. Additionally, at very light loads, the switching frequency reduces (PFM
operation) to regulate the required load current, thus improving efficiency by reducing switching losses. At
heavier loads, when the inductor current valley is above 0 A, the device operates in continuous conduction mode
(CCM), where the switching frequency is fixed and set by the RT pin.
In forced PWM (FPWM) mode, the device operates in CCM (at a fixed frequency) regardless of load. In this
mode, inductor current can go negative. At light loads, the efficiency in FPWM mode is lower than in Auto mode,
due to higher conduction losses and higher switching losses. The fact that the switching frequency is fixed over
the entire load range is beneficial in noise sensitive applications.
7.3.13 Soft Start and Voltage Tracking
The soft-start and tracking features control the output voltage ramp during start-up. The soft-start feature reduces
inrush current during start-up and improves system performance and reliability. If the SS/TRK pin is floating, the
LMZM33604 starts up following the fixed, 5-ms internal soft-start ramp. Use CSS to extend soft-start time when
there are a large amount of output capacitors, or the output voltage is high, or the output is heavily loaded during
start-up.
If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to AGND. There is a
2 µA (typical) internal current source, ISSC, to charge the external capacitor. For a desired soft-start time tSS,
capacitance of CSS can be found by Equation 6.
CSS = ISSC × tSS
where
•
•
•
CSS = soft-start capacitor value (F)
ISSC = soft-start charging current (A)
tSS = desired soft-start time(s)
(6)
LMZM33604 can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the internal
soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise interfering
with the reference voltage. Figure 40 shows how to use resistor divider to set VOUT to follow an external ramp.
EXT
RAMP
RTRT
SS/TRK
RTRB
PGND
Figure 40. Soft-Start Tracking External Ramp
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7.3.14 Voltage Dropout
Voltage dropout is the minimum difference between the input voltage and output voltage that is required to
maintain output voltage regulation while providing the rated output current.
To ensure the LMZM33604 maintains output voltage regulation at the recommended switching frequency, over
the operating temperature range, the following requirements apply:
For output voltages ≤ 5 V, the minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater.
For output voltages > 5 V, the minimum VIN is (1.1 × VOUT).
space
However, if fixed switching frequency operation is not required, the LMZM33604 operates in a frequency
foldback mode when the dropout voltage is less than the recommendations above. Frequency foldback reduces
the switching frequency to allow the output voltage to maintain regulation as input voltage decreases. Figure 41
through Figure 44 show typical dropout voltage and frequency foldback curves for 5 V and 12 V outputs at TA =
25°C. (As ambient temperature increases, dropout voltage and frequency foldback occur at higher input
voltages.)
5.4
600
5.2
550
5.0
500
4.8
450
Frequency (kHz)
Output Voltage (V)
4.6
4.4
4.2
4.0
400
350
300
3.8
250
3.6
200
3.4
Iout
0.1 A
2.0 A
4.0 A
3.2
3.0
4.0
4.2
4.4
4.6
VOUT = 5 V
4.8
5.0
5.2
Input Voltage (V)
5.4
5.6
5.8
Iout
0.1 A
2.0 A
4.0 A
150
100
4.6
6.0
4.8
5.0
5.2
D021
fSW = 500 kHz
VOUT = 5 V
Figure 41. Voltage Dropout
5.4
5.6
Input Voltage (V)
5.8
6.0
6.2
6.4
D022
fSW = 500 kHz
Figure 42. Frequency Foldback
12.4
1000
12.2
900
12.0
800
11.8
700
Frequency (kHz)
Output Voltage (V)
11.6
11.4
11.2
11.0
600
500
400
10.8
300
10.6
200
10.4
Iout
0.1 A
2.0 A
4.0 A
10.2
10.0
11.0
11.2
11.4
VOUT = 12 V
11.6
11.8
12.0
12.2
Input Voltage (V)
12.4
12.6
fSW = 800 kHz
12.8
Iout
0.1 A
2.0 A
4.0 A
100
13.0
0
11.8
12.0
12.2
D023
VOUT = 12 V
Figure 43. Voltage Dropout
12.4
12.6
12.8
Input Voltage (V)
13.0
13.2
13.4
13.6
D024
fSW = 800 kHz
Figure 44. Frequency Foldback
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7.3.15 Overcurrent Protection (OCP)
The LMZM33604 is protected from overcurrent conditions. Hiccup mode is activated if a fault condition persists to
prevent overheating. In hiccup mode, the regulator is shut down and kept off for 10 ms (typical) before the
LMZM33604 tries to start again. If an overcurrent or short-circuit fault condition still exists, hiccup repeats until
the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions and
prevents overheating and potential damage to the device. Once the fault is removed, the module automatically
recovers and returns to normal operation.
7.3.16 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 135°C
(typical).
7.4 Device Functional Modes
7.4.1 Active Mode
The LMZM33604 is in active mode when VIN is above the turnon threshold and the EN pin voltage is above the
EN high threshold. The simplest way to enable the LMZM33604 is to connect the EN pin to VIN. This allows self
start-up of the LMZM33604 when the input voltage is in the operation range of 3.5 V to 36 V.
7.4.2 Auto Mode
In Auto mode, the LMZM33604 operates in discontinuous conduction mode (DCM) at light loads. In DCM, the
inductor current stops flowing when it reaches 0 A. Additionally, at very light loads, the switching frequency
reduces (PFM operation) to regulate the required load current, thus improving efficiency by reducing switching
losses. At heavier loads, when the inductor current valley is above 0 A, the device operates in continuous
conduction mode (CCM), where the switching frequency is fixed and set by the RT pin.
7.4.3 FPWM Mode
In forced PWM (FPWM) mode, the LMZM33604 operates in CCM (at a fixed frequency) regardless of load. In
this mode, inductor current can go negative. At light loads, the efficiency in FPWM mode is lower than in Auto
mode, due to higher conduction losses and higher switching losses.
7.4.4 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMZM33604. When the EN pin voltage is below the
EN low threshold, the device is in shutdown mode. In shutdown mode the standby current is 0.8 μA typical. If VIN
falls below the turn-off threshold, the output of the regulator is turned off.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZM33604 is a synchronous step-down DC-DC power module. It is used to convert a higher DC voltage to
a lower DC voltage with a maximum output current of 4 A. The following design procedure can be used to select
components for the LMZM33604. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes an iterative design procedure and
accesses comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Application
The LMZM33604 only requires a few external components to convert from a wide input-voltage-supply range to a
wide range of output voltages. Figure 45 shows a typical LMZM33604 schematic.
VIN = 24 V
VIN
PGOOD
EN
VOUT
VOUT = 5 V
10 µF
50 V
10 µF
50 V
LMZM33604
RT
40.2 kO
100 pF
SS/TRK
FB
SYNC/MODE
100 µF
6.3 V
100 µF
6.3 V
BIAS_SEL
AGND
PGND
10 kO
Figure 45. LMZM33604 Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 8 as the input parameters and follow the design
procedures in Detailed Design Procedure.
Table 8. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage VIN
24 V typical
Output voltage VOUT
5V
Output current rating
4A
Operating frequency
500 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Setpoint
The output voltage of the LMZM33604 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. The value for RFBT can be selected from Table 1 or calculated using the Equation 7:
RFBT =
10 x
(V
OUT
- VFB
) (k )
(7)
For the desired output voltage of 5 V, the formula yields a value of 40 kΩ. Choose the closest available value of
40.2 kΩ for RFBT.
8.2.2.2 Setting the Switching Frequency
The recommended switching frequency for a 5-V application is 500 kHz. To set the switching frequency to
500 kHz, the RT pin can be left open to operate at the default 500-kHz switching frequency.
8.2.2.3 Input Capacitors
The LMZM33604 requires a minimum input capacitance of 20-µF ceramic type. High-quality ceramic type X5R or
X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input capacitors must be
greater than the maximum input voltage.
For this design, 2x 10-µF, 50-V ceramic capacitors are selected.
8.2.2.4 Output Capacitor Selection
The LMZM33604 requires a minimum amount of output capacitance for proper operation. The minimum amount
of required output varies depending on the output voltage. See Table 3 for the required output capacitance.
For this design example, 2 × 100-µF, 6.3-V ceramic capacitors are used.
8.2.2.5 Feed-Forward Capacitor (CFF)
For typical applications, an external feed-forward capacitor, CFF is not required. Applications requiring optimum
transient performance can benefit from placing a CFF capacitor in parallel with the top resistor divider, RFBT. The
value for CFF can be calculated using Equation 2. The recommended CFF value for 5-V application is 100 pF.
8.2.2.6 Application Curves
VIN = 24 V
VOUT = 5 V
IOUT = 4 A
VIN = 24 V
Figure 46. Start-up Waveforms
28
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VOUT = 5 V
COUT = 200 µF
IOUT = 1 A to 3 A
Slew rate: 1 A/µs
Figure 47. Transient Response
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9 Power Supply Recommendations
The LMZM33604 is designed to operate from an input voltage supply range between 3.5 V and 36 V. This input
supply must be able to withstand maximum input current and maintain a stable voltage. The resistance of the
input supply rail must be low enough that an input current transient does not cause a high enough drop at the
LMZM33604 supply voltage that can cause a turn-off and system reset.
If the input supply is located more than a few inches from the LMZM33604 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 100-µF
electrolytic capacitor.
10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 48 thru
Figure 51, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Connect all PGND pins together using copper plane or thick copper traces.
• Connect the SW pins together using a small copper island under the device for thermal relief.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. AGND and PGND are connected internal to the device.
• Place RFBT, RFBB, RRT, and CFF as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
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10.2 Layout Examples
30
Figure 48. Typical Top-Layer Layout
Figure 49. Typical Layer-2 Layout
Figure 50. Typical Layer 3 Layout
Figure 51. Typical Bottom-Layer Layout
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10.3 Theta JA vs PCB Area
The amount of PCB copper effects the thermal performance of the device. Figure 52 shows the effects of copper
area on the junction-to-ambient thermal resistance (RθJA) of the LMZM33604. The junction-to-ambient thermal
resistance is plotted for a 4-layer PCB and a 6-layer PCB with PCB area from 16 cm2 to 100 cm2.
To determine the required copper area for an application:
1. Determine the maximum power dissipation of the device in the application by referencing the power
dissipation graphs in the Typical Characteristics section.
2. Calculate the maximum θJA using Equation 8 and the maximum ambient temperature of the application.
(125ÛC ± TA(max))
(ÛC/W)
JA =
PD(max)
(8)
3. Reference Figure 52 to determine the minimum required PCB area for the application conditions.
20
4-layer PCB
6-layer PCB
Theta JA (°C/W)
18
16
14
12
10
15
30
45
60
PCB Area (cm²)
75
90
105
D027
Figure 52. θJA vs PCB Area
10.4 Package Specifications
Table 9. Package Specifications Table
LMZM33604
Weight
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
VALUE
UNIT
2.0
grams
85.5
MHrs
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10.5 EMI
The LMZM33604 is compliant with EN55011 radiated emissions. Figure 53, Figure 54, and Figure 55 show
typical examples of radiated emissions plots for the LMZM33604. The graphs include the plots of the antenna in
the horizontal and vertical positions.
10.5.1 EMI Plots
EMI plots were measured using the standard LMZM33604EVM with no input filter.
Figure 53. Radiated Emissions 12-V Input, 1.2-V Output, 4-A Load
Figure 54. Radiated Emissions 12-V Input, 3.3-V Output, 4-A Load
32
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EMI (continued)
Figure 55. Radiated Emissions 24-V Input, 5-V Output, 4-A Load
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMZM33604RLXR
B2QFN
RLX
41
500
330.0
32.4
10.45
16.45
4.4
16.0
32.0
Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
38
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZM33604RLXR
B2QFN
RLX
41
500
383.0
353.0
58.0
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20-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
LMZM33604RLXR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
B2QFN
RLX
41
500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
RoHS Exempt
& Green
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
LMZM33604
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
Samples
PACKAGE OUTLINE
RLX0041A
B3QFN - 4.1 mm max height
SCALE 1.000
PLASTIC QUAD FLATPACK - NO LEAD
A
10.15
9.85
B
PIN 1
INDEX AREA
16.15
15.85
0.08 C
C
4.1 MAX
SEATING PLANE
0.05
0.00
2X 6.4
2X 3.55
16X 0.8
(0.27) TYP
2X 1.92 0.05
2X 0.335
2X 1.75 0.05
11
19
41
(0.23) TYP
4X 1.17 0.05
2X 1.1 0.05
2.32
4X 1
40
2X 1.2
2X 1 0.05
39
2.79
1.6
38
2.2
PKG
2X 13.6
33
35
37
32
34
36
2.4
6X 1.44 0.05
3.2
28
1
26X 0.8
PIN 1 ID
31
0.6
0.45
27X
0.4
0.35
0.1
C A B
0.05
52X
6X 1 0.05
2X 2.4
PKG
4223882/A 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RLX0041A
B3QFN - 4.1 mm max height
4X (1.4)
10X (1.7)
(2)
10X (2.4)
(2.8)
10X (3.1)
2X (2.4)
13X (0.7)
(0.4)
0.000 PKG
(0.4)
13X (0.7)
PLASTIC QUAD FLATPACK - NO LEAD
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
4X (0.43)
31
4X (7.96)
(7.85)
28
1
4X (1.17)
32
34
26X (0.8)
6X (6.5)
3X (5.6)
6X (5.5)
36
6X (4.5)
6X (3.5)
6X (2.5)
3X (2.4)
37
35
33
6X (1.44)
6X (1.5)
2X (1.2)
6X (1)
(0.27) TYP
6X (0.5)
0.000 PKG
2X (1.1)
4X (0.825)
(1.2)
(1.6)
2X (1)
(2)
4X (2.375)
3X (0.5)
38
3X (1.5)
40
3X (2.5)
(2.79)
4X (1)
3X (3.5)
3X (3.45)
(3.8)
3X (4.15)
39
3X (4.5)
41
(5.11)
3X (5.5)
2X (1.92)
2X (1.75)
11
52X (0.4)
4X (7.185)
19
(7.85)
27X (0.7)
( 0.2) TYP
VIA
(4.85)
3X (4.98)
(3.1)
2X (3.55)
(3.8)
(2.4)
(1.7)
0.05 MIN
TYP
2X (0.335)
(4.85)
4X (4.5)
16X (0.8)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE: 8X
4223882/A 10/2017
NOTES: (continued)
4. This package designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RLX0041A
B3QFN - 4.1 mm max height
4X (1.4)
(2.4)
(2.4)
0.000
PKG
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.43)
(0.27) TYP
31
4X (1.06)
(7.85)
28
1
32
26X (0.8)
34
36
(5.6)
SOLDER MASK
OPENING
TYP
33
6X (1.3)
37
35
(2.4)
METAL UNDER
SOLDER MASK
TYP
6X
(0.95)
0.000 PKG
2X (1.04)
2X (1.2)
38
(1.6)
40
(2.79)
4X (1)
39
(5.11)
1.72
(3.8)
41
2X 0.95
2X (1.56)
11
19
(7.85)
(4.85)
2X (3.55)
52X (0.4)
2X (0.335)
(4.85)
27X (0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
PADS 1,11,19,28,38 & 39: 90%; PADS 32-37: 86%; PADS 40 & 41: 80%
SCALE: 8X
4223882/A 10/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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