Texas Instruments | TPS27S100x 40-V, 4-A, 80-mΩ Single-Channel High-Side Switch (Rev. B) | Datasheet | Texas Instruments TPS27S100x 40-V, 4-A, 80-mΩ Single-Channel High-Side Switch (Rev. B) Datasheet

Texas Instruments TPS27S100x 40-V, 4-A, 80-mΩ Single-Channel High-Side Switch (Rev. B) Datasheet
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TPS27S100
SLVSE42B – OCTOBER 2017 – REVISED SEPTEMBER 2019
TPS27S100x 40-V, 4-A, 80-mΩ Single-Channel High-Side Switch
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
80-mΩ Single-channel High-side switch with full
diagnostics
– TPS27S100A: Open-drain status output
– TPS27S100B: Current monitor analog output
Wide operating voltage 3.5 V to 40 V
Very-low standby current, <0.5 µA
Operating junction temperature, –40 to 150°C
Input control, 3.3-V and 5-V logic compatible
High-accuracy current monitor, ±30 mA at 1 A
Adjustable current limit (0.5-A to 6-A) with external
resistor, ±20% at 0.5 A
Diagnostic enable function for multiplexing of
MCU, analog or digital interface
Excellent ESD protection on IN and OUT pins
– ±16 kV IEC 61000-4-2 ESD contact discharge
– ±4 kV IEC 61000-4-4 Electrical fast transient
– ±1.0 kV/42 Ω IEC 61000-4-5 Surge
Protection
– Overload and short-circuit-to-GND protection
– Inductive load negative voltage clamp
– Undervoltage lockout (UVLO) protection
– Thermal shutdown and swing with self
recovery
– Loss of GND protection
Diagnostic
– On- and Off-State output Open-Load / short to
supply detection
– Overload and short to ground detection
– Thermal shutdown and swing detection
Thermally-Enhanced 14-Pin PWP or 16-Pin QFN
package
Programmable logic controller
Building automation
Telecom/networks
3 Description
The TPS27S100x is a single-channel, fully-protected,
high-side switch with an integrated NMOS and charge
pump. Full diagnostics and high-accuracy currentmonitor features enable intelligent control of the load.
An adjustable current-limit function greatly improves
the reliability of the whole system. The device
diagnostic reporting has two versions to support both
digital fault status and analog current monitor output.
Accurate current monitor and adjustable current limit
features differentiate it from the market.
Device Information(1)
PART NUMBER
TPS27S100x
PACKAGE
BODY SIZE (NOM)
HTSSOP (14)
4.40 mm × 5.00 mm
QFN (16)
4.00 mm × 3.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
V+
FIELD_POWER
IN
EN
TPS27S100
OUT
A0
DIAG_EN
Fault
Current
Sense
Back-plane
ASIC
Digital
Isolator
FLT
(A version)
IMON
(B version)
µC
TPS27S100
TPS27S100
A1
A7
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS27S100
SLVSE42B – OCTOBER 2017 – REVISED SEPTEMBER 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 6
Timing Requirements – Current Monitor
Characteristics ........................................................... 8
6.7 Switching Characteristics .......................................... 9
6.8 Typical Characteristics ............................................ 11
7
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 23
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application ................................................. 25
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision A (February 2018) to Revision B
Page
•
Added the QFN Package to the Features section ................................................................................................................. 1
•
Added Package QFN (16) and Body Size 4.00 mm × 3.5 mm to the Device Information table ............................................ 1
•
Updated the Typical Application Schematic ........................................................................................................................... 1
•
Added RRK Package to the Pin Out Drawing and Pin Functions table ................................................................................. 3
•
Updated the Specifications Absolute Maximum Ratings table .............................................................................................. 4
•
Changed the Operation junction temperature range MAX from 150°C to 125°C in the Specifications Recommended
Operating Conditions table .................................................................................................................................................... 4
•
Added RRK package to the Specifications Thermal Information table .................................................................................. 4
•
Updated the Operating Current section in the Specifications Electrical Characteristics table ............................................... 4
Changes from Original (October 2017) to Revision A
Page
•
Added footnote 2 and 3 to the Electrical Characteristics table............................................................................................... 4
•
Added reverse current protection information to the Reverse Current Protection section................................................... 22
2
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5 Pin Configuration and Functions
TPS27S100A PWP Package
14-Pin HTSSOP With Exposed Thermal Pad
Top View
FLT
GND
2
13
ILIM
NC
4
11
NC
OUT
IN
OUT
6
9
IN
OUT
7
8
IN
OUT
OUT
IN
ILIM
DIAG_EN
NC
IN
IN
IN
NC – No internal connection
NC – No internal connection
TPS27S100B RRK Package
16-Pin QFN With Exposed Thermal Pad
Top View
12
DIAG_EN
NC
4
11
NC
OUT
5
10
IN
OUT
6
9
IN
OUT
7
8
IN
OUT
OUT
15 14 13 12 11 10
3
9
EN
NC
OUT
16
ILIM
8
13
7
2
EN
6
GND
GND
5
IMON
4
14
3
1
IMON
2
NC
NC
1
TPS27S100B PWP Package
14-Pin HTSSOP With Exposed Thermal Pad
Top View
Tab
9
10
8
5
7
OUT
6
Tab
NC
OUT
5
12
4
3
3
EN
EN
FLT
2
GND
DIAG_EN
NC
15 14 13 12 11 10
14
16
1
1
NC
TPS27S100A RRK Package
16-Pin QFN With Exposed Thermal Pad
Top View
OUT
IN
ILIM
DIAG_EN
NC
IN
IN
IN
NC – No internal connection
NC – No internal connection
Pin Functions
PIN
NAME
TPS27S100
A PWP
TPS27S100 TPS27S100
B PWP
A RRK
TPS27S100B
RRK
I/O
DESCRIPTION
DIAG_EN
12
12
14
14
I
Enable and disable pin for diagnostic functions.
Connect to device GND if not used.
EN
3
3
3
3
I
Enable control for channel activation.
FLT
14
—
16
—
O
Open-drain diagnostic status output. Leave floating
if not used.
GND
2
2
2
2
—
Ground pin.
ILIM
13
13
15
15
O
adjustable current-limit pin. Connect to device GND
if external current limit is not used.
IMON
—
14
—
16
O
Current-monitor output. Leave floating if not used.
9, 10, 11, 12
I
Power supply.
IN
8, 9, 10
8, 9, 10
9, 10, 11,
12
NC
1, 4, 11
1, 4, 11
1, 4, 13
1, 4, 13
—
No-connect pin; leave floating.
OUT
5, 6, 7
5, 6, 7
5, 6, 7, 8
5, 6, 7, 8
O
Output, connected to load.
—
—
—
—
—
Thermal pad. Connect to device GND or leave
floating.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Supply voltage
40
Supply voltage (for transients less than 400 ms)
48
V
V
mA
Current on GND pin, t < 2 minutes
–250
100
Voltage on EN and DIAG_EN pins
–0.3
7
Current on EN and DIAG_EN pins
–10
Voltage on FLT pin
–0.3
7
V
Current on FLT pin
–30
10
mA
Voltage on ILIM pin
–0.3
7
V
Voltage on IMON pin
–2.7
6.5
V
70
mJ
V
mA
Inductive load switch-off energy dissipation, single pulse (3)
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Test condition: VIN = 13.5 V, L = 8 mH, R = 0 Ω, TJ = 150°C. FR4 2s2p board, 2- × 70-μm Cu, 2- × 35-μm Cu. 600-mm2 board copper
area.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM)
(1)
IN, OUT, GND
±5000
Human body model (HBM)
(1)
Other pins
±4000
Charged device model (CDM)
V(ESD)
V(ESD)
Contact/Air discharge, per IEC 61000-4-2
Electrostatic
discharge
(1)
(2)
V
±750
(2)
Electrical fast transient, per IEC 61000-4-4
(2)
Surge protection with 42 Ω, per IEC 61000-4-5; 1.2/50 μs
V(ESD)
UNIT
(2)
IN, OUT
±16000
V
IN, OUT
±4000
V
IN, OUT
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Tested with application circuit shown in Figure 35 with CVIN1= 47 μF, CVIN2= 100 nF, CVOUT= 22 nF and SM15T30A TVS input clamp.
Supply voltage of 24 V DC is always ON, EN Inputs are High, so output is High (ON) and floating (no load).
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
Operating voltage
5
40
UNIT
V
VENx
Voltage on EN and DIAG_EN pins
0
5
V
VFLT
Voltage on FLT pin
0
5
V
IL,nom
Nominal dc load current
0
4
A
TJ
Operating junction temperature range
–40
125
°C
6.4 Thermal Information
TPS27S100x
THERMAL METRIC (1)
PWP (HTSSOP)
RRK (QFN)
14 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
41
42.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.7
31.3
°C/W
RθJB
Junction-to-board thermal resistance
25.1
16.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
TPS27S100x
THERMAL METRIC (1)
PWP (HTSSOP)
RRK (QFN)
14 PINS
16 PINS
UNIT
ψJT
Junction-to-top characterization parameter
0.9
0.4
°C/W
ψJB
Junction-to-board characterization parameter
24.8
16.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
4.6
°C/W
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6.5 Electrical Characteristics
5 V < VIN < 40 V; –40°C < TJ < 150°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
VIN(nom)
Nominal operating voltage
VIN(uvr)
Undervoltage restart
VIN rises up
VIN(uvf)
Undervoltage shutdown
VIN falls down
40
V
3.5
4
3.7
4
V
3
3.2
3.5
V
V(uv,hys)
0.5
V
OPERATING CURRENT
I(op)
Nominal operating current
VEN = 5 V, VDIAG_EN = 0 V, 5 V < VIN < 30 V, no
load; –40°C TJ < 125°C
2.5
3.2
mA
I(op)
Nominal operating current
VEN = 5 V, VDIAG_EN = 0 V, 5 V < VIN < 40 V, no
load; –40°C TJ < 150°C
2.5
5
mA
I(op)
Nominal operating current
VEN = 5 V, VDIAG_EN = 0 V, 24-Ω load
10
mA
I(off)
Standby mode current
VIN = 24 V, VEN = VDIAG_EN = VIMON = VILIM = VOUT =
0 V, TJ = 25°C
2
µA
I(off,diag)
Standby current with diagnostic enabled
1.2
mA
(1)
t(off,deg)
Standby mode deglitch time
Ilkg(out)
Off-state output leakage current
VIN = 24 V, VEN = 0 V, VDIAG_EN = 5 V
EN from high to low, if deglitch time > t(off,deg), the
device enters into standby mode.
2
VIN = 24 V, VEN = VOUT = 0, TJ = 25°C
ms
0.5
µA
POWER STAGE
VIN > 5 V, TJ = 25°C
rDS(on)
On-state resistance
IILIM(int)
Internal current limit
IILIM(TSD)
Current limit during thermal shutdown
VDS(clamp)
Drain-to-source internal clamp voltage
100
mΩ
VIN > 5 V, TJ = 150°C
80
166
mΩ
VIN = 3.5 V, TJ = 25°C
120
mΩ
13
A
Internal current limit value, ILIM pin connected to
GND
7
Internal current limit value under thermal shutdown
5
A
External current limit value under thermal shutdown
as a percentage of the external current limit setting
value
50
%
50
70
V
OUTPUT DIODE CHARACTERISTICS
VF
Drain-to-source diode voltage
VEN = 0, IOUT = −0.2 A
0.7
V
I(R1)
Continuous reverse current from source to
drain
t < 60 s, VEN = 0, TJ = 25°C. Short-to-supply
condition.
2
A
I(R2)
Continuous reverse current from source to
drain
t < 60 s, VEN = 0, TJ = 25°C. With GND network, 1kΩ resistor in parallel with A diode. Reverse-polarity
condition.
3
A
LOGIC INPUT (EN AND DIAG_EN)
VIH
Logic high-level voltage
VIL
Logic low-level voltage
R(EN,pd)
EN pulldown resistor
500
kΩ
R(DIAG,pd)
DIAG_EN pulldown resistor
150
kΩ
(1)
6
2
V
0.8
V
Value is specified by design, not subject to production test.
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Electrical Characteristics (continued)
5 V < VIN < 40 V; –40°C < TJ < 150°C unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.4
1.8
2.6
UNIT
DIAGNOSTICS
V(ol,off)
Open-load detection threshold in off-state
VEN = 0 V, When VIN – VOUT < V(ol,off), duration
longer than td(ol,off). Open load detected.
I(ol,off)
Off-state output sink current with open
load
VEN = 0 V, VIN = VOUT = 24 V, TJ = 125°C.
td(ol,off)
Open-load detection-threshold deglitch
time in off state
VEN = 0 V, When VIN – VOUT < Vol,off, duration longer
than tol,off. Open load detected.
I(ol,on)
Open-load detection threshold in on state
VEN = 5 V, when IOUT < I(ol,on), duration longer than
td(ol,on). Open load detected.
Version A only
td(ol,on)
Open-load detection-threshold deglitch
time in on-state
VEN = 5 V, when IOUT < I(ol,on), duration longer than
td(ol,on). Open load detected.
V(FLT)
Fault low output voltage
IFLT = 2 mA
T(SD)
Thermal shutdown threshold
175
°C
T(SD,rst)
Thermal shutdown status reset
155
°C
T(SW)
Thermal swing shutdown threshold
60
°C
T(hys)
Hysteresis for resetting the thermal
shutdown and swing
10
°C
–150
V
µA
600
2
6
µs
10
700
mA
µs
0.4
V
CURRENT MONITOR AND CURRENT LIMIT
K(IMON)
Current sense current ratio
K(ILIM)
Current limit current ratio
dK(IMON)/K(IMON)
500
2000
Current-monitor accuracy
Iload ≥ 5 mA
–80
80
Iload ≥ 25 mA
–12
12
Iload ≥ 50 mA
–8
8
Iload ≥ 0.1 A
–5
5
Iload ≥ 1 A
dK(ILIM)/K(ILIM)
External current-limit accuracy (2),
(3)
–3
3
Ilimit ≥ 0.5 A, 25°C < TJ < 150°C
–20
20
%
Ilimit ≥ 0.5 A, -40°C < TJ < 25°C
–28
28
%
Ilimit ≥ 1.6 A, 25°C < TJ < 150°C
–15
15
Ilimit ≥ 1.6 A, -40°C < TJ < 25°C
–18
18
dK(ILIM)/K(ILIM)
External current-limit accuracy (2),
VIMON(lin)
Current-monitor voltage linear voltage
range (1)
VIN ≥ 5 V
0
4
V
IOUT(lin)
Current-monitor voltage linear current
range (1)
VIN ≥ 5 V, VIMON(lin) ≤ 4 V
0
4
A
VIMON(H)
IMON pin voltage in Fault mode
IIMON(H)
IMON pin current in Fault mode
VIMON(th)
Current limit internal threshold voltage (1)
(2)
(3)
(3)
%
VIN ≥ 7 V, fault mode
4.3
VIN ≥ 5 V, fault mode
Min(VIN –
0.8, 4.3)
VIMON = 4.3 V, VIN > 7 V, fault mode
4.75
%
4.9
4.9
10
V
mA
1.233
V
External current limit set is recommended to be higher than 500 mA.
External current limit accuracy is only applicable to overload conditions greater than 1.5 x the current limit setting.
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6.6 Timing Requirements – Current Monitor Characteristics (1)
MIN
NOM
MAX
UNIT
tIMON(off1)
IMON settling time from
VEN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 5 to 0 V. IMON to 10% of sense value.
DIAG_EN disabled
10
µs
tIMON(on1)
IMON settling time from
VEN = 5 V, Iload ≥ 5 mA. VDIAG_EN from 0 to 5 V. IMON to 90% of sense value.
DIAG_EN enabled
10
µs
tIMON(off2)
IMON settling time from VDIAG_EN = 5 V, Iload ≥ 5 mA. EN from 5 to 0 V. IMON to 10% of sense value.
EN falling edge
VDIAG_EN = 5 V, Iload ≥ 5 mA. EN from 5 to 0 V. Current limit triggered.
10
µs
180
µs
tIMON(on2)
IMON settling time from VIN = 24 V, VDIAG_EN = 5 V, Iload ≥ 100 mA. VEN from 0 to 5 V. IMON to 90%
EN rising edge
of sense value.
150
µs
(1)
8
Value specified by design, not subject to production test.
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6.7 Switching Characteristics
VIN = 24 V, Rload = 24 Ω, over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(on)
Turn-on delay time
EN rising edge to VOUT = 10%, DIAG_EN high
20
50
td(off)
Turn-off delay time
EN falling edge to VOUT = 90%, DIAG_EN high
40
80
µs
dV/dt(on)
Slew rate on
VOUT = 10% to 90%, DIAG_EN high
0.1
0.5
V/µs
dV/dt(off)
Slew rate off
VOUT = 90% to 10%, DIAG_EN high
0.1
0.5
V/µs
(1)
µs
Value specified by design, not subject to production test.
Figure 1. Pin Current and Voltage Conventions
VEN
90%
VOUT
td(on)
10%
90%
dV/dt(off)
dV/dt(on)
10%
td(off)
Figure 2. Output Delay Characteristics
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VEN
IOUT
VDIAG_EN
VIMON
tIMON(on2) tIMON(off1)
tIMON(on1) tIMON(off2)
Figure 3. Current sense Delay Characteristics
Open
Load
Open Load
EN
VIMON(H)
IMON
td(ol,off)
FLT
td(ol,on)
td(ol,off)
Figure 4. Open Load Blanking Time Characteristics
10
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6.8 Typical Characteristics
All the below data are based on the mean value of the three lots samples, VIN = 24 V if not specified.
10
4
Inom (no load)
Inom (24-O load)
Vs,uvr
Vs,uvf
8
Current (mA)
Voltage (V)
3.8
3.6
3.4
4
2
3.2
3
-40
6
-15
10
35
60
Temperature (°C)
85
0
-40
110 125
1.2
35
60
Temperature (qC)
85
110 125
D002
1.8
1
1.6
0.8
1.4
Voltage (V)
Current (mA)
10
Figure 6. Inom With No Load and 24-Ω Load
Figure 5. IN Pin Undervoltage Rising and Falling Thresholds
VIN,UVR and VIN,UVF
0.6
1
0.2
0.8
-15
10
35
60
Temperature (qC)
85
110 125
Vlogic,h
Vlogic,l
1.2
0.4
0
-40
-15
D001
0.6
-40
D004
Figure 7. Ioff,diag as a Function of Temperature
-15
10
35
60
Temperature (°C)
85
110 125
Figure 8. Vlogic,h and Vlogic,l
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Typical Characteristics (continued)
All the below data are based on the mean value of the three lots samples, VIN = 24 V if not specified.
0.9
65
0.8
Voltage (V)
Voltage (V)
60
0.7
55
0.6
0.5
-40
-15
10
35
60
Temperature (qC)
85
50
-40
110 125
-15
10
D006
Figure 9. Drain-to-source Diode Voltage VF
Figure 10. VDS,
130
Rdson_3P5V
Rdson_5V
Rdson_13P5
Rdson_40V
110 125
D007
Clamp
10.5
100
85
10
9.5
70
55
-40
85
11
Current (A)
Resistance (mO)
115
35
60
Temperature (°C)
-15
10
35
60
Temperature (qC)
85
9
-40
110 125
-15
10
D008
Figure 11. FET RDSON
35
60
Temperature (qC)
85
110 125
D009
Figure 12. Current Limit Ilim,nom
70
0.44
65
0.42
60
Slew Rate (V/PS)
Time (Ps)
55
50
45
40
35
0.4
0.38
0.36
0.34
30
25
20
-40
0.32
TD_On
TD_Off
-15
10
35
60
Temperature (qC)
85
110 125
0.3
-40
D010
Figure 13. TDon and TDoff
12
dV/dtON
dV/dtOFF
-15
10
35
60
Temperature (qC)
85
110 125
D011
Figure 14. dV/dtON and dV/dtOFF
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Typical Characteristics (continued)
All the below data are based on the mean value of the three lots samples, VIN = 24 V if not specified.
1.95
9
1.9
Current (mA)
Voltage (V)
8
1.85
1.8
7
6
1.75
1.7
-40
-15
10
35
60
Temperature (qC)
85
110 125
5
-40
-15
D013
Figure 15. Vol,off
10
35
60
Temperature (°C)
85
110 125
D014
Figure 16. Iol,on
10%
20%
8%
15%
6%
10%
4%
5%
2%
0
0
-2%
-5%
-4%
-10%
-6%
-15%
-20%
-40
-8%
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
-10%
-40
10%
1.5%
8%
1.25%
6%
1%
4%
0.75%
2%
0.5%
0
0.25%
-2%
0
-4%
-0.25%
-6%
-0.5%
-8%
-20
0
20
40
60
80
Temperature (qC)
100
120
140
-10%
-40
-10
D019
Figure 19. K(IMON) at IOUT = 50 mA, VIN = 24 V
20
50
Temperature (qC)
80
110 125
D017
Figure 18. K(IMON) at IOUT = 25 mA, VIN = 24 V
Figure 17. K(IMON) at IOUT = 5 mA, VIN = 24 V
1.75%
-0.75%
-40
-10
D015
20
50
Temperature (°C)
80
110 125
D016
Figure 20. K(IMON) at IOUT = 100 mA, VIN = 24 V
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Typical Characteristics (continued)
All the below data are based on the mean value of the three lots samples, VIN = 24 V if not specified.
10%
3%
8%
2.5%
2%
6%
1.5%
4%
1%
2%
0.5%
0
0
-2%
-0.5%
-4%
-1%
-6%
-1.5%
-8%
-10%
-40
-2%
-10
20
50
Temperature (°C)
80
110 125
-2.5%
-40
-10
D018
Figure 21. K(IMON) at IOUT = 1 A, VIN = 24 V
20
50
Temperature (qC)
80
110 125
D020
Figure 22. K(ILIM) at IILIM = 0.5 A, VIN = 24 V
10%
8%
6%
4%
2%
0
-2%
-4%
-6%
-8%
-10%
-40
-10
20
50
Temperature (°C)
80
110 125
D021
Figure 23. K(ILIM) at IILIM = 1.6 A, VIN = 24 V
14
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7 Detailed Description
7.1 Overview
The TPS27S100x is a single-channel, fully-protected, high-side switch with an integrated NMOS and charge
pump. Full diagnostics and high-accuracy current-monitor features enable intelligent control of the load. An
adjustable current-limit function greatly improves the reliability of the whole system. The device diagnostic
reporting has two versions to support both digital fault status and analog current monitor output.
For TPS27S100A, the digital fault status report is implemented with an open-drain structure. For TPS27S100B,
high-accuracy current-monitor allows a better real-time monitoring effect and more-accurate diagnostics without
further calibration. A current mirror is used to source a fraction ( 1 / K(IMON)) of the load current. K(IMON) is a nearly
constant value across the temperature and supply voltage.
The external high-accuracy current limit allows setting the current limit value by application. Under start-up or
short-circuit conditions, it improves the reliability of the system significantly by clamping the inrush current
effectively. It can also save system costs by reducing PCB trace, connector size, and the preceding power-stage
capacity. An internal current limit is also implemented in this device. The lower value of the external or internal
current-limit value is applied.
An active drain to source voltage clamp is built in to address switching off the energy of inductive loads, such as
relays, solenoids, motors, and so forth. During switching-off cycle, both the energy of the power supply and the
inductive load are dissipated on the device itself. See Inductive-Load Switching-Off Clamp for more details.
The TPS27S100x device can be used as a high-side switch to drive a wide variety of resistive, inductive, and
capacitive loads.
7.2 Functional Block Diagram
IN
Internal LDO
Charge Pump
VDS Clamp
Internal Reference
EN
Gate Driver
DIAG_EN
FLT
Diagnostics
& Protection
Open Load
Detection
Current Limit
ILIM
Thermal Monitor
Current Sense
OUT
IMON
GND
7.3 Feature Description
7.3.1 Accurate Current Monitor
For TPS27S100B, the high-accuracy current-monitor function is internally implemented, which allows a better
real-time monitoring effect. A current mirror is used to source 1 / KIMON of the load current, flowing out to the
external resistor between the IMON and GND.
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Feature Description (continued)
KIMON is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage range. Each part is factory calibrated during production test, so user-calibration is not required in
most cases.
IN
IOUT/
K(IMON)
IOUT
VIMON(H)
OUT
FAULT
IMON
RIMON
Figure 24. Current-monitor Block Diagram
When a fault occurs, the IMON pin also works as a fault report with a pullup voltage, VIMON(H).
VIMON
VIMON(H)
VIMON(lin)
Fault report
Normal Operating
IOUT
On-state: current limit, thermal fault
Off-state: open load/ short to supply
On-state: open load/ short to supply
Figure 25. IMON Output-Voltage Curve
Use Equation 1 to calculate RIMON. Also, please ensure VIMON is within the current-sense linear region VIMON(lin)
across the full range of the load current.
R IMON
16
VIMON
I IMON
VIMON u K (IMON)
I OUT
(1)
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Feature Description (continued)
7.3.2 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
over-stressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When the current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to IILIM(TSD) to reduce the power dissipation on the power FET.
The device has two current-limit thresholds.
Internal current limit – The internal current limit is fixed at IILM(int). Tie the ILIM pin directly to the device GND for
large-transient-current applications.
External adjustable current limit – An external resistor is used to set the current-limit threshold. Use Equation 2
below to calculate the RILIM. VILIM(th) is the internal band-gap voltage. K(ILIM) is the ratio of the output current and
the current-limit set value. It is constant across the temperature and supply voltage. The external adjustable
current limit allows the flexibility to set the current limit value by applications.
R ILIM
VIILM(th) ˜ K (ILIM)
I OUT
(2)
Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the
ILIM pin must be connected with device GND.
IN
IOUT/
K(ILIM)
Internal Current Limit
VILIM(th)
+
+
+
IOUT
OUT
External Current Limit
VILIM(th)
+
ILIM
Figure 26. Current-Limit Block Diagram
For better protection from a hard short-to-GND condition (when the EN pin is enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the channel before the current-limit closed loop
is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device can achieve
better inrush current-suppression performance.
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Feature Description (continued)
7.3.3 Inductive-Load Switching-Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp).
IN
VDS(clam
p)
L
OUT
R
GND
+
Figure 27. Drain-to-Source Clamping Structure
EN
VIN
VOUT
VDS(clamp)
IOUT
t(decay)
Figure 28. Inductive-Load Switching-Off Diagram
7.3.4 Full Protections and Diagnostics
Table 1 is when DIAG_EN enabled. When DIAG_EN is low, all the diagnostics is disabled accordingly. The
output is in high-impedance mode. Refer to Table 2 for details.
Table 1. Fault Table
CONDITIONS
Normal
Short to GND
18
IN
OUT
CRITERION
FLT
(TPS27S100A)
IMON
(TPS27S100B)
L
L
H
0
H
H
H
In linear region
H
L
L
VIMON(H)
Current limit triggered.
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FAULT RECOVERY
AUTO
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Feature Description (continued)
Table 1. Fault Table (continued)
CONDITIONS
IN
OUT
CRITERION
FLT
(TPS27S100A)
IMON
(TPS27S100B)
FAULT RECOVERY
Open load (1)
Short to supply
H
H
TPS27S100A: IOUT< I(ol,on)
TPS27S100B: Judged by users
L
Almost 0
AUTO
L
H
VIN – VOUT < V(ol,off)
L
VIMON(H)
AUTO
Thermal shutdown
H
TSD triggered
L
VIMON(H)
Recovery when TJ <
T(SD,rst)or when EN
toggles.
Thermal swing
H
TSW triggered
L
VIMON(H)
AUTO
(1)
Need external pull-up resistor during off-state
Table 2. DIAG_EN Logic Table
DIAG_EN
HIGH
EN
PROTECTIONS AND DIAGNOSTICS
ON
See Table 1
OFF
See Table 1
ON
Diagnostics disabled, protection normal
IMON or FLT is high Impedance
OFF
Diagnostics disabled, no protections
IMON or FLT is high impedance
LOW
7.3.4.1 Short-to-GND and Overload Detection
When the switch is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is IILIM(TSD)to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.
7.3.4.2 Open-Load Detection
When the channel is on, for TPS27S100A, if the current flowing through the output is less than I(ol,on), the device
recognizes an open-load fault. For TPS27S100B, if an open-load event occurs, it can be detected as an ultra-low
VIMON and handled by the microcontroller.
When the channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VIN – VOUT < V(ol,off)), and the fault is reported out.
There is always a leakage current I(ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 15 kΩ.
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Open Load Detection in Off-State
V(ol,off)
R(pullup)
Vds
Load
Figure 29. Open-Load Detection Circuit in Off-State
7.3.4.3 Short-to-Supply Detection
Short-to-Supply has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See Table 1 for more details.
7.3.4.4 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thermal shutdown occurs, the
respective output turns off.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET) –
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). Thermal swing function improves the device reliability when subjected to repetitive
fast thermal variation.
20
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Thermal behaviors after Short to GND
EN
T(SD)
TJ
T(hys)
T(SD,rst)
T(hys)
T(SW)
IILIM
IILIM(TSD)
IOUT
VILM(H)
VILM
FLT
Figure 30. Thermal Behavior Diagram
7.3.4.5 UVLO Protection
The device monitors the supply voltage VIN, to prevent unpredicted behaviors when VIN is too low. When VIN falls
down to VIN(uvf), the device shuts down. When VIN rises up to VIN(uvr), the device turns on.
7.3.4.6 Loss of GND Protection
When loss of GND occurs, output is shut down regardless of whether the EN pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
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7.3.4.7 Reverse Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
● When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the limit
of the reverse current.
● In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin. IR(2)
specifies the limit of the reverse current.
To protect the device, TI recommends two types of external circuitry.
● Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
Load
Figure 31. Reverse-Current External Protection, Method 1
● Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network. The
recommended selection are 1-kΩ resistor in parallel with an >100-mA diode. The reverse current protection diode
in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a minimum
resistance of 4.7 K is recommended on the I/O pins.
22
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Load
Figure 32. Reverse-Current External Protection, Method 2
7.3.4.8 Protection for MCU I/Os
TI recommends serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
IOs
MCU
High Side Switch
Load
Figure 33. MCU I/O External Protection
7.4 Device Functional Modes
7.4.1 Working Mode
The device has three working modes: the normal mode, the standby mode, and the standby mode with
diagnostics.
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Device Functional Modes (continued)
Standby Mode
(EN low, DIAG_EN low)
DIAG_EN high to low
EN low to high
DIAG_EN low
AND
EN high to low
AND
t > t(off,deg)
DIAG_EN low to high
Standby Mode
With DIAG
(EN low, DIAG_EN high)
EN low to high
Normal Mode
(EN high)
EN high to low
AND
DIAG_EN high
AND
t > t(off,deg)
Figure 34. Working Modes
24
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is capable of driving a wide variety of resistive, inductive, and capacitive loads. Full diagnostics and
high accuracy current-monitor features enable intelligent control of the load. An external adjustable current limit
improves the reliability of the whole system by clamping the inrush or overload current.
8.2 Typical Application
Figure 35 shows an example of how to design the external circuitry parameters.
CVIN1
CVIN2
3.5 V to 40 V
Supply Voltage
D_TVS
IN
RSER
EN
RSER
DIAG_EN
OUT
3.3 / 5 V
MCU
RSER
CVOUT
General Resistive,
Capacitive, Inductive
Loads
Rpullup
FLT (TPS27S100A)
IMON (TPS27S100B)
RIMON
ILIM
GND
GND
RILIM
GND
Figure 35. Typical Application Circuitry
Table 3. Recommended External Components
COMPONENT
TYPICAL VALUE
RSER
15 kΩ
Protect microcontroller and device I/O pins
RIMON
1 kΩ
Translate the sense current into sense voltage
CSNS
100 pF - 10 nF
RILIM
0.82 kΩ
CVIN1/2
PURPOSE
Low-pass filter for the ADC input
Set current limit threshold
4.7 nF to Device GND
Filtering of high frequency noise
220 nF to Module GND
Stabilize the input supply and voltage spike suppression for surge transient
immunity.
COUT
22 nF
DTVS
36V TVS diode
Immunity to ESD
Transient voltage clamp for surge transient immunity
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8.2.1 Design Requirements
• VIN range from 9 V to 30 V
• Nominal current of 2 A
• Current Monitor for fault monitoring
• Expected current limit value of 5 A
• Full diagnostics with 5-V MCU
8.2.2 Detailed Design Procedure
To keep the 2-A nominal current in the 0 to 4-V current-sense range, calculate the RIMON resistor using Equation
3. To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
R IMON
VIMON u K (IMON)
I OUT
4 u 500
2
1000
(3)
To set the adjustable current limit value at 5-A, calculate RILIM using Equation 4.
R ILIM
VLIM(th) ˜ K (ILIM)
I OUT
1.233 ˜ 2000
5
493.2
(4)
TI recommends RSER = 10 kΩ for 5-V MCU, and Rpullup = 10 kΩ as the pull-up resistor.
8.2.3 Application Curves
Figure 36 shows a an example of initial inrush or short-circuit current limit. Test conditions: EN is from low to
high, load is resistive short-to-GND or with a 470-µF capacitive load, external current limit is 2 A. CH1 is the
output current. CH3 is the EN step.
Figure 37 shows an example of current limit during hard short-circuit. Test conditions: EN is high, load is (5 µH +
100 mΩ), external current limit is 1 A. A short to GND suddenly happens.
Figure 36. Initial Short-to-GND Waveform
26
Figure 37. Hard Short-to-GND Waveform
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9 Power Supply Recommendations
The device is qualified for both 12-V and 24-V applications. The typical power input is a 12-V or 24-V industrial
power supply.
10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. If the output current is very high, the power
dissipation may be large. The HTSSOP package has good thermal impedance. However, the PCB layout is very
important. Good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability
of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heatflow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the board opposite the
package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
10.2 Layout Example
10.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
NC
1
14
FLT/IMON
GND
2
13
ILIM
EN
3
12
DIAG_EN
NC
4
11
NC
OUT
5
10
IN
OUT
6
9
IN
OUT
7
8
IN
Thermal
Pad
Figure 38. Layout Without a GND Network
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Layout Example (continued)
10.2.2 With a GND Network
With a GND network, tie the thermal pad with a single trace through the GND network to the board GND copper.
GND Network
1
14
FLT/IMON
2
13
ILIM
EN
3
12
DIAG_EN
NC
4
11
NC
OUT
5
10
IN
OUT
6
9
IN
OUT
7
8
IN
NC
GND
Thermal
Pad
Figure 39. Layout With a GND Network
28
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
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from the experts. Search existing answers or ask your own question to get the quick design help you need.
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11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TPS27S100
29
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS27S100APWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
27S1A
TPS27S100APWPT
ACTIVE
HTSSOP
PWP
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
27S1A
TPS27S100ARRKR
ACTIVE
WQFN
RRK
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
27S100A
TPS27S100ARRKT
ACTIVE
WQFN
RRK
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
27S100A
TPS27S100BPWPR
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
27S1B
TPS27S100BPWPT
ACTIVE
HTSSOP
PWP
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
27S1B
TPS27S100BRRKR
ACTIVE
WQFN
RRK
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
27S100B
TPS27S100BRRKT
ACTIVE
WQFN
RRK
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
27S100B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS27S100APWPR
HTSSOP
PWP
14
2000
330.0
12.4
TPS27S100APWPT
HTSSOP
PWP
14
250
180.0
TPS27S100ARRKR
WQFN
RRK
16
3000
330.0
TPS27S100ARRKT
WQFN
RRK
16
250
TPS27S100BPWPR
HTSSOP
PWP
14
TPS27S100BPWPT
HTSSOP
PWP
TPS27S100BRRKR
WQFN
RRK
TPS27S100BRRKT
WQFN
RRK
6.9
5.6
1.6
8.0
12.0
Q1
12.4
6.9
5.6
1.6
8.0
12.0
Q1
12.4
3.8
4.3
1.5
8.0
12.0
Q1
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
16
250
180.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS27S100APWPR
HTSSOP
PWP
14
2000
350.0
350.0
43.0
TPS27S100APWPT
HTSSOP
PWP
14
250
210.0
185.0
35.0
TPS27S100ARRKR
WQFN
RRK
16
3000
367.0
367.0
35.0
TPS27S100ARRKT
WQFN
RRK
16
250
210.0
185.0
35.0
TPS27S100BPWPR
HTSSOP
PWP
14
2000
350.0
350.0
43.0
TPS27S100BPWPT
HTSSOP
PWP
14
250
210.0
185.0
35.0
TPS27S100BRRKR
WQFN
RRK
16
3000
367.0
367.0
35.0
TPS27S100BRRKT
WQFN
RRK
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
RRK0016A
PLASTIC QUAD FLATPACK- NO LEAD
3.65
3.35
B
A
4.15
3.85
PIN 1 INDEX AREA
C
0.8
0.7
SEATING PLANE
0.05
0.00
0.08 C
2.05±0.1
2X 1.5
8
(0.1) TYP
9
(0.2)MIN
10X 0.5
2X 2.5
7
10
PKG
0.21±0.1
17
15
2
PIN 1 ID
(OPTIONAL)
1
PKG
16
16X 0.29
0.19
0.1
0.05
C A B
C
16X0.5
0.3
4424663 / A 11/2018
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RRK0016A
PLASTIC QUAD FLATPACK- NO LEAD
(2.05)
2X(1.5)
1
16
16X (0.6)
PKG
15
2
16X (0.24)
(1.025)
10X (0.5)
PKG
(2.55)
(3.8)
17
(Ø0.2) VIA
(TYP)
7
10
(R0.05) TYP
9
8
(0.775)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4424663 / A 11/2018
NOTES: (continued)
3.
4.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RRK0016A
PLASTIC QUAD FLATPACK- NO LEAD
2X(1.5)
(R0.05) TYP
0.56
1
16
16X (0.6)
2
15
16X (0.24)
10X (0.5)
(0.67)
PKG
(3.8)
17
4X(1.13)
7
10
PKG
EXPOSED METAL
8
9
4X(0.92)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 17: 79%
SCALE: 20X
4424663 / A 11/2018
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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