Texas Instruments | bq29209-Q1 Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries (Rev. B) | Datasheet | Texas Instruments BQ29209-Q1 Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries (Rev. C) Datasheet

Texas Instruments BQ29209-Q1 Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries (Rev. C) Datasheet
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BQ29209-Q1
SLUSC62C – JUNE 2015 – REVISED MAY 2019
BQ29209-Q1 Voltage Protection with Automatic Cell Balance
for 2-Series Cell Li-Ion Batteries
1 Features
3 Description
•
•
The BQ29209-Q1 device is a secondary overvoltage
protection IC for 2-series cell lithium-ion battery packs
that
incorporates
a
high-accuracy
precision
overvoltage detection circuit and automatic cell
imbalance correction.
1
•
•
•
•
•
•
•
•
•
2-series cell secondary protection
Automatic cell imbalance correction with external
enable control
– ±30-mV enable, 0-mV disable thresholds
typical
External capacitor-controlled delay timer
External resistor-controlled cell balance current
Low power consumption ICC < 3 µA typical
(VCELL(ALL) < VPROTECT)
Internal cell balancing handles current
up to 15 mA
External cell balancing mode supported
High-accuracy overvoltage protection:
– ±25 mV with TA = 0°C to 60°C
Fixed overvoltage protection threshold:
4.30 V
Small 8L DRB package
Automotive-qualified AEC Q100 grade two
The voltage of each cell in a 2-series cell battery
pack is compared to a factory programmed internal
reference voltage. If either cell reaches an
overvoltage condition, the OUT pin changes from low
to high state.
The BQ29209-Q1 can perform automatic voltagebased cell imbalance correction. Balancing can start
when the cell voltages are different by nominally
30 mV or more and stops when the difference is
nominally 0 mV. Cell balancing is enabled and
disabled by the CB_EN pin.
Device Information(1)
PART NUMBER
BQ29209-Q1
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
VSON (8)
2nd level protection in li-ion battery packs
– Emergency call (eCall)
– Netbook computers
– Power tools
– Portable equipment and instrumentation
– Battery backup systems
Simplified Schematic
PACK+
RIN2
CELL2
CIN
RIN1
CIN
1 VC2
OUT 8
2 VC1
VDD 7
3 VC1_CB
CELL1
RCBext
4 CD
RVD
CB_EN 6
GND 5
CVD
PWR PAD
CCD
PACK-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ29209-Q1
SLUSC62C – JUNE 2015 – REVISED MAY 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
3
4
4
4
4
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Recommended Cell Balancing Configurations .........
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
9.3 System Example ..................................................... 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1 Receiving Notification of Documentation Updates
.................................................................................16
12.2 Community Resources.......................................... 16
12.3 Trademarks ........................................................... 16
12.4 Electrostatic Discharge Caution ............................ 16
12.5 Glossary ................................................................ 16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision B (November 2018) to Revision C
•
Page
Added a clarification regarding operation if GND is not connected first in sequence ............................................................ 8
Changes from Revision A (March 2016) to Revision B
Page
•
Changed component names in the Simplified Schematic ..................................................................................................... 1
•
Changed a component name in Recommended Operating Conditions ................................................................................. 4
•
Added the value of internal cell balancing switch resistances to Electrical Characteristics................................................... 5
•
Changed resistor names ....................................................................................................................................................... 6
•
Added Figure 5 to clarify the cell balancing description; updated the equations .................................................................. 9
•
Changed values and component names in Figure 10.......................................................................................................... 12
•
Changed component names and values used in the design example ................................................................................ 12
•
Changed external cell balancing figure, equations, and description .................................................................................... 13
Changes from Original (June 2015) to Revision A
Page
•
Changed resistor RVD location, added PACK+ and PACK– in the Simplified Schematic ..................................................... 1
•
Deleted the Lead Temperature (soldering) from the Absolute Maximum Ratings table ....................................................... 3
•
Changed resistor RVD location in Figure 10 ......................................................................................................................... 12
•
Added title to Table 1............................................................................................................................................................ 12
•
Changed resistor RVD location, added PACK+ and PACK– in Figure 12 ............................................................................ 14
2
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5 Device Options
TA
PART NUMBER
OVP
–40°C to +105°C
BQ29209-Q1
4.3 V
6 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
VC2
1
VC1
2
8
OUT
7
VDD
PWR PAD
VC1_CB
3
6
CB_EN
CD
4
5
GND
Pin Functions
PIN
DESCRIPTION
NAME
NO.
CB_EN
6
Cell balance enable
CD
4
Connection to external capacitor for programmable delay time
GND
5
Ground pin
OUT
8
Output
Thermal Pad
PWR PAD
VC1
2
Sense voltage input for bottom cell
VC1_CB
3
Cell balance input for bottom cell
VC2
1
Sense voltage input for top cell
VDD
7
Power supply
GND pin to be connected to the PWRPAD on the printed circuit board for proper operation
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range, VMAX
Input voltage range, VIN
Output voltage range, VOUT
MIN
MAX
UNIT
VDD–GND
–0.3
16
V
VC2–GND, VC1–GND
–0.3
16
V
VC2–VC1, CD–GND
–0.3
8
V
CB_EN–GND
–0.3
16
V
OUT–GND
–0.3
16
V
Continuous total power dissipation, PTOT
See Thermal Information.
Storage temperature, Tstg
(1)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (VC2, CD,
OUT, and GND)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
Supply voltage, VDD
NOM
MAX
UNIT
4
10
V
0
5
V
Input voltage range
VC2–VC1, VC1–GND
Delay time capacitance, td(CD)
CCD (See Figure 10.)
Voltage monitor filter resistance
RIN (See Figure 10.)
100
1K
Ω
Voltage monitor filter capacitance
CIN (See Figure 10.)
0.01
0.1
µF
Supply voltage filter resistance
RVD (See Figure 10.)
100
Supply voltage filter capacitance
CVD (See Figure 10.)
0.1
Cell balance resistance
RCBext (See Figure 10 and Protection (OUT) Timing.)
0.1
Operating ambient temperature range, TA
µF
1K
Ω
µF
100
4.7K
Ω
–40
105
°C
7.4 Thermal Information
BQ29209-Q1
THERMAL METRIC (1)
DRB
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
50.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
25.1
°C/W
RθJB
Junction-to-board thermal resistance
19.3
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
18.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
5.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 105°C
and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
VPROTECT
Overvoltage detection
voltage
VHYS
Overvoltage detection
hysteresis
VOA
Overvoltage detection
accuracy
VOA_DRIFT
Overvoltage threshold
temperature drift
XDELAY
Overvoltage delay time
scale factor
4
TEST CONDITIONS
MIN
TYP MAX
4.3
200
300
V
400
mV
mV
TA = 25°C
–10
10
TA = 0°C to 60°C
–0.4
0.4
TA = –40°C to 110°C
–0.6
0.6
TA = 0°C to 60°C
Note: Does not include external capacitor variation.
6
9
12
TA = –40°C to 110°C
Note: Does not include external capacitor variation.
5.5
9
13.5
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UNIT
mV°/C
s/µF
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Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 105°C
and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
TYP MAX
UNIT
XDELAY_CTM (1)
Overvoltage delay time
scale factor in Customer
Test Mode
TEST CONDITIONS
MIN
0.08
s/µF
ICD(CHG)
Overvoltage detection
charging current
150
nA
ICD(DSG)
Overvoltage detection
discharging current
60
µA
VCD
Overvoltage detection
external capacitor
comparator threshold
1.2
V
ICC
Supply current
(VC2–VC1) = (VC1–GND) = 3.5 V (See Figure 8.)
(VC2–VC1) or (VC1–GND) > VPROTECT,
VDD = 10 V, IOH = 0
(VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT,
IOH = –100 µA, TA = 0°C to 60°C
VOUT
OUT pin drive voltage
3
6
µA
6
8.25
9.5
V
1.75
2.5
(VC2–VC1) and (VC1–GND) < VPROTECT ,
IOL = 100 µA, TA = 25°C
(VC2–VC1) and (VC1–GND) < VPROTECT ,
IOL = 0 µA, TA = 25°C
0
VC2 = VC1 = VDD = 4 V, IOL = 100 µA
IOH
High-level output current
OUT = 1.75 V, (VC2–VC1) or (VC1–GND) = VPROTECT, VDD
= VPROTECT to 10 V, TA = 0°C to 60°C
IOL
Low-level output current
OUT = 0.05 V, (VC2–VC1) or (VC1–GND) < VPROTECT, VDD
= VPROTECT to 10 V, TA = 0°C to 60°C
IOH_ZV
High-level short-circuit
output current
OUT = 0 V, (VC2–VC1) = (VC1–GND) = VPROTECT
VDD = 4 to 10 V
IIN
Input current at VCx pins
Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V,
TA = 0°C to 60°C (See Figure 8.)
–100
30
V
200
mV
10
mV
200
mV
µA
–0.2
Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V,
TA = 0°C to 60°C (See Figure 8.)
85
µA
–8
mA
0.2
µA
2.5
µA
VMM_DET_ON
Cell mismatch detection
threshold for turning ON
(VC2–VC1) versus (VC1–GND) and vice-versa when cell
balancing is enabled. VC2 = VDD = 7.6 V
17
30
45
mV
VMM_DET_OFF
Cell mismatch detection
threshold for turning OFF
Delta between (VC2–VC1) and (VC1–GND) when cell
balancing is disabled. VC2 = VDD = 7.6 V
–9
0
9
mV
VCB_EN_ON
Cell balance enable ON
threshold
Active LOW pin at CB_EN
1
V
VCB_EN_OFF
Cell balance enable OFF
threshold
Active HIGH at CB_EN
ICB_EN
Cell balance enable ON
input current
CB_EN = GND (See Figure 9.)
RCB1int
Internal cell balance
switch resistance
CB_EN = GND
300
Ω
RCB2int
Internal cell balance
switch resistance
CB_EN = GND
235
Ω
(1)
2.2
V
0.2
µA
Specified by design. Not 100% tested in production.
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7.6 Recommended Cell Balancing Configurations
Typical values stated where TA = 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Minimum and maximum values stated where
TA = –40°C to 105°C, VDD = 4 V to 10 V, and (VC2–VC1), (VC1–GND) = 3 V to 4.2 V. All values assume recommended
supply voltage filter resistance RVD of 100 Ω and 5% accurate or better cell balance resistor RCBext.
MIN NOM MAX
ICB
Cell balance input current
RCBext = 4700 Ω
0.5
0.75
1
RCBext = 2200 Ω
1
1.5
2
RCBext = 910 Ω
2
3
4
RCBext = 560 Ω
3
4.5
6
RCBext = 360 Ω
3.5
6
8.5
RCBext = 240 Ω
4
7.5
11
RCBext = 120 Ω
5
10
15
UNIT
mA
-80
80
-90
75
-100
ICD Discharge Current (PA)
ICD Charge Current (nA)
7.7 Typical Characteristics
-110
-120
-130
-140
-150
-160
65
60
55
50
45
-170
-180
-40
70
-20
0
20
40
60
Temperature (qC)
80
40
-40
100
-20
0
D001
Figure 1. ICD Charge Current
20
40
60
Temperature (qC)
80
100
D002
Figure 2. ICD Discharge Current
3.3
3.2
ICC (uA)
3.1
3.0
2.9
2.8
2.7
2.6
2.5
-40
0
25
60
Operating Temperature (ƒC)
110
C002
Figure 3. Average ICC During Normal Operation Across Operational Temperature
6
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8 Detailed Description
8.1 Overview
The BQ29209-Q1 provides overvoltage protection and cell balancing for 2-series cell lithium-ion battery packs.
8.1.1 Voltage Protection
Each cell voltage is continuously compared to a factory configured internal reference threshold. If either cell
reaches an overvoltage condition, the BQ29209-Q1 device starts a timer that provides a delay proportional to the
capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low to high state.
8.1.2 Cell Balancing
If enabled, the BQ29209-Q1 performs automatic cell-balance correction where the two cells are automatically
corrected for voltage imbalance by loading the cell with the higher voltage with a small balancing current. When
the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied if the
imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the CB_EN pin
low, and disabled when CB_EN is pulled to greater than 2.2 V, for example, VDD.
If the internal cell balancing current of up to 15 mA is insufficient, the BQ29209-Q1 may be configured via
external circuitry to support much higher external cell balancing current.
8.2 Functional Block Diagram
VDD
5-V LDO
and POR
VC2
CTRL
+
CB2_EN
CB1 _EN
CB
Logic
Hys.
ICD =
150 nA
–
VC1
VC1_CB
+
OUT
–
GND
CB_EN
CD
0.1 µF
8.3 Feature Description
8.3.1 Protection (OUT) Timing
Sizing the external capacitor is based on the desired delay time as follows:
CCD =
td
XDELAY
Where td is the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds
per microfarad. XDELAY is nominally 9 s/µF. For example, if a nominal delay of 3 seconds is desired, use a CCD
capacitor that is 3 s / 9 s/µF = 0.33 µF.
The delay time is calculated as follows:
t d = CCD ´ XDELAY
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Feature Description (continued)
If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
8.3.2 Cell Voltage > VPROTECT
When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay
begins to count to td. If the input remains above VPROTECT for the duration of td, the BQ29209-Q1 output changes
from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V
when IOH = 0 mA.
The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V
typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.
VPROTECT
VPROTECT - VHYS
Cell Voltage
VC2-VC1,
VC1-GND
td
L
H
OUT
Figure 4. Timing for Overvoltage Sensing
8.3.3 Cell Connection Sequence
NOTE
Before connecting the cells, populate the overvoltage delay timing capacitor, CCD.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
NOTE
Using any cell connection sequence that does not connect GND first may result in
increased leakage current drawn by the VDD pin.
8
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Feature Description (continued)
8.3.4 Cell Balance Enable Control
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower state-of-charge (SOC) levels.
8.3.5 Cell Balance Configuration
The following cell balancing details relate to Figure 5.
Figure 5. Simplified Schematic for Cell Balancing Description
The cell balancing current may be calculated as follows:
For Cell 1 balancing current, ICB1:
(1)
For Cell 2 balancing current, ICB2:
(2)
Where:
RCBext = resistor connected between the top of Cell 1 and the VC1_CB pin
RIN1 = resistor connected between the top of Cell 1 and the VC1 pin
RIN2 = resistor connected between the top of Cell 2 and the VC2 pin
RVDD = resistor connected between the top of Cell 2 and the VDD pin
8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage)
The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The
recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3 V and 4.2
V. Below VDD = 6 V, it is recommended to pull CB_EN high to disable the cell balancing function.
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Feature Description (continued)
111%
100%
79%
VC2
6V
8.4 V
7.6 V
Figure 6. VMM_DET_ON and VMM_DET_OFF Threshold
8.3.7 Customer Test Mode
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of
approximately 0.08, thereby reducing the delay time during an overvoltage condition.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into CTM. Also, avoid exceeding absolute maximum voltages for the individual cell
voltages (VC1–GND) and (VC2–VC1). Stressing the pins beyond the rated limits may
cause permanent damage to the device.
To exit CTM, power off the device and then power it back on.
10
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Feature Description (continued)
15 V
VDD
Test Mode Entered
VC2
> 10 ms
4.5 V
(VC2–VC1)
or
(VC1–GND)
VPROTECT
VPROTECT –VHYST
4V
<<td
OUT
Figure 7. Voltage Test Limits
8.3.8 Test Conditions
IIN
IIN
1 VC2
OUT 8
2 VC1
VDD 7
______
CB_EN 6
3 VC1_CB
4 CD
Icc
GND 5
Figure 8. ICC, IIN Measurement
VCELL
ICB
VCELL±VCB
1 VC2
OUT 8
2 VC1
VDD 7
______
CB_EN 6
3 VC1_CB
4 CD
ICB
ICB_EN
GND 5
Figure 9. ICB Measurement
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8.4 Device Functional Modes
This device monitors the voltage of the cells connected to the VCx pins and depending on these voltages and the
overall battery voltage at VDD the device enters different operating modes.
8.4.1 NORMAL Mode
The device is operating in NORMAL mode when the cell voltage range is between the over-charge detection
threshold (VPROTECT) and the minimum supply voltage.
If this condition is satisfied, the device turns OFF the OUT pin.
8.4.2 PROTECTION Mode
The device is operating in PROTECTION mode when the cell over voltage protection feature has been triggered.
See Cell Voltage > VPROTECT for more details on this feature.
If this condition is satisfied, the device turns ON the OUT pin.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The BQ29209-Q1 is designed to be used in 2-series Li-Ion battery packs and with the option to include voltagebased cell balancing. The number of parallel cells or the overall capacity of the battery only affects the cell
balancing circuit due to the level of potential imbalance that needs to be corrected.
9.2 Typical Applications
9.2.1 Battery Connection
Figure 10 shows the configuration for the 2-series cell battery connection with cell balancing enabled.
Figure 10. 2-Series Cell Configuration
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1.
12
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Typical Applications (continued)
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE at TA = 25°C
Input voltage range
4 V to 10 V
Overvoltage Protection (OVT)
4.3 V
Overvoltage detection delay time
3s
Overvoltage detection delay timer capacitor
0.33 µF
Cell Balancing Enabled
Yes
Cell Balancing Current, ICB1 and ICB2
5 mA (targeted at a nominal cell voltage of 3.8 V)
Cell Balancing Resistors, RCBext, RIN1, RIN2 and RVD
RCBext = 440 Ω, RIN1 = 260 Ω, RIN2 = 260 Ω, RVD = 100 Ω
9.2.1.2 Detailed Design Procedure
The BQ29209-Q1 has limited features but there are some key calculations to be made when selecting external
component values.
• Calculate the required CCD capacitor value for the voltage protection delay time. Care should be taken to
evaluate the tolerances of the capacitor and the BQ29209-Q1 to ensure system specifications are met.
• Calculate the cell balancing resistor values to provide a suitable level of balancing current that will, at a
minimum, counter act an increase in imbalance during normal operation of the battery. Care should be taken
to ensure any connectivity resistance is also considered as this will also reduce the balancing current level.
9.2.1.3 Application Curve
2
1
V(OA) (mV)
0
±1
±2
±3
±4
VC1 V(PROTECT)
±5
VC2 V(PROTECT)
±6
-40
0
25
60
Operating Temperature (ƒC)
110
C001
Figure 11. Average VPROTECT Accuracy (VOA) Across Operation Temperature
9.3 System Example
9.3.1 External Cell Balancing
Higher cell balancing currents can be supported by means of a simple external network, as shown in Figure 12.
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13
BQ29209-Q1
SLUSC62C – JUNE 2015 – REVISED MAY 2019
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System Example (continued)
Figure 12. External Cell Balancing Configuration
The VC1_CB pin is tri-stated when cell balancing is disabled, is driven low by the internal logic to enable
balancing on CELL1, and is driven high by the internal logic to enable balancing on CELL2. RCLAMP ensures that
both Q1 and Q2 remain off when balancing is disabled, and should be sized above 2 kΩ to prevent excessive
internal device current when the balancing network is activated. If RCLAMP is too small, then the gate-source
voltage required to enable the external FETs cannot be achieved. RCBext determines the value of the balancing
current, and is dependent on the voltage of the balanced cell and the specific Q1 and Q2 transistors used in the
design (due to the transistors operating in saturation mode during balancing). The balancing currents (assuming
the current through RCLAMP is not significant) are given as follows:
(3)
(4)
10 Power Supply Recommendations
The recommended power supply for this device is a maximum 10-V operation on the VDD input pin.
14
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Product Folder Links: BQ29209-Q1
BQ29209-Q1
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SLUSC62C – JUNE 2015 – REVISED MAY 2019
11 Layout
11.1 Layout Guidelines
The following are the recommended layout guidelines:
1. Ensure the input filters to the VC1 and VC2 pins are as close to the IC as possible to improve noise
immunity.
2. If the OUT pin is used to control a high current path, for example: to blow a chemical fuse, then care should
be taken to ensure the high current path creates minimal interference of the BQ29209-Q1 voltage sense
inputs.
3. The input RC filter on the VDD pin should be close to the terminal of the IC.
11.2 Layout Example
1
Additional circuitry required based on usage of the OUT pin
Via connects between two layers
1
PACK -
OUT
8
VDD
7
CB_EN
6
GND
5
VC2
PACK +
1
PWRPAD
2
VC1
3
VC1_CB
4
CD
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Product Folder Links: BQ29209-Q1
15
BQ29209-Q1
SLUSC62C – JUNE 2015 – REVISED MAY 2019
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: BQ29209-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ29209TDRBRQ1
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
209Q1
BQ29209TDRBTQ1
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
209Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2018
OTHER QUALIFIED VERSIONS OF BQ29209-Q1 :
• Catalog: BQ29209
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ29209TDRBRQ1
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
BQ29209TDRBTQ1
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ29209TDRBRQ1
SON
DRB
8
3000
367.0
367.0
35.0
BQ29209TDRBTQ1
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
8X
0.5
0.3
0.35
0.25
0.1
0.05
C A B
C
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
8X (0.6)
METAL
TYP
1
8
8X (0.3)
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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