Texas Instruments | TPS57140-EP 1.5-A 42-V Step-Down DC/DC Converter With Eco-mode™ Control (Rev. B) | Datasheet | Texas Instruments TPS57140-EP 1.5-A 42-V Step-Down DC/DC Converter With Eco-mode™ Control (Rev. B) Datasheet

Texas Instruments TPS57140-EP 1.5-A 42-V Step-Down DC/DC Converter With Eco-mode™ Control (Rev. B) Datasheet
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TPS57140-EP
SLVSD01B – SEPTEMBER 2015 – REVISED MAY 2019
TPS57140-EP 1.5-A 42-V Step-Down DC/DC Converter With Eco-mode™ Control
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
3.5-V to 42-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads With PulseSkipping Eco-mode™ Control Scheme
116-μA Operating Quiescent Current
1.5-μA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start and Sequencing
Undervoltage and Overvoltage Power-Good
Output
Adjustable Undervoltage Lockout (UVLO) Voltage
and Hysteresis
0.8-V Internal Voltage Reference
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
•
12-V and 24-V Industrial and Commercial LowPower Systems
Aftermarket Automotive Accessories: Video, GPS,
Entertainment
3 Description
The TPS57140-EP device is a 42-V, 1.5-A step-down
regulator with an integrated high-side MOSFET.
Current-mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no-load,
regulated output supply current to 116 μA. Using the
enable pin reduces the shutdown supply current to
1.5 μA.
UVLO is internally set at 2.5 V, but can be increased
using the enable pin. The slow-start pin, which is also
configurable for sequencing or tracking, controls the
output voltage start-up ramp. An open-drain powergood signal indicates the output is within 92% to
109% of its nominal voltage.
A wide switching-frequency range allows optimization
of efficiency and external component size. Frequency
foldback and thermal shutdown protect the part
during an overload condition.
The TPS57140-EP is available in a 10-pin VSON
package (DRC).
Device Information(1)
PART NUMBER
TPS57140-EP
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Efficiency vs Load Current
90
VIN
PWRGD
85
TPS57140-EP
BOOT
PH
SS/TR
RT/CLK
COMP
Efficiency - %
EN
80
75
70
65
VI = 12 V,
VO = 3.3 V,
fsw = 1200 kHz
60
VSENSE
GND
55
50
0
0.25
0.50
0.75
1
1.25
Load Current - A
1.50
1.75
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS57140-EP
SLVSD01B – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 25
8
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application .................................................. 30
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 41
10.3 Power-Dissipation Estimate .................................. 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2015) to Revision B
•
Editorial changes only; no technical content changed .......................................................................................................... 1
Changes from Original (September 2015) to Revision A
•
2
Page
Page
Added derating chart ............................................................................................................................................................. 7
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
BOOT
VIN
EN
SS/TR
RT/CLK
1
10
2
4
Exposed 9
Thermal 8
Pad
7
5
6
3
PH
GND
COMP
VSENSE
PWRGD
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor below the
minimum required by the output device forces the output to switch off pending a refresh of the capacitor.
COMP
8
O
Error-amplifier output and input to the output-switch current comparator. Connect frequency-compensation
components to this pin.
EN
3
I
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
UVLO with two resistors.
GND
9
—
PH
10
I
The source of the internal high-side power MOSFET
PWRGD
6
O
An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or
EN shutdown.
Ground
RT/CLK
5
I
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. Pulling the pin above the PLL upper threshold
causes a mode change whereby the pin becomes a synchronization input. Disabling of the internal amplifier
occurs, and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, re-enabling of
the internal amplifier occurs, and the mode returns to a resistor-set function.
SS/TR
4
I
Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. The voltage on
this pin overrides the internal reference, allowing use of the pin for tracking and sequencing.
VIN
2
I
Input supply voltage, 3.5 to 42 V
VSENSE
7
I
Inverting node of the transconductance (gm) error amplifier
Thermal pad
—
—
GND pin must have an electrical connection to the exposed pad on the printed-circuit board for proper
operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
47
EN (2)
–0.3
5
BOOT
VIN
Input voltage
55
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
47
–1
47
–2
47
PH to BOOT
VOUT
Output voltage
30 ns
Maximum DC voltage, TJ = –40°C
VDIFF
Differential voltage
ISOURCE
Source current
PAD to GND
–0.85
–200
200
100
μA
BOOT
100
mA
VSENSE
10
μA
100
μA
100
μA
PWRGD
10
mA
SS/TR
200
μA
Current limit
RT/CLK
VIN
Sink current
Current limit
COMP
TJ
Operating junction temperature
–55
160
Tstg
Storage temperature
–65
150
(1)
(2)
mV
EN
PH
ISINK
V
8
200 ns
PH
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See Enable and Adjusting UVLO for details.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
4
3.5
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NOM
MAX
42
UNIT
V
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6.4 Thermal Information
TPS57140-EP
THERMAL METRIC (1) (2)
DRC (VSON)
UNIT
10 PINS
Standard board
56.5
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
52.1
°C/W
RθJB
Junction-to-board thermal resistance
20.8
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
20.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.2
°C/W
(1)
(2)
(3)
Custom board
(3)
°C/W
61.5
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to increase substantially. See Power-Dissipation Estimate for more information.
Test-board conditions:
(a) 3 inches (7.62 cm) × 3 inches (7.62 cm), 2 layers, thickness: 0.062 inch (1.57 mm)
(b) 2-oz. (0.071-mm thick) copper traces located on the top of the PCB
(c) 2-oz. (0.071-mm thick) copper ground plane, bottom layer
(d) 6 thermal vias (13 mil (1 mil = 0.0254 mm)) located under the device package
6.5 Electrical Characteristics
TJ = –55°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal UVLO threshold
Shutdown supply current
Operating: nonswitching supply
current
3.5
42
No voltage hysteresis, rising and falling
2.5
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V
1.5
4
EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V
1.9
6.5
VSENSE = 0.83 V, VIN = 12 V, 25°C
116
140
1.25
1.36
V
V
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling, 25°C
1.15
Enable threshold 50 mV
–3.8
Enable threshold –50 mV
–0.9
Hysteresis current
V
μA
–2.9
μA
VOLTAGE REFERENCE
Voltage reference
TJ = 25°C
0.790
0.8
0.808
0.780
0.8
0.819
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gm)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
97
μS
Error amplifier transconductance (gm)
during slow start
–2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V
26
μS
Error amplifier dc gain
VVSENSE = 0.8 V
10 000
V/V
2700
kHz
±7
μA
6
S
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
COMP to switch current
transconductance
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Electrical Characteristics (continued)
TJ = –55°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8
2.7
A
182
°C
CURRENT LIMIT
Current-limit threshold
VIN = 12 V, TJ = 25°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW
Switching-frequency range using RT
mode
VIN = 12 V
100
Switching frequency
VIN = 12 V, RT = 200 kΩ
450
Switching-frequency range using CLK
mode
VIN = 12 V
300
Minimum CLK pulse duration
581
2500
kHz
720
kHz
2200
kHz
40
RT/CLK high threshold
VIN = 12 V
1.9
RT/CLK low threshold
VIN = 12 V
RT/CLK falling-edge to PH rising-edge
delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
0.45
ns
2.2
V
0.7
V
60
ns
100
μs
SLOW START AND TRACKING (SS/TR)
Charge current
VSS/TR = 0.4 V
2
μA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
SS/TR discharge voltage
1
V
112
μA
VSENSE = 0 V
54
mV
VSENSE falling
92%
POWER GOOD (PWRGD PIN)
VVSENSE
6
VSENSE rising
94%
VSENSE rising
109%
VSENSE falling
107%
Hysteresis
VSENSE falling
2%
Output-high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
10
On-resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
50
Minimum VIN for defined output
V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA
VSENSE threshold
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0.95
nA
Ω
1.5
V
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Estimated EM Failure Mode Lifetime (Years)
1000
700
500
300
200
100
70
50
30
20
10
7
5
3
2
1
0.7
0.5
80
90
100
110
120
130
Continuous Junction Temperature, TJ(qC)
140
150
160
D019
(1)
Electromigration fail mode = Time at temperature with bias
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime versus junction temperature is based on reliability modeling and available
qualification data.
Figure 1. Predicted Lifetime Derating Chart for TPS57140-EP
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0.816
500
VI = 12 V
BOOT-PH = 3V
BOOT-PH = 6V
VREF - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - m
6.6 Typical Characteristics
375
250
125
0
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
0.808
0.8
0.792
0.784
-65
-40
10
35
60
85
110
TJ - Junction Temperature - °C
D002
610
VI = 12 V
fS - Switching Frequency - KHz
VI = 12 V
3
2.5
2
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
600
RT = 200K:
590
580
570
560
550
-65
160
-40
-15
D003
Figure 4. Switch Current Limit vs Junction Temperature
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D004
Figure 5. Switching Frequency vs Junction Temperature
2500
1000
VI = 12 V,
TJ = 25°C
VI = 12 V,
TJ = 25°C
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
160
Figure 3. Voltage Reference vs Junction Temperature
3.5
1500
1000
500
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
Figure 6. Switching Frequency vs RT/CLK Resistance, HighFrequency Range
8
135
D001
Figure 2. On Resistance vs Junction Temperature
Switch Current - A
-15
800
600
400
200
0
100
200
300
400
500
600
700
RT/CLK - Resistance - kW
800
900
1000
Figure 7. Switching Frequency vs RT/CLK Resistance, LowFrequency Range
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Typical Characteristics (continued)
40
150
VI = 12 V
VI = 12 V
130
gm - uS
gm - uS
30
110
90
20
70
10
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
50
-65
160
Figure 8. EA Transconductance During Slow Start vs
Junction Temperature
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D006
Figure 9. EA Transconductance vs Junction Temperature
-3.25
1.4
VI = 12 V
VI = 12 V
-3.5
VI(EN) = Threshold +50 mV
1.3
I(EN) - uA
EN - Threshold - V
-40
D005
-3.75
1.2
-4
1.1
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
-4.25
-65
160
Figure 10. EN Pin Voltage vs Junction Temperature
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D008
Figure 11. EN Pin Current vs Junction Temperature
VI = 12 V
VI = 12 V
VI(EN) = Threshold -50 mV
-1.5
I(SS/TR) - uA
I(EN) - uA
-15
-1
-0.9
-0.95
-40
D007
-1
-1.05
-2
-2.5
-1.1
-1.15
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
-3
-65
-40
D009
Figure 12. EN Pin Current vs Junction Temperature
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D010
Figure 13. SS/TR Charge Current vs Junction Temperature
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Typical Characteristics (continued)
140
100
VI = 12 V,
TJ = 25°C
VI = 12 V
135
80
% of Nominal fsw
II(SS/TR) - uA
130
125
120
60
40
20
115
110
-65
0
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
0
0.2
0.4
VSENSE - V
D011
0.6
0.8
Figure 15. Switching Frequency vs VSENSE
Figure 14. SS/TR Discharge Current vs Junction
Temperature
3.5
2
VI = 12 V
TJ = 25°C
3
1.5
I(VIN) - mA
I(VIN) - uA
2.5
2
1
1.5
0.5
1
0.5
-65
0
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
0
10
D012
Figure 16. Shutdown Supply Current vs Junction
Temperature
20
VI - Input Voltage - V
30
40
Figure 17. Shutdown Supply Current vs Input Voltage (VIN)
140
140
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
VI = 12 V
VI(VSENSE) = 0.83 V
130
120
I(VIN) - mA
I(VIN) - uA
130
110
100
90
-65
110
100
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
90
0
20
VI - Input Voltage - V
D013
Figure 18. VIN Supply Current vs Junction Temperature
10
120
40
Figure 19. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
100
125
PWRGD Threshold - % of V REF
VI = 12 V
RDSON - :
80
60
40
20
0
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
115
110
105
100
95
90
85
-65
160
-15
3
2.3
2.75
2.1
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D015
Figure 21. PWRGD Threshold vs Junction Temperature
2.5
VI(VIN) - V
VI(BOOT-PH) - V
-40
D014
Figure 20. PWRGD On Resistance vs Junction Temperature
1.9
2.5
2.25
1.7
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
2
-65
160
-40
-15
D016
Figure 22. BOOT-PH UVLO vs Junction Temperature
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D017
Figure 23. Input Voltage (UVLO) vs Junction Temperature
60
600
VIN = 12 V
TJ = 25°C
500
V(SS/TR) = 0.2 V
55
400
VI = 12 V
50
Offset - mV
Offset Voltage Threshold (mV)
VSENSE Rising
VSENSE Falling
VSENSE Rising
VSENSE Falling
VI = 12V
120
300
45
200
40
100
35
0
0
200
400
600
Voltage Sense (mV)
Figure 24. SS/TR to VSENSE Offset vs VSENSE
800
30
-65
-40
-15
10
35
60
85
110
TJ - Junction Temperature - °C
135
160
D018
Figure 25. SS/TR to VSENSE Offset vs Temperature
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7 Detailed Description
7.1 Overview
The TPS57140-EP device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. To improve performance during line and load transients, the device implements a constant-frequency,
current-mode control which reduces output capacitance and simplifies external frequency-compensation design.
The wide switching frequency of 100 to 2500 kHz allows for efficiency and size optimization when selecting the
output-filter components. Using a resistor to ground on the RT/CLK pin adjusts the switching frequency. The
device has an internal phase-locked loop (PLL) on the RT/CLK pin that synchronizes the power-switch turnon to
a falling edge of an external system clock.
The TPS57140-EP has a default start-up voltage of approximately 2.5 V. The EN pin has an internal pullup
current source that the designer can use to adjust the input-voltage UVLO threshold with two external resistors.
In addition, the pullup current provides a default condition. When the EN pin is floating, the device operates. The
operating current is 116 μA when not switching and under no load. With the device disabled, the supply current is
1.5 μA.
The integrated 200-mΩ high-side MOSFET allows for high-efficiency power-supply designs capable of delivering
1.5 A of continuous current to a load. The TPS57140-EP reduces the external component count by integrating
the boot recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the integrated
high-side MOSFET. A UVLO circuit monitors the boot-capacitor voltage and turns the high-side MOSFET off
when the boot voltage falls below a preset threshold. The TPS57140-EP can operate at high duty cycles
because of the boot UVLO. Stepping down of the output voltage can extend as low as the 0.8-V reference.
The TPS57140-EP has a power-good comparator (PWRGD) which asserts when the regulated output voltage is
<92% or >109% of the nominal output voltage. The PWRGD pin is an open-drain output which deasserts when
the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowing the pin to transition
high when a pullup resistor is used.
The TPS57140-EP minimizes excessive output overvoltage (OV) transients by taking advantage of the OV
power-good comparator. With the OV comparator activated, the high-side MOSFET turns off and remains
masked from turning on until the output voltage is lower than 107%.
Use the SS/TR (slow-start/tracking) pin to minimize inrush currents or provide power-supply sequencing during
power up. Couple a small-value capacitor to the pin to adjust the slow-start time. The designer can couple a
resistor divider to the pin for critical power-supply sequencing requirements. Discharge of the SS/TR pin occurs
before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO
fault, or a disabled condition.
The TPS57140-EP also discharges the slow-start capacitor during overload conditions with an overload-recovery
circuit. The overload-recovery circuit slow-starts the output from the fault voltage to the nominal regulation
voltage on removal of a fault condition. A frequency-foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current.
12
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7.2 Functional Block Diagram
PWRGD
6
EN
3
VIN
2
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
Overload
Recovery
Maximum
Clamp
Frequency
Shift
11 POWERPAD
Oscillator
with PLL
9 GND
5
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS57140-EP uses an adjustable fixed-frequency, peak-current mode control. External resistors on the
VSENSE pin compare the output voltage to an internal voltage reference by an error amplifier which drives the
COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device compares the
error-amplifier output to the high-side power-switch current. When the power-switch current reaches the COMP
voltage level, the power switch turns off. The COMP pin voltage increases and decreases as the output current
increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. A minimum clamp on the COMP pin implements the Eco-mode control scheme.
7.3.2 Slope-Compensation Output Current
The TPS57140-EP adds a compensating ramp to the switch-current signal. This slope compensation prevents
subharmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.
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Feature Description (continued)
7.3.3 Bootstrap Voltage (Boot)
The TPS57140-EP has an integrated boot regulator and requires a small ceramic capacitor between the BOOT
and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic capacitor
should be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric because of the stable
characteristics over temperature and voltage. To improve dropout, the TPS57140-EP operates at 100% duty
cycle as long as the BOOT-to-PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops
below 2.1 V, the high-side MOSFET turns off using a UVLO circuit, allowing for the low-side diode to conduct,
which allows refreshing of the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is
low, the high-side MOSFET can remain on for more switching cycles than it refreshes; thus, the effective dutycycle limitation attributed to the boot regulator system is high.
7.3.4 Low-Dropout Operation
The voltage drops across the power MOSFET, inductor, low-side diode, and PCB resistance mainly determine
the duty cycle during dropout of the regulator. During operating conditions in which the input voltage drops, the
high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation until the BOOT-to-PH
voltage falls below 2.1 V.
After the high side is off, the low-side diode conducts and the BOOT capacitor recharges. During this bootcapacitor recharge time, the inductor current ramps down until the high-side MOSFET turns on. The recharge
time is longer than the typical high-side off-time of previous switching cycles, and thus the inductor-current ripple
is larger, resulting in more ripple voltage on the output. The recharge time is a function of the input voltage, bootcapacitor value, and the impedance of the internal boot-recharge diode.
Pay attention in maximum-duty-cycle applications which experience extended time periods without a load
current. When the voltage across the BOOT capacitors falls below the 2.1-V threshold in applications that have a
difference in the input voltage and output voltage that is <3 V, the high-side MOSFET turns off, but there is not
enough current in the inductor to pull the PH pin down to recharge the boot capacitor. The regulator does not
switch because the boot capacitor is less than 2.1 V, and the output capacitor decays until the difference
between the input voltage and output voltage is 2.1 V. At this time, the boot UVLO is exceeded and the device
switches until reaching the desired output voltage.
Figure 26 and Figure 27 show the start and stop voltages for 3.3-V and 5-V applications. The graphs plot
voltages versus the load current. The definition of start voltage is the input voltage needed to regulate within 1%.
The definition of stop voltage is the input voltage at which the output drops by 5% or stops switching.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
5.2
Start
5
Stop
4.8
3.2
4.6
3
0
0.05
0.10
IO - Output Current - A
0.15
0.20
0
Figure 26. 3.3-V Start and Stop Voltage
14
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0.05
0.10
IO - Output Current - A
0.15
0.20
Figure 27. 5-V Start and Stop Voltage
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Feature Description (continued)
7.3.5 Error Amplifier
The TPS57140-EP has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gm) of the error amplifier is 97 μS during normal operation. During the slow-start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 25 μS.
The frequency-compensation components (capacitor, series resistor, and capacitor) are added from the COMP
pin to ground.
7.3.6 Voltage Reference
The voltage-reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature-stable band-gap circuit.
7.3.7 Adjusting the Output Voltage
A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends to use 1%
tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To
improve efficiency at very-light loads, consider using larger-value resistors. If the values are too high, the
regulator is more susceptible to noise, and voltage errors from the VSENSE input current become noticeable.
æ Vout - 0.8V ö
R1 = R2 ´ ç
÷
0.8 V
è
ø
(1)
7.3.8 Enable and Adjusting UVLO
The VIN pin voltage falling below 2.5 V disables the TPS57140-EP. If an application requires a higher UVLO, use
the EN pin as shown in Figure 28 to adjust the input-voltage UVLO by using two external resistors. Though it is
not necessary to use the UVLO adjust resistors, for operation, TI highly recommends providing consistent powerup behavior. The EN pin has an internal pullup current source, I1, of 0.9 μA that provides the default condition of
the TPS57140-EP operating when the EN pin floats. When the EN pin voltage exceeds 1.25 V, an additional 2.9
μA of hysteresis, Ihys, is added. This additional current facilitates input-voltage hysteresis. Use Equation 2 to set
the external hysteresis for the input voltage. Use Equation 3 to set the input start voltage.
TPS57140-EP
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
–
Figure 28. Adjustable UVLO
V
- VSTOP
R1 = START
IHYS
R2 =
(2)
VENA
VSTART - VENA
+ I1
R1
(3)
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Feature Description (continued)
Figure 29 shows another technique to add input-voltage hysteresis. The designer can use this method if the
resistance values are high from the previous method and there is a need for a wider voltage hysteresis. Resistor
R3 sources additional hysteresis current into the EN pin.
TPS57140-EP
VIN
Ihys
R1
I1
0.9 mA
2.9 mA
+
EN
R2
1.25 V
–
VOUT
R3
Figure 29. Adding Additional Hysteresis
R1 =
R2 =
VSTART - VSTOP
V
IHYS + OUT
R3
(4)
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
Do not place a low-impedance voltage source with >5 V directly on the EN pin. Do not place a capacitor directly
on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage. The node voltage
(see Figure 30) must remain ≤5.8 V. The Zener diode can sink up to 100 μA. The EN pin voltage can be >5 V if
the VIN voltage source has a high impedance and does not source more than 100 μA into the EN pin.
VIN
IA
RUVLO1
EN
10 kW
Node
3
IB
RUVLO2
IC
5.8 V
UDG-10065
Figure 30. Node Voltage
16
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Feature Description (continued)
7.3.9 Slow-Start or Tracking Pin (SS/TR)
The TPS57140-EP effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage
as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow-start time. The TPS57140-EP has an internal pullup current source of 2 μA that
charges the external slow-start capacitor. The calculations for the slow-start (Equation 6) show the time (10% to
90%). The voltage reference (VREF) is 0.8 V and the slow-start current (ISS) is 2 μA. The slow-start capacitor
should remain lower than 0.47 μF and greater than 0.47 nF.
Tss(ms) ´ Iss(m A)
Css(nF) =
Vref (V) ´ 0.8
(6)
At power up, the TPS57140-EP does not start switching until the slow-start pin discharges to <40 mV; to ensure
proper power up, see Figure 31.
During normal operation, the TPS57140-EP stops switching and the SS/TR must discharge to 40 mV when the
VIN UVLO is exceeded, EN pin is pulled below 1.2 V, or a thermal shutdown event occurs.
The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is >85% of the internal reference voltage, the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 24).
The SS/TR voltage ramps linearly until clamped at 1.7 V.
EN
SS/TR
VSENSE
VOUT
Figure 31. Operation of SS/TR Pin When Starting
7.3.10 Overload Recovery Circuit
The TPS57140-EP has an overload recovery (OLR) circuit. The OLR circuit slow-starts the output from the
overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit discharges
the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of 100 μA
when the error amplifier is changed to a high voltage from a fault condition. On removal of the fault condition, the
output slow-starts from the fault voltage to the nominal output voltage.
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Feature Description (continued)
7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS57140-EP is adjustable over a wide range from approximately 100-kHz to
2500-kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 7 or the curves in Figure 32 or Figure 33. To reduce the solution size, the designer
would typically set the switching frequency as high as possible, but consider tradeoffs of the supply efficiency,
maximum input voltage, and minimum controllable on-time.
The minimum controllable on time is typically 130 ns, which limits the maximum operating input voltage.
The frequency-shift circuit also limits the maximum switching frequency. The following contains more discussion
on the details of the maximum switching frequency.
206033
RT (kW) =
¦ SW (kHz )1.0888
(7)
500
2500
2000
Switching Frequency (kHz)
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
400
300
200
100
0
200
300
400
500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW)
C006
Figure 33. Low-Range RT
Figure 32. High-Range RT
7.3.12 Overcurrent Protection and Frequency Shift
The TPS57140-EP implements current-mode control, which uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle-by-cycle basis. During each cycle, the device compares the switch current and COMP pin
voltage. When the peak switch current intersects the COMP voltage, the high-side switch turns off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
increasing the switch current. The internal clamping of the error amplifier output functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages, the TPS57140-EP implements a
frequency shift. The divisor of the switching frequency goes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V
on the VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still has frequency-shift protection.
During short-circuit events (particularly with high-input-voltage applications), the control loop has a finite minimum
controllable on-time and the output has a very-low voltage. During the switch on-time, the inductor current ramps
to the peak current limit because of the high input voltage and minimum on-time. During the switch off time, the
inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the rampup amount. The frequency shift effectively increases the off-time, allowing the current to ramp down.
18
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Feature Description (continued)
7.3.13 Selecting the Switching Frequency
The selected switching frequency should be the lower value of the two equations, Equation 8 and Equation 9.
Equation 8 is the maximum switching frequency limitation set by the minimum controllable on-time. Setting the
switching frequency above this value causes the regulator to skip switching pulses.
Equation 9 is the maximum switching-frequency limit set by the frequency-shift protection. To have adequate
output short-circuit protection at high input voltages, set the switching frequency to be less than the ƒSW(maxshift)
frequency. In Equation 9, to calculate the maximum switching frequency, take into account that the output
voltage decreases from the nominal voltage to 0 V and that the ƒDIV integer increases from 1 to 8, corresponding
to the frequency shift.
In Figure 34, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is 0 V, the resistance of the inductor is 0.1 Ω, the FET on-resistance is 0.2 Ω, and the voltage
drop of the diode is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter
these equations in a spreadsheet or other software, or use the SwitcherPro design software to determine the
switching frequency.
fSW (max skip ) =
fSWshift =
1
tON
æ I ´R + V
dc
OUT + Vd
´ç L
ç VIN - IL ´ RDS(on ) + Vd
è
fDIV æç IL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - IL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(8)
ö
÷
÷
ø
where
•
•
•
•
•
•
•
•
•
IL = Inductor current
Rdc = Inductor resistance
VIN = Maximum input voltage
VOUT = Output voltage
VOUTSC = Output voltage during short
Vd = Diode voltage drop
rDS(on) = Switch on-resistance
tON = Controllable on-time
ƒDIV = Frequency divide (equals 1, 2, 4, or 8)
(9)
2500
fs - Switching Frequency - kHz
VO = 3.3 V
2000
Shift
1500
Skip
1000
500
0
10
20
30
VI - Input Voltage - V
40
Figure 34. Maximum Switching Frequency vs Input Voltage
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Feature Description (continued)
7.3.14 How to Interface to RT/CLK Pin
The designer can use the RT/CLK pin to synchronize the regulator to an external system clock. To implement the
synchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 35. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range
is 300 to 2200 kHz. The rising edge of PH synchronizes to the falling edge of the signal on the RT/CLK pin.
Design the external synchronization circuit in such a way that the device has the default frequency-set resistor
connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends using a
frequency-set resistor connected as shown in Figure 35 through a 50-Ω resistor to ground. The resistor should
set the switching frequency close to the external CLK frequency. TI recommends ac-coupling the synchronization
signal through a 10-pF ceramic capacitor and a 4-kΩ series resistor to the RT/CLK pin. The series resistor
reduces PH jitter in heavy-load applications when synchronizing to an external clock, and in applications which
transition from synchronizing to RT mode. The first time CLK rises above the CLK threshold, the device switches
from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source opens and the CLK pin becomes
high-impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the
switching frequency can be higher or lower than the frequency set with the external resistor. The device
transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency
until the PLL locks onto the CLK frequency within 100 µs.
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz; then reapply the 0.5-V voltage, and the resistor then sets the switching frequency. The
divisor of the switching frequency goes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the VSENSE
pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal
start-up and fault conditions. Figure 36, Figure 37, and Figure 38 show the device synchronized to an external
system clock in continuous-conduction mode (CCM), discontinuous-conduction mode (DCM), and pulse-skip
mode (PSM).
TPS57140-EP
10 pF
4 kΩ
PLL
Rfset
EXT
Clock
Source
50 Ω
RT /CLK
Figure 35. Synchronizing to a System Clock
20
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Feature Description (continued)
EXT
EXT
VOUT
IL
PH
PH
IL
Figure 36. Plot of Synchronizing in CCM
Figure 37. Plot of Synchronizing in DCM
EXT
IL
PH
Figure 38. Plot of Synchronizing in PSM
7.3.15 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output. When the VSENSE pin is between 94% and 107% of the internal
voltage reference, the PWRGD pin deasserts and the pin floats. TI recommends using a pullup resistor between
the values of 1 and 100 kΩ to a voltage source that is ≤5.5 V. PWRGD is in a defined state when the VIN input
voltage is greater than 1.5 V, but with reduced current-sinking capability. PWRGD achieves full current-sinking
capability as the VIN input voltage approaches 3 V.
The PWRGD pin goes low when VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, PWRGD goes low if UVLO or thermal shutdown asserts or the EN pin goes low.
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Feature Description (continued)
7.3.16 Overvoltage Transient Protection (OVTP)
The TPS57140-EP incorporates an OVTP circuit to minimize voltage overshoot when recovering from output fault
conditions or strong unload transients on power-supply designs with low-value output capacitance. For example,
with the power-supply output overloaded, the error amplifier compares the actual output voltage to the internal
reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time,
the output of the error amplifier responds by clamping the error-amplifier output to a high voltage, thus requesting
the maximum output current. On removal of the condition, the regulator output rises and the error-amplifier output
transitions to the steady-state duty cycle. In some applications, the power-supply output voltage can respond
faster than the error-amplifier output can respond; this actuality leads to the possibility of an output overshoot.
The OVTP feature minimizes the output overshoot when using a low-value output capacitor by implementing a
circuit to compare the VSENSE pin voltage to OVTP threshold, which is 109% of the internal voltage reference.
A VSENSE pin voltage greater than the OVTP threshold disables the high-side MOSFET, preventing current
from flowing to the output and minimizing output overshoot. The VSENSE voltage dropping lower than the OVTP
threshold allows the high-side MOSFET to turn on at the next clock cycle.
7.3.17 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. When the die temperature decreases below 182°C, the device reinitiates the power-up sequence
by discharging the SS/TR pin.
7.3.18 Small-Signal Model for Loop Response
Figure 39 shows an equivalent model for the TPS57140-EP control loop which the designer can model in a
circuit-simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gmEA of 97 μS. The designer can model the error amplifier using an ideal
voltage-controlled current source. Resistor Ro and capacitor Co model the open-loop gain and frequency
response of the amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop
for the frequency-response measurements. Plotting c / a shows the small-signal response of the frequency
compensation. Plotting a / b shows the small-signal response of the overall loop. The designer can check the
dynamic loop response in a time-domain analysis by replacing RL with a current source having the appropriate
load-step amplitude and step rate. This equivalent model is only valid for CCM designs.
PH
VO
Power Stage
gmps 6 S
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
COUT
VSENSE
gmea
97 mS
R2
C1
Figure 39. Small-Signal Model for Loop Response
22
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Feature Description (continued)
7.3.19 Simple Small-Signal Model for Peak-Current-Mode Control
Figure 40 describes a simple small-signal model that the designer can use to understand how to design the
frequency compensation. The designer can approximate the TPS57140-EP power stage by a voltage-controlled
current source (duty-cycle modulator) supplying current to the output capacitor and load resistor. Equation 10
shows the control-to-output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero.
The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 39) is the
power-stage transconductance. The gmPS for the TPS57140-EP is 6 S. The low-frequency gain of the powerstage frequency response is the product of the transconductance and the load resistance as shown in
Equation 11.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of
Figure 40. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions, which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency-compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number of
frequency-compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 13).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 40. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
æ
s ö
ç1 +
÷
2p ´ fZ ø
VOUT
è
= Adc ´
VC
æ
s ö
ç1 +
÷
2
p
´ fP ø
è
Adc = gmps ´ RL
(10)
(11)
1
fP =
COUT ´ RL ´ 2p
(12)
1
fZ =
COUT ´ RESR ´ 2p
(13)
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Feature Description (continued)
7.3.20 Small-Signal Model for Frequency Compensation
The TPS57140-EP uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Figure 41 shows compensation circuits Type 2A, Type 2B, and
Type 1. Type 2 circuits are most likely used in high-bandwidth power-supply designs using low-ESR output
capacitors. Power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors likely use the Type
1 circuit. Equation 14 and Equation 15 show how to relate the frequency response of the amplifier to the smallsignal model in Figure 41. Modeling of the open-loop gain and bandwidth uses the RO and CO shown in
Figure 41. See Application and Implementation for a design example using a Type 2A network with a low-ESR
output capacitor.
Equation 14 through Equation 23 are a reference for those who prefer to compensate using the preferred
methods. Those who prefer to use a prescribed method must use the method outlined in Application and
Implementation or use switched information.
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 41. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 42. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
COUT
24
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
(14)
(15)
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Feature Description (continued)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
2
p
´
p
´
f
f
P1 ø è
P2 ø
è
(16)
R2
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
A0 = gmea ´ Ro ´
A1 = gmea
P1 =
Z1 =
(17)
(18)
1
2p ´ Ro ´ C1
(19)
1
2p ´ R3 ´ C1
(20)
1
P2 =
type 2a
2p ´ R3 | | R ´ (C2 + COUT )
(21)
1
P2 =
type 2b
2p ´ R3 | | R ´ COUT
(22)
P2 =
1
type 1
2p ´ R ´ (C2 + COUT )
(23)
7.4 Device Functional Modes
7.4.1 Sequencing
The designer can implement many of the common power-supply sequencing methods using the SS/TR, EN, and
PWRGD pins. Implement the sequential method using an open-drain output of a power-on-reset pin of another
device. Figure 43 shows the sequential method using two TPS57140-EP devices. The power-good pin connects
to the EN pin on the TPS57140-EP, which enables the second power supply when the primary supply reaches
regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms startup delay. Figure 44 shows the results of Figure 43.
Figure 45 shows a method for a ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup
current source must be doubled in Equation 6. Figure 46 shows the results of Figure 45.
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Device Functional Modes (continued)
TPS57140-EP
EN
TPS57140-EP
PWRGD
EN
PWRGD
EN1
SS/TR
SS/TR
PWRGD1
VOUT1
VOUT2
Figure 43. Schematic for Sequential Start-Up Sequence
Figure 44. Sequential Start-Up Using EN and PWRGD
TPS57140-EP
3
EN
4
SS/TR
6
PWRGD
EN1, EN2
VOUT1
TPS57140-EP
3
EN
4
SS/TR
6
PWRGD
VOUT2
Figure 45. Schematic for Ratiometric Start-Up Using
Coupled SS/TR Pins
26
Figure 46. Ratiometric Start-Up Using Coupled SS/TR Pins
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Device Functional Modes (continued)
TPS57140-EP
EN
VOUT 1
SS/TR
PWRGD
TPS57140-EP
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 47. Schematic for Ratiometric and Simultaneous Start-Up Sequence
The designer can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor
network of R1 and R2 shown in Figure 47 to the output of the power supply that requires tracking, or to another
voltage reference source. Using Equation 24 and Equation 25, calculate values for the tracking resistors to
initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 26 is the voltage difference
between Vout1 and Vout2 at 95% of nominal output regulation.
The deltaV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR-toVSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the equations include Vssoffset and Iss as variables.
To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 24 through Equation 26 for deltaV. Equation 26 results in
a positive number for applications in which Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
Because the SS/TR pin must be below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, a
design requires careful selection of the tracking resistors to ensure the device restarts after a fault. Make sure
the calculated R1 value from Equation 24 is greater than the value calculated in Equation 27 to ensure the
device can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, Vssoffset becomes larger as
the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 24.
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Device Functional Modes (continued)
Vout2 + deltaV
Vssoffset
´
VREF
Iss
VREF ´ R1
R2 =
Vout2 + deltaV - VREF
deltaV = Vout1 - Vout2
R1 > 2800 ´ Vout1 - 180 ´ deltaV
R1 =
(24)
(25)
(26)
(27)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 48. Ratiometric Start-Up With VOUT2 Leading VOUT1
VOUT2
Figure 49. Ratiometric Start-Up With VOUT1 Leading VOUT2
EN
VOUT1
VOUT2
Figure 50. Simultaneous Start-Up With Tracking Resistor
28
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Device Functional Modes (continued)
7.4.2 Pulse-Skip Eco-mode Control Scheme
The TPS57140-EP enters the pulse-skip mode when the voltage on the COMP pin is the minimum clamp value.
The TPS57140-EP operates in a pulse-skip mode at light load currents to improve efficiency. The peak switch
current during the pulse-skip mode is the greater value of either 50 mA or the peak inductor current that is a
function of the minimum on-time, input voltage, output voltage, and inductance value. When the load current is
low and the output voltage is within regulation, the device enters a sleep mode and draws only 116 μA of input
quiescent current. While the device is in sleep mode, the output capacitor delivers the output power. As the load
current decreases, the time the output capacitor supplies the load current increases and the switching frequency
decreases, reducing gate-drive and switching losses. As the output voltage drops, the TPS57140-EP wakes up
from sleep mode and the power switch turns on to recharge the output capacitor, see Figure 51. The internal PLL
remains operating when in sleep mode. When operating at light load currents in pulse-skip mode, the switching
transitions occur synchronously with the external clock signal.
VOUT(ac)
IL
PH
Figure 51. Operation in Pulse-Skip Mode
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS57140-EP DC-DC converter is designed to provide up to a 1.5-A output from an input voltage source of
3.5 V to 42 V. The high-side MOSFET is incorporated inside the TPS57140-EP package along with the gatedrive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS57140-EP device to achieve
high efficiencies and helps keep the junction temperature low at high output currents. The compensation
components are external to the integrated circuit (IC), and an external divider allows for an adjustable output
voltage. Additionally, the TPS57140-EP device provides adjustable slow start and undervoltage-lockout inputs.
8.2 Typical Application
L1
10 µH
C1
U1
TPS57140QDGQREP
BOOT
VIN
C2
C3
C4
2.2 µF 2.2 µF 0.1 µF
R3
VIN
GND
EN
COMP
SS/TR
332 kΩ
RT/CLK
CSS
R4
61.9 kΩ
0.01 µF
D1
B220A
+
VSNS
CF
PWRGD
6.8 pF
COUT
VOUT
47 µF/6.3 V
PH
PwPd
8 to 18 V
3.3 V at 1.5 A
0.1 µF
RC
76.8 kΩ
RT
90.9 kΩ
CC
2700 pF
R1
31.6 kΩ
R2
10 kΩ
Figure 52. High-Frequency, 3.3-V Output Power-Supply Design With Adjusted UVLO
8.2.1 Design Requirements
This example details the design of a high-frequency switching regulator design using ceramic output capacitors.
The designer must know a few parameters in order to start the design process. The determination of these
parameters is typically at the system level. This example starts with the following known parameters in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
30
VALUE
Output voltage
3.3 V
Transient response, 0- to 1.5-A load step
ΔVout = 4%
Maximum output current
1.5 A
Input voltage
12-V nominal, 8 to 18 V
Output voltage ripple
<33 mVpp
Start input voltage (rising VIN)
7.25 V
Stop input voltage (falling VIN)
6.25 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user wants to choose the
highest switching frequency possible, because this produces the smallest solution size. The high switching
frequency allows for lower-valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that the designer can select has limits imposed by the
minimum on-time of the internal power switch, the input voltage, the output voltage, and the frequency-shift
limitation.
Use Equation 8 and Equation 9 to find the maximum switching frequency for the regulator; choose the lower
value of the two equations. Switching frequencies higher than this value result in pulse skipping or a lack of
overcurrent protection during a short circuit.
The typical minimum on-time, tonmin, is 130 ns for the TPS57140-EP. For this example, the output voltage is 3.3 V
and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when
including the inductor resistance, on-resistance, and diode voltage in Equation 8. To ensure overcurrent runaway
is not a concern during short circuits in the design, use Equation 9 or the solid curve in Figure 34 to determine
the maximum switching frequency. With a maximum input voltage of 20 V, assuming a diode voltage of 0.5 V,
inductor resistance of 100 mΩ, switch resistance of 200 mΩ, and an output current of 2.8 A, the maximum
switching frequency is approximately 1600 kHz.
Choosing the lower of the two values and adding some margin, this example uses a switching frequency of 1200
kHz. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in
Figure 32.
Resistor Rt sets the switching frequency as shown in Figure 52.
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts
the selection of the output capacitor, because the output capacitor must have a ripple-current rating equal to or
greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer;
however, the designer can use the following guidelines.
For designs using low-ESR output capacitors such as ceramics, use a value as high as KIND = 0.3. When using
higher-ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the
PWM control system, the inductor ripple current should always be >100 mA for dependable operation. In a wideinput voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor
to still have a measurable ripple current with the input voltage at its minimum.
For this design example, use KIND = 0.2 and the calculated minimum inductor value is 7.6 μH. For this design, the
choice was a nearest standard value of 10 μH. For the output filter inductor, it is important not to exceed the
RMS-current and saturation-current ratings. Find the RMS and peak inductor current from Equation 30 and
Equation 31.
For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen
inductor is a MSS6132-103. It has a saturation current rating of 1.64 A and an RMS current rating of 1.9 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch-current limit rather than the peak inductor current.
Vinmax - Vout
Vout
Lo min =
´
Io ´ KIND
Vinmax ´ ƒsw
(28)
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IRIPPLE £ IO ´ KIND
IL(rms) =
1
(29)
- VOUT ) ö
÷
÷
Vinmax ´ LO ´ fSW
ø
æ VOUT ´
(IO )2 + 12 ´ çç
è
(Vinmax
2
Iripple
ILpeak = Iout +
2
(30)
(31)
8.2.2.3 Output Capacitor
The three primary considerations for selecting the value of the output capacitor are: the output capacitor
determines the modulator pole, the output-voltage ripple, and how the regulator responds to a large change in
load current. Select the output capacitance based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for
the regulator where the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator also temporarily is not able to supply sufficient
output current if there is a large, fast increase in the current needs of the load, such as transitioning from no load
to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load
current and output voltage and adjust the duty cycle to react to the change. The output-capacitor size must be
adequate to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a
tolerable amount of droop in the output voltage. Calculate the minimum output capacitance necessary to
accomplish this using Equation 32.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 0 A (no
load) to 1.5 A (full load). For this example, ΔIout = 1.5 – 0 = 1.5 A and ΔVout = 0.04 × 3.3 V = 0.132 V. Using
these numbers gives a minimum capacitance of 18.9 μF. This value does not take the ESR of the output
capacitor into account in the output-voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that the designer must
take into account.
The catch diode of the regulator cannot sink current, so any stored energy in the inductor produces an output
voltage overshoot when the load current rapidly decreases, see Figure 53. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that is stored in the output capacitor increases the voltage on the capacitor. The capacitor
must be sized to maintain the desired output voltage during these transient periods. UseEquation 33 to calculate
the minimum capacitance to keep the output voltage overshoot to a desired value. For this example, the worstcase load step is from 1.5 to 0 A. The output voltage increases during this load transition, and the stated
maximum in our specification is 4% of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial
capacitor voltage, which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a
minimum capacitance of 25.3 μF.
Use Equation 34 to calculate the minimum output capacitance needed to meet the ripple specification for output
voltage. Equation 34 yields 0.7 μF.
Use Equation 35 to calculate the maximum ESR an output capacitor can have to meet the ripple specification for
the output voltage. Equation 35 indicates the ESR should be less than 147 mΩ.
The most stringent criterion for the output capacitor is 25.3 μF of capacitance to keep the output voltage in
regulation during an unload transient.
Factor in additional capacitance deratings for aging, temperature, and dc bias, increasing this minimum value.
For this example, select a 47-μF 6.3-V X7R ceramic capacitor with 5 mΩ of ESR.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets
specify the root-mean-square (RMS) value of the maximum ripple current. Use Equation 36 to calculate the RMS
ripple current that the output capacitor must support. For this application, Equation 36 yields 64.8 mA.
32
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COUT >
2 ´ DIOUT
fSW ´ DVOUT
where
•
•
•
ΔIout is the change in output current.
ƒSW is the switching frequency of the regulator.
ΔVout is the allowable change in the output voltage.
COUT > LO ´
((I )
((V )
OH
f
2
2
(32)
)
- (V ) )
- (IOL )2
i
2
where
•
•
•
•
•
COUT
L is the value of the inductor.
IOH is the output current under heavy load.
IOL is the output under light load.
VF is the final peak output voltage.
Vi is the initial capacitor voltage
(33)
1
1
>
´
8 ´ fSW æ VOUT(ripple ) ö
ç
÷
ç IRIPPLE ÷
è
ø
where
•
•
•
RESR =
ƒSW is the switching frequency.
Voripple is the maximum allowable output-voltage ripple.
Iripple is the ripple current of the inductor.
(34)
VOUT(ripple )
IRIPPLE
ICOUT(rms) =
(35)
(
VOUT ´ VIN(max ) - VOUT
)
12 ´ VIN(max ) ´ LO ´ fSW
(36)
8.2.2.4 Catch Diode
The TPS57140-EP requires an external catch diode between the PH pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be
greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes
are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of
the diode, the higher the efficiency of the regulator is.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Because the
design example has an input voltage up to 18 V, select a diode with a minimum of 20-V reverse voltage.
For the example design, Schottky diode selection is the B220A for its lower forward voltage, and it comes in a
larger package size, which has good thermal characteristics over small devices. The typical forward voltage of
the B220A is 0.5 V.
The diode selection must also have an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time multiplied by the
forward voltage of the diode equals the conduction losses of the diode. At higher switch frequencies, take the ac
losses of the diode into account. The ac losses of the diode are due to the charging and discharging of the
junction capacitance and reverse recovery. Use Equation 37 to calculate the total power dissipation, conduction
losses plus ac losses, of the diode.
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The B220A has a junction capacitance of 120 pF. Using Equation 37, the selected diode dissipates 0.632 W.
This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in the diode
when the input voltage is 18 V and the load current is 1.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD
(V
=
IN(max ) - VOUT
)´ I
OUT
VIN(max )
´ Vf d
2
C j ´ fSW ´ (VIN + Vf d)
+
2
(37)
8.2.2.5 Input Capacitor
The TPS57140-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF
of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any dcbias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS57140EP. Calculate the input-ripple current using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The designer can minimize the capacitance variations due to temperature by selecting a dielectric
material that is stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power
regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over
temperature. The designer must also take the dc bias into account for output capacitor selection. The
capacitance value of a capacitor decreases as the dc bias across a capacitor increases.
This example design requires a ceramic capacitor with at least a 20-V voltage rating to support the maximum
input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V,
and 100 V, so select a 25-V capacitor. For this example, the selection is two 2.2-μF, 25-V capacitors in parallel.
Table 2 shows a selection of high-voltage capacitors. The input capacitance value determines the input-voltage
ripple of the regulator. Calculate the input-voltage ripple using Equation 39. Using the design example values,
Ioutmax = 1.5 A, Cin = 4.4 μF, ƒSW = 1200 kHz, yields an input-voltage ripple of 71 mV and an RMS input-ripple
current of 0.701 A.
Icirms = Iout ´
Vout
´
Vin min
(Vin min
- Vout )
Vin min
Iout max ´ 0.25
ΔVin =
Cin ´ ¦ sw
34
(38)
(39)
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Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 10 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIELECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
8.2.2.6 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage-slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to charge the
capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor may make the
TPS57140-EP reach the current limit, or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Use Equation 40 to find the minimum slow start time, tSS, necessary
to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow-start
current of Issavg. In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing the
average input current to be 0.125 A would require a 1-ms slow-start time.
After the slow-start time is known, calculate the slow-start capacitor value using Equation 6. For the example
circuit, the slow-start time is not too critical, because the output capacitor value is 47 μF, which does not require
much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 1 ms,
which requires a 3.3-nF capacitor.
Cout ´ Vout ´ 0.8
Tss >
Issavg
(40)
8.2.2.7 Bootstrap Capacitor Selection
Connect a 0.1-μF ceramic capacitor between the BOOT and PH pins for proper operation. TI recommends using
a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage
rating.
8.2.2.8 UVLO Set Point
The designer can adjust the UVLO using an external voltage divider on the EN pin of the TPS57140-EP. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching when the input voltage increases above 7.25 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.25 V (UVLO stop).
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Set the programmable UVLO and enable voltages by using a resistor divider between Vin and ground to the EN
pin. Use Equation 2 through Equation 3 to calculate the resistance values necessary. For the example
application, 332 kΩ between Vin and EN and 61.9 kΩ between EN and ground are required to produce the 7.25and 6.25-V start and stop voltages.
8.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, the selected resistance for R2 is 10 kΩ. Using Equation 1, the calculated value of R1 is
31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current
flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values decreases
quiescent current and improves efficiency at low output currents, but may introduce noise-immunity problems.
8.2.2.10 Compensation
Several industry techniques are used to compensate dc-dc regulators. The method presented here yields high
phase margins. For most conditions, the regulator has a phase margin between 60° and 90°. The method
presented here ignores the effects of the slope compensation that is internal to the TPS57140-EP. Ignoring the
slope compensation usually causes the actual crossover frequency to be lower than the crossover frequency
used in the calculations.
Use SwitcherPro software for a more accurate design.
The uncompensated regulator has a dominant pole, typically located between 300 Hz and 3 kHz, due to the
output capacitor and load resistance, and a pole due to the error amplifier. One zero exists due to the output
capacitor and the ESR. The zero frequency is higher than either of the two poles.
If left uncompensated, the double pole created by the error amplifier and the modulator would lead to an unstable
regulator. Stabilizing the regulator requires one pole to be canceled out. One design approach is to locate a
compensating zero at the modulator pole. Then, select a crossover frequency that is higher than the modulator
pole. Calculate the gain of the error amplifier to achieve the desired crossover frequency. The capacitor used to
create the compensation zero, along with the output impedance of the error amplifier, forms a low-frequency pole
to provide a minus-one slope through the crossover frequency. Then, adding a compensating pole cancels the
zero due to the output-capacitor ESR. If the ESR zero resides at a frequency higher than the switching
frequency, then it can be ignored.
To compensate the TPS57140-EP using this method, first calculate the modulator pole and zero using the
following equations:
Ioutmax
¦p mod =
2 × p × Vout × Cout
where
•
•
•
Ioutmax is the maximum output current.
Cout is the output capacitance.
Vout is the nominal output voltage.
(41)
1
¦ z mod =
2 ´ p ´ Resr × Cout
(42)
For the example design, the location of the modulator pole is at 1.5 kHz and the ESR zero is at 338 kHz.
Next, the designer must select a crossover frequency which determines the bandwidth of the control loop. The
crossover-frequency location must be at a frequency at least 5× higher than the modulator pole. The crossoverfrequency selection must also be such that the available gain of the error amplifier at the crossover frequency is
high enough to allow for proper compensation.
Use Equation 47 to calculate the maximum crossover frequency when the ESR-zero location is at a frequency
that is higher than the desired crossover frequency. This is usually the case for ceramic or low-ESR tantalum
capacitors. Aluminum electrolytic and tantalum capacitors typically produce a modulator zero at a low frequency
due to their high ESR.
The example application uses a low-ESR ceramic capacitor with 10 mΩ of ESR, making the zero at 338 kHz.
36
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This value is much higher than typical crossover frequencies, so calculate the maximum crossover frequency
using both Equation 43 and Equation 46.
Using Equation 46 gives a minimum crossover frequency of 7.6 kHz and Equation 43 gives a maximum
crossover frequency of 45.3 kHz.
Arbitrarily select a crossover frequency of 45 kHz from this range.
Fc max £ 2100
Fc max £
Fc max £
Fc min
51442
Vout
Fpmod
Vout
for ceramic capacitors.
(43)
for Tantalum or Aluminum capacitors.
(44)
Fsw
for all cases.
5
³ 5 ´ Fpmod for all cases.
(45)
(46)
After selection of a crossover frequency, Fc, calculate the gain of the modulator at the crossover frequency using
Equation 47.
gm(PS ) ´ RLOAD ´ (2p ´ fC ´ COUT ´ RESR + 1)
GMOD( f c ) =
2p ´ fC ´ COUT ´ (RLOAD + RESR ) + 1
(47)
For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, calculate the
compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor
in parallel to these two components forms the compensating pole. However, calculating the values of these
components varies, depending on whether the ESR-zero location is above or below the crossover frequency. For
ceramic or low-ESR tantalum output capacitors, the zero location is usually above the crossover frequency. For
aluminum electrolytic and tantalum capacitors, the modulator-zero location is usually lower in frequency than the
crossover frequency. For cases where the modulator zero is higher than the crossover frequency (ceramic
capacitors):
VOUT
RC =
GMOD( f c ) ´ gm(EA ) ´ VREF
(48)
Cc =
1
p × Rc × ¦p mod
(49)
Co × Resr
C¦ =
Rc
(50)
For cases where the modulator zero is less than the crossover frequency (aluminum or tantalum capacitors), the
equations are:
VOUT
RC =
GMOD( f c ) ´ f Z(mod) ´ gm(EA ) ´ VREF
(51)
1
Cc =
p × Rc × ¦p mod
C¦ =
(52)
1
2 ´ p ´ Rc ´ ¦ z mod
(53)
For the example problem, the ESR-zero location is at a higher frequency compared to the crossover frequency,
so use Equation 50 through Equation 53 to calculate the compensation components. For the example problem,
the calculated components are: Rc = 76.2 kΩ, Cc = 2710 pF, and Cf = 6.17 pF.
The calculated value of the Cf capacitor is not a standard value, so use a value of 2700 pF. Use 6.8 pF for Cc.
The Rc resistor sets the gain of the error amplifier, which determines the crossover frequency. The calculated Rc
resistor is not a standard value, so use 76.8 kΩ.
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8.2.3 Application Curves
VIN
VO
VOUT
EN
IO
IL
Figure 53. Load Transmit
Figure 54. Startup With EN
VOUT
VOUT
IL
PH
VIN
IL
Figure 55. VIN Power Up
Figure 56. Output Ripple, CCM
VOUT
VOUT
IL
IL
PH
Figure 57. Output Ripple, DCM
38
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PH
Figure 58. Output Ripple, PSM
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SLVSD01B – SEPTEMBER 2015 – REVISED MAY 2019
VIN
VIN
IL
IL
PH
PH
Figure 60. Input Ripple, DCM
Figure 59. Input Ripple, CCM
95
VO = 3.3 V,
fsw = 1200 kHz
VI = 8 V
90
85
VIN
Efficiency - %
80
IL
VI = 12 V
75
VI = 16 V
70
65
PH
60
55
50
0
0.25
0.75
1
1.25
IL - Load Current - A
1.5
1.75
2
Figure 62. Efficiency vs Load Current
Figure 61. Input Ripple, PSM
1.015
60
150
VI = 12 V
1.010
40
100
Phase
1.005
0
Gain
0
-50
Regulation (%)
20
Phase - o
50
Gain - dB
0.50
1.000
0.995
-100
-20
0.990
-150
-40
100
1-103
1-104
f - Frequency - Hz
1-105
1-106
0.985
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Load Current - A
Figure 63. Overall Loop Frequency Response
Figure 64. Regulation vs Load Current
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1.015
IO = 0.5 A
1.010
Regulation (%)
1.005
1.000
0.995
0.990
0.985
5
10
15
20
VI - Input Voltage - V
Figure 65. Regulation vs Input Voltage
40
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9 Power Supply Recommendations
The input decoupling capacitors and bootstrap capacitor must be located as close as possible to the TPS57140EP. In addition, the voltage set-point resistor divider components must also be kept close to the IC. The voltage
divider network ties the output voltage to the point of regulation, the copper VOUT trace past the output
capacitors. Ensure that input power supply is clean. TI recommends adding an additional input bulk capacitor
depending on the board connection to the input supply.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. There are several signals paths that conduct quickly
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power-supply performance. To reduce these problems, bypass the VIN pin to ground with a lowESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the
bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66 for a PCB layout
example. Tie the GND pin directly to the thermal pad under the IC and the exposed thermal pad.
Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Route the
PH pin to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching
node, locate the catch diode and output inductor very close to the PH pins, and minimize the area of the PCB
conductor to prevent excessive capacitive coupling. For operation at full-rated load, the top-side ground area
must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise, so locate the RT resistor as
close as possible to the IC and route the traces to minimize their lengths. Place the additional external
components approximately as shown. It may be possible to obtain acceptable performance with alternate PCB
layouts; however, this layout produces good results and can serve as a guideline.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Output
Inductor
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 66. PCB Layout Example
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10.3 Power-Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under CCM operation. Do not use these
equations used if the device is working in DCM.
The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate-drive loss (Pgd), and
supply current (Pq).
Vout
Pcon = Io2 ´ RDS(on) ´
Vin
(54)
2
–9
PSW = VIN × fSW × IO × 0.25×10 sec/V
(55)
–9
Pgd = VIN × 3×10 Asec × fSW
(56)
Pq = 116µA × VIN
where
•
•
•
•
•
IOUT is the output current (A).
Rdson is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
ƒSW is the switching frequency (Hz).
(57)
So,
PTOT
Pcon
PSW
Pgd
Pq
(58)
For a given TA,
TJ TA R th u PTOT
(59)
For a given TJMAX = 150°C
7A(max) 7J(max) ± 5th u 3TOT
where
•
•
•
•
•
•
PTOT is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJ(max) is maximum junction temperature (°C).
TA(max) is maximum ambient temperature (°C).
(60)
There are additional power losses in the regulator circuit, due to the inductor ac and dc losses, the catch diode,
and trace resistance, that impact the overall efficiency of the regulator.
42
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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43
PACKAGE OPTION ADDENDUM
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1-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS57140MDRCREP
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
5714M
V62/15604-01YE
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
5714M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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1-May-2019
OTHER QUALIFIED VERSIONS OF TPS57140-EP :
• Automotive: TPS57140-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS57140MDRCREP
Package Package Pins
Type Drawing
VSON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS57140MDRCREP
VSON
DRC
10
3000
370.0
355.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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