Texas Instruments | TPS560200-Q1 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With Advanced Eco-mode™ (Rev. B) | Datasheet | Texas Instruments TPS560200-Q1 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With Advanced Eco-mode™ (Rev. B) Datasheet

Texas Instruments TPS560200-Q1 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With Advanced Eco-mode™ (Rev. B) Datasheet
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TPS560200-Q1
SLVSCW4B – APRIL 2016 – REVISED MAY 2019
TPS560200-Q1 4.5-V to 17-V Input, 500-mA Synchronous Step-Down Converter With
Advanced Eco-mode™
1 Features
3 Description
•
The TPS560200-Q1 is an 17-V, 500-mA, low-Iq,
adaptive on-time D-CAP2 mode synchronous
monolithic buck converter with integrated MOSFETs
in easy-to-use 8-pin MSOP package.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Temperature Range: Grade 1 -40°C to 125°C
– HBM ESD Classification: H2
– CDM ESD Classification: C4B
Integrated Monolithic 0.95-Ω High-Side and 0.33Ω Low-Side MOSFETs
500-mA Continuous Output Current
Output Voltage Range: 0.8 V to 6.5 V
0.8-V Voltage Reference With ±1.3% Accuracy
Over Temperature
Auto-Skip Advanced Eco-mode™ for High
Efficiency at Light Loads
D-CAP2™ Mode Enables Fast Transient
Responses
No External Compensation Needed
600-kHz Switching Frequency
2-ms Internal Soft Start
Safe Start-Up into Prebiased VOUT
Thermal Shutdown
–40°C to 125°C Operating Junction Temperature
Range
Available in 8-pin MSOP Package
The TPS560200-Q1 lets system designers complete
the suite of various end-equipment power bus
regulators with a cost-effective, low component count
and low standby current solution. The main control
loop for the device uses the D-CAP2 mode control
that provides a fast transient response with no
external compensation components. The adaptive ontime control supports seamless transition between
PWM mode at higher load conditions and advanced
Eco-Mode operation at light loads.
The TPS560200-Q1 also has a proprietary circuit that
enables the device to adopt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 17-V
VIN input. The output voltage can be programmed
between 0.8 V and 6.5 V. The device also features a
fixed 2-ms soft-start time. The device is available in
the 8-pin MSOP package.
Device Information(1)
PART NUMBER
TPS560200-Q1
2 Applications
•
•
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Electric Vehicle (EV) Charging Station
Infotainment System
Simplified Schematic
Lo
VIN
VIN
VOUT
PH
Cin
Co
R1
EN
VSENSE
R2
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS560200-Q1
SLVSCW4B – APRIL 2016 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2016) to Revision B
•
Editorial updates only; no technical changes ........................................................................................................................ 1
Changes from Original (April 2016) to Revision A
•
2
Page
Page
Changed the device status From: Preview To: Production ................................................................................................... 1
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5 Pin Configuration and Functions
DGK Package
8- Pin VSSOP
(Top View)
GND
PH
VIN
NC
8
7
6
5
1
2
3
4
EN
GND VSENSE NC
Pin Functions
PIN
NAME
EN
NO.
I/O
DESCRIPTION
1
I
2, 8
—
3
I
NC
4, 5
—
VIN
6
I
Supplies the control circuitry of the power converter
PH
7
O
The switch node
GND
VSENSE
Enable pin. Float to enable
Return for control circuitry and low-side power MOSFET
Converter feedback input. Connect to output voltage with feedback resistor divider
No connection inside, can be connected to any node or can be floating
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
19
V
EN
–0.3
7
V
VSENSE
–0.3
3
V
PH
–0.6
19
V
–2
21
V
±100
µA
PH 10-ns transient
EN
Source current
Sink current
PH
Current limit
A
PH
Current limit
A
Operating junction temperature
–40
150
Storage temperature, Tstg
–65
150
(1)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ES
D)
(1)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000, 2000 pins
(1)
±2000
Charged-device model (CDM), per AEC Q100-011, all pins
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI
Input voltage range
4.5
17
UNIT
V
TJ
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS560200-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 Pins
RθJA
Junction-to-ambient thermal resistance
184.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
76.8
°C/W
RθJB
Junction-to-board thermal resistance
106.0
°C/W
ψJT
Junction-to-top characterization parameter
14.4
°C/W
ψJB
Junction-to-board characterization parameter
104.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
17
V
4.35
4.5
V
SUPPLY VOLTAGE (VIN PIN)
VIN Operating input voltage
4.5
VIN Internal UVLO wakeup
VIN Rising
VIN Internal UVLO shutdown
VIN Fallling
3.9
4.15
VIN Shutdown supply current
EN = 0 V, VIN = 12 V
2.0
3.7
9
µA
VIN Operating – non switching supply current
VSENSE = 850 mV, VIN = 12 V
35
60
95
µA
1.16
1.29
V
V
ENABLE (EN PIN)
Enable threshold
Internal Soft-Start
Rising
Falling
1.05
VSENSE ramps from 0 V to 0.8 V
1.13
V
2
ms
OUTPUT VOLTAGE
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 5
mA, Pulse-Skipping
Voltage reference
0.796
0.804
0.812
V
25°C, VIN = 12 V, VOUT = 1.05 V, IOUT = 100
mA, Continuous current mode
0.792
0.800
0.808
V
VIN = 12 V, VOUT = 1.05 V, IOUT = 100 mA,
Continuous current mode
0.789
0.800
0.811
V
MOSFET
High-side switch resistance (1)
VIN = 12 V
0.50
0.95
1.50
Ω
Low-side switch resistance (1)
VIN = 12 V
0.20
0.33
0.55
Ω
LOUT = 10 µH, Valley current, VOUT = 1.05 V
570
670
795
mA
CURRENT LIMIT
Low-side switch sourcing current limit
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
160
°C
10
°C
ON-TIME TIMER CONTROL
On time
VIN = 12 V
Minimum off time
25°C, VSENSE = 0.5 V
130
165
200
ns
250
400
ns
63
69
%VREF
OUTPUT UNDERVOLTAGE PROTECTION
Output UVP threshold
Falling
Hiccup time
(1)
56
15
ms
Not production tested
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6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted).
6
100
EN = 0 V
Ivccsdn - Shutdown Current (µA)
ICC - Supply Current (µA)
80
60
40
20
5
4
3
2
1
0
0
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
0
50
100
150
TJ Junction Temperature (ƒC)
C001
Figure 1. Supply Current vs Junction Temperature
C002
Figure 2. Shutdown Current vs Junction Temperature
40
700
IOUT = 500mA
VOUT=1.05V
675
Switching Frequency (kHz)
EN Input Current (PA)
30
20
10
0
650
625
600
575
550
VOUT=1.05V
VOUT=1.8V
VOUT=3.3V
525
-10
500
0
2
4
6
EN Input Voltage (V)
8
10
4
6
8
VIN
D000
Figure 3. EN Input Current vs EN Input Voltage
10
12
14
Input Voltage (V)
16
18
D001
Figure 4. Switching Frequency vs Input Voltage
800
0.806
700
0.804
fSW
VSENSE Voltage (V)
Switching Frequency (kHz)
IO = 100 mA
600
500
400
300
0.802
0.800
0.798
0.796
200
Vout=1.05
Vout=1.8
Vout=3.3
100
0.794
±50
0
0
0.1
IOUT
0.2
0.3
Output Current (A)
0.4
50
100
TJ Junction Temperature (ƒC)
0.5
150
C006
D002
Figure 5. Switching Frequency vs Output Current
6
0
Figure 6. VSENSE Voltage vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS560200-Q1 is a 500-mA synchronous step-down (buck) converter with two integrated N-channel
MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the
output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use
of low-ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
VIN
VREF
VSENSE
HS
Drive
VSS
VREF
Soft
Start
EN
SSDONE
START
VIN
XCON
PH
UVLO
VREF
Control
Logic
VIN
LS
Drive
TON
One-Shot
PGND
AGND
GND
VTHERMAL
PH
Thermal
Shutdown
Bandgap
Reference
ZCD
ZCD
VREF
VREF
PGND
BGOK
LS
OCP
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS560200-Q1 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VOUT, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2 mode control.
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Feature Description (continued)
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS560200-Q1 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator.
The TPS560200-Q1 runs with a pseudo-constant frequency of 600 kHz by using the input voltage and output
voltage to set the on-time, one-shot timer. The on-time is inversely proportional to the input voltage and
proportional to the output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
7.3.3 Advanced Auto-Skip Eco-Mode Control
The TPS560200-Q1 is designed with advanced auto-skip Eco-Mode to increase higher light-load efficiency. As
the output current decreases from heavy-load condition, the inductor current is also reduced. If the output current
is reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in
Equation 1.
(V -V )×VOUT
1
IOUT(LL) =
× IN OUT
2×LOUT ×fsw
VIN
(1)
7.3.4 Soft-Start and Prebiased Soft-Start
The TPS560200-Q1 has an internal 2-ms soft-start. When the EN pin becomes high, internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS560200-Q1 contains a unique circuit to prevent current from being pulled from the output during start-up
if the output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal softstart becomes greater than feedback voltage VVSENSE), the controller slowly activates synchronous rectification by
starting the first low-side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VOUT) starts and
ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to
normal mode operation.
7.3.5 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the PH pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS560200-Q1
constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the lowside on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is
incremented per each switching cycle and the converter maintains the low-side switch on until the measured
voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and
a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current
is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This protection is nonlatching. When the VSENSE voltage becomes lower than 63% of the target
voltage, the UVP comparator detects it. After 7 µs detecting the UVP voltage, device shuts down and re-starts
after hiccup time.
8
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Feature Description (continued)
When the overcurrent condition is removed, the output voltage returns to the regulated value.
7.3.6 Thermal Shutdown
TPS560200-Q1 monitors the temperature of itself. If the temperature exceeds the threshold value
(typically 160°C), the device is shut off. This is nonlatch protection.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS560200-Q1 can operate in its normal switching modes. Normal continuous conduction mode (CCM) occurs
when the minimum switch current is above 0 A. In CCM, the TPS560200-Q1 operates at a quasi-fixed frequency
of 600 kHz.
7.4.2 Eco-Mode Operation
When the TPS560200-Q1 is in the normal CCM operating mode and the switch current falls to 0 A, the
TPS560200-Q1 begins operating in pulse-skipping Eco-Mode. Each switching cycle is followed by a period of
energy-saving sleep time. The sleep time ends when the VFB voltage falls below the Eco-Mode threshold
voltage. As the output current decreases the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS560200-Q1 is operating in either normal CCM or Eco-Mode, it may be placed in standby by
asserting the EN pin low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS560200-Q1 is used as a step-down converter which converts a voltage of 4.5 V to 17 V to a lower
voltage. WEBENCH® software is available to aid in the design and analysis of circuits.
8.2 Typical Application
U1
TPS560200
VIN 4.5-17V
6
C1
C2
10µF
0.1µF
1
3
VIN
PH
L1
VOUT 1.05V, 0.5 A
EN
VSENSE
GND
10µH
7
C3
C4
10µF
10µF
R1
6.19k
C5
open
R2
20.0k
2,8
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Figure 7. Typical Application Schematic
8.2.1 Design Requirements
For this design example, refer to the application parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUES
4.5 V to 17 V
1.05 V
Output current
500 mA
Output voltage ripple
30 mV/pp
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads, consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VSENSE input current are more noticeable.
R1´ 0.8 V
R2 =
VOUT -0.8V
(2)
8.2.2.2 Output Filter Selection
The output filter used with the TPS560200-Q1 is an LC circuit. This LC filter has double pole at:
F =
P
2p L
10
1
OUT
x COUT
(3)
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS560200-Q1. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 2.
Table 2. Recommended Component Values
C5
(pF)
L1
(µH)
Output Voltage
(V)
R1
(kΩ)
R2
(kΩ)
1.0
4.99
20.0
10
10 + 10
1.05
6.19
20.0
10
10 + 10
1.2
10.0
20.0
10
10 + 10
1.5
17.4
20.0
10
10 + 10
1.8
24.9
20.0
optional
10
10 + 10
2.5
42.2
20.0
optional
10
10 + 10
3.3
61.9
20.0
optional
10
10 + 10
5.0
105
20.0
optional
10
10 + 10
MIN
TYP
MAX
C3 + C4
(µF)
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feed-forward capacitor (C5) in parallel
with R1. The feed-forward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 600 kHz for
fSW.
Use 600 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
ILPP =
V
- VOUT
V
OUT x IN(max)
V
L
x fsw
IN(max)
OUT
(4)
ILPP
ILPEAK = IOUT +
2
IL
OUT (RMS)
=
IOUT 2 +
(5)
1
2
I
12 LPP
(6)
For this design example, the calculated peak current is 0.582 A and the calculated RMS current is 0.502 A. The
inductor used is a Würth 744777910 with a peak current rating of 2.6 A and an RMS current rating of 2 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS560200-Q1 is intended for
use with ceramic or other low-ESR capacitors. The recommended values are given in Table 2. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
IC
OUT (RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LOUT x fsw
(7)
For this design two MuRata GRM32DR61E106KA12L 10-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.047 A and each output capacitor is rated for 3 A.
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SLVSCW4B – APRIL 2016 – REVISED MAY 2019
www.ti.com
8.2.2.3 Input Capacitor Selection
The TPS560200-Q1 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF
capacitor (C2) from pin 6 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating must be greater than the maximum input voltage.
8.2.3 Application Curves
VIN = 12 V, VOUT = 1.05 V, TA = 25°C (unless otherwise noted).
100
90
90
80
80
70
60
Efficiency (%)
Efficiency (%)
70
60
50
40
50
40
30
30
20
20
VIN=5V
VIN=12V
10
VIN=5V
VIN=12V
10
0
0
0
100
200
300
Output Current (mA)
400
500
1
10
100
Output Current (mA)
D003
Figure 8. Efficiency
1.1025
1.071
1.05
1.0395
1.029
1.0185
VIN=5V
VIN=12V
1.008
1%/div
1.092
1.0815
Output Voltage (V)
1%/div
Output Voltage (V)
1.092
1.0605
D004
Figure 9. Light-Load Efficiency
1.1025
1.0815
1000
1.0605
1.071
1.05
1.0395
1.029
1.0185
1.008
0.9975
IOUT=0.25A
0.9975
0
100
200
300
Output Current (mA)
400
500
4
6
8
D005
Figure 10. Load Regulation
10
12
Input Voltage (V)
14
16
18
D013
Figure 11. Line Regulation
60
180
40
120
800
0
0
-20
-60
600
500
400
300
200
IOUT
Output Current (100mA/div)
60
Output Voltage (50mV/div)
20
Phase (degree)
Gain (dB)
700
VOUT (ac coupled)
100
-40
-120
Gain
Phase
-60
10 20
50 100
0
1000
10000
Frequency (Hz)
100000
-180
1000000
D006
Time (10Ps/div)
D007
Figure 13. Transient Response, 25% to 75% Load Step
Figure 12. Loop Response, IOUT = 0.25 A
12
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800
10.0
500
400
300
200
VEN
Output Voltage (500mV/div)
600
0
-5.0
1.5
1.0
0.5
100
0
0
-0.5
IOUT
VOUT
Time (10Ps/div)
Time (2ms/div)
D008
D009
Figure 14. Transient Response, 2% to 50% Load Step
Figure 15. Start-Up Relative to EN
VPH
VOUT (ac coupled)
PH Voltage (5V/div)
Output Voltage (20mV/div)
VOUT (ac coupled)
PH Voltage (5V/div)
Output Voltage (20mV/div)
EN Input Voltage (5V/div)
5.0
VOUT (ac coupled)
Output Current (100mA/div)
Output Voltage (50mV/div)
700
VPH
Time (1Ps/div)
Time (4Ps/div)
D010
Figure 16. Output Ripple, IOUT = 500 mA
D011
Figure 17. Output Ripple, IOUT = 30 mA
PH Voltage (5V/div)
Output Voltage (20mV/div)
VOUT (ac coupled)
VPH
Time (2ms/div)
D012
Figure 18. Output Ripple, IOUT = 0 mA
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TPS560200-Q1
SLVSCW4B – APRIL 2016 – REVISED MAY 2019
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9 Power Supply Recommendations
The TPS560200-Q1 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck
converters require the input voltage to be higher than the output voltage for proper operation. The maximum
recommended operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO /
0.75.
10 Layout
10.1 Layout Guidelines
The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Take care to minimize the
loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The typical
recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is
closest to the VIN and GND pins of the device. An additional high-frequency bypass capacitor may be added.
See for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. The
PH pin should be routed to a small copper area directly adjacent to the pin. Make the circulating loop from PH to
the output inductor, output capacitors and back to GND as tight as possible while preserving adequate etch width
to reduce conduction losses in the copper. Use vias adjacent to the IC to tie top-side ground copper plane to the
internal or bottom layer ground planes. The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate layout schemes; however, this layout
produced good results and is intended as a guideline.
10.2 Layout Example
OUTPUT
FILTER
CAPACITOR
GND
TO ENABLE
CONTROL
EN
GND
GND
PH
VSENSE
VIN
NC
NC
FEEDBACK
RESISTORS
OPTIONAL
FEED FORWARD
CAPACITOR
OUTPUT
INDUCTOR
VOUT
VIN
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
VIN
INPUT
BYPASS
CAPACITOR
VIA to Ground Plane
Figure 19. Layout Schematic
14
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Product Folder Links: TPS560200-Q1
TPS560200-Q1
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SLVSCW4B – APRIL 2016 – REVISED MAY 2019
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Eco-mode, D-CAP2, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS560200-Q1
15
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS560200QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZDNK
TPS560200QDGKTQ1
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
ZDNK
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2019
OTHER QUALIFIED VERSIONS OF TPS560200-Q1 :
• Catalog: TPS560200
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS560200QDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPS560200QDGKTQ1
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS560200QDGKRQ1
VSSOP
DGK
8
2500
366.0
364.0
50.0
TPS560200QDGKTQ1
VSSOP
DGK
8
250
366.0
364.0
50.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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