Texas Instruments | LMZ10505 5-A Power Module With 5.5-V Maximum Input Voltage (Rev. K) | Datasheet | Texas Instruments LMZ10505 5-A Power Module With 5.5-V Maximum Input Voltage (Rev. K) Datasheet

Texas Instruments LMZ10505 5-A Power Module With 5.5-V Maximum Input Voltage (Rev. K) Datasheet
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LMZ10505
SNVS633K – JANUARY 2010 – REVISED APRIL 2019
LMZ10505 5-A Power Module With 5.5-V Maximum Input Voltage
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
Integrated Shielded Inductor
Flexible Start-up Sequencing Using External SoftStart, Tracking, and Precision Enable
Protection Against In-Rush Currents and Faults
such as Input UVLO and Output Short-Circuit
Single Exposed Pad and Standard Pinout for Easy
Mounting and Manufacturing
Pin-to-Pin Compatible With
– LMZ10503 (3-A/15-W Maximum)
– LMZ10504 (4-A/20-W Maximum)
Fully Enable for WEBENCH® and Power Designer
Electrical Specifications
– 25-W Maximum Total Output Power
– Up to 5-A Output Current
– Input Voltage Range 2.95 V to 5.5 V
– Output Voltage Range 0.8 V to 5 V
– ±1.63% Feedback Voltage Accuracy Over
Temperature
– Efficiency up to 96%
Performance Benefits
– Operates at High Ambient Temperatures
– High Efficiency up to 96% Reduces System
Heat Generation
– Low Radiated Emissions (EMI) Tested to
EN55022 Class B Standard (EN 55022:2006,
+A1:2007, FCC Part 15 Subpart B: 2007. See
Table 9 and Layout for Information on Device
Under Test.)
– Passes 10-V/m Radiated Immunity EMI Tested
to Standard EN61000 4-3
– Fast Transient Response for Powering FPGAs
and ASICs
Create a Custom Design Using the LMZ10505
With the WEBENCH® Power Designer
Typical Application Circuit
VIN
VOUT
1
VIN
Cin
2
FB
SS
The LMZ10505 power module is a complete, easy-touse, DC-DC solution capable of driving up to a 5-A
load with exceptional power conversion efficiency,
output voltage accuracy, line and load regulation. The
LMZ10505 is available in an innovative package that
enhances thermal performance and allows for hand
or machine soldering.
The LMZ10505 can accept an input voltage rail
between 2.95 V and 5.5 V and can deliver an
adjustable and highly accurate output voltage as low
as 0.8 V. One megahertz fixed-frequency PWM
switching provides a predictable EMI characteristic.
Two external compensation components can be
adjusted to set the fastest response time, while
allowing the option to use ceramic or electrolytic
output capacitors. Externally programmable soft-start
capacitor
facilitates
controlled
start-up.
The
LMZ10505 is a reliable and robust solution with the
following features: lossless cycle-by-cycle peak
current limit to protect for overcurrent or short-circuit
fault, thermal shutdown, input undervoltage lockout,
and prebiased start-up.
Device Information(1)(2)
PART NUMBER
LMZ10505
PACKAGE
BODY SIZE (NOM)
TO-PMOD (7)
9.85 mm × 10.16 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See Design Summary
LMZ1xxx and LMZ2xxx Power Module Family (SNAA214) for
more details.
Efficiency VOUT = 3.3 V
CO
5
GND
4, EP
3
3 Description
VOUT
6, 7
LMZ10505
EN
•
•
Point-of-Load Conversions from 3.3-V and 5-V
Rails
Space-Constrained Applications
Noise-Sensitive Applications (Such as
Transceiver, Medical)
Rfbt
CSS
Rcomp
Ccomp
Rfbb
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ10505
SNVS633K – JANUARY 2010 – REVISED APRIL 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
8.3 System Examples ................................................... 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines .................................................
10.2 Layout Examples...................................................
10.3 Estimate Power Dissipation and Thermal
Considerations .........................................................
10.4 Power Module SMT Guidelines ............................
23
24
27
28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (June 2016) to Revision K
•
Page
Editorial changes only; no change to technical data ............................................................................................................. 1
Changes from Revision I (September 2015) to Revision J
Page
•
Changed language of WEBENCH list item; added additional content and links for WEBENCH further in data sheet ......... 1
•
Updated Equation 1 ............................................................................................................................................................. 10
Changes from Revision H (October 2013) to Revision I
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision G (April 2013) to Revision H
Page
•
Deleted 10 mils....................................................................................................................................................................... 4
•
Changed 10 mils................................................................................................................................................................... 23
•
Changed 10 mils................................................................................................................................................................... 27
•
Added Power Module SMT Guidelines................................................................................................................................. 28
2
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5 Pin Configuration and Functions
NDW Package
7-Lead TO-PMOD
Top View
Exposed Pad
Connect to GND
7
VOUT
6
VOUT
5
FB
4
GND
3
SS
2
EN
1
VIN
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
EN
2
Analog
Active-high enable input for the device.
Exposed Pad
—
Ground
Exposed pad is used as a thermal connection to remove heat from the device. Connect this
pad to the PCB ground plane in order to reduce thermal resistance value. EP must also
provide a direct electrical connection to the input and output capacitors ground terminals.
Connect EP to pin 4.
FB
5
Analog
Feedback pin. This is the inverting input of the error amplifier used for sensing the output
voltage. Keep the copper area of this node small.
GND
4
Ground
Power ground and signal ground. Provide a direct connection to the EP. Place the bottom
feedback resistor as close as possible to GND and FB pin.
SS
3
Analog
Soft-start control pin. An internal 2-µA current source charges an external capacitor
connected between SS and GND pins to set the output voltage ramp rate during start-up.
The SS pin can also be used to configure the tracking feature.
VIN
1
Power
Power supply input. A low-ESR input capacitance should be located as close as possible to
the VIN pin and exposed pad (EP).
6, 7
Power
The output terminal of the internal inductor. Connect the output filter capacitor between
VOUT pin and EP.
VOUT
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
VIN, VOUT, EN, FB, SS to GND
Power Dissipation
MIN
MAX
UNIT
–0.3
6
V
150
°C
245
°C
150
°C
Internally Limited
Junction Temperature
Peak Reflow Case Temperature (30 sec)
Storage Temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
For soldering specifications, refer to the Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM)
VALUE
UNIT
±2000
V
(1)
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Test method is per JESD22-AI14S.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN to GND
2.95
5.5
UNIT
V
Junction Temperature (TJ)
–40
125
°C
6.4 Thermal Information
LMZ10505
THERMAL METRIC (1)
NDW (TO-PMOD)
UNIT
7 PINS
RθJA
Junction-to-ambient thermal resistance (2)
20
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (no air flow)
1.9
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
RθJA measured on a 2.25-in × 2.25-in (5.8 cm × 5.8 cm) 4-layer board, with 1-oz. copper, thirty six thermal vias, no air flow, and 1-W
power dissipation. Refer to Layout Examples or Evaluation Board Application Note: AN-2022 LMZ1050x Evaluation Board (SNVA421).
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6.5 Electrical Characteristics
Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
SYSTEM PARAMETERS
V FB
Total Feedback
Voltage Variation
Including Line and
Load Regulation
VIN = 2.95 V to 5.5 V
VOUT = 2.5 V
IOUT = 0 A to 5 A
V FB
Feedback Voltage
Variation
VIN = 3.3 V, VOUT = 2.5
V
IOUT = 0 A
V FB
Feedback Voltage
Variation
VIN = 3.3 V, VOUT = 2.5
V
IOUT = 5 A
0.8
over the operating junction
temperature range TJ of
–55°C to 125°C
0.78
0.82
V
0.8
over the operating junction
temperature range TJ of
–55°C to 125°C
0.787
0.812
V
0.798
over the operating junction
temperature range TJ of
–55°C to 125°C
0.785
0.81
V
2.6
over the operating junction
temperature range TJ of
–55°C to 125°C
Rising
VIN(UVLO)
Input UVLO Threshold
(Measured at VIN pin)
Soft-Start Current
V
2.4
over the operating junction
temperature range TJ of
–55°C to 125°C
Falling
ISS
2.95
1.95
Charging Current
2
µA
1.55
IQ
Non-Switching Input
Current
ISD
Shutdown Quiescent
Current
IOCL
Output Current Limit
(Average Current)
VOUT = 2.5 V
fFB
Frequency Fold-back
In current limit
over the operating junction
temperature range TJ of
–55°C to 125°C
VFB = 1 V
3
mA
267
VIN = 5.5 V, VEN = 0 V
over the operating junction
temperature range TJ of
–55°C to 125°C
500
µA
7.3
over the operating junction
temperature range TJ of
–55°C to 125°C
5.1
8.7
250
A
kHz
PWM SECTION
1000
fSW
Switching Frequency
over the operating junction temperature range TJ of
–55°C to 125°C
750
1160
Drange
PWM Duty Cycle
Range
over the operating junction temperature range TJ of
–55°C to 125°C
0%
100%
kHz
ENABLE CONTROL
VEN-IH
EN Pin Rising
Threshold
VEN-IF
EN Pin Falling
Threshold
(1)
(2)
1.23
over the operating junction temperature range TJ of
–55°C to 125°C
1.8
V
1.06
over the operating junction temperature range TJ of
–55°C to 125°C
0.8
V
Minimum and maximum limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating
temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate
Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics (continued)
Specifications are for TJ = 25°C unless otherwise specified. Minimum and maximum limits are ensured through test, design,
or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. VIN = VEN = 3.3 V, unless otherwise indicated in the conditions column.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
THERMAL CONTROL
TSD
TJ for Thermal
Shutdown
TSD-HYS
Hysteresis for Thermal
Shutdown
145
°C
10
°C
PERFORMANCE PARAMETERS
ΔVOUT
Output Voltage Ripple
Refer to Table 1
VOUT = 2.5 V
Bandwidth Limit = 2 MHz
mVpk-pk
ΔVOUT
Output Voltage Ripple
Refer to Table 5 Bandwidth Limit = 20 MHz
ΔVFB / VFB
Feedback Voltage Line
Regulation
ΔVIN = 2.95 V to 5.5 V
IOUT = 0 A
0.04%
ΔVOUT /
VOUT
Output Voltage Line
Regulation
ΔVIN = 2.95 V to 5.5 V
IOUT = 0 A, VOUT = 2.5 V
0.04%
ΔVFB / VFB
Feedback Voltage
Load Regulation
IOUT = 0 A to 5 A
0.25%
ΔVOUT /
VOUT
Output Voltage Load
Regulation
IOUT = 0 A to 5 A
VOUT = 2.5 V
0.25%
VOUT = 3.3 V
96.1%
VOUT = 2.5 V
94.8%
VOUT = 1.8 V
93.1%
VOUT = 1.5 V
92%
VOUT = 1.2 V
90.4%
VOUT = 0.8 V
86.8%
VOUT = 2.5 V
95.75
VOUT = 1.8 V
94.1%
VOUT = 1.5 V
93.0%
VOUT = 1.2 V
91.6%
VOUT = 0.8 V
88.3%
VOUT = 3.3 V
93.1%
VOUT = 2.5 V
91.2%
VOUT = 1.8 V
88.5%
VOUT = 1.5 V
86.7%
VOUT = 1.2 V
84.1%
VOUT = 0.8 V
78.2%
VOUT = 2.5 V
89.8%
VOUT = 1.8 V
86.9%
VOUT = 1.5 V
85.1%
VOUT = 1.2 V
82.5%
VOUT = 0.8 V
76.2%
10
5
mVpk-pk
EFFICIENCY
η
η
η
η
6
Peak Efficiency (1A)
VIN = 5 V
Peak Efficiency (1A)
VIN = 3.3 V
Full Load Efficiency
(3A) VIN = 5 V
Full Load Efficiency
(3A) VIN = 3.3 V
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VOUT = 3.3 V
VOUT = 2.5 V
Figure 1. Efficiency
VOUT = 1.8 V
Figure 2. Efficiency
VOUT = 1.5 V
Figure 3. Efficiency
VOUT = 1.2 V
Figure 4. Efficiency
VOUT = 0.8 V
Figure 5. Efficiency
Figure 6. Efficiency
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VIN = 5 V, θJA = 20°C/W
VIN = 3.3 V, θJA = 20°C/W
Figure 7. Current Derating
Figure 8. Current Derating
VOUT = 2.5 V, IOUT = 0 A
VIN = 5 V, VOUT = 2.5 V, IOUT = 5 A Evaluation Board
Figure 9. Radiated Emissions (EN 55022, Class B)
VOUT = 2.5 V, IOUT = 0 A
Figure 10. Start-Up
VIN = 3.3 V, VOUT = 2.5 V, IOUT = 0.5-A to 4.5-A to 0.5-A step
20-MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
Figure 12. Load Transient Response
Figure 11. Prebiased Start-Up
8
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5 V, CIN is 47-µF 10-V X5R ceramic capacitor; TA =
25°C for efficiency curves and waveforms.
VIN = 5.0 V, VOUT = 2.5 V, IOUT = 0.5-A to 4.5-A to 0.5-A step
20-MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
VIN = 3.3 V, VOUT = 2.5 V, IOUT = 5 A, 20 mV/DIV
Refer to Table 5 for BOM
Figure 13. Load Transient Response
Figure 14. Output Voltage Ripple
VIN = 5.0 V, VOUT = 2.5 V, IOUT = 5 A,
20 mV/DIV Refer to Table 5 for BOM
Figure 15. Output Voltage Ripple
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7 Detailed Description
7.1 Overview
The LMZ10505 power module is a complete, easy-to-use DC-DC solution capable of driving up to a 5-A load
with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. The LMZ10505 is
available in an innovative package that enhances thermal performance and allows for hand or machine
soldering. The LMZ10505 is a reliable and robust solution with the following features: lossless cycle-by-cycle
peak current limit to protect for overcurrent or short-circuit fault, thermal shutdown, input undervoltage lockout,
and prebiased start-up.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Enable
The LMZ10505 features an enable (EN) pin and associated comparator to allow the user to easily sequence the
LMZ10505 from an external voltage rail, or to manually set the input UVLO threshold. The turnon or rising
threshold and hysteresis for this comparator are typically 1.23 V and 0.15 V, respectively. The precise reference
for the enable comparator allows the user to ensure that the LMZ10505 will be disabled when the system
demands it to be.
The EN pin should not be left floating. For always-on operation, connect EN to VIN.
7.3.2 Enable and UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level according to:
R
Renb
VIN(UVLO) 1.23 V u ent
Renb
(1)
For example, suppose that the required input UVLO level is 3.69 V. Choosing Renb = 10 kΩ, then we calculate
Rent = 20 kΩ.
10
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Feature Description (continued)
VIN
VIN
LMZ10505
Rent
Cin1
EN
Renb
GND
Figure 16. Setting Enable and UVLO
Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements
commonly found in FPGA and other multi-rail applications. Figure 17 shows an LMZ10505 that is sequenced to
start based on the voltage level of a master system rail (VOUT1).
Master Power Supply
VOUT1
VIN
VIN
VOUT2
VOUT
Rent
Cin1
LMZ10505
CO1
EN
Renb
GND
Figure 17. Setting Enable and UVLO Using External Power Supply
7.3.3 Soft-Start
The LMZ10505 begins to operate when both the VIN and EN, voltages exceed the rising UVLO and enable
thresholds, respectively. A controlled soft-start eliminates inrush currents during start-up and allows the user
more control and flexibility when sequencing the LMZ10505 with other power supplies.
In the event of either VIN or EN decreasing below the falling UVLO or enable threshold respectively, the voltage
on the soft-start pin is collapsed by discharging the soft-start capacitor by a 14-µA (typical) current sink to
ground.
7.3.4 Soft-Start Capacitor
Determine the soft-start capacitance with the following relationship:
t ss u Iss
CSS
VREF
where
•
•
•
VFB is the internal reference voltage (nominally 0.8 V),
ISS is the soft-start charging current (nominally 2 µA),
and CSS is the external soft-start capacitance.
(2)
Thus, the required soft-start capacitor per unit output voltage startup time is given by:
CSS 2.5 nF / ms
(3)
For example, a 4-ms soft-start time will yield a 10-nF capacitance. The minimum soft-start capacitance is 680 pF.
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Feature Description (continued)
7.3.5 Tracking
The LMZ10505 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS pin. In this way, the output voltage slew rate of the LMZ10505 will be controlled by a master supply for
loads that require precise sequencing. When the tracking function is used, a small value soft-start capacitor
should be connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit
fault.
Master Power
Supply
VOUT1
VIN
VIN
VOUT2
VOUT
Rtrkt
Cin1
EN
LMZ10505
CO1
SS
VSS
Rtrkb
GND
Figure 18. Tracking Using External Power Supply
7.3.6 Tracking - Equal Soft-Start Time
One way to use the tracking feature is to design the tracking resistor divider so that the master supply output
voltage, VOUT1, and the LMZ10505 output voltage, VOUT2, both rise together and reach their target values at the
same time. This is termed ratiometric start-up. For this case, the equation governing the values of tracking divider
resistors Rtrkb and Rtrkt is given by:
R trkt
R trkb
VOUT1 1.0 V
(4)
The above equation includes an offset voltage, of 200 mV, to ensure that the final value of the SS pin voltage
exceeds the reference voltage of the LMZ10505. This offset will cause the LMZ10505 output voltage to reach
regulation slightly before the master supply. For a value of 33 kΩ, 1% is recommended for Rtrkt as a compromise
between high precision and low quiescent current through the divider while minimizing the effect of the 2-µA softstart current source.
For example, if the master supply voltage VOUT1 is 3.3 V and the LMZ10505 output voltage was 1.8 V, then the
value of Rtrkb needed to give the two supplies identical soft-start times would be 14.3 kΩ. Figure 19 shows an
example of tracking using the equal soft-start time.
RATIOMETRIC STARTUP
VOUT1
VOLTAGE
VOUT2
EN
TIME
Figure 19. Timing Diagram for Tracking Using Equal Soft-Start Time
12
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Feature Description (continued)
7.3.7 Tracking - Equal Slew Rates
Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as
simultaneous start-up. In this case, the tracking resistors can be determined based on Equation 5:
0.8 V
R trkb
u R trkt
VOUT 2 0.8 V
(5)
and to ensure proper overdrive of the SS pin:
VOUT 2 0.8 u VOUT1
(6)
For the example case of VOUT1 = 5 V and VOUT2 = 2.5 V, with Rtrkt set to 33 kΩ as before, Rtrkb is calculated from
the above equation to be 15.5 kΩ. Figure 20 shows an example of tracking using the equal slew rates.
SIMULTANEOUS STARTUP
VOUT1
VOLTAGE
VOUT2
EN
TIME
Figure 20. Timing Diagram for Tracking Using Equal Slew Rates
7.3.8 Current Limit
When a current greater than the output current limit (IOCL) is sensed, the ON-time is immediately terminated and
the low-side MOSFET is activated. The low-side MOSFET stays on for the entire next four switching cycles.
During these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by
a current sink on the soft-start pin of nominally 14 µA. Subsequent overcurrent events will drain more and more
charge from the soft-start capacitor, effectively decreasing the reference voltage as the output droops due to the
pulse skipping. Reactivation of the soft-start circuitry ensures that when the overcurrent situation is removed, the
part will resume normal operation smoothly.
7.3.9 Overtemperature Protection
When the LMZ10505 senses a junction temperature greater than 145°C (typical), both switching MOSFETs are
turned off and the part enters a standby state. Upon sensing a junction temperature below 135°C (typical), the
part will re-initiate the soft-start sequence and begin switching once again.
7.4 Device Functional Modes
7.4.1 Prebias Start-Up Capability
At start-up, the LMZ10505 is in a prebiased state when the output voltage is greater than zero. This often occurs
in many multi-rail applications such as when powering an ASIC, FPGA, or DSP. The output can be prebiased in
these applications through parasitic conduction paths from one supply rail to another. Even though the
LMZ10505 is a synchronous converter, it will not pull the output low when a prebias condition exists. The
LMZ10505 will not sink current during start-up until the soft-start voltage exceeds the voltage on the FB pin.
Because the device does not sink current it protects the load from damage that might otherwise occur if current
is conducted through the parasitic paths of the load.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ10505 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 5 A. The following design procedure can be used to select
components for the LMZ10505. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
This section provides several application solutions with an associated bill of materials. The compensation for
each solution was optimized to work over the full input range. Many applications have a fixed input voltage rail. It
is possible to modify the compensation to obtain a faster transient response for a given input voltage operating
point.
U1
VIN
1
2
VOUT
6, 7
VOUT
VIN
CO1
LMZ10505
EN
5
FB
Cin1
SS
3
GND
4, EP
Rfbt
CSS
Rcomp
Ccomp
Rfbb
Figure 21. Typical Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist.
• VIN = 5 V
• VOUT = 2.5 V
• IOUT = 5 A
• ΔVOUT = 20 mVpk-pk
• ΔVo_tran = ±20 mVpk-pk
Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A,
Optimized for Electrolytic Input and Output Capacitance
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
U1
Power module
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
150 µF, 6.3 V, 18 mΩ
C2, 6.0 x 3.2 x 1.8 mm
Sanyo
6TPE150MIC2
1
CO1
330 µF, 6.3 V, 18 mΩ
D3L, 7.3 x 4.3 x 2.8
mm
Sanyo
6TPE330MIL
1
Rfbt
100 kΩ
0603
Vishay Dale
CRCW0603100KFKEA
1
14
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Typical Application (continued)
Table 1. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A,
Optimized for Electrolytic Input and Output Capacitance (continued)
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
Rfbb
47.5 kΩ
0603
Vishay Dale
CRCW060347K5FKEA
1
Rcomp
15 kΩ
0603
Vishay Dale
CRCW060315K0FKEA
1
Ccomp
330 pF, ±5%, C0G, 50 V
0603
TDK
C1608C0G1H331J
1
CSS
10 nF, ±10%, X7R, 16 V
0603
Murata
GRM188R71C103KA01
1
Table 2. Bill of Materials, VIN = 3.3 V, VOUT = 0.8 V, IOUT (MAX) = 5 A,
Optimized for Solution Size and Transient Response
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
U1
Power module
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1, CO1
47 µF, X5R, 6.3 V
1206
TDK
C3216X5R0J476M
2
Rfbt
110 kΩ
0402
Vishay Dale
CRCW0402100KFKED
1
Rcomp
1.0 kΩ
0402
Vishay Dale
CRCW04021K00FKED
1
Ccomp
27 pF, ±5%, C0G, 50 V
0402
Murata
GRM1555C1H270JZ01
1
CSS
10 nF, ±10%, X7R, 16 V
0402
Murata
GRM155R71C103KA01
1
8.2.2 Detailed Design Procedure
LMZ10505 is fully supported by WEBENCH and offers the following: component selection, performance,
electrical, and thermal simulations as well as the Build-It board, for a reduced design time. On the other hand, all
external components can be calculated by following the design procedure below.
1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient
requirements.
2. Determine the necessary input and output capacitance.
3. Calculate the feedback resistor divider.
4. Select the optimized compensation component values.
5. Estimate the power dissipation and board thermal requirements.
6. Follow the PCB design guideline.
7. Learn about the LMZ10505 features such as enable, input UVLO, soft-start, tracking, prebiased start-up,
current limit, and thermal shutdown.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ10504 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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8.2.2.2 Input Capacitor Selection
A 22-µF or 47-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage
is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed
pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PCB and supply
lines.
Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a
triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as
follows:
I
u Du (1 D)
Cin t OUT
fsw u ' VIN
where
•
D
the PWM duty cycle, D, is given by Equation 8:
(7)
VOUT
VIN
(8)
If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz
§ 2.5 V · § 2.5 V ·
5 Au ¨
¸ u ¨1 5 V ¸
© 5V ¹ ©
¹ t 25 P F
Cin t
1 MHz u 50mV
(9)
A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS
current rating of the input capacitor to a buck regulator can be estimated by:
ICin(RMS)
IOUT u D(1 D)
ICin(RMS)
5 Au
2.5 V §
2.5 V ·
1
¨
5V ©
5 V ¸¹
(10)
2.5 A
(11)
With this high AC current present in the input capacitor, the RMS current rating becomes an important
parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an
input capacitor rated for at least the maximum calculated ICin(RMS).
Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input
capacitance and parasitic inductance.
8.2.2.3 Output Capacitor Selection
In general, 22-µF to 100-µF high-quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum
output voltage is sufficient given the optimal high-frequency characteristics and low ESR of ceramic dielectrics.
Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density.
Two output capacitance equations are required to determine the minimum output capacitance. One equation
determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO
based on the load transient characteristics. Select the largest capacitance value of the two.
The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by
Equation 12:
' iL
CO t
8 u fsw u > ' VOUT ( ' iL u RESR )@
where
•
' iL
16
the peak to peak inductor current ripple (ΔiL) is equal to Equation 13:
(VIN VOUT ) u D
Lu fsw
(12)
(13)
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RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 1.5
µH, and fSW = 1 MHz. Therefore, per the design example:
V
(5 V 2.5 V) u 2.5
5V
' iL
833 mA
1.5 P H u 1 MHz
(14)
The minimum output capacitance requirement due to the PWM ripple voltage is:
833 mA
CO t
8 u 1 MHzu ª¬20 mV 833 mAu 3 m : º¼
(15)
CO t 6 P F
(16)
Three mΩ is a typical RESR value for ceramic capacitors.
Equation 17 provides a good first pass capacitance requirement for a load transient:
Istep u VFB u Lu VIN
CO t
4 u VOUT u (VIN VOUT ) u ' Vo_tran
where
•
•
•
Istep is the peak to peak load step (10% to 90% of the maximum load for this example),
VFB = 0.8 V,
and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV.
(17)
Therefore the capacitance requirement for the given design parameters is:
4 Au 0.8 Vu 1.5P Hu 5 V
CO t
4 u 2.5 Vu (5 V 2.5 V) u 20mV
(18)
CO t 48 P F
(19)
In this particular design the output capacitance is determined by the load transient requirements.
Table 3 lists some examples of commercially available capacitors that can be used with the LMZ10505.
Table 3. Recommended Output Filter Capacitors
CO (µF)
VOLTAGE (V), RESR (mΩ)
MAKE
MANUFACTURER
PART NUMBER
CASE SIZE
22
6.3, < 5
Ceramic, X5R
TDK
C3216X5R0J226M
1206
47
6.3, < 5
Ceramic, X5R
TDK
C3216X5R0J476M
1206
47
6.3, < 5
Ceramic, X5R
TDK
C3225X5R0J476M
1210
47
10.0, < 5
Ceramic, X5R
TDK
C3225X5R1A476M
1210
100
6.3, < 5
Ceramic, X5R
TDK
C3225X5R0J107M
1210
100
6.3, 50
Tantalum
AVX
TPSD157M006#0050
D, 7.5 × 4.3 × 2.9 mm
100
6.3, 25
Organic Polymer
Sanyo
6TPE100MPB2
B2, 3.5 × 2.8 × 1.9 mm
150
6.3, 18
Organic Polymer
Sanyo
6TPE150MIC2
C2, 6.0 × 3.2 × 1.8 mm
330
6.3, 18
Organic Polymer
Sanyo
6TPE330MIL
D3L, 7.3 × 4.3 × 2.8
mm
470
6.3, 23
Niobium Oxide
AVX
NOME37M006#0023
E, 7.3 × 4.3 × 4.1 mm
8.2.2.3.1 Output Voltage Setting
A resistor divider network from VOUT to the FB pin determines the desired output voltage as follows:
R
R fbb
VOUT 0.8 Vu fbt
R fbb
(20)
Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage.
Resistors are normally selected as 0.5% or 1% tolerance. Higher accuracy resistors such as 0.1% are also
available.
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The feedback voltage (at VOUT = 2.5 V) is accurate to within –2.5% / +2.5% over temperature and over line and
load regulation. Additionally, the LMZ10505 contains error nulling circuitry to substantially eliminate the feedback
voltage variation over temperature as well as the long-term aging effects of the internal amplifiers. In addition the
zero nulling circuit dramatically reduces the 1/f noise of the bandgap amplifier and reference. The manifestation
of this circuit action is that the duty cycle will have two slightly different but distinct operating points, each evident
every other switching cycle.
8.2.2.4 Loop Compensation
The LMZ10505 preserves flexibility by integrating the control components around the internal error amplifier while
utilizing three small external compensation components from VOUT to FB. An integrated type II (two pole, one
zero) voltage-mode compensation network is featured. To ensure stability, an external resistor and small value
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,
two zero) compensation network. The compensation components recommended in Table 4 provide type III
compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80
kHz. Calculated output capacitance values not listed in Table 4 should be verified before designing into
production. The AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER Power Module (SNVA417) is a
detailed application note that provides verification support. In general, calculated output capacitance values
below the suggested value will have reduced phase margin and higher control loop bandwidth. Output
capacitance values above the suggested values will experience a lower bandwidth and increased phase margin.
Higher bandwidth is associated with faster system response to sudden changes such as load transients. Phase
margin changes the characteristics of the response. Lower phase margin is associated with underdamped ringing
and higher phase margin is associated with overdamped response. Losing all phase margin will cause the
system to be unstable; an optimized area of operation is 30° to 60° of phase margin, with a bandwidth of 100
kHz ±20 kHz.
Figure 22. Loop Compensation Control Components
Table 4. LMZ10505 Compensation Component Values
VIN (V)
5
(1)
18
ESR (mΩ)
Rfbt (kΩ) (1)
Ccomp (pF) (1)
Rcomp (kΩ) (1)
20
200
27
1.5
20
124
68
1.4
1
10
82.5
150
0.681
150
1
5
63.4
220
1
150
10
25
63.4
220
3.48
150
26
50
226
62
12.1
220
15
30
150
100
6.98
220
31
60
316
560
14
CO (µF)
MIN
MAX
22
2
47
2
100
In the special case where the output voltage is 0.8 V, TI recommends to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III
compensation.
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Table 4. LMZ10505 Compensation Component Values (continued)
VIN (V)
3.3
CO (µF)
ESR (mΩ)
MIN
MAX
22
2
20
47
2
20
100
1
10
Rfbt (kΩ) (1)
Ccomp (pF) (1)
Rcomp (kΩ) (1)
118
43
9.09
76.8
100
3.32
49.9
180
2.49
150
1
5
40.2
330
1
150
10
25
43.2
330
4.99
150
26
50
143
100
7.5
220
15
30
100
180
4.99
220
31
60
200
100
8.06
8.2.3 Application Curves
VOUT = 3.3 V
VOUT = 3.3 V
Figure 23. Current Derating
Figure 24. Efficiency
Figure 25. Radiated Emissions (EN 55022, Class B)
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8.3 System Examples
8.3.1 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output With Optimized Ripple and Transient
Response
U1
Optional
VIN
1
2
Cin2
+
VOUT
VIN
EN
CO1
LMZ10505
Cin1
Ccomp
FB
5
CO3
CO2
Rfbt
GND
4, EP
SS
3
VOUT
6, 7
Rcomp
CSS
Optional
Rfbb
Figure 26. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 5. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A,
Optimized for Low Input and Output Ripple Voltage and Fast Transient Response
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
U1
Power module
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
22 µF, X5R, 10 V
1210
AVX
1210ZD226MAT
2
Cin2
220 µF, 10 V, AL-Elec
E
Panasonic
EEE1AA221AP
1*
CO1
4.7 µF, X5R, 10 V
0805
AVX
0805ZD475MAT
1*
CO2
22 µF, X5R, 6.3 V
1206
AVX
12066D226MAT
1*
CO3
100 µF, X5R, 6.3 V
1812
AVX
18126D107MAT
1
Rfbt
75 kΩ
0402
Vishay Dale
CRCW040275K0FKED
1
Rfbb
34.8 kΩ
0402
Vishay Dale
CRCW040234K8FKED
1
Rcomp
1.0 kΩ
0402
Vishay Dale
CRCW04021K00FKED
1
Ccomp
100 pF, ±5%, C0G, 50 V
0402
Murata
GRM1555C1H101JZ01
1
CSS
10 nF, ±10%, X7R, 16 V
0402
Murata
GRM155R71C103KA01
1
Table 6. Output Voltage Setting (Rfbt = 75 kΩ)
20
VOUT
Rfbb
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
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8.3.2 Application Schematic for 3.3-V to 5-V Input and 2.5-V Output
U1
VIN
1
VOUT
VIN
+
Cin4
Cin3
Cin2
Cin1
CO1
LMZ10505
Ren1
Cin5
VOUT
6, 7
2
FB
EN
SS
3
CO2
CO3
5
GND
4, EP
Rfbt
CSS
Rcomp
Ccomp
Rfbb
Figure 27. Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 7. Bill of Materials, VIN = 3.3 V to 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
U1
Power module
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
1 µF, X7R, 16 V
0805
TDK
C2012X7R1C105K
1
Cin2, CO1
4.7 µF, X5R, 6.3 V
0805
TDK
C2012X5R0J475K
2
Cin3, CO2
22 µF, X5R, 16 V
1210
TDK
C3225X5R1C226M
2
Cin4
47 µF, X5R, 6.3 V
1210
TDK
C3225X5R0J476M
1
Cin5
220 µF, 10 V, AL-Elec
E
Panasonic
EEE1AA221AP
1
CO3
100 µF, X5R, 6.3 V
1812
TDK
C4532X5R0J107M
1
Rfbt
75 kΩ
0805
Vishay Dale
CRCW080575K0FKEA
1
Rfbb
34.8 kΩ
0805
Vishay Dale
CRCW080534K8FKEA
1
Rcomp
1.1 kΩ
0805
Vishay Dale
CRCW08051K10FKEA
1
Ccomp
180 pF, ±5%, C0G, 50 V
0603
TDK
C1608C0G1H181J
1
Ren1
100 kΩ
0805
Vishay Dale
CRCW0805100KFKEA
1
CSS
10 nF, ±5%, C0G, 50 V
0805
TDK
C2012C0G1H103J
1
Table 8. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
Rfbb
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
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8.3.3 EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
U1
VIN
1
VOUT
VIN
VOUT
6, 7
CO1
LMZ10505
Cin3
Cin2
Cin1
2
FB
EN
SS
3
5
GND
4, EP
Rfbt
CSS
Rcomp
Ccomp
Rfbb
Figure 28. EMI Tested Schematic for 2.5-V Output Based on 3.3-V to 5-V Input
Table 9. Bill of Materials, VIN = 5 V, VOUT = 2.5 V, IOUT (MAX) = 5 A,
Tested With EN55022 Class B Radiated Emissions
DESIGNATOR
DESCRIPTION
CASE SIZE
MANUFACTURER
MANUFACTURER P/N
QUANTITY
U1
Power module
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
1 µF, X7R, 16 V
0805
TDK
C2012X7R1C105K
1
Cin2
4.7 µF, X5R, 6.3 V
0805
TDK
C2012X5R0J475K
1
Cin3
47 µF, X5R, 6.3 V
1210
TDK
C3225X5R0J476M
1
CO1
100 µF, X5R, 6.3 V
1812
TDK
C4532X5R0J107M
1
Rfbt
75 kΩ
0805
Vishay Dale
CRCW080575K0FKEA
1
Rfbb
34.8 kΩ
0805
Vishay Dale
CRCW080534K8FKEA
1
Rcomp
1.1 kΩ
0805
Vishay Dale
CRCW08051K10FKEA
1
Ccomp
180 pF, ±5%, C0G, 50 V
0603
TDK
C1608C0G1H181J
1
CSS
10 nF, ±5%, C0G, 50 V
0805
TDK
C2012C0G1H103J
1
Table 10. Output Voltage Setting (Rfbt = 75 kΩ)
22
VOUT
Rfbb
3.3 V
23.7 kΩ
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
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9 Power Supply Recommendations
The LMZ10505 device is designed to operate from an input voltage supply range between 2.95 V and 5.5 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the LMZ10505 supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is more than a few inches from the LMZ10505, additional bulk capacitance may
be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current
that does not overlap contains high di/dt, see Figure 29. Therefore physically place input capacitor (Cin1) as
close as possible to the LMZ10505 VIN pin and GND exposed pad to avoid observable high frequency noise
on the output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for
both the input and output capacitor should consist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed only to the
GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces.
If not properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be
located close to the FB pin. Since the FB node is high impedance, keep the copper area as small as
possible. This is most important as relatively high-value resistors are used to set the output voltage.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer
heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils
thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the
junction temperature below 125°C.
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10.2 Layout Examples
The PCB design is available in the LMZ10505 product folder at www.ti.com.
VIN
LMZ10505
VIN
VOUT
VOUT
High dI
dt
Cin1
CO1
GND
Loop 2
Loop 1
Figure 29. Critical Current Loops to Minimize
Top View
Thermal V ias
GND
GND
E XP OSE D P AD
1
2
3
4 5
6 7
VIN
SS
EN
FB
GND
VOUT
VOUT
CIN
VIN
RENT
CSS
RENB
COUT
VOUT
RFB T
CFF
RFB B
GND Plane
Figure 30. PCB Layout Guide
24
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Layout Examples (continued)
Figure 31. Top Copper
Figure 32. Internal Layer 1 (Ground)
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Layout Examples (continued)
Figure 33. Internal Layer 2 (Ground and Signal Traces)
Figure 34. Bottom Copper
26
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10.3 Estimate Power Dissipation and Thermal Considerations
Use the current derating curves in the Typical Characteristics section to obtain an estimate of power loss
(PIC_LOSS). For the design case of VIN = 5 V, VOUT = 2.5 V, IOUT = 5 A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the
device must see a thermal resistance from case to ambient (θCA) of less than:
TJ(MAX) TA(MAX)
TCA t
TJC
PIC_LOSS
(21)
TCA
O
125 O C 85 O C
C
1.9
1.36 W
W
O
27.5
C
W
(22)
Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typ.). Continuously operating at a
TJ greater than 125°C will have a shorten life span.
To reach θCA = 27.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat,
a good estimate of the required board area covered by 1-oz. copper on both the top and bottom metal layers is:
Board Area_cm 2 t
Board Area_cm 2 t
500 o Cu cm 2
u
W
T CA
500
o
27.5
C
W
o
u
Cu cm
W
(23)
2
(24)
As a result, approximately 18 square cm of 1-oz. copper on top and bottom layers is required for the PCB
design.
The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 8 mils thermal
vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an extended
discussion and formulations of thermal rules of thumb, refer to AN-2020 Thermal Design By Insight, Not
Hindsight (SNVA419). For an example of a high thermal performance PCB layout with θJA of 20°C/W, refer to the
evaluation board application note AN-2022 LMZ1050x Evaluation Board (SNVA421) and for results of a study of
the effects of the PCB designs, refer to AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE
SWITCHER Power Modules (SNVA424).
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10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness – 0.125 to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Maximum number of reflows allowed is one
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.
Figure 35. Sample Reflow Profile
Table 11. Sample Reflow Profile Table
28
PROBE
MAX TEMP
(°C)
REACHED
MAX TEMP
TIME ABOVE
235°C
REACHED
235°C
TIME ABOVE
245°C
REACHED
245°C
TIME ABOVE
260°C
REACHED
260°C
1
242.5
6.58
0.49
6.39
2
242.5
7.10
0.55
6.31
0.00
–
0.00
–
0.00
7.10
0.00
3
241.0
7.09
0.42
6.44
–
0.00
–
0.00
–
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ10505 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module (SNVA425)
• Absolute Maximum Ratings for Soldering (SNOA549)
• AN-2022 LMZ1050x Evaluation Board (SNVA421)
• AN-2013 LMZ1050x/LMZ1050xEXT SIMPLE SWITCHER Power Module (SNVA417)
• AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
• AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
• Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
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Community Resources (continued)
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
30
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LMZ10505
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11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMZ10505TZ-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
250
RoHS Exempt
& Green
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ10505
TZ-ADJ
LMZ10505TZE-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
45
RoHS Exempt
& Green
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ10505
TZ-ADJ
LMZ10505TZX-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
500
RoHS Exempt
& Green
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ10505
TZ-ADJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMZ10505TZ-ADJ/NOPB
LMZ10505TZX-ADJ/NOP
B
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TOPMOD
NDW
7
250
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
TOPMOD
NDW
7
500
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ10505TZ-ADJ/NOPB
TO-PMOD
NDW
7
250
367.0
367.0
45.0
LMZ10505TZX-ADJ/NOPB
TO-PMOD
NDW
7
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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