Texas Instruments | TPS2HB50-Q1 40-V, 50-mΩ Dual-Channel Smart High-Side Switch (Rev. A) | Datasheet | Texas Instruments TPS2HB50-Q1 40-V, 50-mΩ Dual-Channel Smart High-Side Switch (Rev. A) Datasheet

Texas Instruments TPS2HB50-Q1 40-V, 50-mΩ Dual-Channel Smart High-Side Switch (Rev. A) Datasheet
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TPS2HB50-Q1
SLVSDZ5A – FEBRUARY 2018 – REVISED APRIL 2019
1 Features
3 Description
•
•
The TPS2HB50-Q1 device is a dual-channel smart
high-side switch intended for use in 12-V automotive
systems. The device integrates robust protection and
diagnostic features to ensure output port protection
even during harmful events like short circuits in
automotive systems. The device protects against
faults through a reliable current limit, which,
depending on device variant, is adjustable from 1.6 A
to 18 A. The high current limit range allows for usage
in loads that require large transient currents, while the
low current limit range provides improved protection
for loads that do not require high peak current. The
device is capable of reliably driving various load
profiles.
1
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: TA = –40°C to
125°C ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
– Withstands 40-V load dump
Dual-channel smart high-side switch with 50-mΩ
RON (TJ = 25°C)
Improve system level reliability through adjustable
current limiting
– Current limit adjustable from 1.6 A to 18 A
Robust integrated output protection:
– Integrated thermal protection
– Protection against short to ground/battery
– Protection against reverse battery events
including automatic switch on with reverse
voltage
– Automatic shut off if loss of battery/ground
occurs
– Integrated output clamp to demagnetize
inductive loads
– Configurable fault handling
Analog sense output can be configured to
accurately measure:
– Load current
– Device temperature
Provides fault indication through SNS pin
– Detection of open load and short-to-battery
The TPS2HB50-Q1 also provides a high accuracy
analog current sense that allows for improved load
diagnostics. By reporting load current and device
temperature to a system MCU, the device enables
predictive maintenance and load diagnostics that
improves the system lifetime.
The TPS2HB50-Q1 is available in a HTSSOP
package which allows for reduced PCB footprint.
Device Information(1)
PART NUMBER
TPS2HB50-Q1
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VBAT /
Supply Voltage
DIA_EN
VBB
Bulbs
SEL1
SEL2
2 Applications
•
•
•
•
•
•
•
Infotainment display
ADAS modules
Heating elements:
– Seat heaters
– Glow plug
– Tank heaters
Transmission control unit
HVAC climate control
Body control modules
Incandescent and LED lighting
SNS
µC
VOUT1
Relays/Motors
ILIM1
ILIM2
Power Module:
Cameras, Sensors
LATCH
EN1
VOUT2
EN2
GND
General Resistive,
Capacitive, Inductive Loads
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
TPS2HB50-Q1 40-V, 50-mΩ Dual-Channel Smart High-Side Switch
TPS2HB50-Q1
SLVSDZ5A – FEBRUARY 2018 – REVISED APRIL 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
1
1
1
2
3
4
6.1 Recommended Connections for Unused Pins .......... 5
7
Specifications......................................................... 6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
SNS Timing Characteristics ...................................... 9
Switching Characteristics ........................................ 10
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
ADVANCE INFORMATION
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 27
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Application ............................................... 32
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 34
12.1 Layout Guidelines ................................................. 34
12.2 Layout Example .................................................... 35
13 Device and Documentation Support ................. 36
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
14 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
Changes from Original (February 2018) to Revision A
•
2
Page
Changes made throughout the data sheet ............................................................................................................................ 1
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5 Device Comparison Table
Table 1. TPS2HB50-Q1 Device Options
Part Number
Current Limit
Current Limit Range
Overcurrent Behavior
A
TPS2HB50A-Q1
Resistor Programmable
1.6 A - 8 A
Disable switch immediately
B
TPS2HB50B-Q1
Resistor Programmable
3.6 A - 18 A
Disable switch immediately
ADVANCE INFORMATION
Device
Version
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6 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
GND
1
16
DIA_EN
SNS
2
15
SEL2
LATCH
3
14
SEL1
13
EN2
EN1
4
ILIM1
5
12
ILIM2
VOUT1
6
11
VOUT2
VOUT1
7
10
VOUT2
VOUT1
8
9
VOUT2
VBB
Pin Functions
ADVANCE INFORMATION
PIN
NO.
NAME
I/O
DESCRIPTION
1
GND
—
Device ground
2
SNS
O
Sense output
3
LATCH
I
Sets fault handling behavior (latched or auto-retry)
4
EN1
I
Channel 1 control input, active high
5
ILIM1
O
Connect pull-up resistor to VBB to set current-limit threshold on CH1
6-8
VOUT1
O
Channel 1 output
9-11
VOUT2
O
Channel 2 output
12
ILIM2
O
Connect pull-up resistor to VBB to set current-limit threshold on CH2
13
EN2
I
Channel 2 control input, active high
14
SEL1
I
Diagnostics select 1
15
SEL2
I
Diagnostics select 2
16
DIA_EN
I
Diagnostic enable, active high
VBB
I
Power supply input
Exposed pad
4
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6.1 Recommended Connections for Unused Pins
The TPS2HB50-Q1 device is designed to provide an enhanced set of diagnostic and protection features.
However, if the system design only allows for a limited number of I/O connections, some pins may be considered
optional.
Table 2. Connections for Optional Pins
PIN NAME
CONNECTION IF NOT USED
IMPACT IF NOT USED
SNS
Ground through 1-kΩ resistor
LATCH
Float or ground through
RPROT resistor
ILIM1, ILIM2
Float
SEL1
Float or ground through
RPROT resistor
SEL1 selects the TJ sensing feature. With SEL1 unused, only CH1 and
CH2 current sensing and open load detection are available.
SEL2
Ground through RPROT
resistor
With SEL2 = 0 V, CH2 current sensing and CH2 open load detection are
not available.
DIA_EN
Float or ground through
RPROT resistor
With DIA_EN unused, the analog sense, open-load, and short-to-battery
diagnostics are not available.
Analog sense is not available.
With LATCH unused, the device will auto-retry after a fault. If latched
behavior is desired, but the system describes limited I/O, it is possible to
use one microcontroller output to control the latch function of several highside channels.
RPROT is used to protect the pins from excess current flow during reverse battery conditions, for more information
please see the section on Reverse Battery protection.
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ADVANCE INFORMATION
If the ILIMx pin is left floating, the device will be set to the default internal
current-limit threshold.
TPS2HB50-Q1
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Maximum continuous supply voltage, VBB
Load dump voltage, VLD
ISO16750-2:2010(E)
Reverse battery voltage, VRev, t ≤ 3 minutes
UNIT
36
V
40
V
–18
V
Enable pin voltage, VEN1 and VEN2
–1
7
V
LATCH pin voltage, VLATCH
–1
7
V
Diagnostic Enable pin voltage, VDIA_EN
–1
7
V
Sense pin voltage, VSNS
–1
18
V
Select pin voltage, VSEL1 and VSEL2
–1
ADVANCE INFORMATION
Reverse ground current, IGND
VBB < 0 V
Energy dissipation during turnoff, ETOFF
Energy dissipation during turnoff, ETOFF
7
mA
Single pulse, one channel, LOUT = 5 mH,
TJ,start = 125°C
TBD (2)
mJ
Repetitive pulse, one channel, LOUT = 5 mH,
TJ,start = 125°C
TBD (2)
mJ
150
°C
170
°C
150
°C
Maximum junction temperature, TJ
Maximum junction temperature - limited duration, TJ
t < 100 hours
Storage temperature, Tstg
(1)
(2)
V
–50
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
For further details, see the section regarding switch-off of an inductive load.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
Charged-device model (CDM), per AEC Q100-011
(1)
All pins except VBB and
VOUTx
±2000
VBB and VOUTx
±4000
All pins
±750
UNIT
V
AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
6
18
V
3
28
V
Enable voltage
–1
5.5
V
VLATCH
LATCH voltage
–1
5.5
V
VDIA_EN
Diagnostic Enable voltage
–1
5.5
V
VSEL1,
VSEL2
Select voltage
–1
5.5
V
VSNS
Sense voltage
TA
Operating free-air temperature
(1)
VBB
Nominal supply voltage
VBB
Extended supply voltage (2)
VEN1,
VEN2
(1)
(2)
6
UNIT
–1
7
V
–40
125
°C
All operating voltage conditions are measured with respect to device GND
Device will function within extended operating range, however some parametric values might not apply
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7.4 Thermal Information
TPS2HB50-Q1
THERMAL METRIC (1) (2)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
32.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
30.8
°C/W
RθJB
Junction-to-board thermal resistance
9.0
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
9.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see TI's SPRA953 application report.
The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
7.5 Electrical Characteristics
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDSCLAMP
VDS clamp voltage
38
46
V
VBBCLAMP
VBB clamp voltage
58
76
V
VUVLOF
VBB undervoltage lockout
falling
Measured with respect to the GND pin of the device
2.0
3
V
VUVLOR
VBB undervoltage lockout
rising
Measured with respect to the GND pin of the device
2.2
3
V
VBB = 13.5 V, TJ = 25°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
0.5
µA
ISB
Standby current (total
device leakage including
both MOSFET channels)
VBB = 13.5 V, TJ = 125°C,
VENx = VDIA_EN = 0 V, VOUT = 0 V
4
µA
ILNOM
Continuous load current,
per channel
IOUT(standby)
Output leakage current
(per channel)
Two channels enabled, TAMB = 70°C
One channel enabled, TAMB = 70°C
VBB = 13.5 V, TJ = 25°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
3
A
4.5
A
0.01
VBB = 13.5 V, TJ = 125°C
VENx = VDIA_EN = 0 V, VOUT = 0 V
0.5
µA
1.5
µA
IDIA
Current consumption in
diagnostic mode
VBB = 13.5 V, ISNS = 0 mA
VENx = 0 V, VDIA_EN = 5 V, VOUT = 0V
3
6
mA
IQ
Quiescent current
VBB = 13.5 V
VENx = VDIA_EN = 5 V, IOUTx = 0 A
3
6
mA
tSTBY
Standby mode delay time VENx = VDIA_EN = 0 V to standby
17
22
ms
12
ADVANCE INFORMATION
INPUT VOLTAGE AND CURRENT
RON CHARACTERISTICS
RON
RON(REV)
On-resistance
(Includes MOSFET and
package)
TJ = 25°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A
On-resistance during
reverse polarity
TJ = 25°C, -18 V ≤ VBB ≤ -7 V
50
TJ = 150°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A
TJ = 25°C, 3 V ≤ VBB ≤ 6 V, IOUT1 = IOUT2 > 1 A
mΩ
100
mΩ
75
mΩ
50
TJ = 105°C, -18 V ≤ VBB ≤ -7 V
mΩ
100
mΩ
CURRENT SENSE CHARACTERISTICS
KSNS
Current sense ratio
IOUTx / ISNS
IOUTX = 1 A
1500
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Electrical Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–4%
–4%
IOUT = 1 A
4%
–4%
4%
–10%
10%
–25%
25%
–35%
%
mA
0.033
IOUT = 50 mA
%
mA
0.067
IOUT = 100 mA
%
mA
0.2
IOUT = 300 mA
%
mA
0.667
VEN = VDIA_EN = 5 V,
VSEL1 = 0 V, VSEL2 = X
UNIT
mA
4%
2.000
IOUT = 3 A
ISNSI
MAX
4.000
IOUT = 6 A
Current sense current
and accuracy
TYP
%
mA
35%
%
TJ SENSE CHARACTERISTICS
ADVANCE INFORMATION
Temperature sense
current
ISNST
dISNST/dT
VDIA_EN = 5 V, VSEL1 = 5
V, VSEL2 = 0 V
TJ = -40°C
0.00
0.12
0.29
mA
TJ = 25°C
0.68
0.85
1.02
mA
TJ = 85°C
1.25
1.52
1.79
mA
TJ = 125°C
1.61
1.96
2.31
mA
TJ = 150°C
1.80
2.25
2.70
Coefficient
0.011
mA
mA/°C
SNS CHARACTERISTICS
ISNSFH
ISNS fault high-level
VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X
ISNSleak
ISNS leakage
VDIA_EN = 0 V
4
4.5
5.3
mA
1
µA
CURRENT LIMIT CHARACTERISTICS
Device Version A, TJ =
-40°C to 150°C
ICL
Current Limit Threshold
Device Version B, TJ =
-40°C to 150°C
KCL
Current Limit Ratio
RILIM = GND, open, or
out of range
11.8
A
RILIM = 5 kΩ
6.2
8
9.36
A
RILIM = 25 kΩ
1.4
1.6
2.28
A
RILIM = GND, open, or
out of range
27
A
RILIM = 5 kΩ
13.68
18
21.6
RILIM = 25 kΩ
A
2.96
3.6
4.44
Version A
31
40
57
A * kΩ
A
Version B
68.4
90
111
A * kΩ
2
3
4
V
300
500
700
µs
50
µs
50
µs
FAULT CHARACTERISTICS
Open-load (OL) detection
VENx = 0 V, VDIA_EN = 5 V
voltage
VOL
OL and STB indicationtime from ENx falling
tOL1
VENx = 5 V to 0 V, VDIA_EN = 5 V, VSEL1 = 0 V
IOUT = 0 mA, VOUTx = 4 V
(1)
(1)
tOL2
OL and STB indicationtime from DIA_EN rising
VENx = 0 V, VDIA_EN = 0 V to 5 V, VSEL1 = 0 V
IOUT = 0 mA, VOUTx = 4 V
tOL3
OL and STB indicationtime from VOUT rising
VENx = 0 V, VDIA_EN = 5 V, VSEL1 = 0 V (1)
IOUT = 0 mA, VOUTx = 0 V to 4 V
TABS
Thermal shutdown
TREL
Relative thermal
shutdown
50
°C
THYS
Thermal shutdown
hysteresis
28
°C
(1)
8
150
°C
SELx must be set to select the relevant channel. Diagnostics are performed on Channel 1 when SELx = 00 and diagnostics are
performed on channel 2 when SELx =01
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Electrical Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tFAULT
Fault shutdown
indication-time
VDIA_EN = 5 V
Time between switch shutdown and ISNS settling at
ISNSFH
tRETRY
Retry time
Time from fault shutdown until switch re-enable
(thermal shutdown or current limit).
EN1 AND EN2 PIN CHARACTERISTICS
Input voltage low-level
No GND network diode
VIH,
Input voltage high-level
No GND network diode
VIHYS,
ENx
2
MAX
UNIT
50
µs
3
ms
0.8
2
Input voltage hysteresis
Internal pulldown resistor
0.5
IIL, EN
Input current low-level
VEN = 0.8 V
IIH,
Input current high-level
VEN = 5 V
V
V
350
RENx
EN
1
TYP
(2)
VIL, ENx
ENx
MIN
1
mV
2
MΩ
0.8
µA
5
µA
DIA_EN PIN CHARACTERISTICS (2)
Input voltage low-level
No GND network diode
VIH,
Input voltage high-level
No GND network diode
DIA_EN
VIHYS,
0.8
2.0
Input voltage hysteresis
200
V
ADVANCE INFORMATION
VIL, DIA_EN
V
350
530
mV
1
2
MΩ
DIA_EN
RDIA_EN
Internal pulldown resistor
IIL, DIA_EN
Input current low-level
VDIA_EN = 0.8 V
IIH,
Input current high-level
VDIA_EN = 5 V
DIA_EN
0.5
0.8
µA
5
µA
SEL1 AND SEL2 PIN Characteristics
VIL, SELx
Input voltage low-level
No GND network diode
VIH,
Input voltage high-level
No GND network diode
SELx
VIHYS,
SELx
Input voltage hysteresis
Internal pulldown resistor
IIL, SELX
Input current low-level
VSELX = 0.8 V
IIH,
Input current high-level
VSELX = 5 V
LATCH PIN CHARACTERISTICS
0.5
V
V
350
RSELx
SELX
0.8
2
1
mV
2
MΩ
0.8
µA
5
µA
(2)
VIL, LATCH
Input voltage low-level
No GND network diode
VIH, LATCH
Input voltage high-level
No GND network diode
0.8
VIHYS,
Input voltage hysteresis
200
350
530
mV
RLATCH
Internal pulldown resistor
0.5
1
2
MΩ
IIL, LATCH
Input current low-level
VLATCH = 0.8 V
IIH,
Input current high-level
VLATCH = 5 V
2
V
V
LATCH
(2)
LATCH
0.8
µA
5
µA
VBB = 3 V to 28 V
7.6 SNS Timing Characteristics
VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
tSNSION1
Settling time from rising edge of DIA_EN
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
tSNSION2
Settling time from rising edge of ENx and
DIA_EN
tSNSION3
Settling time from rising edge of ENx
40
µs
VENx = VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
165
µs
VENx = 0 V to 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, RL ≤ 6 Ω
165
µs
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SNS Timing Characteristics (continued)
VBB = 6 V to 18 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSNSIOFF1
Settling time from falling edge of DIA_EN
VENx = 5 V, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ, RL ≤ 6 Ω
20
µs
tSETTLEH
Settling time from rising edge of load step
VEN1 = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 5 A to 1 A
20
µs
tSETTLEL
Settling time from falling edge of load step
VENx = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 5 A to 1 A
20
µs
SNS TIMING - TEMPERATURE SENSE
tSNSTON1
Settling time from rising edge of DIA_EN
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
40
µs
tSNSTON2
Settling time from rising edge of DIA_EN
VENx = 0 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ
70
µs
tSNSTOFF
Settling time from falling edge of DIA_EN
VENx = X, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ
20
µs
VENx = X, VDIA_EN = 5 V
VSEL1 = 5 V to 0 V, VSEL2 = X
RSNS = 1 kΩ, RL ≤ 6 Ω
60
µs
20
µs
60
µs
SNS TIMING - MULTIPLEXER
ADVANCE INFORMATION
Settling time from temperature sense to
current sense
VENx = X, VDIA_EN = 5 V
Settling time from current sense on CHx to
VSEL1 = 0 V, VSEL2 = 0 V to 5 V
CHy
RSNS = 1 kΩ, IOUT1 = 2 A, IOUT2 = 4 A
tMUX
Settling time from current sense to
temperature sense
VENx = X, VDIA_EN = 5 V
VSEL1 = 0 V to 5 V, VSEL2 = X
RSNS = 1 kΩ, RL ≤ 6 Ω
7.7 Switching Characteristics
VBB = 13.5 V, TJ = -40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tDR
Turnon delay time
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 10% VOUT rising
20
60
100
µs
tDF
Turnoff delay time
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
falling to 90% VOUT Falling
20
60
100
µs
SRR
VOUTx rising slew rate
VBB = 13.5 V, 20% to 80% of VOUT,
RL ≤ 6 Ω
0.1
0.4
0.7
V/µs
SRF
VOUTx falling slew rate
VBB = 13.5 V, 80% to 20% of VOUT,
RL ≤ 6 Ω
0.1
0.4
0.7
V/µs
tON
Turnon time
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 80% VOUT rising
39
87
145
µs
tOFF
Turnoff time
VBB = 13.5 V, RL ≤ 6 Ω, 50% EN
rising to 80% VOUT rising
39
87
147
µs
tON - tOFF
Turnon and turnoff matching
200-µs enable pulse
–50
0
50
µs
EON
Switching energy losses during
turnon
VBB = 13.5 V, RL ≤ 6 Ω
0.4
mJ
EOFF
Switching energy losses during
turnoff
VBB = 13.5 V, RL ≤ 6 Ω
0.4
mJ
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VEN(1)
50%
50%
90%
90%
tDR
tDF
VOUT
10%
tON
(1)
ADVANCE INFORMATION
10%
tOFF
Rise and fall time of VENx is 100 ns.
Figure 1. Switching Characteristics Definitions
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VEN1
VDIA_EN
IOUT1
ISNS
ADVANCE INFORMATION
tSNSION1
tSNSION2
tSETTLEH
tSETTLEL
tSNSTON1
tSNSTON2
tSNSION3
tSNSIOFF1
VEN1
VDIA_EN
IOUT1
ISNS
VEN1
VDIA_EN
TJ
ISNS
tSNSTOFF
NOTE1: Rise and fall times of control signals are 100 ns. Control signals include: EN1, EN2, DIA_EN, SEL1, SEL2.
NOTE2: SEL1 and SEL2 must be set to the appropriate values.
Figure 2. SNS Timing Characteristics Definitions
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8 Parameter Measurement Information
Figure 3. Parameter Definitions
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9 Detailed Description
9.1 Overview
The TPS2HB50-Q1 device is a dual-channel smart high-side switch intended for use with 12-V automotive
batteries. Many protection and diagnostic features are integrated in the device.
Diagnostics features include the analog SNS output that is capable of providing a signal that is proportional to
load current or device temperature. The high-accuracy load current sense allows for diagnostics of complex
loads.
This device includes protection through thermal shutdown, current limiting, transient withstand, and reverse
battery operation. For more details on the protection features, refer to the Feature Description and Application
Information sections of the document.
The TPS2HB50-Q1 is one device in a family of TI high side switches. For each device, the part number indicates
elements of the device behavior. Figure 4 gives an example of the device nomenclature.
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Figure 4. Naming Convention
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9.2 Functional Block Diagram
VBB
VBB to GND
Clamp
Internal Power
Supply
VBB to VOUT
Clamp
GND
VOUT1
Gate Driver
EN1
Power FET
Channel 1/2
EN2
VOUT2
LATCH
Current Limit
ILIM1
ADVANCE INFORMATION
Thermal
Shutdown
ILIM2
Open-load /
Short-to-Bat
Detection
DIA_EN
SEL1
SEL2
Fault Indication
SNS
SNS Mux
Current Sense
Temperature
Sense
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9.3 Feature Description
9.3.1 Protection Mechanisms
The TPS2HB50-Q1 is designed to operate in the automotive environment. The protection mechanisms allow the
device to be robust against many system-level events such as load dump, reverse battery, short-to-ground, and
more.
There are two protection features which, if triggered, will cause the switch to automatically disable:
• Thermal Shutdown
• Current Limit
When any of these protections are triggered, the device will enter the FAULT state. In the FAULT state, the fault
indication will be available on the SNS pin (see the Diagnostic Mechanisms section of the data sheet for more
details).
The switch is no longer held off and the fault indication is reset when all of the below conditions are met:
• LATCH pin is low
• tRETRY has expired
• All faults are cleared (thermal shutdown, current limit)
ADVANCE INFORMATION
NOTE
CH1 and CH2 operate independently. If there is a fault on one channel, the other channel
is not affected.
9.3.1.1 Thermal Shutdown
The device includes a temperature sensor on each power FET and also within the controller portion of the
device. There are two cases that the device will consider to be a thermal shutdown fault:
• TJ,FET > TABS
• (TJ,FET – TJ,controller) > TREL
After the fault is detected, the relevant switch will turn off. Each channel is turned off based on the measurement
of temperature sensor for that channel. Therefore, if the thermal fault is detected on only one channel, the other
channel continues operation. If TJ,FET passes TABS, the fault is cleared when the switch temperature decreases
by the hysteresis value, THYS. If instead the TREL threshold is exceeded, the fault is cleared after TRETRY passes.
9.3.1.2 Current Limit
When IOUT reaches the current limit threshold, ICL, the channel will switch off immediately. The ICL value will vary
with slew rate and a fast current increase that occurs during a powered-on short circuit can temporarily go above
the specified ICL value. When the switch is in the FAULT state it will output an output current ISNSFH on the SNS
pin.
During a short circuit event, the device will hit the ICL value that is listed in the Electrical Characteristics table (for
the given device version and RILIM) and then turn the output off to protect the device. The device will register a
short circuit event when the output current exceeds ICL, however the measured maximum current may exceed
the ICL value due to the TPS2HB50-Q1 deglitch filter and turn-off time. The device is guaranteed to protect itself
during a short circuit event up to 24 V at 125°C.
9.3.1.2.1 Current Limit Foldback
Version B of the TPS2HB50-Q1 implements a current limit foldback feature that is designed to protect the device
in the case of a long-term fault condition. If the device undergoes fault shutdown events (either of thermal
shutdown or current limit) seven consecutive times, the current limit will be reduced to half of the original value.
The device will revert back to the original current limit threshold if either of the following occurs:
• The device goes to standby mode.
• The switch turns on and turns off without any fault occurring.
Version A does not implement the current limit foldback due to the lower current limit causing less harm during
repetitive long-term faults.
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Feature Description (continued)
9.3.1.2.2 Programmable Current Limit
The TPS2HB50-Q1 includes an adjustable current limit. Some applications (for example, incandescent bulbs) will
require a high current limit. Other applications can benefit from a lower current limit threshold. In general,
wherever possible a lower current limit is recommended due to allowing system advantages through:
• Reduced size and cost in current carrying components such as PCB traces and module connectors
• Less disturbance at the power supply (VBB pin) during a short circuit event
• Improved protection of the downstream load
To set the current limit threshold, connect a resistor from ILIM to VBB. The current limit threshold is determined by
Equation 1 (RILIM in kΩ):
ICL = KCL / RILIM
(1)
NOTE
Capacitance on the ILIM pin can cause ILIM to go out of range during short circuit events.
For accurate current limiting, place RILIM near to the device with short traces to ensure <5
pF capacitance to GND on the ILIM pin.
9.3.1.2.3 Undervoltage Lockout (UVLO)
The device monitors the supply voltage VBB to prevent unpredicted behaviors in the event that the supply voltage
is too low. When the supply voltage falls down to VUVLOF, the output stage is shut down automatically. When the
supply rises up to VUVLOR, the device turns back on.
During an initial ramp of VBB from 0 V at a ramp rate slower than 1 V/ms, VEN pin will have to beBB held low until
VBB is above UVLO threshold (with respect to board ground) and the supply voltage to the device has reliably
reached above the UVLO condition. For best operation, ensure that V has risen above UVLO before setting the
VEN pin to high.
9.3.1.2.4 VBB During Short-to-Ground
When VOUT is shorted to ground, the module power supply (VBB) can have a transient decrease. This is caused
by the sudden increase in current flowing through the wiring harness cables. To achieve ideal system behavior, it
is recommended that the module maintain VBB > 3 V (above the maximum VUVLOF) during VOUT short-to-ground.
This is typically accomplished by placing bulk capacitance on the power supply node.
9.3.1.3 Voltage Transients
The TPS2HB50-Q1 device describes two types of voltage clamps which protect the FET against system-level
voltage transients. The two different clamps are shown in Figure 5.
The clamp from VBB to GND is primarily used to protect the controller from positive transients on the supply line
(for example, ISO7637-2). The clamp from VBB to VOUT is primarily used to limit the voltage across the FET when
switching off an inductive load. If the voltage potential from VBB to GND exceeds the VBB clamp level, the clamp
will allow current to flow through the device from VBB to GND (Path 2). If the voltage potential from VBB to VOUT
exceeds the clamping voltage, the power FET will allow current to flow from VBB to VOUT (Path 3). Additional
capacitance from VBB to GND can increase the reliability of the system during ISO 7637 pulse 2A testing.
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The RILIM range is between 5 kΩ and 25 kΩ. An RILIM resistor is required, however in the fault case where the pin
is floating, grounded, or outside of this range the current limit will default to an internal level that is defined in the
Specifications section of this document.
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Feature Description (continued)
Ri
Positive Supply Transient
(e.g. ISO7637 pulse 2a/3b)
(1)
VBB
VDS
Clamp
(3)
(2)
Controller
VBB
Clamp
VOUT
Load
GND
ADVANCE INFORMATION
Figure 5. Current Path During Supply Voltage Transient
9.3.1.3.1 Load Dump
The TPS2HB50-Q1 device is tested according to ISO 16750-2:2010(E) suppressed load dump pulse. The device
supports up to 40-V load dump transient and will maintain normal operation during the load dump pulse. If the
switch is enabled, it will stay enabled and if the switch is disabled, it will stay disabled.
9.3.1.4 Driving Inductive Loads
When switching off an inductive load, the inductor may impose a negative voltage on the output of the switch.
The TPS2HB50-Q1 includes a voltage clamp to limit voltage across the FET. The maximum acceptable load
inductance is a function of the device robustness.
For more information on driving inductive loads, refer to TI's How To Drive Inductive, Capacitive, and Lighting
Loads with Smart High Side Switches application report.
9.3.1.5 Reverse Battery
In the reverse battery condition, the switch will automatically be enabled regardless of the state of EN1/EN2 to
prevent excess power dissipation inside the MOSFET body diode. In many applications (for example, resistive
loads), the full load current may be present during reverse battery. In order to activate the automatic switch on
feature, the SEL2 pin must have a path to module ground. This may be path 1 as shown in Figure 6, or if the
SEL2 pin is unused, the path may be through RPROT to module ground.
Protection features like thermal shutdown are not available during a reverse battery event. Care must be taken to
ensure that excessive power is not dissipated in the switch during the reverse battery condition.
There are two options for blocking reverse current in the system. The first option is to place a blocking device
(FET or diode) in series with the battery supply, blocking all current paths. The second option is to place a
blocking diode in series with the GND node of the high-side switch. This method will protect the controller portion
of the switch (path 2), but it will not prevent current from flowing through the load (path 3). The diode used for the
second option may be shared amongst multiple high-side switches.
Path 1 shown in Figure 6 is blocked inside of the device.
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Feature Description (continued)
Reverse blocking
FET or diode
BAT
Option 1
0V VBB
µC
VDD
(3)
(2)
Controller
GPIO
GPIO
RPROT
VOUT
VBB
Clamp
Load
ADVANCE INFORMATION
(1)
GND
Option 2
13.5V
Figure 6. Current Path During Reverse Battery
9.3.1.6 Fault Event – Timing Diagrams
NOTE
All timing diagrams assume that the SELx pins are set to select the relevant channel.
The LATCH, DIA_EN, and ENx pins are controlled by the user. The timing diagrams
represent a possible use-case.
Figure 7 shows the immediate current limit switch off and the retry behavior of versions A and B of the device. As
shown, the switch will remain latched off until the LATCH pin is low.
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Feature Description (continued)
µC
resets
the latch
LATCH
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
ADVANCE INFORMATION
VOUTx
ENx
tRETRY
ICL
IOUTx
t
Load reaches limit.
Switch is Disabled.
Switch follows ENx.
Normal operation.
Figure 7. Current Limit – Version A and B - Latched Behavior
Figure 8 shows the immediate current limit switch off behavior of versions A and B. In this example, LATCH is
tied to GND; hence, the switch will retry after the fault is cleared and tRETRY has expired.
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Feature Description (continued)
DIA_EN
ISNSFH
SNS
High-z
Current
Sense
High-z
High-z
Current
Sense
High-z
VOUTx
ENx
ICL
IOUTx
t
Load reaches limit.
Switch is Disabled.
Switch follows ENx.
Normal operation.
Figure 8. Current Limit – Version A and B - LATCH = 0
Figure 9 illustrates auto-retry behavior and provides a zoomed-in view of the fault indication during retry. When
the switch retries after a shutdown event, the SNS fault indication will remain at the fault state until VOUT has
risen to VBB – 1.8 V. Once VOUT has risen, the SNS fault indication is reset and current sensing is available. If
there is a short-to-ground and VOUT cannot rise, the SNS fault indication will remain indefinitely.
NOTE
Figure 9 assumes that tRETRY has expired by the time that TJ reaches the hysteresis
threshold.
LATCH = 0 V and DIA_EN = 5 V
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tRETRY
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Feature Description (continued)
ISNSFH
ISNSFH
ISNSFH
ISNSFH
SNS
VOUTx
ENx
TABS
THYS
TJ
t
ADVANCE INFORMATION
ISNSFH
ISNSI
SNS
VBB t 1.8 V
VOUTx
ENx
TABS
THYS
TJ
t
Figure 9. Fault Indication During Retry
9.3.2 Diagnostic Mechanisms
9.3.2.1 VOUTx Short-to-Battery and Open-Load
The TPS2HB50-Q1 is capable of detecting short-to-battery and open-load events regardless of whether the
switch is turned on or off, however the two conditions use different methods.
9.3.2.1.1 Detection With Switch Enabled
When the switch is enabled, the VOUTx short-to-battery and open-load conditions can be detected by the current
sense feature. In both cases, the load current will be measured through the SNS pin as below the expected
value.
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Feature Description (continued)
9.3.2.1.2 Detection With Switch Disabled
(1)
This figure assumes that the device ground and the load ground are at the same potential. In a real system, there
may be a ground shift voltage of 1 V to 2 V.
Figure 10. Short to Battery and Open Load Detection
The detection circuitry is only enabled when DIA_EN = HIGH and EN = LOW. If VOUT > VOL, the SNS pin will go
to the fault level, but if VOUT < VOL there will be no fault indication. The fault indication will only occur if the SEL1
pin is set to diagnose the respective channel.
While the switch is disabled and DIA_EN is high, the fault indication mechanisms will continuously represent the
present status. For example, if VOUT decreases from greater than VOL to less than VOL, the fault indication is
reset. Additionally, the fault indication is reset upon the falling edge of DIA_EN or the rising edge of EN.
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While the switch is disabled, if DIA_EN is high, an internal comparator will detect the condition of VOUT. If the
load is disconnected (open load condition) or there is a short to battery the VOUT voltage will be higher than the
open load threshold (VOL,off) and a fault is indicated on the SNS pin . An internal pull-up of 1 MΩ is in series with
an internal MOSFET switch, so no external component is required if only a completely open load must be
detected. However, if there is significant leakage or other current draw even when the load is disconnected, a
lower value pull-up resistor and switch can be added externally to set the VOUT voltage above the VOL,off during
open load conditions.
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Feature Description (continued)
DIA_EN
ISNSFH
High-z
SNS
High-z
tOL2
Enabled
VOUT depends on external conditions
ADVANCE INFORMATION
VOL
VOUT
EN
t
Switch is disabled and DIA_EN goes
high.
The condition is determined by the
internal comparator.
The open-load fault is
indicated.
Device standby
Figure 11. Open Load
9.3.2.2 SNS Output
The SNS output may be used to sense the load current or device temperature. The SELx pins will select the
desired sense signal. The sense circuit will provide a current that is proportional to the selected parameter. This
current will be sourced into an external resistor to create a voltage that is proportional to the selected parameter.
This voltage may be measured by an ADC or comparator.
To ensure accurate sensing measurement, the sensing resistor should be connected to the same ground
potential as the μC ADC.
Table 3. Analog Sense Transfer Function
PARAMETER
TRANSFER FUNCTION
Load current
ISNSI = IOUT / KSNS (1500)
Device temperature
ISNST = (TJ – 25°C) × dISNST / dT + 0.85
The SNS output will also be used to indicate system faults. ISNS will go to the predefined level, ISNSFH, when there
is a fault. ISNSFH, dISNST/dT, and KSNS are defined in the Specifications section.
9.3.2.2.1 RSNS Value
The following factors should be considered when selecting the RSNS value:
• Current sense ratio (KSNS)
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•
•
•
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Largest and smallest diagnosable load current required for application operation
Full-scale voltage of the ADC
Resolution of the ADC
For an example of selecting RSNS value, reference Selecting the RSNS Value in the applications section of this
datasheet.
9.3.2.2.1.1 High Accuracy Load Current Sense
9.3.2.2.1.2 SNS Output Filter
To achieve the most accurate current sense value, it is recommended to filter the SNS output. There are two
methods of filtering:
• Low-Pass RC filter between the SNS pin and the ADC input. This filter is illustrated in Figure 15 with typical
values for the resistor and capacitor. The designer should select a CSNS capacitor value based on system
requirements. A larger value will provide improved filtering but a smaller value will allow for faster transient
response.
• The ADC and microcontroller can also be used for filtering. It is recommended that the ADC collects several
measurements of the SNS output. The median value of this data set should be considered as the most
accurate result. By performing this median calculation, the microcontroller can filter out any noise or outlier
data.
9.3.2.3 Fault Indication and SNS Mux
The following faults will be communicated through the SNS output:
• Switch shutdown, due to:
– Thermal Shutdown
– Current limit
• Open-Load / VOUT shorted-to-battery
Open-load / Short-to-battery are not indicated while the switch is enabled, although these conditions can still be
detected through the sense current. Hence, if there is a fault indication corresponding to an enabled channel,
then it must be either due to an over-current or over-temperature event.
The SNS pin will only indicate the fault if the SELx pins are selecting the relevant channel. When the device is
set to measure temperature, the pin will be measuring the temperature of whichever channel is at a higher
temperature.
Table 4. Version A/B SNS Mux
INPUTS
(1)
OUTPUTS
FAULT DETECT
(1)
DIA_EN
SEL1
SEL2
0
X
X
X
High-Z
SNS
1
0
0
0
CH1 current
1
0
1
0
CH2 current
1
1
0
0
Device temperature
Fault Detect encompasses multiple conditions:
(a) Switch shutdown and waiting for retry
(b) Open Load / Short To Battery
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In many automotive modules, it is required that the high-side switch provide diagnostic information about the
downstream load. With more complex loads, high accuracy sensing is required. A few examples follow:
• LED lighting: In many architectures, the body control module (BCM) must be compatible with both
incandescent bulbs and also LED modules. The bulb may be relatively simple to diagnose. However, the LED
module will consume less current and also can include multiple LED strings in parallel. The same BCM is
used in both cases, so the high-side switch can accurately diagnose both load types.
• Solenoid protection: Often solenoids are precisely controlled by low-side switches. However, in a fault
event, the low-side switch cannot disconnect the solenoid from the power supply. A high-side switch can be
used to continuously monitor several solenoids. If the system current becomes higher than expected, the
high-side switch can disable the module.
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Table 4. Version A/B SNS Mux (continued)
INPUTS
OUTPUTS
DIA_EN
SEL1
SEL2
FAULT DETECT (1)
1
1
1
0
N/A
1
0
0
1
ISNSFH
1
0
1
1
ISNSFH
1
1
0
1
Device temperature
1
1
1
1
N/A
SNS
9.3.2.4 Resistor Sharing
Multiple high-side channels may use the same SNS resistor as shown in the figure below. This reduces the total
number of passive components in the system and the number of ADC terminals that are required of the
microcontroller.
Microcontroller
ADVANCE INFORMATION
GPIO
DIA_EN
Switch 1
SNS
GPIO
DIA_EN
Switch 2
SNS
GPIO
DIA_EN
Switch 3
SNS
GPIO
DIA_EN
Switch 4
SNS
ADC
RPROT
CSNS
RSNS
Figure 12. Sharing RSNS Among Multiple Devices
9.3.2.5 High-Frequency, Low Duty-Cycle Current Sensing
Some applications will operate with a high-frequency, low duty-cycle PWM or require fast settling of the SNS
output. For example, a 250 Hz, 5% duty cycle PWM will have an on-time of only 200 µs that must be
accommodated. The micro-controller ADC may sample the SNS signal after the defined settling time tSNSION3.
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DIA_EN
ENx
IOUT
SNS
Figure 13. Current Sensing in Low-Duty Cycle Applications
9.4 Device Functional Modes
During typical operation, the TPS2HB50-Q1 can operate in a number of states that are described below and
shown as a state diagram in Figure 14.
9.4.1 Off
Off state occurs when the device is not powered.
9.4.2 Standby
Standby state is a low-power mode used to reduce power consumption to the lowest level. Diagnostic
capabilities are not available in Standby mode.
9.4.3 Diagnostic
Diagnostic state may be used to perform diagnostics while the switches are disabled.
9.4.4 Standby Delay
The Standby Delay state is entered when EN1, EN2, and DIA_EN are low. After tSTBY, if the ENx and DIA_EN
pins are still low, the device will go to Standby State.
9.4.5 Active
In Active state, one or more of the switches are enabled. The diagnostic functions may be turned on or off during
Active state.
9.4.6 Fault
The Fault state is entered if a fault shutdown occurs (thermal shutdown or current limit). After all faults are
cleared, the LATCH pin is low, and the retry timer has expired, the device will transition out of Fault state. If the
relevant ENx pin is high, the switch will re-enable. If the relevant ENx pin is low, the switch will remain off.
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t
tSNSION3
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Device Functional Modes (continued)
VBB < UVLO
OFF
ANY STATE
VBB > UVLO
EN1 & EN2 = Low
DIA_EN = Low
t > tSTBY
STANDBY
EN1 & EN2 = Low
DIA_EN = High
ADVANCE INFORMATION
EN1 & EN2 = Low
DIA_EN = Low
EN1 || EN2 = High
DIA_EN = X
STANDBY
DELAY
DIAGNOSTIC
EN1 & EN2 = Low
DIA_EN = High
EN1 & EN2 = Low
DIA_EN = High
EN1 || EN2 = High
DIA_EN = X
ACTIVE(1)
EN1 & EN2 = Low
DIA_EN = Low
!OT_ABS & !OT_REL & !ILIM
& LATCH = Low & tRETRY
expired
EN1 || EN2 = High
DIA_EN = X
OT_ABS || OT_REL
|| ILIM
FAULT(1)
(1)
CH1 and CH2 operate independently. Each channel is enabled/disabled independently. Also, if there is a fault on one
channel, the other channel is not affected.
Figure 14. State Diagram
28
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Figure 15 shows the schematic of a typical application for the TPS2HB50-Q1. It includes all standard external
components. This section of the datasheet discusses the considerations in implementing commonly required
application functionality.
VBB
DIA_EN
RPROT
CVBB
BAT
SEL1
GND
RGND
ADVANCE INFORMATION
RPROT
SEL2
RPROT
DGND
(1)
EN1
RPROT
(1)
EN2
Load
RPROT
VOUT1
Microcontroller
LATCH
COUT
RPROT
VBB
Load
RILIM1
VOUT2
ILIM1
COUT
VBB
RILIM2
ILIM2
Legend
SNS
ADC
Chassis GND
RPROT
RSNS
CSNS
Module GND
Device GND
(1)
With the ground protection network, the device ground will be offset relative to the microcontroller ground.
Figure 15. System Diagram
Table 5. Recommended External Components
COMPONENT
TYPICAL VALUE
RPROT
15 kΩ
Protect microcontroller and device I/O pins
RSNS
1 kΩ
Translate the sense current into sense voltage
CSNS
100 pF - 10 nF
RGND
4.7 kΩ
DGND
BAS21 Diode
PURPOSE
Low-pass filter for the ADC input
Stabilize GND potential during turn-off of inductive load
Protects device during reverse battery
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Application Information (continued)
Table 5. Recommended External Components (continued)
COMPONENT
TYPICAL VALUE
RILIM
5 kΩ - 25 kΩ
CVBB
PURPOSE
Set current limit threshold
220 nF to Device GND
Filtering of voltage transients (for example, ESD, ISO7637-2) and improved
emissions
100 nF to Module GND
Stabilize the input supply and filter out low frequency noise.
COUT
22 nF
Filtering of voltage transients (for example, ESD, ISO7637-2)
CGND
1 µF from Device GND to
Module GND
Optional capacitance to help with RF immunity.
10.1.1 Ground Protection Network
As discussed in the Reverse Battery section, DGND may be used to prevent excessive reverse current from
flowing into the device during a reverse battery event. Additionally, RGND is placed in parallel with DGND if the
switch is used to drive an inductive load. The ground protection network (DGND and RGND) may be shared
amongst multiple high-side switches.
ADVANCE INFORMATION
A minimum value for RGND may be calculated by using the absolute maximum rating for IGND. During the reverse
battery condition, IGND = VBB / RGND:
RGND ≥ VBB / IGND
• Set VBB = –13.5 V
• Set IGND = –50 mA (absolute maximum rating)
RGND ≥ –13.5 V / –50 mA = 270 Ω
(2)
In this example, it is found that RGND must be at least 270 Ω. It is also necessary to consider the power
dissipation in RGND during the reverse battery event:
PRGND = VBB2 / RGND
(3)
2
PRGND = (13.5 V) / 270 Ω = 0.675 W
In practice, RGND may not be rated for such a high power. In this case, a larger resistor value should be selected.
10.1.2 Interface With Microcontroller
The ground protection network will cause the device ground to be at a higher potential than the module ground
(and microcontroller ground). This offset will impact the interface between the device and the microcontroller.
Logic pin voltage will be offset by the forward voltage of the diode. For input pins (for example, EN1), the
designer must consider the VIH specification of the switch and the VOH specification of the microcontroller. For a
system that does not include DGND, it is required that VOH > VIH. For a system that does include DGND, it is
required that VOH > (VIH + VF). VF is the forward voltage of DGND.
The sense resistor, RSNS, should be terminated to the microcontroller ground. In this case, the ADC can
accurately measure the SNS signal even if there is an offset between the microcontroller ground and the device
ground.
10.1.3
I/O Protection
RPROT is used to protect the microcontroller I/O pins during system-level voltage transients such as ISO pulses or
reverse battery. The SNS pin voltage can exceed the ADC input pin maximum voltage if the fault or saturation
current causes a high enough voltage drop across the sense resistor. If that can occur in the design (for
example, by switching to a high value RSNS to improve ADC input level), then an appropriate external clamp has
to be designed to prevent a high voltage at the SNS output and the ADC input.
10.1.4 Inverse Current
Inverse current occurs when 0 V < VBB < VOUTx. In this case, current may flow from VOUTx to VBB. Inverse current
cannot be caused by a purely resistive load. However, a capacitive or inductive load can cause inverse current.
For example, if there is a significant amount of load capacitance and the VBB node has a transient droop, VOUTx
may be greater than VBB.
30
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The TPS2HB50-Q1 will not detect inverse current. When the switch is enabled, inverse current will pass through
the switch. When the switch is disabled, inverse current may pass through the MOSFET body diode. The device
will continue operating in the normal manner during an inverse current event.
10.1.5 Loss of GND
The ground connection may be lost either on the device level or on the module level. If the ground connection is
lost, both switches will be disabled. If the switch was already disabled when the ground connection was lost, the
switch will remain disabled. When the ground is reconnected, normal operation will resume.
10.1.6 Automotive Standards
The TPS2HB50-Q1 is designed to be protected against all relevant automotive standards to ensure reliable
operations when connected to a 12-V automotive battery.
10.1.6.1 ISO7637-2
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as: “The function does not
perform as designed during the test but returns automatically to normal operation after the test”. See Table 6 for
ISO7637-2:2011 (E) expected results.
Table 6. ISO7637-2:2011 (E) Results
TEST
PULSE
(1)
TEST PULSE SEVERITY LEVEL WITH
STATUS II FUNCTIONAL PERFORMANCE
LEVEL
US
MINIMUM NUMBER
OF PULSES OR TEST
TIME
BURST CYCLE / PULSE REPETITION TIME
MIN
MAX
1
III
–112 V
500 pulses
0.5 s
--
2a (1)
III
+55 V
500 pulses
0.20
5s
2b
IV
+10 V
10 pulses
0.5 s
5s
3a
IV
–220 V
1 hour
90 ms
100 ms
3b
IV
+150 V
1 hour
90 ms
100 ms
1 µF capacitance on CVBB is required for passing level 3 ISO7637 pulse 2A.
10.1.6.2 AEC – Q100-012 Short Circuit Reliability
The TPS2HB50-Q1 is tested according to the AEC-Q100-012 Short Circuit Reliability standard. This test is
performed to demonstrate the robustness of the device against VOUT short-to-ground events. Test conditions and
test procedures are summarized in Table 7. For further details, refer to the AEC - Q100-012 standard document.
Test conditions:
• LATCH = 0 V
• ILIM = 5 kΩ
• 10 units from 3 separate lots for a total of 30 units.
• Lsupply = 5 μH, Rsupply = 10 mΩ
• VBB = 14 V
Test procedure:
• Parametric data is collected on each unit pre-stress
• Each unit is enabled into a short-circuit with the required short circuit cycles or duration as specified
• Functional testing is performed on each unit post-stress to verify that the part still operates as expected
The cold repetitive test is run at 85ºC which is the worst case condition for the device to sustain a short circuit.
The cold repetitive test refers to the device being given time to cool down between pulses, rather than being run
at a cold temperature. The load short circuit is the worst case situation, since the energy stored in the cable
inductance can cause additional harm. The fast response of the device ensures current limiting occurs quickly
and at a current close to the load short condition. In addition, the hot repetitive test is performed as well.
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The TPS2HB50-Q1 is tested according to the ISO7637-2:2011 (E) standard. The test pulses are applied both
with the switches enabled and disabled. The test setup includes only the DUT and minimal external components:
CVBB, COUT, DGND, and RGND.
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Table 7. AEC - Q100-012 Test Results
TEST
LOCATION OF SHORT
DEVICE
VERSION
NO. OF CYCLES /
DURATION
NO. OF
UNITS
NO. OF
FAILS
Cold Repetitive - Long
Pulse
Load Short Circuit, Lshort = 5 μH, Rshort =
100 mΩ, TA = 85ºC
B
100 k cycles
30
0
Hot Repetitive - Long Pulse
Load Short Circuit, Lshort = 5 μH, Rshort =
100 mΩ, TA = 25ºC
B
100 hours
30
0
10.2 Typical Application
This application example demonstrates how the TPS2HB50-Q1 device can be used to power resistive heater
loads in automotive seats. In this example, we consider dual heater loads that are powered independently by the
two channels of the device. A dual-channel device is the ideal solution as it will yield a smaller solution size
relative to two single-channel devices.
+12 V Battery
ADVANCE INFORMATION
DIA_EN
VBB
SEL1
SEL2
SNS
µC
ILIM1
ILIM2
LATCH
EN1
EN2
GND
VOUT1
VOUT2
HEATER LOAD
R1
HEATER LOAD
R2
Figure 16. Block Diagram for Powering Dual Heater Loads
10.2.1 Design Requirements
For this design example, use the input parameters shown in Table 8.
Table 8. Design Parameters
32
DESIGN PARAMETER
EXAMPLE VALUE
VBB
13.5 V
Load Ch1 - Heater 1
32 W max
Load Ch2 - Heater 2
32 W max
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Table 8. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Load Current Sense
30 mA to 6 A
ILIM
4A
Ambient temperature
70°C
RθJA
32.5°C/W (depending on PCB)
Device Version
A
10.2.2 Detailed Design Procedure
10.2.2.1 Thermal Considerations
The DC current in each channel under maximum load power condition will be around 2.4 A. Both heater loads
can be ON at the same time, so the case where both channels are enabled simultaneously is considered to
assume worst case heating.
PFET = I2 × RON
PFET = (2.4 A)2 × 100 mΩ = 0.58 W
(4)
(5)
If both channels are enabled, then the total power dissipation is 1.15 W. The junction temperature of the device
can be calculated using Equation 6 and the RθJA value from the Specifications section.
TJ = TA + RθJA × PFET
TJ = 70°C + 32.5°C/W × 1.15 W = 107.5°C
(6)
The maximum junction temperature rating for the TPS2HB50-Q1 device is TJ = 150°C. Based on the above
example calculation, the device temperature will stay below the maximum rating.
10.2.2.2 RILIM Calculation
In this application, the TPS2HB50-Q1 must allow for the maximum 2.4 A current with margin but minimize the
energy in the switch during a fault condition by minimizing the current limit. For this application, the best ILIM set
point is approximately 4 A. Equation 7 allows you to calculate the RILIM value that is placed from the ILIMX pins to
VBB. RILIM is calculated in kΩ.
RILIM = KCL / ICL
(7)
Because this device is version A, the KCL value in the Specifications section is 40 A × kΩ.
RILIM = 40 A × kΩ / 4 A = 10 kΩ
(8)
For a ILIM of 4 A, the RILIM value should be set at approximately 10 kΩ.
10.2.2.3 Diagnostics
If the resistive heating load is disconnected (heater malfunction), an alert is desired. Open-load detection can be
performed in the switch-enabled state with the current sense feature of the TPS2HB50-Q1 device. Under open
load condition, the current in the SNS pin will be the fault current and the can be detected from the sense voltage
measurement.
10.2.2.3.1 Selecting the RSNS Value
Table 9 shows the requirements for the load current sense in this application. The KSNS value is specified for the
device and can be found in the Specifications section.
Table 9. RSNS Calculation Parameters
PARAMETER
EXAMPLE VALUE
Current Sense Ratio (KSNS)
1500
Largest diagnosable load current
6A
Smallest diagnosable load current
30 mA
Full-scale ADC voltage
5-V
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Power dissipation in the switch is calculated in Equation 4. RON is assumed to be 100 mΩ because this is the
maximum specification at high temperature. In practice, RON will almost always be lower.
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Table 9. RSNS Calculation Parameters (continued)
PARAMETER
EXAMPLE VALUE
ADC resolution
10-bit
The load current measurement requirements of 6 A ensures that even in the event of a overcurrent surpassing
the device internal 4 A limit, the MCU can register and react by shutting down the TPS2HB50-Q1, while the low
level of 30 mA allows for accurate measurement of low load currents.
The RSNS resistor value should be selected such that the largest diagnosable load current puts VSNS at about
95% of the ADC full-scale. With this design, any ADC value above 95% can be considered a fault. Additionally,
the RSNS resistor value should ensure that the smallest diagnosable load current does not cause VSNS to fall
below 1 LSB of the ADC. With the given example values, a 1.2 kΩ sense resistor satisfies both requirements
shown in Table 10.
Table 10. VSNS Calculation
LOAD (A)
SENSE RATIO
ISNS (mA)
RSNS (Ω)
VSNS (V)
0.030
1500
0.02
1200
0.024
% of 5-V ADC
0.5%
6
1500
4
1200
4.800
96.0%
ADVANCE INFORMATION
11 Power Supply Recommendations
The TPS2HB50-Q1 device is designed to operate in a 12-V automotive system. The nominal supply voltage
range is 6 V to 18 V as measured at the VBB pin with respect to the GND pin of the device. In this range the
device meets full parametric specifications as listed in the Electrical Characteristics table. The device is also
designed to withstand voltage transients beyond this range. When operating outside of the nominal voltage range
but within the operating voltage range, the device will exhibit normal functional behavior. However, parametric
specifications may not be specified outside the nominal supply voltage range.
Table 11. Operating Voltage Range
VBB Voltage Range
Note
3 V to 6 V
Transients such as cold crank and start-stop, functional operation
are specified but some parametric specifications may not apply. The
device is completely short-circuit protected up to 125°C
6 V to 18 V
Nominal supply voltage, all parametric specifications apply. The
device is completely short-circuit protected up to 125°C
18 V to 24 V
Transients such as jump-start and load-dump, functional operation
specified but some parametric specifications may not apply. The
device is completely short-circuit protected up to 125°C
18 V to 40 V
Transients such as jump-start and load-dump, functional operation
specified but some parametric specifications may not apply.
12 Layout
12.1 Layout Guidelines
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,
the pour may extend beyond the package dimensions as shown in the example below. In addition to this, it is
recommended to also have a VBB plane either on one of the internal PCB layers or on the bottom layer.
Vias should connect this plane to the top VBB pour.
Ensure that all external components are placed close to the pins. Device current limiting performance can be
harmed if the RILIM is far from the pins and extra parasitics are introduced.
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12.2 Layout Example
GND
DIA_EN
SNS
SEL2
LATCH
SEL1
To µC
To µC
NC
EN
VBB
NC
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
ADVANCE INFORMATION
ST
Figure 17. PWP Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• TI's How To Drive Inductive, Capacitive, and Lighting Loads with Smart High Side Switches
• TI's Short Circuit Reliability Test for Smart Power Switch
• TI's Adjustable Current Limit of Smart Power Switches
• TI's TPS2HB35-Q1 40-V, 35-mΩ Dual-Channel Smart High-Side Switch
• TI's Improved Automotive Short Circuit Reliability with Adjustable Current Limiting
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
ADVANCE INFORMATION
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
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PACKAGE OPTION ADDENDUM
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15-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PTPS2HB50BQPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
TBD
Call TI
Call TI
-40 to 125
TPS2HB50BQPWPRQ1
PREVIEW
HTSSOP
PWP
16
3000
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-3-260C-168HRS
-40 to 125
TPS2HB50FQPWPRQ1
PREVIEW
HTSSOP
PWP
16
2000
TBD
Call TI
Call TI
-40 to 125
2HB50BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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15-Nov-2019
Addendum-Page 2
PACKAGE OUTLINE
PWP0016M
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
6.6
TYP
6.2
PIN 1 INDEX
AREA
A
C
0.1 C
SEATING
PLANE
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
4.5
4.3
16X
SEE DETAIL A
(0.15) TYP
2X 0.6 MAX
NOTE 5
THERMAL
PAD
8
9
2X 0.31 MAX
NOTE 5
0.25
GAGE PLANE
3.37
2.48
1.2 MAX
17
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
16
1
0.32
0.16
NOTE 5
2X
2X (0.13)
2.78
2.20
0.45
0.25
NOTE 5
2X
TYPICAL
4223886/B 09/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016M
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.78)
16X (1.5)
16X (0.45)
METAL COVERED
BY SOLDER MASK
SYMM
16
1
(1.2) TYP
(R0.05) TYP
(3.37)
SYMM
17
14X (0.65)
( 0.2) TYP
VIA
(5)
NOTE 9
(0.6)
9
8
(1.2) TYP
SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223886/B 09/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016M
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.78)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
16X (0.45)
1
METAL COVERED
BY SOLDER MASK
16
(R0.05) TYP
SYMM
(3.37)
BASED ON
0.125 THICK
STENCIL
17
14X (0.65)
8
9
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.11 X 3.77
2.78 X 3.37 (SHOWN)
2.54 X 3.08
2.35 X 2.85
4223886/B 09/2019
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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