Texas Instruments | DCP01B Series 1-W, Isolated, Unregulated DC/DC Converter Modules (Rev. H) | Datasheet | Texas Instruments DCP01B Series 1-W, Isolated, Unregulated DC/DC Converter Modules (Rev. H) Datasheet

Texas Instruments DCP01B Series 1-W, Isolated, Unregulated DC/DC Converter Modules (Rev. H) Datasheet
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DCP010505B, DCP010512B, DCP010515B
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
DCP01B Series 1-W, Isolated, Unregulated DC/DC Converter Modules
1 Features
3 Description
•
•
The DCP01B series is a family of 1-W, isolated,
unregulated DC/DC converter modules. Requiring a
minimum of external components and including onchip device protection, the DCP01B series of devices
provide extra features such as output disable and
synchronization of switching frequencies.
1
•
•
•
•
1-kV Isolation (operational): 1-second test
Continuous voltage applied across isolation
barrier: 60 VDC / 42.5 VAC
Device-to-device synchronization
EN55022 Class B EMC performance
UL1950 Recognized Component
7-Pin PDIP and 7-pin SOP packages
This combination of features and small size makes
the DCP01B series of devices suitable for a wide
range of applications, and is an easy-to-use solution
in applications requiring signal path isolation.
2 Applications
•
•
•
•
•
WARNING: This product has operational isolation
and is intended for signal isolation only. It should not
be used as a part of a safety isolation circuit requiring
reinforced isolation. See definitions in the Feature
Description section.
Signal path isolation
Ground loop elimination
Data acquisition
Industrial control and instrumentation
Test equipment
Device Information
PART NUMBER
DCP01xxxxB
PACKAGE
PDIP (7)
SOP (7)
(1)
BODY SIZE (NOM)
19.18 mm × 10.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single Output Block Diagram
SYNCOUT
SYNCIN
Oscillator
800 kHz
Divide-by-2
Reset
Watchdog
Startup
+VOUT
Power
Stage
±VOUT
Thermal
Shutdown
+VS
Power Controller
Copyright © 2017, Texas Instruments Incorporated
±VS
Dual Output Block Diagram
SYNCOUT
SYNCIN
Oscillator
800 kHz
Divide-by-2
Reset
Watchdog
Startup
+VOUT
Power
Stage
±VOUT
COM
PSU Thermal
Shutdown
+VS
Power Controller
Copyright © 2017, Texas Instruments Incorporated
±VS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagrams ..................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2017) to Revision H
Page
•
Added Light Load Operation (< 10%) section ...................................................................................................................... 14
•
Added Load Regulation (10% to 100%) section................................................................................................................... 14
•
Added Power-Up Characteristics section ............................................................................................................................. 15
Changes from Revision F (October 2015) to Revision G
•
Page
Adjusted Operating temperature specification to "ambient temperature range, TA" in Recommended Operating
Conditions table ...................................................................................................................................................................... 5
Changes from Revision E (December 2000) to Revision F
Page
•
Added Dual Output Block Diagram ....................................................................................................................................... 1
•
Renamed pin "0V" to "COM" (output side common pin) in table............................................................................................ 4
•
Renamed pin "VS " to "+VS " (input voltage pin) in table ........................................................................................................ 4
•
Renamed pin "0V" to "–VS " (input side common pin) in table ............................................................................................... 4
•
Added Recommended Operating Conditions table ................................................................................................................ 5
•
Added Thermal Information table ........................................................................................................................................... 5
•
Added information to the ISOLATION section of the Electrical Characteristics table ........................................................... 6
•
Added Isolation section to the Feature Description section ................................................................................................. 13
•
Added a typical application design to the Application Information section........................................................................... 18
•
Added Power Supply Recommendations section................................................................................................................. 21
2
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
5 Device Comparison Table
at TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 0.1 µF, (unless otherwise noted)
OUTPUT
VOLTAGE
VNOM @ VS (TYP) (V)
75% LOAD
INPUT
VOLTAGE
VS (V)
DEVICE NUMBER
MIN
TYP
MAX
DEVICE
OUTPUT
CURRENT
(mA) (1)
LOAD
REGULATION
10% TO 100%
LOAD (2)
NO LOAD
CURRENT
IQ (mA)
0% LOAD
EFFICIENCY
(%)
100% LOAD
BARRIER
CAPACITANCE
CISO (pF)
VISO = 750Vrms
MIN
TYP
MAX
MAX
TYP
MAX
TYP
TYP
TYP
4.75
5
5.25
200
19
31
20
80
3.6
DCP010505DBP
DCP010505DBP-U
±4.25
±5
±5.75
200 (3)
18
32
22
81
3.8
DCP010507DBP
DCP010507DBP-U
±5.75
±6.5
±7.25
153 (3)
21
35
38
81
3.0
11.4
12
12.6
83
21
38
29
85
5.1
DCP010512DBP
DCP010512DBP-U
±11.4
±12
±12.6
83 (3)
19
37
40
82
4.0
DCP010515BP
DCP010515BP-U
14.25
15
15.75
66
26
42
34
82
3.8
±14.25
±15
±15.75
66 (3)
19
41
42
85
4.7
±11.4
±12
±12.6
83
11
39
19
78
2.5
±14.25
±15
±15.75
66 (3)
12
39
20
80
2.5
4.75
5
5.25
200
13
23
14
77
2.5
±14.25
±15
±15.75
66 (3)
10
35
17
76
3.8
DCP010505BP
DCP010505BP-U
DCP010512BP
DCP010512BP-U
4.5
5
5.5
DCP010515DBP
DCP010515DBP-U
DCP011512DBP
DCP011512DBP-U
DCP011515DBP
DCP011515DBP-U
DCP012405BP
DCP012405BP-U
DCP012415DBP
DCP012415DBP-U
(1)
(2)
(3)
13.5
21.6
15
24
16.5
26.4
POUT(max) = 1 W
Load regulation = (VOUT at 10% load – VOUT at 100%)/VOUT at 75% load
IOUT1 + IOUT2
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3
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
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6 Pin Configuration and Functions
NVA and DUA Package
7-Pin PDIP and SOP (Single Output)
(Top View)
+VS
1
–VS
2
14
SYNCIN
8
SYNCOUT
DCP01B
–VOUT
5
+VOUT
6
NC
7
NVA and DUA Package
7-Pin PDIP and SOP (Dual Output)
(Top View)
+VS
1
–VS
2
14
SYNCIN
8
SYNCOUT
DCP01B
COM
5
+VOUT
6
–VOUT
7
Pin Functions
PIN NUMBER
PIN NAME
SINGLEOUTPUT
DUALOUTPUT
I/O
(1)
Description
COM
—
5
O
Output side common
NC
7
—
—
No connection
SYNCIN
14
14
I
Synchronization. Synchronize multiple devices by connecting the SYNC
pins of each. Pulling this pin low disables the internal oscillator.
SYNCOUT
8
8
O
Synchronization output. Unrectified transformer output
+VOUT
6
6
O
Positive output voltage
+VS
1
1
I
Input voltage
–VOUT
5
7
O
Negative output voltage
–VS
2
2
I
Input side common
(1)
4
I = Input, O = Output
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DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Input voltage
MAX
5-V input devices
7
15-V input devices
18
24-V input devices
29
Lead temperature (soldering, 10 s)
Storage temperature, Tstg
(1)
–60
UNIT
V
270
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
UNIT
±1000
(2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
NOM
MAX
5-V input devices
4.5
5
5.5
15-V input devices
13.5
15
16.5
24-V input devices
21.6
24
26.4
Operating ambient temperature range, TA
–40
UNIT
V
100
°C
7.4 Thermal Information
THERMAL METRIC
(1)
DCP01B
DCP01B
NVA (PDIP)
DUA (SOP)
UNIT
7 PINS
7 PINS
RθJA
Junction-to-ambient thermal resistance
61
61
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26
26
°C/W
RθJB
Junction-to-board thermal resistance
24
24
°C/W
ψJT
Junction-to-top characterization parameter
7
7
°C/W
ψJB
Junction-to-board characterization parameter
24
24
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2000–2019, Texas Instruments Incorporated
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5
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
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7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, CIN = 2.2 µF, COUT = 0.1 µF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
POUT
Output power
ILOAD = 100% (full load)
VRIPPLE
Output voltage ripple
COUT = 1 μF, ILOAD = 50%
Voltage vs. Temperature
1
W
20
mVPP
–40°C ≤ TA ≤ 25°C
0.046
%/°C
25°C ≤ TA ≤ 100°C
0.016
%/°C
INPUT
VS
Input voltage range
–10%
10%
ISOLATION
Voltage
1-second
flash test
VISO
Isolation
1
kVrms
dV/dt
500
Leakage current
30
µA
DC
60
VDC
AC
42.5
VAC
Continuous
working voltage
across isolation
barrier
V/s
LINE REGULATION
VOUT
Output voltage
IOUT ≥ 10% load current and
constant,
VS (min) to VS (typ)
1%
15%
IOUT ≥ 10% load current and
constant,
VS (typ) to VS (max)
1%
15%
RELIABILITY
Demonstrated
TA = 55°C
55
FITS
THERMAL SHUTDOWN
TSD
Die temperature at shutdown
ISD
Shutdown current
150
°C
3
mA
7.6 Switching Characteristics
at TA = +25°C, +VS = nominal, CIN = 2.2 µF, COUT = 0.1 µF, (unless otherwise noted)
PARAMETER
fOSC
Oscillator frequency
VIL
Low-level input voltage, SYNC
ISYNC
Input current, SYNC
tDISABLE
Disable time
CSYNC
Capacitance loading on SYNC
pin (1)
(1)
6
TEST CONDITIONS
MIN
fSW = fOSC/2
TYP
0
VSYNC = 2 V
External
MAX
800
UNIT
kHz
0.4
V
75
µA
2
µs
3
pF
The application report External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035) describes this configuration.
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
7.7 Typical Characteristics
At TA = 25°C, V+VS = nominal, (unless otherwise noted)
5.5
50
40
5.3
35
Output Voltage (V)
Ripple (mVPP)
5.4
1-mF Ceramic
4.7-mF Ceramic
10-mF Ceramic
45
30
25
20
15
5.2
5.1
5.0
4.9
4.8
4.7
10
4.6
5
4.5
0
10
20
30
40
50
60
70
80
90
4.4
4.5
100
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Input Voltage (V)
Load (%)
DCP010505B
DCP010505B
20-MHz BW
Figure 2. Line Regulation
Figure 1. Output Ripple vs Load
85
5.8
5.7
80
5.5
Efficiency (%)
Output Voltage (V)
5.6
5.4
5.3
5.2
5.1
75
70
65
5.0
4.9
60
4.8
55
4.7
10
20
30
40
50
60
70
80
90
10
100
20
30
40
50
DCP010505B
Note:
60
70
90
100
DCP010505B
Operation under 10% Load
Figure 4. Efficiency vs Load
Figure 3. Load Regulation
60
60
Standard Limits
Class A
Class B
40
30
20
10
0
10
Standard Limits
50
Emission Level, Peak (dBµA)
50
Emission Level, Peak (dBµA)
80
Load (%)
Load (%)
Class A
Class B
40
30
20
10
0
±10
20
0.15
1
Frequency(MHz)
10
DCP010505B
Figure 5. Conducted Emissions
Copyright © 2000–2019, Texas Instruments Incorporated
30
125% Load
±20
0.15
1
Frequency(MHz)
10
DCP010505B
30
8% Load
Figure 6. Conducted Emissions
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7
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
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Typical Characteristics (continued)
At TA = 25°C, V+VS = nominal, (unless otherwise noted)
5.8
85
+VOUT
5.7
±VOUT
80
5.5
5.4
Efficiency (%)
Output Voltage (V)
5.6
5.3
5.2
5.1
75
70
65
5.0
4.9
60
4.8
4.7
10
20
30
40
50
60
70
80
90
55
10
100
20
30
40
Load (%)
50
60
70
80
90
100
90
100
90
100
Load (%)
DCP010505DB
DCP010505DB
Figure 7. Load Regulation
Figure 8. Efficiency vs Load
85
7.6
+VOUT
7.4
±VOUT
80
75
Efficiency (%)
Output Voltage (V)
7.2
7
6.8
6.6
65
60
6.4
55
6.2
6
10
70
50
20
30
40
50
60
70
80
90
100
20
30
40
Load (%)
DCP010507DB
70
80
Figure 10. Efficiency vs Load
14.5
90
14.0
85
80
13.5
Efficiency (%)
Output Voltage (V)
60
DCP010507DB
Figure 9. Load Regulation
13.0
12.5
12.0
75
70
65
60
11.5
55
11.0
10
20
30
40
50
60
70
80
90
100
50
10
20
30
40
DCP010512B
Figure 11. Load Regulation
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50
60
70
80
Load (%)
Load (%)
8
50
Load (%)
DCP010512B
Figure 12. Efficiency vs Load
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DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
Typical Characteristics (continued)
At TA = 25°C, V+VS = nominal, (unless otherwise noted)
14.5
85
14.0
80
13.5
75
Efficiency (%)
VOUT (V)
13.0
12.5
12.0
11.5
70
65
60
11.0
+VOUT
-VOUT
10.5
55
10.00
50
10
20
30
40
50
60
70
80
90
100
10
20
30
40
Load (%)
DCP010512DB
17.0
80
16.5
75
16.0
15.5
90
100
65
60
14.5
55
14.0
40
80
70
15.0
30
70
Figure 14. Efficiency vs Load
85
Efficiency (%)
Output Voltage (V)
Figure 13. Load Regulation
20
60
DCP010512DB
17.5
10
50
Load (%)
50
60
70
80
90
50
10
100
20
30
40
50
Load (%)
60
70
80
90
100
Load (%)
DCP010515B
DCP010515B
Figure 15. Load Regulation
Figure 16. Load Regulation
90
18
85
80
Efficiency (%)
VOUT (V)
17
16
75
70
65
60
15
+VOUT
-VOUT
55
50
14
10
20
30
40
50
60
70
80
Load (%)
DCP010515DB
Figure 17. Load Regulation
Copyright © 2000–2019, Texas Instruments Incorporated
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
DCP010515DB
Figure 18. Efficiency vs Load
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9
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
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Typical Characteristics (continued)
At TA = 25°C, V+VS = nominal, (unless otherwise noted)
5.60
90
5.50
80
70
Efficiency (%)
VOUT (V)
5.40
5.30
5.20
5.10
60
50
40
30
5.00
20
4.90
10
0
4.80
10
20
30
40
50
60
70
80
10
100
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCP012405B
DCP012405B
Figure 19. Load Regulation
13.5
Figure 20. Efficiency vs Load
80
+VOUT
75
±VOUT
13.0
65
Efficiency (%)
Output Voltage (V)
70
12.5
12.0
11.5
60
55
50
45
11.0
40
10.5
10
30
10
35
20
30
40
50
60
70
80
90
100
20
30
40
Load (%)
50
60
70
80
90
100
90
100
Load (%)
DCP011512DB
DCP011512DB
Figure 21. Load Regulation
Figure 22. Efficiency vs Load
90
17
+VOUT
16.5
±VOUT
80
Efficiency (%)
Output Voltage (V)
16
15.5
15
14.5
70
60
50
14
40
13.5
13
10
20
30
40
50
60
70
80
90
100
30
10
20
30
40
DCP011515DB
Figure 23. Load Regulation
10
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50
60
70
80
Load (%)
Load (%)
DCP011515DB
Figure 24. Efficiency vs Load
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Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
Typical Characteristics (continued)
At TA = 25°C, V+VS = nominal, (unless otherwise noted)
90
16.5
+VOUT
±VOUT
80
70
15.5
Efficiency (%)
Output Voltage (V)
16
15
14.5
60
50
40
14
30
13.5
10
20
30
40
50
60
70
80
90
100
20
10
20
30
40
DCP012415DB
Figure 25. Load Regulation
Copyright © 2000–2019, Texas Instruments Incorporated
50
60
70
80
90
100
Load (%)
Load (%)
DCP012415DB
Figure 26. Efficiency vs Load
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11
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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8 Detailed Description
8.1 Overview
The DCP01B offers up to 1 W of isolated, unregulated output power from a 5-V, 15-V, or 24-V input source with
a typical efficiency of up to 85%. This efficiency is achieved through highly integrated packaging technology and
the implementation of a custom power stage and control device. The DCP01B devices are specified for
operational isolation only. The circuit design uses an advanced BiCMOS and DMOS process.
8.2 Functional Block Diagrams
SYNCOUT
SYNCIN
Oscillator
800 kHz
Divide-by-2
Reset
Watchdog
Startup
+VOUT
Power
Stage
±VOUT
Thermal
Shutdown
+VS
Power Controller
Copyright © 2017, Texas Instruments Incorporated
±VS
Figure 27. Single Output Device
SYNCOUT
SYNCIN
Oscillator
800 kHz
Divide-by-2
Reset
Watchdog
Startup
+VOUT
Power
Stage
±VOUT
COM
PSU Thermal
Shutdown
+VS
Power Controller
Copyright © 2017, Texas Instruments Incorporated
±VS
Figure 28. Dual Output Device
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42 V peak or 60 VDC for more than 1 second.
8.3.1.1 Operation or Functional Isolation
Operational or functional isolation is defined by the use of a high-potential (hipot) test only. Typically, this
isolation is defined as the use of insulated wire in the construction of the transformer as the primary isolation
barrier. The hipot one-second duration test (dielectric voltage, withstand test) is a production test used to verify
that the isolation barrier is functioning. Products with operational isolation should never be used as an element in
a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated
wire in the construction of the transformer. Input and output circuits must also be physically separated by
specified distances.
8.3.1.3 Continuous Voltage
For a device that has no specific safety agency approvals (operational isolation), the continuous voltage that can
be applied across the part in normal operation is less than 42.4 VRMS, or 60 VDC. Ensure that both input and
output voltages maintain normal SELV limits. The isolation test voltage represents a measure of immunity to
transient voltages.
WARNING
Do not use the device as an element of a safety isolation system that exceeds
the SELV limit.
If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the
isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any useraccessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test
voltage all describe a similar idea. They describe a test voltage applied for a specified time across a component
designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCP01B series of dc-dc
converters are all 100% production tested at 1.0 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on
materials, construction, and environment. The DCP01B series of dc-dc converters have toroidal, enameled, wire
isolation transformers with no additional insulation between the primary and secondary windings. While a device
can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire
insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
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13
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Feature Description (continued)
8.3.2 Power Stage
The DCP01B series of devices uses a push-pull, center-tapped topology. The DCP01B devices switch at 400
kHz (divide-by-2 from an 800-kHz oscillator).
8.3.3 Oscillator And Watchdog Circuit
The onboard, 800-kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be
synchronized to other DCP01B series device circuits or an external source, and is used to minimize system
noise.
A watchdog circuit checks the operation of the oscillator circuit. The oscillator can be disabled by pulling the
SYNCIN pin low. When the SYNCIN pin goes low, the output pins transition into tri-state mode, which occurs
within 2 μs.
8.3.4 Thermal Shutdown
The DCP01B series of devices are protected by a thermal-shutdown circuit.
If the on-chip temperature rises above 150°C, the device shuts down. Normal operation resumes as soon as the
temperature falls below 150°C. While the over temperature condition continues, operation randomly cycles on
and off. This cycling continues until the temperature is reduced.
8.3.5 Synchronization
When more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference can
be generated. This interference occurs because of the small variations in switching frequencies between the
DC/DC converters.
The DCP01B series of devices overcomes this interference by allowing devices to synchronize to one another.
Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the
capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can
sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3.0 V.
For an application that uses more than eight synchronized devices use an external device to drive the SYNC
pins. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
describes this configuration.
NOTE
During the start-up period, all synchronized devices draw maximum current from
the input simultaneously. If the input voltage falls below approximately 4 V, the
devices may not start up. A 2.2-μF capacitor should be connected close to each
device input pin.
8.3.6 Light Load Operation (< 10%)
Operation below 10% load can cause the output voltage to increase up to double the typical output voltage. For
applications that operate less than 10% of rated output current, it is recommended to add a minimum load to
ensure the output voltage of the device is within the load regulation range. For example, connect a 250-Ω preload resistor to meet the 10% minimum load condition for the DCP010505BP.
8.3.7 Load Regulation (10% to 100%)
The load regulation of the DCP01B series of devices is specified at 10% to 100% load. Placing a minimum 10%
load will ensure the output voltage is within the range specified in the Electrical Characteristics table. For more
information regarding operation below 10% load, see the Light Load Operation (< 10%) section.
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
Feature Description (continued)
8.3.8 Construction
The basic construction of the DCP01B series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCP01B series of devices are constructed using an IC, rectifier diodes, and
a wound magnetic toroid on a lead frame. Because the package contains no solder, the devices do not require
any special printed circuit board (PCB) assembly processing. This architecture results in an isolated DC/DC
converter with inherently high reliability.
8.3.9 Thermal Management
Due to the high power density of these devices, it is advisable to provide ground planes on the input and output
rails.
8.3.10 Power-Up Characteristics
The DCP01B series of devices do not include a soft-start feature. Therefore, a high in-rush current during power
up is expected. Refer to the DCPA1 series of devices for a 1-W, isolated, unregulated DC/DC converter module
with soft-start included. Figure 29 shows the typical start-up waveform for a DCP010505BP, operating from a 5-V
input with no load on the output. Figure 30 shows the start-up waveform for a DCP010505BP starting up into a
10% load. Figure 31 shows the start-up waveform starting up into a full (100%) load.
Figure 29. DCP010505BP Start-Up at No Load
Figure 30. DCP010505BP Start-Up at 10% Load
Figure 31. DCP010505BP Start-Up at 100% Load
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15
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
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8.4 Device Functional Modes
8.4.1 Disable and Enable (SYNCIN pin)
Each of the DCP01B series devices can be disabled or enabled by driving the SYNCIN pin using an open drain
CMOS gate. If the SYNCIN pin is pulled low, the DCP01B becomes disabled. The disable time depends upon the
external loading. The internal disable function is implemented within 2 μs. Removal of the pull down causes the
DCP01B to be enabled.
Capacitive loading on the SYNCIN pin should be minimized (≤ 3 pF) in order to prevent a reduction in the
oscillator frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC
Converters (SBAA035) describes disable and enable control circuitry.
8.4.2 Decoupling
8.4.2.1 Ripple Reduction
The high switching frequency of 400 kHz allows simple filtering. To reduce ripple, it is recommended that a
minimum of 1-μF capacitor be used on the +VOUT pin. For dual output devices, decouple both of the outputs to
the COM pin. The required 2.2-μF, low ESR ceramic input capacitor also helps to reduce ripple and noise, (24-V
input voltage versions require only 0.47 µF of input capacitance). See DC-to-DC Converter Noise Reduction
(SBVA012).
8.4.2.2 Connecting the DCP01B in Series
Multiple DCP01B isolated 1-W DC/DC converters can be connected in series to provide non-standard voltage
rails. This configuration is possible by using the floating outputs provided by the galvanic isolation of the DCP01.
Connect the +VOUT from one DCP01B to the –VOUT of another (see Figure 32). If the SYNCIN pins are tied
together, the self-synchronization feature of the DCP01B prevents beat frequencies on the voltage rails. The
synchronization feature of the DCP01B allows easy series connection without external filtering, thus minimizing
cost.
VIN
+VS
CIN
SYNCIN
CIN
+VOUT1
DCP
COUT
1.0 µF
01B
–VS
–VOUT1
VS
+VOUT2
SYNCIN
DCP
–VS
VOUT1
+
VOUT2
COUT
1.0 µF
01B
–VOUT2
Figure 32. Multiple DCP01B Devices Connected in Series
The outputs of a dual-output DCP01B can also be connected in series to provide two times the magnitude of
+VOUT, as shown in Figure 33. For example, connect a dual-output, 15-V, DCP012415DB device to provide a 30V rail.
VIN
+VS
CIN
+VOUT
DCP
–VS
01B
+VOUT
COUT
1.0 µF
–VOUT
–VOUT
COUT
1.0 µF
COM
Figure 33. Dual Output Devices Connected in Series
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
8.4.2.3 Connecting the DCP01B in Parallel
If the output power from one DCP01B is not sufficient, it is possible to parallel the outputs of multiple DCP01Bs,
as shown in Figure 34, (applies to single output devices only). The synchronization feature allows easy
synchronization to prevent power-rail beat frequencies at no additional filtering cost.
VIN
+VS
SYNCIN
CIN
+VOUT1
DCP
01B
–VS
COUT
1.0 µF
–VOUT1
2 × Power Out
+VS
CIN
SYNCIN
–VS
+VOUT2
DCP
COUT
1.0 µF
01B
–VOUT2
GND
Figure 34. Multiple DCP01B Devices Connected in Parallel
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17
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
VIN
+VOUT
+VS
CIN
2.2 µF
+VOUT
DCP01B
SYNC
COUT
1.0 µF
–VS
–VOUT
–VOUT
Figure 35. Typical DCP010505 Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 and follow the design procedures shown in
Detailed Design Procedure section.
Table 1. Design Example Parameters
PARAMETER
VALUE
UNIT
5
V
V(+VS)
Input voltage
V(+VOUT)
Output voltage
5
V
IOUT
Output current rating
200
mA
fSW
Operating frequency
400
kHz
9.2.2 DCP010505 Application Curves
85
5.8
5.7
5.6
Output Voltage (V)
Efficiency (%)
80
75
70
65
5.5
5.4
5.3
5.2
5.1
5.0
4.9
60
4.8
55
10
20
30
40
50
60
70
80
90
100
4.7
10
20
30
40
Load (%)
DCP010505B Efficiency
Figure 36. DCP010505B Efficiency
18
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50
60
70
80
90
100
Load (%)
DCP010505B Load Regulation
Figure 37. DCP010505B Load Regulation
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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SBVS012H – DECEMBER 2000 – REVISED MAY 2019
9.2.3 Detailed Design Procedure
9.2.3.1 Input Capacitor
For all 5-V and 15-V input voltage designs, select a 2.2-μF low-ESR ceramic input capacitor to ensure a good
startup performance. 24-V input applications require only 0.47-μF of input capacitance.
9.2.3.2 Output Capacitor
For any DCP01B design, select a 1.0-μF low-ESR ceramic output capacitor to reduce output ripple.
9.2.3.3 SYNCIN Pin
In a stand-alone application, leave the SYNCIN pin floating.
9.2.4 PCB Design
The copper losses (resistance and inductance) can be minimized by the use of mutual ground and power planes
(tracks) where possible. If that is not possible, use wide tracks to reduce the losses. If several devices are being
powered from a common power source, a star-connected system for the track must be deployed. Do not connect
the devices in series, because that type of connection cascades the resistive losses. The position of the
decoupling capacitors is important. They must be as close to the devices as possible in order to reduce losses.
See the PCB Layout section for more details.
9.2.5 Decoupling Ceramic Capacitors
Capacitor Impedance (Ÿ )
All capacitors have losses because of internal equivalent series resistance (ESR), and to a lesser degree,
equivalent series inductance (ESL). Values for ESL are not always easy to obtain. However, some
manufacturers provide graphs of frequency versus capacitor impedance. These graphs typically show the
capacitor impedance falling as frequency is increased (as shown in Figure 38). In Figure 38, XC is the reactance
due to the capacitance, X L is the reactance due to the ESL, and f0 is the resonant frequency. As the frequency
increases, the impedance stops decreasing and begins to rise. The point of minimum impedance indicates the
resonant frequency of the capacitor. This frequency is where the components of capacitance and inductance
reactance are of equal magnitude. Beyond this point, the capacitor is not effective as a capacitor.
Z
XC
XL
0
Frequency (Hz)
f0
Figure 38. Capacitor Impedance vs Frequency
However, there is a 180° phase difference resulting in cancellation of the imaginary component. The resulting
effect is that the impedance at the resonant point is the real part of the complex impedance, namely, the value of
the ESR. The output capacitor's resonant frequency must be higher than the default switching frequency
(800 kHz) of the device to properly decouple noise at and below the switching frequency.
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The effect of the ESR is to cause a voltage drop within the capacitor. The value of this voltage drop is simply the
product of the ESR and the transient load current, as shown in Equation 1.
VIN = VPK – (ESR × ITR)
where
•
•
•
VIN is the voltage at the device input
VPK is the maximum value of the voltage on the capacitor during charge
ITR is the transient load current
(1)
The other factor that affects the performance is the value of the capacitance. However, for the input and the full
wave outputs (single-output voltage devices), ESR is the dominant factor.
9.2.6 Input Capacitor and the Effects of ESR
If the input decoupling capacitor is not ceramic (and has an ESR greater than 20 mΩ), then at the instant the
power transistors switch on, the voltage at the input pins falls momentarily. If the voltage falls below
approximately 4 V, the device detects an undervoltage condition and switches the internal drive circuits to a
momentary off state. This detection is carried out as a precaution against a genuine low input voltage condition
that could slow down or even stop the internal circuits from operating correctly. A slow-down or stoppage results
in the drive transistors being turned on too long, causing saturation of the transformer and destruction of the
device.
Following detection of a low input voltage condition, the device switches off the internal drive circuits until the
input voltage returns to a safe value, at which time the device tries to restart. If the input capacitor is still unable
to maintain the input voltage, shutdown recurs. This process repeats until the input capacitor charges sufficiently
to start the device correctly.
Normal startup should occur in approximately 1 ms after power is applied to the device. If a considerably longer
startup duration time is encountered, it is likely that either (or both) the input supply or the capacitors are not
performing adequately.
For 5-V to 15-V input devices, a 2.2-μF, low-ESR ceramic capacitor ensures good startup performance. For 24-V
input voltage devices, 0.47-μF ceramic capacitors are recommended. Tantalum capacitors are not
recommended, since most do not have low-ESR values and will degrade performance. If tantalum capacitors
must be used, close attention must be paid to both the ESR and voltage as derated by the vendor.
NOTE
During the start-up period, these devices may draw maximum current from the input
supply. If the input voltage falls below approximately 4 V, the devices may not start
up. Connect a 2.2-μF ceramic capacitor close to the input pins.
9.2.7 Ripple and Noise
A good quality, low-ESR ceramic capacitor placed as close as practical across the input reduces reflected ripple
and ensures a smooth startup.
A good quality, low-ESR ceramic capacitor placed as close as practical across the rectifier output terminal and
output ground gives the best ripple and noise performance. See DC-to-DC Converter Noise Reduction
(SBVA012), for more information on noise rejection.
9.2.7.1 Output Ripple Calculation Example
The following example shows that increasing the capacitance has a much smaller effect on the output ripple
voltage than does reducing the value of the ESR for the filter capacitor.
To
•
•
•
•
•
20
calculate the output ripple for a DCP010505 device:
VOUT = 5 V
IOUT = 0.2 A
At full output power, the load resistor is 25Ω
Ceramic output capacitor of 1μF, ESR of 0.1Ω
Capacitor discharge time 1% of 800 kHz (ripple frequency)
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DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
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tDIS = 0.0125 μs
τ = C × RLOAD
τ = 1 × 10-6 × 12.5 = 12.5 μs
VDIS = VO(1 – EXP(–tDIS/τ))
VDIS = 5 mV
By contrast, the voltage dropped because of ESR:
VESR = ILOAD × ESR
VESR = 20 mV
Ripple voltage = 25 mV
9.2.8 Dual DCP01B Output Voltage
The voltage output for dual DCP01B devices is half wave rectified; therefore, the discharge time is 1.25 μs.
Repeating the above calculations using the 100% load resistance of 50 Ω (0.1 A per output), the results are:
τ = 25 μs
tDIS = 1.25 μs
VDIS = 244 mV
VESR = 10 mV
Ripple Voltage = 133 mV
This time, it is the capacitor discharging that contributes to the largest component of ripple. Changing the output
filter to 10 μF, and repeating the calculations, the result is:
Ripple Voltage = 25 mV.
This value is composed of almost equal components.
The previous calculations are offered as a guideline only. Capacitor parameters usually have large tolerances
and can be susceptible to environmental conditions.
9.2.9 Optimizing Performance
Optimum performance can only be achieved if the device is correctly supported. The very nature of a switching
converter requires power to be instantly available when it switches on. If the converter has DMOS switching
transistors, the fast edges will create a high current demand on the input supply. This transient load placed on
the input is supplied by the external input decoupling capacitor, thus maintaining the input voltage. Therefore, the
input supply does not see this transient (this is an analogy to high-speed digital circuits). The positioning of the
capacitor is critical and must be placed as close as possible to the input pins and connected via a low-impedance
path.
The optimum performance primarily depends on two factors:
• Connection of the input and output circuits for minimal loss.
• The ability of the decoupling capacitors to maintain the input and output voltages at a constant level.
10 Power Supply Recommendations
The DCP01B is a switching power supply, and as such can place high peak current demands on the input
supply. In order to avoid the supply falling momentarily during the fast switching pulses, ground and power
planes should be used to connect the power to the input of DCP01 device. If this connection is not possible, then
the supplies must be connected in a star formation with the traces made as wide as possible.
Copyright © 2000–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
21
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
www.ti.com
11 Layout
11.1 Layout Guidelines
Due to the high power density of these devices, provide ground planes on the input and output rails.
Figure 39 and Figure 40 show the schematic for the two DIP through-hole packages, and two SOP surfacemount packages for the DCP family of products which include DCP01B, DCP02, DCV01, DCR01, and DCR02.
Figure 41 and Figure 42 illustrate a printed circuit board (PCB) layout for the schematics.
Including input power and ground planes provides a low-impedance path for the input power. For the output, the
COM signal connects via a ground plane, while the connections for the positive and negative voltage outputs
conduct via wide traces in order to minimize losses.
The output should be taken from the device using ground and power planes, thereby ensuring minimum losses.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
Allow the unused SYNC pin, to remain configured as a floating pad. It is advisable to place a guard ring
(connected to input ground) or annulus connected around this pin to avoid any noise pick up. When connecting a
SYNC pin to one or more SYNC design the linking trace to be short and narrow to avoid stray capacitance.
Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on
this pin. The stray capacitance affects the performance of the oscillator.
11.2 Layout Example
CON1
VS1
1
+VS SYNC 14
CON3
JP1
VS3
1
C1
+VS SYNC 28
JP1
C11
NC 27
0V1
2
0V3
–VS
DCP02xxxxP
+V1
6
C3
C2-1
+VOUT
+V3
C2
–VS
3
–VS
C12
R5
5
COM1
C5
C4-1
NC 26
13 +VOUT
C13
R1
2
DCP02xxxxU
COM
12 COM
C4
COM3
C14
R2
C15
R6
– V1
7
–VOUT
– V3
14 –VOUT
CON2
VS2
1
+VS SYNC 14
CON4
JP2
VS4
1
C6
+VS SYNC 28
JP2
C16
NC 27
0V2
2
–VS
0V4
DCP02xxxxP
+V2
6
C8
C7-1
+VOUT
C7
+V4
COM2
C10
C9-1
12 COM
COM4
R4
– V2
C20
C19
R8
7
–VOUT
Figure 39. PCB Schematic, P Package
22
–VS
DCP02xxxxU
COM
C9
3
NC 26
C18
R7
5
–VS
13 +VOUT
C17
R3
2
Submit Documentation Feedback
– V4
14 –VOUT
Figure 40. PCB Schematic, U Package
Copyright © 2000–2019, Texas Instruments Incorporated
Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
www.ti.com
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
Layout Example (continued)
Figure 41. PCB Layout Example, Component-Side View
Figure 42. PCB Layout Example, Non-Component-Side View
Copyright © 2000–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
23
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
DCP01
05
05
(D)
B
(P)
Basic model number: 1-W product
Voltage input:
5, 15, or 24
Voltage output:
5, 7, 12 or 15
Output type:
S (single) or D (dual)
Series
Series B
Package code:
P = 7-pin PDIP (NVA package)
P-U = 7-pin SOP (DUA package)
Figure 43. Supplemental Ordering Information
12.2 Documentation Support
12.2.1 Related Documentation
DC-to-DC Converter Noise Reduction (SBVA012)
External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
Optimizing Performance of the DCP01/02 Series of DC/DC Converters (SBVA013)
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
24
Submit Documentation Feedback
Copyright © 2000–2019, Texas Instruments Incorporated
Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
DCP010505B, DCP010512B, DCP010515B
DCP012405B, DCP010505DB, DCP010507DB, DCP010512DB
DCP010515DB, DCP011512DB, DCP011515DB, DCP012415DB
www.ti.com
SBVS012H – DECEMBER 2000 – REVISED MAY 2019
12.4 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DCP010505B
Click here
Click here
Click here
Click here
Click here
DCP010512B
Click here
Click here
Click here
Click here
Click here
DCP010515B
Click here
Click here
Click here
Click here
Click here
DCP012405B
Click here
Click here
Click here
Click here
Click here
DCP010505DB
Click here
Click here
Click here
Click here
Click here
DCP010507DB
Click here
Click here
Click here
Click here
Click here
DCP010512DB
Click here
Click here
Click here
Click here
Click here
DCP010515DB
Click here
Click here
Click here
Click here
Click here
DCP011512DB
Click here
Click here
Click here
Click here
Click here
DCP011515DB
Click here
Click here
Click here
Click here
Click here
DCP012415DB
Click here
Click here
Click here
Click here
Click here
12.5 Trademarks
E2E is a trademark of Texas Instruments.
Underwriters Laboratories, UL are trademarks of UL LLC.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2000–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DCP010505B DCP010512B DCP010515B DCP012405B DCP010505DB DCP010507DB
DCP010512DB DCP010515DB DCP011512DB DCP011515DB DCP012415DB
25
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCP010505BP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010505BP
DCP010505BP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505BP-U
DCP010505BP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505BP-U
DCP010505BP-U/7E4
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505BP-U
DCP010505BP-UE4
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505BP-U
DCP010505DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010505DBP
DCP010505DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505DBP-U
DCP010505DBP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505DBP-U
DCP010505DBP-U/7E4
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010505DBP-U
DCP010507DBP-U/7E4
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010507DBP-U
DCP010507DBP-UE4
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010507DBP-U
DCP010507DBPE4
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010507DBP
DCP010512BP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010512BP
DCP010512BP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010512BP-U
DCP010512BP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010512BP-U
DCP010512DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010512DBP
DCP010512DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010512DBP-U
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
1-Apr-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCP010512DBP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010512DBP-U
DCP010512DBPE4
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010512DBP
DCP010515BP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010515BP
DCP010515BP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010515BP-U
DCP010515BP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010515BP-U
DCP010515DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP010515DBP
DCP010515DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010515DBP-U
DCP010515DBP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP010515DBP-U
DCP011512DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP011512DBP
DCP011512DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP011512DBP-U
DCP011515DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP011515DBP
DCP011515DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP011515DBP-U
DCP011515DBP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP011515DBP-U
DCP012405BP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP012405BP
DCP012405BP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP012405BP-U
DCP012415DBP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 100
DCP012415DBP
DCP012415DBP-U
ACTIVE
SOP
DUA
7
25
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP012415DBP-U
DCP012415DBP-U/700
ACTIVE
SOP
DUA
7
700
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 100
DCP012415DBP-U
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2019
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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