Texas Instruments | UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with 3.3-mm Channel-to-Channel Spacing (Rev. C) | Datasheet | Texas Instruments UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with 3.3-mm Channel-to-Channel Spacing (Rev. C) Datasheet

Texas Instruments UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with 3.3-mm Channel-to-Channel Spacing (Rev. C) Datasheet
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UCC21530-Q1
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver
with 3.3-mm Channel-to-Channel Spacing
1 Features
3 Description
•
The UCC21530-Q1 is an isolated dual-channel gate
driver with 4-A source and 6-A sink peak current. It is
designed to drive IGBTs and SiC MOSFETs up to 5MHz with best-in-class propagation delay and pulsewidth distortion.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Universal: Dual Low-Side, Dual High-Side or HalfBridge Driver
Wide Body SOIC-14 (DWK) Package
3.3mm spacing between driver channels
Switching Parameters:
– 19-ns Typical Propagation Delay
– 10-ns Minimum Pulse Width
– 5-ns Maximum Delay Matching
– 6-ns Maximum Pulse-Width Distortion
Common-Mode Transient Immunity (CMTI)
Greater than 100-V/ns
Surge Immunity up to 12.8-kVPK
Isolation Barrier Life >40 Years
4-A Peak Source, 6-A Peak Sink Output
TTL and CMOS Compatible Inputs
3-V to 18-V Input VCCI Range
Up to 25-V VDD Output Drive Supply
Programmable Overlap and Dead Time
Rejects Input Pulses and Noise Transients
Shorter than 5 ns
Operating Temperature Range –40 to +125°C
Safety-Related Certifications:
– 8000-VPK Isolation per DIN V VDE V 0884-11
:2017-01 (Planned)
– 5.7-kVRMS Isolation for 1 Minute per UL 1577
– CSA Certification per IEC 60950-1, IEC 623681, IEC 61010-1 and IEC 60601-1 End
Equipment Standards (Planned)
– CQC Certification per GB4943.1-2011
(Planned)
AEC-Q100 Qualified With:
– Device Temperature Grade 1
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
The input side is isolated from the two output drivers
by a 5.7-kVRMS reinforced isolation barrier, with a
minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1850 V.
This driver can be configured as two low-side drivers,
two high-side drivers, or a half-bridge driver with
programmable dead time (DT). The EN pin pulled low
shuts down both outputs simultaneously and allows
for normal operation when left open or pulled high. As
a fail-safe measure, primary-side logic failures force
both outputs low.
The device accepts VDD supply voltages up to 25 V.
A wide input VCCI range from 3 V to 18 V makes the
driver suitable for interfacing with both analog and
digital controllers. All the supply voltage pins have
under voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21530-Q1
enables high efficiency, high power density, and
robustness in a wide variety of power applications.
Device Information(1)
PART NUMBER
UCC21530-Q1
PACKAGE
DWK SOIC (14)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
2 Applications
•
•
•
•
•
•
HEV and BEV Battery Chargers
Solar String and Central Inverters
AC-to-DC and DC-to-DC Charging Piles
AC Inverter and Servo Drive
AC-to-DC and DC-to-DC Power Delivery
Energy Storage Systems
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC21530-Q1
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
7.6 CMTI Testing........................................................... 17
1
1
1
2
3
4
8
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety-Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
Propagation Delay and Pulse Width Distortion.......
Rising and Falling Time .........................................
Input and Enable Response Time...........................
Programable Dead Time ........................................
Power-Up UVLO Delay to OUTPUT .......................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information ................ 15
7.1
7.2
7.3
7.4
7.5
Detailed Description ............................................ 18
15
15
15
16
16
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
13.1 Package Option Addendum .................................. 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2019
C
Initial Release
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5 Pin Configuration and Functions
DWK Package
14-Pin SOIC
Top View
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
DT
6
I
DT pin configuration:
•
Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
•
Placing a resistor (RDT) between DT and GND adjusts dead time according to the
equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a
ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity.
EN
5
I
Enable both driver outputs if asserted high, disable the output if set low. It is recommended
to tie this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF
low ESR/ESL capacitor close to EN pin when connecting to a micro controller with distance.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC
7
–
No internal connection.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor
located as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P =Power, I= Input, O= Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.5
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.5
30
V
OUTA to VSSA, OUTB to VSSB
–0.5
VVDDA+0.5,
VVDDB+0.5
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.5,
VVDDB+0.5
V
–0.5
VVCCI+0.5
V
–2
VVCCI+0.5
V
Output signal voltage
INA, INB, EN, DT to GND
Input signal voltage
INA, INB Transient for 200ns
Channel to channel internal isolation voltage
Junction temperature, TJ
|VSSA-VSSB|
(2)
Storage temperature, Tstg
(1)
(2)
1850
V
–40
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3
18
V
Driver output bias supply refer to Vss
14.7
25
V
TA
Ambient Temperature
–40
125
°C
TJ
Junction Temperature
–40
130
°C
VCCI
VCCI Input supply voltage
VDDAVSSA,
VDDBVSSB
4
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6.4 Thermal Information
UCC21530-Q1
THERMAL METRIC (1)
DWK-14 (SOIC)
UNIT
RθJA
Junction-to-ambient thermal resistance
68.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.7
°C/W
RθJB
Junction-to-board thermal resistance
27.6
°C/W
ψJT
Junction-to-top characterization parameter
17.7
°C/W
ψJB
Junction-to-board characterization parameter
27
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PD
Power dissipation by UCC21530-Q1
PDI
Power dissipation by transmitter side of
UCC21530-Q1
PDA, PDB
Power dissipation by each driver side of
UCC21530-Q1
VCCI = 18 V, VDDA/B = 15 V, INA/B = 3.3 V,
3.9 MHz 50% duty cycle square wave 1-nF
load
VALUE
UNIT
1810
mW
50
mW
880
mW
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6.6 Insulation Specifications
VALUE
UNIT
CLR
PARAMETER
External clearance (1)
Shortest pin-to-pin distance through air
TEST CONDITIONS
>8
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 10.5 µm)
>21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage (3)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 1)
1500
VRMS
DC voltage
2121
VDC
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;
<5
Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s
Method a, After environmental tests subgroup 1.
Vini = VIOTM, tini = 60s;
Apparent charge (4)
qpd
<5
pC
Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s
Method b1; At routine
preconditioning (type test)
test
(100%
production)
and
<5
Vini = 1.2 × VIOTM; tini = 1s;
Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output (5)
VIO = 0.4 sin (2πft), f =1 MHz
1.2
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS =150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
Plan to certify according
to DIN V VDE V 088411:2017-01 and DIN EN
60950-1 (VDE 0805 Tiel
1):2014-08
UL
Plan to certify according to IEC 60950-1,
IEC 62368-1, IEC 61010-1 and IEC
60601-1
CQC
Recognized under UL 1577
Component Recognition
Program
Plan to certify according to GB
4943.1-2011
Single protection, 5700 VRMS
Certification number:
TBD
Master contract number: TBD
File number: E181974
Certificate number: TBD
6.8 Safety-Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
RθJA = 68.3ºC/W, VDDA/B = 15 V, TA =
25°C, TJ = 150°C
IS
Safety output supply
current
Safety supply power
TS
Safety temperature (1)
(1)
MIN
TYP
MAX
UNIT
DRIVER A,
DRIVER B
58
mA
DRIVER A,
DRIVER B
35
mA
INPUT
50
RθJA = 68.3ºC/W, TA = 25°C, TJ = 150°C
DRIVER A
880
See Figure 3
DRIVER B
880
TOTAL
1810
See Figure 2
RθJA = 68.3ºC/W, VDDA/B = 25 V, TA =
25°C, TJ = 150°C
See Figure 2
PS
SIDE
150
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI per operating current
(f = 500 kHz) current per channel
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 15 V
3.0
mA
VCCI TO GND UNDERVOLTAGE THRESHOLDS
VVCCI_ON
UVLO Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
UVLO Falling threshold
2.35
2.5
2.65
V
VVCCI_HYS
UVLO Threshold hysteresis
0.2
V
VDD TO VSS UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold
12.5
13.5
14.5
V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold
11.5
12.5
13.5
V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis
1.0
V
INA and INB
VINAH, VINBH
Input high threshold voltage
1.6
1.8
2
V
VINAL, VINBL
Input low threshold voltage
0.8
1
1.2
V
VINA_HYS,
VINB_HYS
Input threshold hysteresis
VINA, VINB
Negative transient, ref to GND, 50
ns pulse
0.8
Not production tested, bench test
only
V
–5
V
EN THRESHOLDS
VENH
Enable high voltage
VENL
Enable low voltage
8
2.0
V
0.8
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pullup performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 15 V, IOUT = –10
mA, TA = 25°C
14.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 15 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
DT pin tied to VCCI
Dead time
RDT = 20 kΩ
Overlap determined by INA INB
160
200
-
240
ns
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
16
ns
7
12
ns
20
ns
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
14
19
30
ns
tPDLH
Propagation delay from INx to OUTx
rising edges
14
19
30
ns
tPWD
Pulse width distortion |tPDLH – tPDHL|
6
ns
tDM
Propagation delays matching
between VOUTA, VOUTB
f = 100 kHz
5
ns
tVCCI+ to
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See Figure 31
INA or INB tied to VCCI
OUT
tVDD+ to
Output off for less than minimum,
COUT = 0 pF
40
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
INA or INB tied to VCCI
See Figure 32
|CMH|
High-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1500 V;
100
|CML|
Low-level common-mode transient
immunity (See CMTI Testing)
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1500 V;
100
µs
50
V/ns
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6.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
87.5%
1.E+9
Time to Fail (s)
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500
1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
70
2000
VDD=15V
VDD=25V
60
Safety Limiting Power (mW)
Safety Limiting Current per Channel (mA)
Figure 1. Reinforced Isolation Capacitor
Life Time Projection
50
40
30
20
1200
800
400
10
0
0
0
25
50
75
100
125
Ambient Temperature (°C)
150
175
0
D001
Figure 2. Thermal Derating Curve for Safety-Related
Limiting Current
(Current in Each Channel with Both Channels Running
Simultaneously)
10
1600
25
50
75
100
125
Ambient Temperature (°C)
150
175
D002
Figure 3. Thermal Derating Curve for Safety-Related
Limiting Power
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6.12 Typical Characteristics
VDDA = VDDB = 15 V, VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted)
16
60
50
Current (mA)
Current (mA)
12
8
40
30
20
4
10
VDD=15V
VDD=25V
0
VDD=15V
VDD=25V
0
0
1000
2000
3000
Frequency (kHz)
4000
5000
0
500
1000
1500
2000
Frequency (kHz)
D003
Figure 4. Per Channel Current Consumption vs. Frequency
(No Load, VDD = 15 V or 25 V)
2500
D004
Figure 5. Per Channel Current Consumption (IVDDA/B) vs.
Frequency (1-nF Load, VDD = 15 V or 25 V)
6
27.5
50kHz
250kHz
500kHz
1MHz
25
5
22.5
VDD Current (mA)
20
17.5
Current (mA)
3000
15
12.5
10
7.5
5
0
0
10
20
30
40
50
60
Frequency (kHz)
70
80
90
3
2
1
VDD=15V
VDD=25V
2.5
4
0
-40
100
-20
0
20
D005
40
60
80 100
Temperature (qC)
120
140
160
D001
Figure 6. Per Channel Current Consumption (IVDDA/B) vs.
Frequency (10-nF Load, VDD = 15 V or 25 V)
Figure 7. Per Channel (IVDDA/B) Supply Current Vs.
Temperature (VDD=15V, No Load, Different Switching
Frequencies)
1.6
2
1.8
Current (mA)
Current (mA)
1.2
0.8
1.6
1.4
0.4
1.2
VDD=15V
VDD=25V
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
VCCI= 3.3V
VCCI= 5V
140
1
-40
-20
D006
Figure 8. Per Channel (IVDDA/B) Quiescent Supply Current vs
Temperature (No Load, Input Low, No Switching)
0
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 9. IVCCI Quiescent Supply Current vs Temperature
(No Load, Input Low, No Switching)
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Typical Characteristics (continued)
25
10
20
8
Resistance (:)
Time (ns)
VDDA = VDDB = 15 V, VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted)
15
10
5
6
Output Pull-Up
Output Pull-Down
4
2
tRISE
tFALL
0
0
2
4
6
8
0
-40
10
Load (nF)
Figure 10. Rising and Falling Times vs. Load
0
20
40
60
80
Temperature (qC)
28
20
24
19
20
16
12
140
D001
17
16
8
-40
Rising Edge (tPDLH)
Falling Edge (tPDHL)
15
-20
0
20
40
60
80
Temperature (qC)
100
120
140
3
6
9
12
15
VCCI (V)
D001
Figure 12. Propagation Delay vs. Temperature
18
D001
Figure 13. Propagation Delay vs. VCCI
5
5
Propagation Delay Matching (ns)
Pulse Width Distortion (ns)
120
18
Rising Edge (tPDLH)
Falling Edge (tPDHL)
3
1
-1
-3
-5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
2.5
0
-2.5
Rising Edge
Falling Edge
-5
10
D001
Figure 14. Pulse Width Distortion vs. Temperature
12
100
Figure 11. Output Resistance vs. Temperature
Propagation Delay (ns)
Propagation Delay (ns)
-20
D001
13
16
19
VDDA/B (V)
22
25
D001
Figure 15. Propagation Delay Matching (tDM) vs. VDD
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Typical Characteristics (continued)
VDDA = VDDB = 15 V, VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted)
1100
1080
1060
2.5
Hysteresis (mV)
Propagation Delay Matching (ns)
5
0
1040
1020
1000
980
960
-2.5
940
Rising Edge
Falling Edge
-5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
920
900
-40
140
Figure 16. Propagation Delay Matching (tDM) vs.
Temperature
INA/B Threshold Hysteresis (mV)
UVLO Threshold (V)
13
12
11
VVDD_ON
VVDD_OFF
40
60
80
Temperature (qC)
100
120
140
D001
-20
0
20
40
60
80
Temperature (qC)
100
120
860
820
780
740
700
-40
140
1.14
1.92
INA/B High Threshold (V)
2
1.08
1.02
0.96
VCC=3.3V
VCC= 5V
VCC=12V
0
20
40
60
80
Temperature (qC)
-20
0
100
120
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 19. INA/B Hysteresis vs. Temperature
1.2
-20
VCC=3.3V
VCC=5V
VCC=12V
D001
Figure 18. UVLO Threshold vs. Temperature
INA/B Low Threshold (V)
20
900
14
0.9
-40
0
Figure 17. UVLO Hysteresis vs. Temperature
15
10
-40
-20
D001
140
1.84
1.76
1.68
1.6
-40
VCC=3.3V
VCC= 5V
VCC=12V
-20
D001
Figure 20. INA/B Low Threshold
0
20
40
60
80
Temperature (qC)
100
120
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D001
Figure 21. INA/B High Threshold
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Typical Characteristics (continued)
VDDA = VDDB = 15 V, VCCI = 3.3 V, TA = 25°C, No load. (unless otherwise noted)
1.1
VCC=3.3V
VCC=5V
VCC=18V
1000
EN Low Threshold (V)
EN Threshold Hysteresis (mV)
1200
800
600
1
0.9
VCC=3.3V
VCC=5.0V
VCC=18V
400
200
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0.8
-40
140
-20
0
20
D001
Figure 22. EN Threshold Hysteresis vs. Temperature
40
60
80
Temperature (°C)
100
120
140
D001
Figure 23. EN Low Threshold
1500
2
RDT= 20k:
RDT= 100k:
1200
Dead Time (ns)
EN High Threshold (V)
1.8
1.6
1.4
VCC=3.3V
VCC=5.0V
VCC=18V
1.2
1
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
900
600
300
0
-40
140
-20
0
20
D001
Figure 24. EN High Threshold
40
60
80
Temperature (qC)
100
120
140
D001
Figure 25. Dead Time vs. Temperature (with RDT = 20 kΩ and
100 kΩ)
5
'DT (ns)
-6
-17
-28
-39
RDT= 20k:
RDT = 100k:
-50
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 26. Dead Time Matching vs. Temperature (with RDT = 20 kΩ and 100 kΩ)
14
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7 Parameter Measurement Information
7.1 Propagation Delay and Pulse Width Distortion
Figure 27 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the propagation
delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the dead
time function by shorting the DT Pin to VCC.
INA/B
tPDHLA
tPDLHA
tDM
OUTA
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB
Figure 27. Overlapping Inputs, Dead Time Disabled
7.2 Rising and Falling Time
Figure 28 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Output Stage.
80%
tRISE
90%
tFALL
20%
10%
Figure 28. Rising and Falling Time Criteria
7.3 Input and Enable Response Time
Figure 29 shows the response time of the enable function. For more information, see Enable Pin .
INx
EN
EN Low
Response Time
EN High
Response Time
OUTx
90%
90%
tPDLH
tPDHL
10%
10%
10%
Figure 29. Enable Pin Timing
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7.4 Programable Dead Time
Tying DT to VCCI disables DT feature and allows the outputs to overlap. Placing a resistor (RDT) between DT pin
and GND can adjust the dead time. For more details on dead time, refer to Programmable Dead Time (DT) Pin .
INA
INB
90%
OUTA
10%
tPDHL
tPDLH
90%
OUTB
10%
tPDHL
Dead Time
(Set by RDT)
Dead Time
(Determined by Input signals if
longer than DT set by RDT)
Figure 30. Dead-Time Switching Parameters
7.5 Power-Up UVLO Delay to OUTPUT
Whenever the supply voltage VCCI crosses from below the falling threshold VVCCI_OFF to above the rising
threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold VVDDx_OFF to
above the rising threshold VVDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI
UVLO this delay is defined as tVCCI+ to OUT, and is typically 40 µs. For VDDx UVLO this delay is defined as tVDD+ to
OUT, and is typically 50 µs. TI recommends allowing some margin before driving input signals, to ensure the
driver VCCI and VDD bias supplies are fully activated. Figure 31 and Figure 32 show the power-up UVLO delay
timing diagram for VCCI and VDD.
Whenever the supply voltage VCCI crosses below the falling threshold VVCCI_OFF, or VDDx crosses below the
falling threshold VVDDx_OFF, the outputs stop responding to the inputs and are held low within 1 µs. This
asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.
VCCI,
INx
VDDx
VVCCI_ON
VVCCI_OFF
VDDx
tVCCI+ to OUT
OUTx
VVDD_ON
tVDD+ to OUT
VVDD_OFF
OUTx
Figure 31. VCCI Power-Up UVLO Delay
16
VCCI,
INx
Figure 32. VDDA/B Power-Up UVLO Delay
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7.6 CMTI Testing
Figure 33 is a simplified diagram of the CMTI testing configuration.
Figure 33. Simplified CMTI Testing Setup
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8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21530-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and
motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC21530-Q1 has
many features that allow it to integrate well with control circuitry and protect the transistors it drives such as:
resistor-programmable dead time (DT) control, an EN pin, and under voltage lock out (UVLO) for both input and
output voltages. The UCC21530-Q1 also holds its outputs low when the inputs are left open or when the input
pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog
power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and
independent control of each of the outputs.
8.2 Functional Block Diagram
18
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8.3 Feature Description
8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC21530-Q1 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of
the status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 34). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically less than 1.5V, when no bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
Figure 34. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is
bound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21530-Q1 also has an internal under voltage lock out (UVLO) protection feature. The
device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. The signal will cease to be
delivered once the pin receives a voltage less than VVCCI_OFF. In the same way as the VDD UVLO, there is
hysteresis (VVCCI_HYS) to ensure stable operation.
UCC21530-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.
Table 1. UCC21530-Q1 VCCI UVLO Feature Logic
CONDITION
INPUTS
INA
OUTPUTS
INB
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
H
L
L
L
VCCI-GND < VVCCI_ON during device start up
L
H
L
L
VCCI-GND < VVCCI_ON during device start up
H
H
L
L
VCCI-GND < VVCCI_ON during device start up
L
L
L
L
VCCI-GND < VVCCI_OFF after device start up
H
L
L
L
VCCI-GND < VVCCI_OFF after device start up
L
H
L
L
VCCI-GND < VVCCI_OFF after device start up
H
H
L
L
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
Table 2. UCC21530-Q1 VDD UVLO Feature Logic
CONDITION
INPUT: INx
OUTPUT: OUTx
VDDx-VSSx < VVDD_ON during device start up
L
L
VDDx-VSSx < VVDD_ON during device start up
H
L
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Table 2. UCC21530-Q1 VDD UVLO Feature Logic (continued)
CONDITION
INPUT: INx
OUTPUT: OUTx
VDDx-VSSx < VVDD_OFF after device start up
L
L
VDDx-VSSx < VVDD_OFF after device start up
H
L
8.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up. See VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes.
Table 3. INPUT/OUTPUT Logic Table (1)
INPUTS
INA
INB
EN
OUTPUTS
OUTA
NOTE
OUTB
L
L
H or Left Open
L
L
L
H
H or Left Open
L
H
H
L
H or Left Open
H
L
H
H
H or Left Open
L
L
DT is left open or programmed with RDT
H
H
H or Left Open
H
H
DT pin pulled to VCCI
Left Open
Left Open
H or Left Open
L
L
X
(1)
X
L
L
L
If Dead Time function is used, output transitions occur after the
dead time expires. See Programmable Dead Time (DT) Pin
Bypass using a ≥ 1-nF low ESR/ESL capacitor close to EN pin
when connecting to a µC with distance
"X" means L, H or left open.
8.3.3 Input Stage
The input signal pins (INA and INB) of UCC21530-Q1 are based on a TTL and CMOS compatible input-threshold
logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control
signals (Such as those from 3.3-V micro-controllers), since UCC21530-Q1 has a typical high threshold (VINA/BH)
of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure 20,Figure 21). A wide
hysterisis (VINA/B_HYS) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever
left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See Functional
Block Diagram). However, it is still recommended to ground an input if it is not being used.
Since the input side of UCC21530-Q1 is isolated from the output drivers, the input signal amplitude can be larger
or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when
integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen
gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI.
20
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8.3.4 Output Stage
The UCC21530-Q1’s output stages features a pull-up structure which delivers the highest peak-source current
when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power
switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel
MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to
provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning
on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The onresistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21530-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter.
The pull-down structure in UCC21530-Q1 is simply composed of an N-channel MOSFET. The ROL parameter,
which is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both
outputs of the UCC21530-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The
output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which
delivers very low drop-out.
VDD
ROH
Input
Signal
ShootThrough
Prevention
Circuitry
RNMOS
OUT
Pull Up
ROL
VSS
Figure 35. Output Stage
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8.3.5 Diode Structure in UCC21530-Q1
Figure 36 illustrates the multiple diodes involved in the ESD protection components of the UCC21530-Q1. This
provides a pictorial representation of the absolute maximum rating for the device.
Figure 36. ESD Structure
8.4 Device Functional Modes
8.4.1 Enable Pin
Setting the EN pin low, i.e. VEN≤0.8V, shuts down both outputs simultaneously. Pull the EN pin high (or left
open), i.e. VEN≥2.0V, allows UCC21530-Q1 to operate normally. The EN pin is quite responsive, as far as
propagation delay and other switching parameters are concerned, the delay between EN are OUTA and OUTB is
about 40ns. The EN pin is only functional (and necessary) when VCCI stays above the UVLO threshold. It is
highly recommended to tie EN to VCCI directly to achieve better noise immunity.
8.4.2 Programmable Dead Time (DT) Pin
UCC21530-Q1 allows the user to adjust dead time (DT) in the following ways:
8.4.2.1 DT Pin Tied to VCC
Outputs completely match inputs, so no minimum dead time is asserted. This allows outputs to overlap. It is
recommended to connect this pin to VCCI directly if it is not used to achieve better noise immunity.
8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
Program tDT by placing a resistor, RDT, between the DT pin and GND. TI recommends bypassing this pin with a
ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity. The appropriate RDT value
can be determined from:
tDT | 10 u RDT
where
•
•
22
tDT is the programmed dead time, in nanoseconds.
RDT is the value of resistance between DT pin and GND, in kilo-ohms.
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Device Functional Modes (continued)
The steady state voltage at the DT pin is about 0.8 V. RDT programs a small current at this pin, which sets the
dead time. As the value of RDT increases, the current sourced by the DT pin decreases. The DT pin current will
be less than 10 µA when RDT = 100 kΩ. For larger values of RDT, TI recommends placing RDT and a ceramic
capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better
dead time matching between both channels.
The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed
dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may
also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a
dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs
will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does
not affect the programmed dead time setting for normal operation. Various driver dead time logic operating
conditions are illustrated and explained in Figure 37.
INA
INB
DT
OUTA
OUTB
A
B
C
D
E
F
Figure 37. Input and Output Logic Relationship With Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,
when INA goes high, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it
immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls
OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to
OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls
OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to
OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21530-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal
capability of the UCC21530-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a
low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With
integrated components, advanced protection features (UVLO, dead time, and enable) and optimized switching
performance; the UCC21530-Q1 enables designers to build smaller, more robust designs for enterprise, telecom,
automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in Figure 38 shows a reference design with UCC21530-Q1 driving a typical half-bridge configuration
which could be used in several popular power converter topologies such as synchronous buck, synchronous
boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. This circuit uses two
supplies (or single-input-double-output power supply). Power supply VA+ determines the positive drive output
voltage and VA– determines the negative turn-off voltage. The configuration for channel B is the same as channel
A.
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. This solution has two separate power supplies for each driver channel, so it provides flexibility
when setting the positive and negative rail voltages.
Figure 38. Typical Application Schematic with Dual Power Supplies
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Typical Application (continued)
9.2.1 Design Requirements
Table 4 lists reference design parameters for the example application: UCC21530-Q1 driving 1000-V SiCMOSFETs in a high side-low side configuration.
Table 4. UCC21530-Q1 Design Requirements
PARAMETER
VALUE
UNITS
Power transistor
C3M0065100K
–
VCC
5.0
V
VDD
15
V
VSS
–4
V
RON
2.2
Ω
ROFF
0
Ω
Input signal amplitude
3.3
V
Switching frequency (fs)
100
kHz
DC link voltage
600
V
9.2.2 Detailed Design Procedure
9.2.2.1 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to 100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.2 Select Dead Time Resistor and Capacitor
From Equation 1, a 10-kΩ resistor is selected to set the dead time to 100 ns. A 2.2-nF capacitor is placed in
parallel close to the DT pin to improve noise immunity.
9.2.2.3 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1.
Limit ringing caused by parasitic inductances/capacitances.
2.
Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3.
Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4.
Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC21530-Q1 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
where
•
•
•
RON: External turn-on resistance,RON=2.2 Ω in this example;.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(2)
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In this example:
(3)
Therefore, the driver peak source current is 2.4 A for each channel. Similarly, the peak sink current can be
calculated with:
where
•
•
•
ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(4)
In this example,
(5)
Therefore, the driver peak sink current is 3.5 A for each channel.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.4 Estimate Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21530-Q1 (PGD) and the
power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not
included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21530-Q1, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with
no load. In this example, VVCCI = 5 V and VVDD-VVSS = 19 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore,
the PGDQ can be calculated with
(6)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
where
•
QG is the gate charge of the power transistor.
(7)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
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So, for this example application:
(8)
QG represents the total gate charge of the power transistor switching 600 V at 20 A, and is subject to change
with different testing conditions. The UCC21530-Q1 gate driver loss on the output stage, PGDO, is part of PGSW.
PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss is
dissipated inside the UCC21530-Q1. If there are external turn-on and turn-off resistances, the total loss will be
distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pullup/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however,
it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
(9)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21530-Q1
gate driver loss can be estimated with:
(10)
Case 2 - Nonlinear Pull-Up/Down Resistor:
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(11)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pulldown based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21530Q1, PGD, is:
(12)
which is equal to 103 mW in the design example.
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9.2.2.5 Estimating Junction Temperature
The junction temperature of the UCC21530-Q1 can be estimated with:
TJ
TC
< JT u PGD
where
•
•
•
TJ is the junction temperature.
TC is the UCC21530-Q1 case-top temperature measured with a thermocouple or some other instrument.
ψJT is the junction-to-top characterization parameter from the Thermal Information table.
(13)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor
and IC Package Thermal Metrics application report.
9.2.2.6 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
9.2.2.6.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
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9.2.2.7 Other Application Example Circuits
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
Instead of using two separate power for generating positive and negative drive voltage Figure 39 shows the
example with negative bias turn-off on the channel-A driver using a Zener diode on the isolated power supply
output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply, VA, is equal to 19
V, the turn-off voltage will be –3.9 V and turn-on voltage will be 19 V -– 3.9 V ≈ 15 V. The channel-B driver circuit
is the same as channel-A, therefore, this configuration needs only one power supply for each driver channel, and
there will be steady state power consumption from RZ.
Figure 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
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Figure 40 shows another example which uses bootstrap to provide power for the channel A, this solution doesn't
have negative rail voltage, it is only suitable for circuits with less ringing or the power device has high threshold
voltage.
Figure 40. Bootstrap Power Supply for the High Side Device
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The last example, shown in Figure 41, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and
the bootstrap power supply can be used for the high side drive. This design requires the least cost and design
effort among the three solutions. However, this solution has limitations:
1.
The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias
voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency
resonant convertors or phase shift convertors which favor this solution.
2.
The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side
switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to
refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply
for the high side, like in the other two example circuits.
Figure 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
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9.2.3 Application Curves
Figure 42 shows a multiple pulses bench test circuit which uses L1 as the inductor load, and a group of control
pulses are generated to evaluate driver and SiC MOSFET switching transient under different load conditions.
The test conditions are: VDC-Link = 600 V, VCC = 5 V, VDD = 15 V, VSS = –4 V, fSW = 500 kHz, RON = 5.1 Ω, ROFF
= 1.0 Ω. Figure 43 shows the turn on and turn off waveforms at around 20 A current
Channel 1 (Yellow): Gate-source voltage signal on the low side MOSFET.
Channel 2 (Blue): Gate-source voltage signal on the high side MOSFET.
Channel 3 (Pink): Drain-source voltage signal for the low side MOSFET.
Channel 4 (Green): Drain-source current signal for the low side MOSFET.
In Figure 43, the gate drive signals on the high and low power transistor have a 100-ns dead time, and both
signals are measured with >= 500 MHz bandwidth probes.
Figure 42. Bench Test Circuit with SiC MOSFET Switching
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Figure 43. SiC MOSFET Switching Waveforms
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10 Power Supply Recommendations
The recommended input supply voltage (VCCI) for UCC21530-Q1 is between 3 V and 18 V. The output bias
supply voltage (VDDA/VDDB) range depends on which version of UCC21530-Q1 one is using. The lower end of
this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each
device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on
UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends
on the maximum gate voltage of the power device being driven by UCC21530-Q1. All versions of UCC21530-Q1
have a recommended maximum VDDA/VDDB of 25 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further
suggested that one place two such capacitors: one with a value of between 220 nF and 10 µF for device biasing,
and an additional 100-nF capacitor in parallel for high frequency filtering.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of UCC21530-Q1, this bypass capacitor has a minimum
recommended value of 100 nF.
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11 Layout
11.1 Layout Guidelines
Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21530-Q1.
11.1.1 Component Placement Considerations
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
• To improve noise immunity when driving the EN pin from a distant micro-controller, TI recommends adding a
small bypass capacitor, ≥ 1 nF, between the EN pin and GND.
• If the dead time feature is used, TI recommends placing the programming resistor RDT and bypassing
capacitor close to the DT pin of the UCC21530-Q1 to prevent noise from unintentionally coupling to the
internal dead time circuit. The capacitor should be ≥ 2.2 nF.
11.1.2 Grounding Considerations
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
11.1.3 High-Voltage Considerations
• To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may
compromise the isolation performance.
• For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout
between the high and low-side PCB traces.
11.1.4 Thermal Considerations
• A large amount of power may be dissipated by the UCC21530-Q1 if the driving voltage is high, the load is
heavy, or the switching frequency is high (refer to Estimate Gate Driver Power Loss for more details). Proper
PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal
impedance (θJB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 45 and Figure 46). However, high voltage PCB
considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces
or copper from different high-voltage planes overlap.
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11.2 Layout Example
Figure 44 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 44. Layout Example
Figure 45 and Figure 46 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 45. Top Layer Traces and Copper
36
Figure 46. Bottom Layer Traces and Copper
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Layout Example (continued)
Figure 47 and Figure 48 are 3D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
Figure 47. 3-D PCB Top View
Figure 48. 3-D PCB Bottom View
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UCC21530-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
UCC21530QDWKQ1
Active
SOIC
DWK
14
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
UCC21530Q
UCC21530QDWKRQ1
Active
SOIC
DWK
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
UCC21530Q
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21530-Q1
39
UCC21530-Q1
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
www.ti.com
13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
PUCC21530QDWKRQ
1
SOIC
DWK
14
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
40
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Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21530-Q1
UCC21530-Q1
www.ti.com
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PUCC21530QDWKRQ1
SOIC
DWK
14
2000
367.0
367.0
38.0
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Product Folder Links: UCC21530-Q1
41
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SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
42
www.ti.com
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21530-Q1
UCC21530-Q1
www.ti.com
SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21530-Q1
43
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SLUSDG3C – AUGUST 2018 – REVISED MARCH 2019
44
www.ti.com
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: UCC21530-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC21530QDWKQ1
ACTIVE
SOIC
DWK
14
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21530Q
UCC21530QDWKRQ1
ACTIVE
SOIC
DWK
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21530Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2019
OTHER QUALIFIED VERSIONS OF UCC21530-Q1 :
• Catalog: UCC21530
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
DWK0014A
SOIC - 2.65 mm max height
SCALE 1.500
SMALL OUTLINE INTEGRATED CIRCUIT
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
11X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
B
7.6
7.4
NOTE 4
14X 0.51
0.31
0.25
C A
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4224374/A 06/2018
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DWK0014A
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
14X (2)
SYMM
14X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
14X (0.6)
14X (0.6)
SYMM
SYMM
11X (1.27)
11X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224374/A 06/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWK0014A
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
SYMM
14X (1.65)
14X (2)
1
1
16
16
14X (0.6)
14X (0.6)
SYMM
SYMM
11X (1.27)
11X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4224374/A 06/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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