Texas Instruments | TPS65295 complete DDR4 memory power solution | Datasheet | Texas Instruments TPS65295 complete DDR4 memory power solution Datasheet

Texas Instruments TPS65295 complete DDR4 memory power solution Datasheet
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TPS65295
SLUSDK5 – FEBRUARY 2019
TPS65295 complete DDR4 memory power solution
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
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Synchronous buck converter (VDDQ)
– Input voltage range: 4.5 V to 18 V
– Output voltage fixed at 1.2 V
– D-CAP3™ mode control for fast transient
response
– Continual output current: 8 A
– Advanced Eco-mode™ pulse skip
– Integrated 22-mΩ and 8.6-mΩ RDS(on) internal
power switch
– 600-kHz switching frequency
– Internal soft start: 1.6 ms
– Cycle-by-cycle overcurrent protection
– Latched output OV and UV protections
Synchronous buck converter (VPP)
– Input voltage range: 3 V to 5.5 V
– Output voltage fixed at 2.5 V
– D-CAP3™ mode control for fast transient
response
– Continual output current: 1 A
– Advanced Eco-mode™ pulse skip
– Integrated 150-mΩ and 120-mΩ RDS(on)
internal power switch
– 580-kHz switching frequency
– Internal soft start: 1 ms
– Cycle-by-cycle overcurrent protection
– Latched output OV and UV protections
1-A LDO (VTT)
– 1-A continual sink and source current
– Requires only 10 μF of ceramic output
capacitor
– Support high-z in S3
– ±30-mV VTT output accuracy (DC+AC)
Buffered reference (VTTREF)
– Buffered, low noise, ±10-mA capability
– 0.8% output accuracy
Low quiescent current: 150 µA
Power good indicator
Output discharge function
Power up and power down sequencing control
Non-latch for OT and UVLO protections
18-pin 3.0-mm × 3.0-mm HotRod™ VQFN
package
DDR4 memory power supplies
Notebook, PC computers, and servers
Ultrabook, tablet computers
Single-board computer, computer on module
3 Description
The TPS65295 device provides a complete power
solution for DDR4 memory system with the lowest
total cost and minimum space. It meets the JEDEC
standard for DDR4 power-up and power-down
sequence requirement. The TPS65295 integrates two
synchronous buck converters (VPP and VDDQ) and a
1-A sink and source tracking LDO (VTT) and a
buffered low noise reference (VTTREF). The
TPS65295 employs D-CAP3™ mode coupled with
600-kHz switching frequency for ease-of-use, fast
transient, and support for ceramic output capacitors
without an external compensation circuit.
The VTTREF tracks ½ VDDQ within excellent 0.8%
accuracy. The VTT, which provides both 1-A sink and
source continual current capabilities, requires only
10-μF of ceramic output capacitor.
The TPS65295 provides rich functions as well as
excellent power supply performance. It supports
flexible power state control, placing VTT at high-Z in
S3 and discharging VDDQ, VTT, and VTTREF in
S4/S5 state. OVP, UVP, OCP, UVLO and thermal
shutdown protections are also available. The part is
available in a thermally enhanced 18-pin HotRod™
VQFN package and is designed to operate under the
–40°C to 125°C junction temperature range.
Device Information(1)
PART NUMBER
PACKAGE
TPS65295
VQFN (18)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
L_VPP
PVIN
PVIN_VPP
5V
BST
VCC_5V
VLDOIN
SLP_S4
C-bst
L_VDDQ
SW
VDDQ
Cout_VDDQ
VDDQSNS
VTT
PGOOD
Cout_VPP
VPPSNS
TPS65295
VDDQ
VPP
SW_VPP
PVIN
VTTSNS
VTTREF
VTT
Cout_VTT
VTT_REF
Cout_VTTREF
VTT_CNTL
PGND_VPP
AGND
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65295
SLUSDK5 – FEBRUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 18
13
14
15
17
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
12.1 Package Option Addendum .................................. 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2019
*
Initial release.
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5 Pin Configuration and Functions
RJE Package
18-Pin VQFN
Top View
BST
SW PGND_VPP
15
SW_VPP
14
PVIN_VPP
3
13
VCC_5V
VTTSNS
4
12
VPPSNS
VDDQSNS
5
11
SLP_S4
VTTREF
6
10
VTT_CNTL
VLDOIN
1
VTT
2
AGND
18
16
17
7
9
8
PVIN PGOOD PGND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VLDOIN
1
P
Power supply input for VTT LDO. Connect VDDQ in typical application.
VTT
2
O
VTT 1-A LDO output. Recommend to connect to 10-μF or larger capacitance for stability.
AGND
3
G
Signal ground.
VTTSNS
4
I
VTT output voltage feedback.
VDDQSNS
5
I
VDDQ output voltage feedback.
VTTREF
6
O
Buffered VTT reference output. Recommend to connect to 0.22-μF or larger capacitance for stability.
PVIN
7
P
Input power supply for VDDQ buck.
PGOOD
8
O
Power good signal open-drain output. PGOOD goes high when VPP and VDDQ output voltage are within
the target range.
PGND
9
G
Power ground for VDDQ buck.
VTT_CNTL
10
I
VTT_CNTL signal input for VTT LDO enable control. For detail control setup, please refer toTable 1.
SLP_S4
11
I
SLP_S4 signal input for VDDQ buck and VPP buck enable control. For detail control setup, please refer
toTable 1.
VPPSNS
12
I
VPP output voltage feedback.
VCC_5V
13
P
Power supply for VPP and VDDQ buck converter control logic circuit.
PVIN_VPP
14
P
Input power supply for VPP buck.
SW_VPP
15
O
VPP switching node connection to the inductor and bootstrap capacitor.
PGND_VPP
16
G
Power ground for VPP buck.
SW
17
O
VDDQ switching node connection to the inductor and bootstrap capacitor.
BST
18
I
High-side MOSFET gate driver bootstrap voltage input for VDDQ buck. Connect a capacitor between the
BST pin and the SW pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
UNIT
PVIN
–0.3
20
V
VBST
–0.3
25
V
VBST-SW
–0.3
6
V
VTT_CNTL, SLP_S4, VCC_5V, PVIN_VPP,
VLDOIN, VDDQSNS, VTTSNS, VPPSNS
–0.3
6
V
PGND, AGND,PGND_VPP
–0.3
0.3
V
SW DC
–0.3
20
V
SW (20-ns transient)
Output voltage
SW_VPP DC
SW_VPP (20-ns transient)
PGOOD, VTT,VTTREF
–3
22
V
–0.3
7
V
–3
8
V
–0.3
6
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Electrostatic
discharge
V(ESD)
(1)
(2)
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22- V C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
MAX
UNIT
PVIN
4.5
18
V
VBST
–0.3
23
V
VBST-SW
–0.3
5.5
V
VTT_CNTL, SLP_S4, VCC_5V, PVIN_VPP,
VLDOIN, VDDQSNS, VTTSNS, VPPSNS
–0.3
5.5
V
PGND, AGND,PGND_VPP
–0.3
0.3
V
SW DC
–0.3
18
V
SW (20-ns transient)
Output voltage
SW_VPP DC
SW_VPP (20-ns transient)
PGOOD, VTT,VTTREF
IVDDQOUT
VDDQ Output current
TJ
Operating junction temperature
4
–3
20
V
–0.3
5.5
V
–3
6.5
V
–0.3
5.5
V
–40
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A
125
°C
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6.4 Thermal Information
TPS65295
THERMAL METRIC (1)
RJE (VQFN)
UNIT
18 PINS
RθJA
Junction-to-ambient thermal resistance
58.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.1
°C/W
RθJB
Junction-to-board thermal resistance
17.7
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
17.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VPP=5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VSLP_S4 = VVTT_CNTL = 0 V
IVCC_5V
VIN
VCC_5V supply current
5
µA
VSLP_S4 = 5 V, VVTT_CNTL = 0 V, no
load
110
µA
VSLP_S4 = VVTT_CNTL = 5 V, no load
150
µA
PVIN input voltage range
4.5
18
V
4.5
V
UVLO
Wake up VCC_5V voltage
UVLO
VCC_5V under-voltage lockout
Shut down VCC_5V voltage
4.1
3.3
Hysteresis VCC_5V voltage
3.6
V
500
mV
VDDQ
VVDDQSNS
VDDQ sense voltage
1.188
1.2
IVDDQSNS
VDDQSNS input current
VVDDQSNS =1.2 V
40
µA
IVDDQDIS
VDDQ discharge current
VSLP_S4 = VVTT_CNTL = 0 V,
VVDDQSNS = 0.5 V
12
mA
tVDDQSS
VDDQ soft-start time
tVDDQDLY
VDDQ ramp up delay time
1.6
1.212
2.65
V
ms
2
ms
22
mΩ
8.6
mΩ
RDSONH
High-side switch resistance
TJ = 25°C, VPVIN = 19V, VVCC_5V =
5V
RDSONL
Low-side switch resistance
TJ = 25°C, VPVIN = 19V, VVCC_5V =
5V
IVDDQOCL
Low-side valley current limited
VOUT = 1.2 V, L = 0.68 µH
fsw
VDDQ switching freqency
600
kHz
tOFF(MIN)
Minimum off time
198
ns
87
%
VDDQSNS / VPPSNS rising (Good)
93
%
VDDQSNS / VPPSNS rising (Fault)
115
%
VDDQSNS / VPPSNS falling (Good)
110
%
8.2
9.8
11.5
A
PGOOD (VDDQ, VPP)
VDDQSNS / VPPSNS falling (Fault)
VTHPG
PGOOD threshold
IPGMAX
PG sink current
VPGOOD =0.5V, VSLP_S4 =VVTT_CNTL
= 5 V, no load
46
mA
tPGDLY
PG start-up delay
PG from low to high
1
ms
VPP
VVPPSNS
VPP sense voltage
IVPPSNS
VPPSNS input current
2.45
VVPPSNS =2.5 V
2.5
20
2.55
V
µA
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Electrical Characteristics (continued)
TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VPP=5V (unless otherwise noted)
PARAMETER
IVPPDIS
VPP discharge current
tVPPSS
VPP soft-start time
TEST CONDITIONS
MIN
VSLP_S4 = VVTT_CNTL = 0 V, VVPPSNS
= 0.5 V
TYP
12
1 .0
RDSONH
High-side switch resistance
TJ = 25°C, VPVIN_VPP = 5V, VVCC_5V
= 5V
RDSONL
Low-side switch resistance
TJ = 25°C, VPVIN_VPP=5V, VVCC_5V =
5V
IVPPOCL
Low-side valley current limited
VOUT = 2.5 V, L = 4.7 µH
fsw
VPP switching frequency
tOFF(MIN)
Minimum off time
tOOA
OOA mode operation period
MAX
1.05
mA
2
ms
150
mΩ
120
mΩ
1.6
2.1
580
VVPPSNS =2.5 V
UNIT
A
kHz
195
ns
31
µs
OVP AND UVP (VDDQ, VPP)
VOVP
OVP threshold voltage
OVP detect voltage
120
125
130
%
VUVP1
UVP threshold voltage
UVP detect voltage
55
60
65
%
tOVPDLY
OVP delay
20
µs
tUVPDLY
UVP delay
250
µs
1/2*
VVDDQSNS
V
VTTREF OUTPUT
VVTTREF
VVTTREF
Output voltage
Output voltage tolerance to VDDQ
TJ = 25°C, |IVTTREF| ≤100 µA,
VVDDQSNS = 1.2 V
49.2
50.8
TJ = 25°C, |IVTTREF| ≤10mA,
VVDDQSNS = 1.2 V
49
51
%
IVTTREFOCLSRC
Source current limit
VVDDQSNS = 1.2 V, VVTTREF= 0 V
10
18
mA
IVTTREFOCLSnk
Sink current limit
VVDDQSNS = 1.2 V, VVTTREF= 1.2 V
10
18
mA
VTTREF discharge current
TJ = 25°C, VSLP_S4 = VVTT_CNTL = 0
V, VVTTREF = 0.5 V
0.8
1.3
mA
VVTTREF
V
IVTTREFDIS
VTT OUTPUT
VVTT
Output voltage
VVTTTOL
Output voltage tolerance
|IVTT| ≤10 mA, VVDDQSNS = 1.2 V,
IVTTREF= 0 A
–20
20
TJ = 25°C,|IVTT| ≤1A, VVDDQSNS =
1.2 V, IVTTREF= 0 A
–30
30
mV
IVTTOCLSRC
Source current limit
VVDDQSNS = 1.2 V, VVTT= VVTTSNS=
0.5 V, IVTTREF=0 A
1
1.7
A
IVTTOCLSnk
Sink current limit
VVDDQSNS = 1.2 V, VVTT= VVTTSNS=
0.7 V, IVTTREF=0 A
1
1.7
A
IVTTLK
Leakage current
TJ = 25°C, VSLP_S4 = 5 V, VVTT_CNTL
= 5 V, VVTT =VVTTREF
IVTTSNSBIAS
VTTSNS input bias current
VSLP_S4 = 5 V, VVTT_CNTL = 5 V,
VVTT =VVTTREF
–0.5
0
0.5
IVTTSNSLK
VTTSNS leakage current
VSLP_S4 = 5 V, VVTT_CNTL = 0 V,
VVTT =VVTTREF
–1
0
1
IVTTDLY
VTT output delay relative to
VTT_CNTL
IVTTDIS
VTT discharge current
5
35
TJ = 25°C, VSLP_S4 = VVTT_CNTL = 0
V, VVDDQSNS = 1.2 V, VVTT =0.5V,
IVTTREF =0 A
5.7
µA
us
mA
SLP_S4, VTT_CNTL LOGIC THRESHOLD
VIH
6
SLP_S4/VTT_CNTL high-level
voltage
1.6
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Electrical Characteristics (continued)
TJ=-40oC to 125oC, VPVIN=12V, VPVIN_VPP=5V (unless otherwise noted)
PARAMETER
VIL
SLP_S4/VTT_CNTL low-level
voltage
RTOGND
SLP_S4/VTT_CNTL resistance to
GND
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
V
500
kΩ
THERMAL PROTECTION
TOTP
OTP trip threshold
150
°C
TOTPHSY
OTP hysteresis
20
°C
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6.6 Typical Characteristics
190
5.6
180
Shutdown current (uA)
Supply Current (uA)
5.4
170
160
150
140
5.2
5
4.8
130
120
-50
-20
VSLP_S4 = 5 V
10
40
70
Junction Temperature (qC)
100
4.6
-50
130
VVTT_CNTL = 5 V
VSLP_S4 = 0 V
2.55
1.206
2.53
1.202
1.198
1.194
100
130
D002
VVTT_CNTL = 0 V
2.51
2.49
2.47
1.19
-50
-20
10
40
70
Junction Temperature (qC)
100
2.45
-50
130
-20
D003
Figure 3. VDDQ Output Voltage vs Junction Temperature
1.14
1.05
1.12
1
1.1
1.08
1.06
1.04
1.02
10
40
70
Junction Temperature (qC)
100
130
D004
Figure 4. VPP Output Voltage vs Junction Temperature
SLP_S4 Off Voltage (V)
SLP_S4 On Voltage (V)
10
40
70
Junction Temperature (qC)
Figure 2. VCC_5V Shutdown Current vs Temperature
1.21
VPP Output Voltage (V)
VDDQ Output Voltage (V)
Figure 1. VCC_5V Supply Current vs Junction Temperature
0.95
0.9
0.85
0.8
0.75
1
-50
-20
10
40
70
Junction Temperature (qC)
100
130
0.7
-50
D005
Figure 5. Enable On Voltage (SLP_S4) vs Junction
Temperature
8
-20
D001
-20
10
40
70
Junction Temperature (qC)
100
130
D007
Figure 6. Enable Off Voltage (SLP_S4) vs Junction
Temperature
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1.12
1
1.1
0.95
VTT_CNTL Off Voltage (V)
VTT_CNTL On Voltage (V)
Typical Characteristics (continued)
1.08
1.06
1.04
1.02
1
-50
0.9
0.85
0.8
0.75
-20
10
40
70
Junction Temperature (qC)
100
0.7
-50
130
Figure 7. Enable On Voltage (VTT_CNTL) vs Junction
Temperature
100
130
D008
VDDQ Low-side RDS(on) (m:)
12
30
25
20
15
-20
10
40
70
Junction Temperature (qC)
100
11
10
9
8
7
6
-50
130
-20
D009
10
40
70
Junction Temperature (qC)
100
130
D010
Figure 9. VDDQ High-Side RDS(on) vs Junction Temperature
Figure 10. VDDQ Low-Side RDS(on) vs Junction Temperature
200
150
VPP Low-side RDS(on) (m:)
VDDQ High-side RDS(on) (m:)
VPP High-side RDS(on) (m:)
10
40
70
Junction Temperature (qC)
Figure 8. Enable Off Voltage (VTT_CNTL) vs Junction
Temperature
35
10
-50
-20
D006
180
160
140
120
100
-50
-20
10
40
70
Junction Temperature (qC)
100
130
140
130
120
110
100
90
-50
D011
Figure 11. VPP High-Side RDS(on) vs Junction Temperature
-20
10
40
70
Junction Temperature (qC)
100
130
D012
Figure 12. VPP Low-Side RDS(on) vs Junction Temperature
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Typical Characteristics (continued)
64
63
128
VDDQ UVP Threshold (%)
VDDQ OVP Threshold (%)
130
126
124
122
-20
10
40
70
Junction Temperature (qC)
100
-20
D013
64
128
63
127
126
125
10
40
70
Junction Temperature (qC)
100
130
D014
Figure 14. VDDQ UVP Threshold vs Junction Temperature
129
VPP UVP Threshold (%)
VPP OVP Threshold (%)
60
58
-50
130
Figure 13. VDDQ OVP Threshold vs Junction Temperature
124
62
61
60
59
123
-50
-20
10
40
70
Junction Temperature (qC)
100
58
-50
130
-20
D015
Figure 15. VPP OVP Threshold vs Junction Temperature
10
40
70
Junction Temperature (qC)
100
130
D016
Figure 16. VPP UVP Threshold vs Junction Temperature
14
VPPSNS Discharge Current (mA)
14
VDDQSNS Discharge Current (mA)
61
59
120
-50
13
12
11
10
9
-50
-20
10
40
70
Junction Temperature (qC)
100
130
13
12
11
10
9
-50
D017
Figure 17. VDDQSNS Discharge Current vs Junction
Temperature
10
62
-20
10
40
70
Junction Temperature (qC)
100
130
D018
Figure 18. VPPSNS Discharge Current vs Junction
Temperature
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Typical Characteristics (continued)
1.35
VTTREF Discharge Current (mA)
VTTSNS Discharge Current (mA)
6.5
6
5.5
5
4.5
4
-50
-20
10
40
70
Junction Temperature (oC)
100
1.3
1.25
1.2
1.15
1.1
-50
130
Figure 19. VTTSNS Discharge Current vs Junction
Temperature
100
130
D036
1.65
VPP Valley Current Limit (A)
VDDQ Valley Current Limit (A)
10
40
70
Junction Temperature (oC)
Figure 20. VTTREF Discharge Current vs Junction
Temperature
11
10.6
10.2
9.8
9.4
9
-50
-20
10
40
70
Junction Temperature (qC)
100
1.6
1.55
1.5
1.45
1.4
-50
130
10
40
70
Junction Temperature (qC)
100
130
D021
Figure 22. VPP Valley Current Limit vs Junction
Temperature
1.8
1.2
VPP Soft-start Time (ms)
1.75
1.7
1.65
1.6
1.55
1.5
-50
-20
D020
Figure 21. VDDQ Valley Current Limit vs Junction
Temperature
VDDQ Soft-start Time (ms)
-20
D019
-20
10
40
70
Junction Temperature (qC)
100
130
1.16
1.12
1.08
1.04
1
-50
D022
Figure 23. VDDQ Soft-Start Time vs Junction Temperature
-20
10
40
70
Junction Temperature (qC)
100
130
D023
Figure 24. VPP Soft-Start Time vs Junction Temperature
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800
800
700
700
Switching Frequency (KHz)
Switching Frequency (kHz)
Typical Characteristics (continued)
600
500
400
300
600
500
400
300
200
200
4
6
8
10
12
PVIN (V)
14
16
3
18
D024
800
700
700
Switching Frequency (KHz)
Switching Frequency (KHz)
800
400
300
200
VPVIN=7.4V
VPVIN=12V
VPVIN=19V
100
4 4.25 4.5
PVIN_VPP(V)
4.75
5
5.25
5.5
D025
600
500
400
300
200
100
0
VPVIN_VPP=3.3V
VPVIN_VPP=5V
0
0
1
2
3
4
5
I-Load (A)
6
7
8
0
0.1
D026
Figure 27. VDDQ Switching Frequency vs Load Current
12
3.75
Figure 26. VPP Switching Frequency vs Input Voltage
Figure 25. VDDQ Switching Frequency vs Input Voltage
500
3.5
IOUT = 1 A
IOUT = 8 A
600
3.25
0.2
0.3
0.4 0.5 0.6
I-Load (A)
0.7
0.8
0.9
1
D027
Figure 28. VPP Switching Frequency vs Load Current
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7 Detailed Description
7.1 Overview
The TPS65295 integrates two synchronous step-down buck converters and two LDOs to support complete DDR4
power solution. The VDDQ buck converter has the fixed 1.2-V output and supports continuous 8-A output
current, and it can operate from 4.5-V to 18-V PVIN input voltage. The VPP buck converter has the fixed 2.5-V
output and supports continuous 1-A output current, and can operate from 3-V to 5.5-V PVIN_VPP input voltage.
The VTTREF LDO tracks the ½ VDDQ output and has about 10-mA both sink and source current capability. The
VTT LDO tracks the VTTREF output and has continuous 1-A both sink and source current capability.
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7.2 Functional Block Diagram
PG high threshold
VPP
+
VPPSNS
+
PG low threshold
VPP
UV threshold
VDDQ
PG high threshold
VDDQ
+
UV
+
OV
PGOOD
Logic
PGOOD
+
+
OV threshold
VDDQ
PG low threshold
VDDQ
+
0.8 V
+
Error
Amp
VCC_5V OK
VCC_5V
4.1 V /
3.6 V
+
+PWM
+
VDDQSNS
Control Logic
BST
Discharge
control
PVIN
VDDQ
Internal Ramp
VDDQ
Ripple injection
VDDQ
Softstart
SW
x
x
x
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
Light load PSM
OVP/UVP/OCP
TSD
Soft-Start
Discharge
PGOOD
Disable/Enable
Sequence Control
SW
XCON
PGND
VDDQ One Shot
+
OCL
SLP_S4 Threshold
+
+
ZC
SLP_S4
+
NOCL
THOK
+
150°C /20°C
VCC_5V
UV threshold
VPP
AGND
OV threshold
VPP
+
UV
+
OV
PVIN_VPP
SW_VPP
XCON
0.8 V
+
PGND_VPP
+
Error Amp
+PWM
+
VPPSNS
+
OCL
Discharge
control
VPP
Internal Ramp
+
ZC
VPP
Ripple injection
VPP
Softstart
+
NOCL
SW_VPP
+
VTT_CNTL
VPP One Shot
VTT_CNTL
threshold
VTTREF
Discharge
control
VDDQSNS
VLDOIN
+
+
VTT
+
Discharge
control
VTTSNS
+
14
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the two bucks is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary DCAP3™ mode control. The DCAP3™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS65295 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the converter input voltage, VIN, and is
inversely proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3™ control topology.
Both VDDQ buck and VPP buck include an error amplifier that makes the output voltage very accurate. For any
control topology that is compensated internally, there is a range of the output filter it can support. The output filter
used with the TPS65295 is a low-pass L-C circuit. This L-C filter has a double-pole frequency described in
Equation 1.
1
¦P =
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the internal output set-point resistor divider network and the
internal gain of the TPS65295. The low-frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high-frequency zero is related to the switching frequency. The inductor and capacitor selected for the output filter
must be such that the double pole is placed close enough to the high-frequency zero, so that the phase boost
provided by this high-frequency zero provides adequate phase margin for the stability requirement. The
crossover frequency of the overall system should usually be targeted to be less than one-fifth of the switching
frequency (FSW).
7.3.2 Advanced Eco-mode™ Control
The VDDQ buck and VPP buck are designed with advanced Eco-mode™ control schemes to maintain high light
load efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced
and eventually comes to a point where the rippled valley touches zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero
inductor current is detected. As the load current further decreases, the converter runs into discontinuous
conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode, so that it
takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage.
This makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency
high. The light load current where the transition to Eco-mode™ operation happens ( IOUT(LL) ) can be calculated
from Equation 2.
(V -V
) × VOUT
1
IOUT(LL) =
× IN OUT
2 × LOUT × FSW
VIN
(2)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
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Feature Description (continued)
7.3.3 Soft Start and Prebiased Soft Start
The VDDQ buck has an internal 1.6-ms soft start and VPP buck has an internal 1-ms soft start. Provide the
voltage supply to PVIN, PVIN_VPP and VCC_5V before asserting SLP_S4 to be high, when the SLP_S4 pin
becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage. This scheme ensures that the converters
ramp up smoothly into regulation point.
7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VDDQSNS and VPPSNS pins voltage are
between 90% and 110% of the target output voltage, the PGOOD is deasserted and floats after a 1-ms de-glitch
time. A pullup resistor of 100 kΩ is recommended to pull the voltage up to VCC_5V. The PGOOD pin is pulled
low when:
• the VDDQSNS pin voltage or VPPSNS pin voltage is lower than 85% or greater than 115% of the target
output voltage
• in an OVP, UVP, or thermal shutdown event
• during the soft-start period.
7.3.5 Overcurrent Protection and Undervoltage Protection
Both VDDQ and VPP bucks have the overcurrent protection and undervoltage protection, and the implementation
is same. The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit.
The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage.
This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will be discharged and latched after a wait time of 256 µs. When the overcurrent condition is
removed, the output voltage is latched till the SLP_S4 is toggled or repower the VCC_5V power input.
7.3.6 Overvoltage Protection
Both VDDQ and VPP bucks have the overvoltage protection feature and have the same implementation. When
the output voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high, and
then the output will be discharged and latched after a wait time of 20 µs. When the over current condition is
removed, the output voltage is latched till the SLP_S4 is toggled or repower the VCC_5V power input.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VCC_5V power input. When the voltage is lower than
UVLO threshold voltage, the device is shut off and outputs are discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The VPP buck, VDDQ buck, VTT LDO, and VTTREF LDO block all have the discharge function by using internal
MOSFETs, which are connected to the corresponding output terminals VPPSNS, VDDQSNS, VTT, and
VTTREF. The discharge is slow due to the lower current capability of these MOSFETs.
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Feature Description (continued)
7.3.9 Thermal Shutdown
The TPS65295 monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latch protection. The device
restarts switching when the temperature goes below the thermal shutdown recover threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation for VDDQ Buck and VPP Buck
When the load is light on the VDDQ or VPP output, the buck enters pulse skip mode after the inductor current
crosses zero. This is the Eco-mode™ which improves the efficiency at light load with a lower switching
frequency. Each switching cycle is followed by a period of energy saving sleep time. The sleep time ends when
the VDDQSNS or VPPSNS voltage falls below the Eco-mode™ threshold voltage. As the output current
decreases, the period time between switching pulses increases.
7.4.2
Output State Control
The TPS65295 has two enable input pins, SLP_S4 and VTT_CNTL, to provide simple control scheme of output
state. All of VPP, VDDQ, VTTREF and VTT are turned on at S0 state (SLP_S4=VTT_CNTL=high). In S3 state
(VTT_CNTL=low, SLP_S4=high), VPP, VDDQ, and VTTREF voltages are kept on while VTT is turned off and left
at high impedance state (high-Z). The VTT output floats and does not sink or source current in this state. In
S4/S5 states (SLP_S4=VTT_CNTL =low), all of the three outputs are turned off and discharged to GND. Each
state code represents as follow: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 =
soft OFF (see Table 1).
Table 1. VTT_CNTL and SLP_S4 Control for Output State
STATE
VTT_CNTL
SLP_S4
VPP
VDDQ
VTTREF
VTT
S0
HI
HI
ON
ON
ON
ON
S3
LO
HI
ON
ON
ON
OFF (High-Z)
S5/S4
LO
LO
OFF (discharge)
OFF (discharge)
OFF (discharge)
OFF (discharge)
7.4.3 Output Sequence Control
There are specific sequencing requirements for the DDR4 VDDQ and VPP rails. The TPS65295 follows the
DDR4 power rail sequence requirements as shown in Figure 29 and Figure 30. VPP is greater than VDDQ at all
times during ramp up, operating, and ramp down. The VTT output ramp and stable within 35 µs after VTT_CNTL
asserted.
SLP_S4
SLP_S4
T4
VTT_CNTL
T1
VPP
VTT
T2
VDDQ
T
T3
High-Z
T1: 1 ms
T2: 2.0 ms
T3: 1.6 ms
T4: 30 ms to 60 ms
Figure 29. Power Sequence, VPP and VDDQ vs
SLP_S4
High-Z
T<35 us
Figure 30. Power Sequence, VTT vs VTT_CNTL
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 31 shows a typical application for TPS65295. For VDDQ buck, the PVIN supports 4.5-V
to 18-V input range with 1.2-V VDDQ output, the continuous current capability is 8 A. Usually the PVIN_VPP and
VCC_5V can share one 5-V power input and supports 2.5-V VPP output with 1-A continuous current capability,
of course the PVIN_VPP can be lowered down to a 3.3-V power supply. The VLDOIN power input usually is
connected to VDDQ output, while also it can be connected to external 1.2-V power supply input. The VTTREF
output voltage will follow the ½ VDDQSNS voltage, and VTT output voltage will follow the VTTREF output
voltage, this is required by DDR4 power supply standard.
8.2 Typical Application
Figure 31. Application Schematic
8.2.1 Design Requirements
Table 2 lists the design parameters for this example.
Table 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDDQ OUTPUT
VOUT
Output voltage
1.2
V
IOUT
Output current
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
40
mV(P-P)
FSW
Switching frequency
600
kHz
VOUT
Output voltage
2.5
V
IOUT
Output current
ΔVOUT
Transient response
VIN
Input voltage
8
8-A load step
A
±60
4.5
12
mV
18
V
VPP OUTPUT
18
1
1-A load step
3
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A
±125
5
mV
5.5
V
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Typical Application (continued)
Table 2. Design Parameters (continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT(ripple)
Output voltage ripple
40
mV(P-P)
FSW
Switching frequency
580
kHz
OTHERS
Start VCC_5V input voltage
VCC_5V Input voltage rising
Internal
UVLO
V
Stop VCC_5V input voltage
VCC_5V Input voltage falling
Internal
UVLO
V
VVCC_5V
Light load operating mode
TA
ECO
Ambient temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 3 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 3 and Equation 4. It is
important that the inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
÷
IL(rms)= ç I OUT + × ç
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø
è
ø
IOUT(ripple)
IL(peak) = IOUT +
2
(3)
(4)
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the device
so it is safe to choose an inductor with a saturation current higher than the peak current under current limit
condition.
8.2.2.1.2 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3, the regulator reacts within one
cycle to the change in the duty cycle so the good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in Table 3.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple).
Table 3. Recommended Component Values
VOUT (V)
1.2
2.5
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
600
0.68
88
132
600
0.56
88
132
600
0.47
88
132
580
6.8
20
66
580
4.7
20
66
580
3.3
20
66
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For VTT output, high quality X5R or X7R 10-µF capacitor is recommended and a 0.47 µF is recommended for
VTTREF output.
8.2.2.1.3 Input Capacitor Selection
The TPS65295 requires input decoupling capacitors on both power supply input PVIN and PVIN_VPP, and the
bulk capacitors are needed depending on the application. The minimum input capacitance required is given in
Equation 5.
IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW
(5)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 30 µF on the VDDQ buck input
voltage pin PVIN, and 10 µF on the VPP buck input voltage pin PVIN_VPP. The voltage rating on the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple of the application. The input ripple current is calculated by
Equation 6:
ICIN(rms) = IOUT ×
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
(6)
An additional 0.1-µF capacitor from PVIN to ground and from PVIN_VPP to ground is optional to provide
additional high frequency filtering. One ceramic capacitor of 10 µF is recommended for the decoupling capacitor
on VLDOIN pin for providing stable power on VTT LDO block. A 1-µF ceramic capacitor is needed for the
decoupling capacitor on VCC_5V input.
8.2.2.1.4 Bootstrap Capacitor and Resistor Selection
A 0.1-µF ceramic capacitor serialized with a 5.1-Ω resistor is recommended between the BST and SW pin for
proper operation. TI recommends using a ceramic capacitor.
8.2.3 Application Curves
95
100
90
95
85
90
Efficiency (%)
Efficiency (%)
Figure 32 through Figure 60 apply to the circuit of Figure 31. VIN = 12 V. TA = 25°C unless otherwise specified.
80
75
70
65
80
75
70
VPVIN=7.4V,VOUT=1.2V
VPVIN=12V, VOUT=1.2V
VPVIN=19V, VOUT=1.2V
60
55
0.001
0.01
0.1
I-Load (A)
1
65
10
VPVIN_VPP=3.3V,VOUT=2.5V
VPVIN_VPP=5V , VOUT=2.5V
60
0.001
0.01
0.1
I-Load (A)
D029
Figure 32. VDDQ Efficiency Curve, VOUT = 1.2 V
20
85
1
D028
Figure 33. VPP Efficiency Curve, VOUT = 2.5 V
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1.25
2.55
1.24
2.54
1.23
2.53
1.22
2.52
Output Voltage (V)
Output Voltage (V)
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1.21
1.2
1.19
1.18
1.17
2.5
2.49
2.48
2.47
VPVIN=7.4V
VPVIN=12V
VPVIN=19V
1.16
2.51
VPVIN_VPP=3.3V
VPVIN_VPP=5V
2.46
1.15
2.45
0
1
2
3
4
5
I-Load (A)
6
7
8
0
0.65
0.65
0.64
0.64
0.63
0.63
0.62
0.62
0.61
0.6
0.59
0.58
0.4
0.6
0.8
0.55
-10
1
-8
-6
-4
-2
0
2
I-Load (mA)
D034
Figure 36. VTT Load Regulation, VOUT = 0.6 V
0.9
1
D031
4
6
8
10
D035
Figure 37. VTTREF Load Regulation, VOUT = 0.6 V
1.3
2.55
1.28
2.54
1.26
2.53
1.24
2.52
Output Voltage (V)
Output Voltage (V)
0.8
0.58
0.56
-0.2
0
0.2
I-Load (A)
0.7
0.59
0.56
-0.4
0.4 0.5 0.6
I-Load (A)
0.6
0.57
-0.6
0.3
0.61
0.57
-0.8
0.2
Figure 35. VPP Load Regulation, VOUT = 2.5 V
Output Votlage (V)
Output Voltage (V)
Figure 34. VDDQ Load Regulation, VOUT = 1.2 V
0.55
-1
0.1
D030
1.22
1.2
1.18
1.16
2.51
2.5
2.49
2.48
2.47
1.14
1.1
4
6
8
10
12
PVIN (V)
14
16
IOUT=0A
IOUT=1A
2.46
IOUT=0A
IOUT=8A
1.12
18
2.45
3.25
3.5
3.75
4
4.25 4.5 4.75
PVIN_VPP (V)
5
5.25
5.5
D033
D032
Figure 38. VDDQ Line Regulation,VOUT = 1.2 V
Figure 39. VPP Line Regulation, VOUT = 2.5 V
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VDDQ=50mV/div
VPP=50mV/div
Io=500mA/div
Io=500mA/div
40ms/div
10ms/div
Figure 40. VDDQ Output Voltage Ripple, IOUT = 0 A
Figure 41. VPP Output Voltage Ripple, IOUT = 0 A
VDDQ=10mV/div
VPP=10mV/div
Io=500mA/div
Io=5A/div
1us/div
1us/div
Figure 42. VDDQ Output Voltage Ripple, IOUT = 8 A
Figure 43. VPP Output Voltage Ripple, IOUT = 1 A
SLP_S4=2V/div
SLP_S4=2V/div
VPP=2V/div
VPP=2V/div
VDDQ=1V/div
VDDQ=1V/div
PGOOD=5V/div
PGOOD=5V/div
2ms/div
2ms/div
Figure 44. Start-Up Through SLP_S4, IVPPOUT = 0 A,
IVDDQOUT = 0 A
22
Figure 45. Start-Up Through SLP_S4, IVPPOUT = 1 A,
IVDDQOUT = 8 A
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SLP_S4=2V/div
SLP_S4=2V/div
VPP=2V/div
VPP=2V/div
VDDQ=1V/div
VDDQ=1V/div
PGOOD=5V/div
PGOOD=5V/div
20ms/div
20ms/div
Figure 46. Shutdown Through SLP_S4, IVPPOUT = 0 A,
IVDDQOUT = 0 A
IVDDQOUT = 0 A
2ms/div
IVTT = 0 A
Figure 47. Shutdown Through SLP_S4, IVPPOUT = 1 A,
IVDDQOUT = 8 A
SLP_S4=2V/div
SLP_S4=2V/div
VTT_CTRL=2V/div
VTT_CTRL=2V/div
VDDQ=1V/div
VDDQ=1V/div
VTT=500mV/div
VTT=500mV/div
IVTTREF = 0 A
Figure 48. VTT Start-Up Through VTT_CNTL
IVDDQOUT = 8 A
SLP_S4=2V/div
VTT_CTRL=2V/div
VTT_CTRL=2V/div
VDDQ=1V/div
VDDQ=1V/div
VTT=500mV/div
VTT=500mV/div
10ms/div
IVTT = 0 A
IVTTREF = 0 A
Figure 50. VTT Shutdown Through VTT_CNTL
IVTTREF = 10m A
Figure 49. VTT Start-Up Through VTT_CNTL
SLP_S4=2V/div
IVDDQOUT = 0 A
2ms/div
IVTT = 1 A
IVDDQOUT = 8 A
4ms/div
IVTT = 1 A
IVTTREF = 10 mA
Figure 51. VTT Shutdown Through VTT_CNTL
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IVDDQOUT = 0 A
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4ms/div
IVTT = 0 A
SLP_S4=2V/div
SLP_S4=2V/div
VDDQ=1V/div
VDDQ=1V/div
VTT=500mV/div
VTT=500mV/div
VTT_REF=500mV/div
VTT_REF=500mV/div
IVTTREF = 0 A
4ms/div
IVTT = 1 A
IVDDQOUT = 8 A
Figure 52. VTT Start-Up Through SLP_S4
IVTTREF = 10 mA
Figure 53. VTT Start-Up Through SLP_S4
SLP_S4=2V/div
SLP_S4=2V/div
VDDQ=1V/div
VDDQ=1V/div
VTT=500mV/div
VTT=500mV/div
VTT_REF=500mV/div
VTT_REF=500mV/div
IVDDQOUT = 0 A
10ms/div
IVTT = 0 A
IVTTREF = 0 A
Figure 54. VTT Shutdown Through SLP_S4
VPP=100mV/div
IVTTREF = 10 mA
Figure 55. VTT Shutdown Through SLP_S4
VDDQ=50mV/div
Io=5A/div
Io=1A/div
400us/div
400us/div
Slew Rate=2.5A/us
Slew Rate=2.5A/us
Figure 56. VPP Transient Response, 0 A to 1 A
24
4ms/div
IVTT = 1 A
IVDDQOUT = 8 A
Figure 57. VDDQ Transient Response, 1.6 A to 8 A
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VDDQ=50mV/div
SW=5V/div
VPP=2V/div
Io=5A/div
IL=1A/div
400us/div
100us/div
Slew Rate=2.5A/us
Figure 58. VDDQ Transient Response, 0.1 A to 6.4 A
Figure 59. VPP Normal Operation to Output Hard Short
SW=5V/div
IL=5A/div
VDDQ=500mV/div
100us/div
Figure 60. VDDQ Normal Operation to Output Hard Short
9 Power Supply Recommendations
TPS65295 is designed for DDR4 complete power solution. PVIN is the power input for VDDQ buck, PVIN_VPP is
the power input for VPP buck, VLDOIN input is for VTT LDO power supply, VCC_5V is power supply for internal
control logic. Below lists the power on sequence scenarios.
• SLP_S4 is high before PVIN or PVIN_VPP has the power input, VCC_5V power supply must be provided
after or same time with PVIN or PVIN_VPP, otherwise the output will be latched, this latch can be recovered
by toggling the SLP_S4 pin or re-power the VCC_5V
• SLP_S4 is low before PVIN and PVIN_VPP has the power input, then there is no power supply input
sequence requirement for VCC_5V, PVIN and PVIN_VPP.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3inch, four-layer PCB with 2-oz. copper used as example.
Place the decoupling capacitors right across PVIN, PVIN_VPP, and VLDOIN as close as possible.
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible. Reserve some space between
VDDQ choke and VPP choke, just minimize radiation crosstalk.
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
VPPSNS/VDDQSNS/VTTSNS could be 10 mil and must be routed away from the switching node, BST node
or other high efficiency signal.
PVIN and PVIN_VPP trace must be wide to reduce the trace impedance and provide enough current
capability.
Output capacitors for VTT and VTTREF should be put as close as output pin.
10.2 Layout Example
Figure 61 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 31.
T
V
V
PVIN
E
T
R
T
T
F
VDDQ
SW
_V
W
S
PVIN_VPP
P
P
PGND
PGND_VPP
VPP
Figure 61. Top-Side Layout
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP3, Eco-mode, HotRod, DCAP3, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
TPS65295RJER
PRE_PRO
D
VQFN-HR
RJE
18
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
65295
TPS65295RJET
PRE_PRO
D
VQFN-HR
RJE
18
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1
YEAR
-40 to 125
65295
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
28
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12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS65295RJER
VQFN-HR
RJE
18
3000
330
12.4
3.3
3.3
1.1
8
12
Q2
TPS65295RJET
VQFN-HR
RJE
18
250
180
12.4
3.3
3.3
1.1
8
12
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
30
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65295RJER
VQFN-HR
RJE
18
3000
367
367
35
TPS65295RJET
VQFN-HR
RJE
18
250
210
185
35
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PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0018B
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 0.45
4X 0.5
0.3
4X 0.48
0.28
4X 0.25
0.15
9
7
6
0.6
0.4
(0.1) TYP
10
6X 0.5
2.09
3X 1.99
2X
2.5
2X
1.5
PKG
15
4X 0.3
0.2
1
16
18
2X 0.25
0.15
2X 0.65
PKG
8X 0.3
0.2
10X 0.5
0.3
C A B
C
4X 0.33
0.23
0.1
0.05
2X 2.48
0.1
0.05
C A B
C
4223865 / B 02/2018
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RJE0018B
PLASTIC QUAD FLATPACK- NO LEAD
4X (1.24)
2X (0.65)
6X (0.2)
8X (0.6)
18
4X (0.58)
16
15
1
8X (0.25)
4X
(1.25)
(2.243)
6X (0.5)
PKG
(2.83)
(0.58)
(R0.05) TYP
2X
(2.238)
4X (0.25)
10
6
7
4X (0.28)
PKG
(0.7)
9
4X (0.6)
(2.8)
2X (0.45)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223865 / B 02/2018
NOTES: (continued)
3.
4.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0018B
PLASTIC QUAD FLATPACK- NO LEAD
4X (1.23)
2X (0.65)
9X (0.2)
8X (0.6)
4X (0.58)
18
16
4X (0.225)
15
1
8X (0.25)
4X
(1.24)
3X (1.19)
6X (0.5)
PKG
2X (0.028)
(1.35)
2X (2.83)
(1.022)
(0.034)
(R0.05) TYP
3X
EXPOSED METAL
4X
(1.019) 6
4X (0.25)
10
7
PKG
9
(0.7)
4X (0.6)
(2.8)
2X (0.45)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 6, 10 &15: 93% & PADS 7-9,17:89%
SCALE: 20X
4223865 / B 02/2018
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65295RJER
ACTIVE
VQFN-HR
RJE
18
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
65295
TPS65295RJET
ACTIVE
VQFN-HR
RJE
18
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
65295
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2019
Addendum-Page 2
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RJE0018A
PLASTIC QUAD FLATPACK- NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
4X 0.45
8X 0.5
0.3
6X 0.5
9
7
4X 0.25
0.15
0.6
0.4
(0.1) TYP
6
10
3X 1.85
1.75
2X 2X
2.5 1.5
PKG
15
4X 0.3
0.2
1
18
PKG
16
8X 0.3
0.2
10X 0.5
0.3
2X 0.25
0.15
0.1
0.05
C A B
C
4X 0.33
0.23
0.1
0.05
2X 2.48
C A B
C
4223562 / B 04/2017
NOTES:
1.
2.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
RJE0018A
PLASTIC QUAD FLATPACK- NO LEAD
4X (1.24)
4X (0.45)
6X (0.2)
8X (0.6)
18
16
15
8X (0.25)
1
4X
(1.25)
6X (0.5)
3X
(2)
PKG
(2.83)
(R0.05) TYP
4X (0.25)
10
6
7
4X (0.28)
PKG
9
(0.7)
8X (0.6)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
(PINS 7-9, 16-18)
NON- SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223562 / B 04/2017
NOTES: (continued)
3.
4.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RJE0018A
PLASTIC QUAD FLATPACK- NO LEAD
4X (1.23)
4X (0.45)
9X (0.2)
8X (0.6)
18
16
4X (0.225)
15
1
8X (0.25)
3X (1.25)
4X
(1.24)
6X (0.5)
6X
PKG (0.9)
(2.83)
3X (0.15)
(1.35)
3X
EXPOSED METAL
(R0.05) TYP
6
4X (0.25)
10
7
PKG
(0.7)
9
8X (0.6)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 6, 10 &15: 93% & PADS 7-9,17:89%
SCALE: 20X
4223562 / B 04/2017
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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