Texas Instruments | UC1843A-SP QML class V, radiation hardened current-mode PWM controller (Rev. A) | Datasheet | Texas Instruments UC1843A-SP QML class V, radiation hardened current-mode PWM controller (Rev. A) Datasheet

Texas Instruments UC1843A-SP QML class V, radiation hardened current-mode PWM controller (Rev. A) Datasheet
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UC1843A-SP
SLUSCI6A – DECEMBER 2016 – REVISED FEBRUARY 2019
UC1843A-SP QML class V, radiation hardened current-mode PWM controller
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
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QML Class V (QMLV) Qualified, SMD 5962-86704
5962P8670409Vxx:
– Radiation Hardness Assurance (RHA) up to
30-krad(Si) Total Ionizing Dose (TID)
– Passes Functional and Specified PostRadiation Parametric Limits at 45 krad at LDR
(10 mrad(Si)/s) per 1.5× Over Test as Defined
in MIL-STD-883 Test Method 1019.9
Paragraph 3.13.3.b
– Exhibits Low-Dose Rate Sensitivity but
Remains Within the Pre-Radiation Electrical
Limits at 30-krad Total Dose Level, as Allowed
by MIL-STD-883, TM1019
Optimized for Offline and DC-to-DC Converters
Low Start-Up Current (< 0.5 mA)
Trimmed Oscillator Discharge Current
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Undervoltage Lockout (UVLO) With Hysteresis
Double-Pulse Suppression
High-Current Totem-Pole Output
Internally-Trimmed Bandgap Reference
500-kHz Operation
Low RO Error Amplifier
•
DC-DC Converters
Supports Various Topologies:
– Flyback, Forward, Buck, Boost
– Push-Pull, Half-Bridge, Full-Bridge With
External Interface Circuit
Available in Military Temperature Range (–55°C to
125°C)
3 Description
The UC1843A-SP control IC is a radiation hardened
pin-for-pin compatible version of the UC184x family.
Providing the necessary characteristics to control
current-mode switched-mode power supplies, this
device has improved features. Start-up current is
specified to be less than 0.5 mA and oscillator
discharge is trimmed to 8.3 mA. During UVLO, the
output stage can sink at least 10 mA at less than 1.2
V for VCC over 5 V.
The Device Comparison Table shows the difference
between members of this family. Reference the
individual product data sheets for ordering the
radiation-improved version if available.
Device Information(1)
PART NUMBER
UC1843A-SP
PACKAGE
BODY SIZE (NOM)
CDIP (8)
6.67 mm × 9.60 mm
LCCC (20)
8.89 mm × 8.89 mm
CFP (10)
6.48 mm × 7.02 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
7
34 V
UVLO
S/R
Gnd
5
5-V
REF
8
VREF
5.0 V
50 mA
2.5 V
Internal
Bias
VREF
Good
Logic
RT/CT
4
2
Comp
1
C/S
3
VC
6
Output
5
Pwr
Ground
Osc
Error
Amplifier
VFB
7
S
2R
R
R
1V
PWM
Latch
Current
Sense
Comparator
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1843A-SP
SLUSCI6A – DECEMBER 2016 – REVISED FEBRUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Original (December 2016) to Revision A
Page
•
Changed the Pin Configuration images ................................................................................................................................. 3
•
Changed CT (pF) To: CT (µF) in Equation 1........................................................................................................................ 15
2
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5 Device Comparison Table
PART NO.
UVLO ON
UVLO OFF
MAXIMUM DUTY CYCLE
UC1842A
16 V
10 V
<100%
UC1843A
8.5 V
7.9 V
<100%
UC1844A
16 V
10 V
<50%
6 Pin Configuration and Functions
JG Package
8-Pin CDIP
Top View
NC
NC
4
18
VCC
VFB
5
17
VC
NC
6
16
NC
ISENSE(C/S)
7
15
Output
NC
8
14
NC
No t to scale
Co mp
1
10
VREF
VFB
2
9
VCC
ISENSE(C/S)
3
8
Output
RT /CT
4
7
Gnd
5
6
NC
NC
NC
9
HKU Package
10-Pin CFP
Top View
19
Gnd
13
5
Gnd
4
VREF
RT /CT
20
Output
12
6
Pwr Gnd
3
NC
ISENSE(C/S)
1
VCC
11
7
NC
2
Co mp
VFB
2
VREF
10
8
RT /CT
1
NC
Co mp
3
FK Package
20-Pin LCCC
Top View
No t to scale
No t to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CDIP
LCCC
CFP
Comp
1
2
1
I
Error amplifier output.
VFB
2
5
2
I
Voltage feedback input to error amplifier.
ISENSE(C/S)
3
7
3
I
Current sense comparator input pin.
RT/CT
4
10
4
I
RC time constant input to oscillator.
NC
—
1, 3, 4, 6, 8, 9,
11, 14, 16, 19
5, 6
—
No connect.
Pwr Gnd
—
12
—
—
Output section ground.
Gnd
5
13
7
—
Ground.
Output
6
15
8
O
Regulated output.
VC
—
17
—
—
Output section supply voltage.
VCC
7
18
9
—
Unregulated supply voltage.
VREF
8
20
10
O
5-V internally generated reference.
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
30
V
6.3
V
Output current
±1
A
Error amplifier output sink current
10
mA
Output energy (capacitive load)
5
μJ
PD
Power dissipation (TA = 25°C)
1
W
Tstg
Storage temperature
150
°C
VCC
Supply voltage, low-impedance source
VI
Input voltage (VFB, ISENSE)
–0.3
Supply current
IO
(1)
(2)
Self limiting
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive in, negative out of the specified terminal.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±4000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (TA = TJ = –55°C to 125°C), unless otherwise noted
VCC
MIN
MAX
12
25
V
Sink/source output current (continuous or time average)
0
200
mA
Reference load current
0
20
mA
Supply voltage
UNIT
7.4 Thermal Information
UC1843A-SP
THERMAL METRIC
(1)
JG (CDIP)
FK (LCCC)
HKU (CFP)
8 PINS
20 PINS
10 PINS
UNIT
103
—
51.9
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(bot)
Junction-to-case (bottom) thermal resistance
9.6
9.0
6.6
°C/W
RθJB
Junction-to-board thermal resistance
69.2
—
31.5
°C/W
ψJT
Junction-to-top characterization parameter
13.9
—
5.42
°C/W
ψJB
Junction-to-board characterization parameter
73
—
31
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
VCC = 15 V (1), RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.95
UNIT
REFERENCE
Output voltage
TJ = 25°C, IO = 1 mA
5
5.06
Line regulation
VIN = 12 to 25 V
6
20
mV
IO = 1 to 20 mA
6
25
mV
0.2
0.4
mV/°C
Load regulation
Temperature stability
(2) (3)
Total output variation (2)
Over line, load, and temperature
Output noise voltage
10 Hz ≤ ƒ ≤ 10 kHz, TJ = 25°C
Long-term stability
1000 hours, TA = 125°C (2)
Short-circuit output current
4.9
5.1
50
–30
V
V
μV
5
25
mV
–100
–180
mA
52
57
kHz
0.2%
1%
OSCILLATOR
Initial accuracy
TJ = 25°C (4)
Voltage stability
VCC = 12 to 25 V
Temperature stability
TJ = –55°C to 125°C (2)
5%
Amplitude peak-to-peak
V pin 4 (2)
1.7
Discharge current
V pin 4 = 2 V (5)
47
TJ = 25°C
7.8
TJ = Full range
7.5
8.3
V
8.8
mA
8.8
mA
ERROR AMPLIFIER
Input voltage
VComp = 2.5 V
2.45
Input bias current
Open-loop voltage gain
VO = 2 to 4 V
(2)
Unity-gain bandwidth
TJ = 25°C
PSRR
VCC = 12 to 25 V
Output sink current
VFB = 2.7 V, VComp = 1.1 V
Output source current
VFB = 2.3 V, VComp = 5 V
High-level output voltage
VFB = 2.3 V, RL = 15 kΩ to ground
Low-level output voltage
VFB = 2.7 V, RL = 15 kΩ to VREF
65
2.50
2.55
V
–0.3
–1
μA
90
dB
0.7
1
MHz
60
70
dB
2
6
mA
–0.5
–0.8
mA
5
6
V
0.7
1.1
V
2.85
3
3.15
V/V
0.9
1
1.1
CURRENT SENSE
Gain (6) (7)
Maximum input signal
VComp = 5 V (6)
PSRR
VCC = 12 to 25 V (6)
70
–2
–10
μA
VISENSE = 0 to 2 V (2)
150
300
ns
Input bias current
Delay to output
(1)
(2)
(3)
(4)
(5)
(6)
(7)
V
dB
Adjust VCC above the start threshold before setting at 15 V.
Parameters ensured by design and/or characterization, if not production tested.
Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
Temperature Stability = VREF (max) – VREF (min) / TJ (max) – TJ (min). VREF (max) and VREF (min) are the maximum and minimum
reference voltage measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the
extremes in temperature.
Output frequency equals oscillator frequency for the UC1842A-SP and UC1843A-SP.
This parameter is measured with RT = 10 kΩ to VREF. This contributes approximately 300 μA of current to the measurement. The total
current flowing into the RT or CT pin will be approximately 300 μA higher than the measured value.
Parameter measured at trip point of latch with VFB = 0 V.
Gain defined as: G = ΔVComp / ΔVISENSE; VISENSE = 0 to 0.8 V.
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Electrical Characteristics (continued)
VCC = 15 V(1), RT = 10 kΩ, CT = 3.3 nF, TA = TJ = –55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ISINK = 20 mA
0.1
0.4
ISINK = 200 mA
1.5
2.2
UNIT
OUTPUT
Output low-level voltage
Output high-level voltage
ISOURCE = –20 mA
13
13.5
ISOURCE = –200 mA
12
13.5
V
V
Rise time
CL = 1 nF, TJ = 25°C (2)
50
150
ns
Fall time
CL = 1 nF, TJ = 25°C (2)
50
150
ns
UVLO saturation
VCC = 5 V, ISINK = 10 mA
0.7
1.2
V
7.8
8.4
9
V
7
7.6
8.2
V
94%
96%
100%
UNDERVOLTAGE LOCKOUT
Start threshold
Minimum operation voltage after turnon
PWM
Maximum duty cycle
Minimum duty cycle
0%
TOTAL STANDBY CURRENT
Start-up current
Operating supply current
VFB = VISENSE = 0 V
VCC Zener voltage
ICC = 25 mA
30
0.3
0.5
mA
11
17
mA
34
V
Saturation Voltage (V)
7.6 Typical Characteristics
I
.01
.02 .03 .04 .05 .07 .1
.2
.3 .4 .5
.7 1.0
Output Current, Source or Sink (A)
Figure 1. Output Saturation Characteristics
6
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8 Detailed Description
8.1 Overview
The UC1843A-SP control IC is a pin-for-pin compatible improved version of the UC184x family. Providing the
necessary characteristics to control current-mode switched-mode power supplies, this device has improved
features. Start-up current is specified to be less than 0.5 mA and oscillator discharge is trimmed to 8.3 mA.
During UVLO, the output stage can sink at least 10 mA at less than 1.2 V for VCC over 5 V.
8.2 Functional Block Diagram
VCC
7
34 V
UVLO
S/R
Gnd
5
5-V
REF
8
VREF
5.0 V
50 mA
2.5 V
Internal
Bias
VREF
Good
Logic
RT/CT
4
2
Comp
1
C/S
3
VC
6
Output
5
Pwr
Ground
Osc
Error
Amplifier
VFB
7
S
2R
R
R
1V
PWM
Latch
Current
Sense
Comparator
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
UC1843A-SP is a current mode controller, used to support various topologies such as forward, flyback, buck,
boost and using an external interface circuit will also support half-bridge, full-bridge, and push-pull configurations.
Figure 2 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal
initiates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor
current reaches a threshold established by the error signal. In this way, the error signal actually controls peak
inductor current. This contrasts with conventional schemes in which the error signal directly controls pulse width
without regard to inductor current.
Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward
characteristic is achieved; that is, the control circuit instantaneously corrects for input voltage variations without
using up any of the error amplifier’s dynamic range. Therefore, line regulation is excellent and the error amplifier
can be dedicated to correcting for load variations exclusively.
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Feature Description (continued)
Figure 2. Two-Loop Current-Mode Control System
For converters in which inductor current is continuous, controlling peak current is nearly equivalent to controlling
average current. Therefore, when such converters employ current-mode control, the inductor can be treated as
an error-voltage-controlled-current-source for the purposes of small-signal analysis (see Figure 3). The two-pole
control-to-output frequency response of these converters is reduced to a single-pole (filter capacitor in parallel
with load) response. One result is that the error amplifier compensation can be designed to yield a stable closedloop converter response with greater gain bandwidth than would be possible with pulse-width control, giving the
supply improved small-signal dynamic response to changing loads. A second result is that the error amplifier
compensation circuit becomes simpler, as shown in Figure 4.
Capacitor Ci and resistor Ri, in Figure 4(A), add a low-frequency zero, which cancels one of the two control-tooutput poles of non-current-mode converters. For large signal load changes, in which converter response is
limited by inductor slew rate, the error amplifier saturates while the inductor is catching up with the load. During
this time, Ci charges to an abnormal level. When the inductor current reaches its required level, the voltage on Ci
causes a corresponding error in supply output voltage. The recovery time is RizCi, which may be long. However,
the compensation network of Figure 4(B) can be used where current-mode control has eliminated the inductor
pole. Large-signal dynamic response is then greatly improved due to the absence of Ci.
Current limiting is greatly simplified with current-mode control. Pulse-by-pulse limiting is, of course, inherent in
the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the
error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while
ensuring reliable supply operation.
Finally, current-mode controlled power stages can be operated in parallel with equal current sharing. This opens
the possibility of a modular approach to power supply design.
8
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Feature Description (continued)
Figure 3. Inductor Looks Like a Current Source to Small Signals
A. Direct duty cycle control
B. Current mode control
Figure 4. Required Error Amplifier Compensation for Continuous Inductor Current Designs
8.3.1 UVLO
The UVLO circuit ensures that VCC is adequate to make the UC1843A-SP fully operational before enabling the
output stage. Figure 5 shows that the UVLO turnon and turnoff thresholds are fixed internally at 16 V and 10 V,
respectively. The 6-V hysteresis prevents VCC oscillations during power sequencing.
Figure 6 shows supply current requirements. Start-up current is < 1 mA for efficient bootstrapping from the
rectified input of an off-line converter, as shown in Figure 7. During normal circuit operation, VCC is developed
from auxiliary winding, WAux, with D1 and CIN. However, at start-up, CIN must be charged to 16 V through RIN.
With a start-up current of 1 mA, RIN can be as large as 100 kΩ and still charge CIN when VAc = 90-V RMS (low
line). Power dissipation in RIN would then be less than 350 mW even under high line (VAc = 130-V RMS)
conditions.
During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as
normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off.
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Feature Description (continued)
ON/OFF command
to rest of IC
VCC
UC1843A-SP
VON
VOFF
8.4 V
7.6 V
Copyright © 2016, Texas Instruments Incorporated
Figure 5. UVLO Turnon TurnOff Threshold
ICC
<17 mA
<1 mA
VOFF
VCC
VON
During UVLO, the output driver is biased to sink minor amounts of current.
Figure 6. Supply Current Requirements
UC1843A-SP
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Figure 7. Providing Power to the UC1843A-SP
10
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Feature Description (continued)
8.3.2 Reference
As highlighted in the Functional Block Diagram, UC1843A-SP incorporates a 5-V internal reference regulator with
±2% set point variation over temperature.
8.3.3 Totem-Pole Output
The UC1843A-SP PWM has a single totem-pole output which can be operated to ±1-A peak for driving MOSFET
gates, and a +200 mA average current for bipolar power U-100A transistors. Cross conduction between the
output transistors is minimal, the average added power with VIN = 30 V is only 80 mW at 200 kHz.
Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and
the gate of the MOSFET. The value is determined by dividing the totem-pole collector voltage VC by the peak
current rating of the IC’s totem-pole. Without this resistor, the peak current is limited only by the dV/dT rate of the
totem-pole switching and the FET gate capacitance.
The use of a Schottky diode from the PWM output to ground prevents the output voltage from going excessively
below ground, causing instabilities within the IC. To be effective, the diode selected should have a forward drop
of less than 0.3 V at 200 mA. Most 1- to 3-A Schottky diodes exhibit these traits above room temperature.
Placing the diode as physically close to the PWM as possible enhances circuit performance. Implementation of
the complete drive scheme is shown in Figure 8 through Figure 10. Transformer-driven circuits also require the
use of the Schottky diodes to prevent a similar set of circumstances from occurring on the PWM output. The
ringing below ground is greatly enhanced by the transformer leakage inductance and parasitic capacitance, in
addition to the magnetizing inductance and FET gate capacitance. Circuit implementation is similar to the
previous example.
Figure 8 through Figure 10 show suggested circuits for driving MOSFETs and bipolar transistors with the
UC1843A-SP output. The simple circuit of Figure 8 can be used when the control IC is not electrically isolated
from the MOSFET turnon and turnoff to ±1 A. It also provides damping for a parasitic tank circuit formed by the
FET input capacitance and series wiring inductance. Schottky diode, D1, prevents the output of the IC from going
far below ground during turnoff.
Figure 9 shows an isolated MOSFET drive circuit which is appropriate when the drive signal must be level shifted
or transmitted across an isolation boundary. Bipolar transistors can be driven efficiently with the circuit of
Figure 10. Resistors R1 and R2 fix the on-state base current while capacitor Cl provides a negative base current
pulse to remove stored charge at turnoff.
Because the UC1843A-SP series has only a single output, an interface circuit is needed to control push-pull,
half-bridge, or full-bridge topologies. The UC1706 dual output driver with internal toggle flip-flop performs this
function. Typical Application shows a typical application for these two ICs. Increased drive capability for driving
numerous FETs in parallel, or other loads can be accomplished using one of the UC1705/6/7 driver ICs.
UC1843A-SP
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Figure 8. Direct MOSFET Drive
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Feature Description (continued)
UC1843A-SP
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Figure 9. Isolated MOSFET Drive
UC1843A-SP
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Bipolar Drive With Negative turnoff Bias
8.4 Device Functional Modes
The UC1843A-SP uses fixed frequency, peak current mode control. An internal oscillator initiates the turn on of
the driver to high-side power switch. The external power switch current is sensed through an external resistor
and is compared via internal comparator. The voltage generated at the COMP pin is stepped down via internal
resistors (as shown in the functional block diagram). When the sensed current reaches the stepped down COMP
voltage, the high-side power switch is turned off.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
UC1843A-SP can be used as a controller to design various topologies such as buck, boost, flyback, and forward.
Using an external interphase circuit can also support push-pull, half-bridge and full-bridge topologies.
9.2 Typical Application
UC1843A-SP
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Typical Application Schematic
9.2.1 Design Requirements
See Table 1 for parameter values.
Table 1. Design Parameters (1)
DESIGN PARAMETER
VALUE
Input voltage
95 VAC to 130 VAC
Line isolation
3750 V
Switching frequency
40 kHz
Efficiency (full load)
(1)
70%
Output voltage (A)
+5 V, ±5%; 1-A to 4-A load; Ripple voltage: 50-mV P-P max
Output voltage (B)
+12 V, ±3%; 0.1-A to 0.3-A load; Ripple voltage: 100-mV P-P max
Output voltage (C)
–12 V, ±3%; 0.1-A to 0.3-A load; Ripple voltage: 100-mV P-P max
See Figure 11 for reference.
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9.2.2 Detailed Design Procedure
See Table 2 for component values.
Table 2. Components (1)
(1)
14
COMPONENT
VALUE
R1
5 Ω, 1 W
R2
56 kΩ, 2 W
R3
20 kΩ
R4
4.7 kΩ
R5
150 kΩ
R6
10 kΩ
R7
22 Ω
R8
1 kΩ
R9
68 Ω
R10
0.55 Ω, 1 W
R11
2.7 kΩ, 2 W
R12
4.7 kΩ, 2 W
R13
20 kΩ
C1
250 µF, 250 V
C2
100 µF, 25 V
C3
22 µF
C4
47 µF, 25 V
C5
0.1 µF
C6
0.0022 µF
C7
470 pF
C8
680 pF, 600 V
C9
3300 pF, 600 V
C10
4700 µF, 10 V
C11
4700 µF, 10 V
C12
2200 µF, 10 V
C13
2200 µF, 10 V
C14
100 pF
D2
1N3612
D3
1N3612
D4
1N3613
D5
1N3613
D6
USD945
D7
UFS1002
D8
UES1002
Q1
UFN833
See Figure 11 for reference.
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Peak Current (IS) is determined by the formula:
ISMAX '
1.0 V
RS
A small RC filter may be required to suppress switch transients.
Figure 12. Current-Sense Circuit
UC1843A-SP
Copyright © 2016, Texas Instruments Incorporated
NOTE: A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50%.
Capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.
Figure 13. Slope Compensation
9.2.2.1 Oscillator
The UC1843A-SP oscillator is programmed as shown in Figure 15. Timing capacitor CT is charged from VREF (5
V) through the timing resistor RT, and discharged by an internal current source. The first step in selecting the
oscillator components is to determine the required circuit dead time. Once obtained, Figure 16 is used to pinpoint
the nearest standard value of CT for a given dead time. Next, the appropriate RT value is interpolated using the
parameters for CT and oscillator frequency. Figure 17 shows the RT/CT combinations versus oscillator frequency.
The timing resistor can be calculated from the following formula.
ƒosc (kHz) =
1.72
RT (kW ) ´ CT (mF)
(1)
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5V
Figure 14. E/A Compensation Circuit for Continuous Boost and Flyback Topologies
The UC1843A-SP has an internal divide-by-two flip-flop driven by the oscillator for a 50% maximum duty cycle.
Therefore, their oscillators must be set to run at twice the desired power supply switching frequency.
Figure 15. Oscillator Programming
16
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30
100
10
RT (kΩ)
td (µs)
30
3
10
1
0.3
2.2
1
4.7
47
10
22
CT (nF)
100
Figure 16. Dead Time vs CT (RT > 5 kΩ)
3
100
1k
10k
100k
Frequency (Hz)
1M
Figure 17. Timing Resistance vs Frequency
9.2.2.2 Current Sensing and Limiting
The UC1843A-SP current sense input is configured as shown in Figure 18. Current-to-voltage conversion is done
externally with ground-referenced resistor RS. Under normal operation, the peak voltage across RS is controlled
by the E/A according to the following relation:
IP
9C ±
9
3 RS
where
•
VC = Control voltage = E/A output voltage
(2)
RS can be connected to the power circuit directly or through a current transformer, as Figure 18 shows. While a
direct connection is simpler, a transformer can reduce power dissipation in RS, reduce errors caused by the base
current, and provide level shifting to eliminate the restraint of ground-referenced sensing. The relation between
VC and peak current in the power stage is given by:
§ V R S (p k ) ·
1¨
¸
© RS
¹
L(p k )
N
3 RS
9C ±
9
where
•
N = Current sense transformer turns ratio = 1 when transformer not used.
(3)
For purposes of small-signal analysis, the control-to-sensed-current gain is:
i(p k )
N
VC
3 RS
(4)
When sensing current in series with the power transistor, as shown in Figure 18, the current waveform often has
a large spike at its leading edge. This spike is due to rectifier recovery and/or inter-winding capacitance in the
power transformer. If unattenuated, this transient can prematurely terminate the output pulse. As shown, a simple
RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the
current spike duration (usually a few hundred nanoseconds).
The inverting input to the UC1843A-SP current-sense comparator is internally clamped to 1 V (Figure 18).
Current limiting occurs if the voltage at pin 3 reaches this threshold value, that is, the current limit is defined by:
im a x
N u1V
RS
(5)
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Figure 18. Transformer-Coupled Current Sensing
9.2.2.3 Error Amplifier
The error amplifier (E/A) configuration is shown in Figure 19. The non-inverting input is not brought out to a pin,
but is internally biased to 5 V ±2%. The E/A output is available at pin 1 for external compensation, allowing the
user to control the converter’s closed-loop frequency response.
Figure 20 shows an E/A compensation circuit suitable for stabilizing any current-mode controlled topology except
for flyback and boost converters operating with inductor current. The feedback components add a pole to the
loop transfer function at ƒp = ½ π RF. RF and CF are chosen so that this pole cancels the zero of the output filter
capacitor ESR in the power circuit. RI and RF fix the low-frequency gain. They are chosen to provide as much
gain as possible while still allowing the pole formed by the output filter capacitor and load to roll off the loop gain
to unity (0 dB) at ƒ ≈ ƒSWITCHING / 4. This technique ensures converter stability while providing good dynamic
response.
5V
+
VFB
Zi
Zf
0.5 mA
–
COMP
Figure 19. E/A Configuration
18
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5V
Figure 20. Compensation
The E/A output sources 0.5 mA and sinks 2 mA. A lower limit for RF is given by:
R F (M IN ) |
9E A O U T (M A X ) ±
9
9 ±
0 .5 m A
9
0 .5 m A
7 k:
(6)
E/A input bias current (2-µA max) flows through RI, resulting in a DC error in output voltage (VO) given by:
' V O (M A X )
(2 µ A ) R I
(7)
Therefore, the designer should keep the value of RI, as low as possible.
Figure 21 shows the open-loop frequency response of the UC1843A-SP E/A. The gain represents an upper limit
on the gain of the compensated E/A. Phase lag increases rapidly as frequency exceeds 1 MHz due to secondorder poles at about 10 MHz and above.
Phase (°)
Voltage Gain (dB)
Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their transfer
function. An additional compensation pole is needed to roll off loop gain at a frequency less than that of the RHP
zero. RP and CP in the circuit of Figure 14 provide this pole.
Frequency (Hz)
Figure 21. Error Amplifier Open-Loop Frequency Response
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9.2.3 Application Curves
100%
Oscillator Frequency (Hz)
Maximum Duty Cycle
80%
60%
40%
1M
100k
10k
20%
300
1.00k
3.00k
10.0k
30.0k
100k
300
RT (Ω)
1.00k
3.00k
10.0k
30.0k
100k
RT (Ω)
Figure 22. Oscillator Frequency vs Timing Resistance
Figure 23. Maximum Duty Cycle vs Timing Resistor
VREF
RT
RT/CT
CT
GROUND
For RT > 5k
ƒ ≈ 1.72 / (RTCT)
Figure 24. Oscillation Schematic
20
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 8 V and 40 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the UC1843A-SP
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum
capacitor with a value of 47 µF is a typical choice; however, this may vary depending upon the output power
being delivered.
UC1843A-SP
Copyright © 2016, Texas Instruments Incorporated
Power supply specifications:
1.
Input voltage: 95 VAC to 130 VAC (50 Hz/60 Hz)
2.
Line isolation: 3750 V
3.
Switching frequency: 40 kHz
4.
Efficiency full load: 70%
5.
Output voltage:
a.
+5 V, ±5%; 1- to 4-A load, ripple voltage: 50 mVP-P max
b.
+12 V, ±3%; 0.1- to 0.3-A load, ripple voltage: 100 mVP-P max
c.
–12 V, ±3%; 0.1- to 0.3-A load, ripple voltage: 100 mVP-P max
Figure 25. Offline Flyback Regulator
11 Layout
11.1 Layout Guidelines
Always try to use a low-EMI inductor with a ferrite-type closed core. Some examples would be toroid and
encased E core inductors. Open core can be used if they have low-EMI characteristics and are located a farther
away from the low-power traces and components. Make the poles perpendicular to the PCB as well if using an
open core. Stick cores usually emit the most unwanted noise.
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Layout Guidelines (continued)
11.1.1 Feedback Traces
Try to run the feedback trace as far as possible from the inductor and noisy power traces. The designer should
also make the feedback trace as direct as possible and somewhat thick. These two guidelines sometimes involve
a trade-off, but keeping the trace away from inductor EMI and other noise sources is the more critical guideline.
Run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two.
11.1.2 Input/Output Capacitors
When using a low-value ceramic input filter capacitor, locate it as close as possible to the VIN pin of the IC. This
eliminates as much trace inductance effects as possible and gives the internal IC rail a cleaner voltage supply.
Some designs require the use of a feed-forward capacitor connected from the output to the feedback pin as well,
usually for stability reasons. In this case, it should also be positioned as close as possible to the IC. Using
surface mount capacitors also reduces lead length and lessens the chance of noise coupling into the effective
antenna created by through-hole components.
11.1.3 Compensation Components
External compensation components for stability should also be placed close to the IC. TI recommends to also
use surface mount components for the same reasons discussed for the filter capacitors. These should not be
located very close to the inductor either.
11.1.4 Traces and Ground Planes
Make all of the power (high-current) traces as short, direct, and thick as possible. It is good practice on a
standard PCB to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor, output
capacitors, and output diode should be as close as possible to each other. This helps reduce the EMI radiated by
the power traces due to the high-switching currents through them. This also reduces lead inductance and
resistance, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The
grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected close
together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the
PCB. This reduces noise by reducing ground loop errors and absorbing more of the EMI radiated by the inductor.
For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane
(where the power traces and components are) and the signal plane (where the feedback and compensation and
components are) for improved performance. On multi-layer boards, vias are required to connect traces and
different planes. It is a good practice to use one standard via per 200 mA of current if the trace needs to conduct
a significant amount of current from one plane to the other. Arrange the components so that the switching current
loops curl in the same direction. Due to the way switching regulators operate, there are two power states: one
state when the switch is on and one when the switch is off. During each state there is a current loop made by the
power components that are currently conducting. Place the power components so that during each of the two
states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the
traces between the two half-cycles and reduces radiated EMI.
22
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11.2 Layout Example
I
I
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used
to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 26. Open-Loop Laboratory Test Fixture
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
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21-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8670406VPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8670406VPA
UC1843A
5962-8670406VXA
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59628670406VXA
UC1843AL
QMLV
5962-8670409VPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
8670409VPA
UC1843A-SP
5962P8670409VPA
ACTIVE
CDIP
JG
8
1
TBD
Call TI
Call TI
-55 to 125
P8670409VPA
UC1843A-SP
5962P8670409VYC
ACTIVE
CFP
HKU
10
1
TBD
Call TI
Call TI
-55 to 125
P8670409VYC
UC1843A-SP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1843A-SP :
• Catalog: UC1843A
• Enhanced Product: UC1843A-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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