Texas Instruments | TPS50601A-SP Radiation Hardened 3-V to 7-V Input, 6-A Synchronous Buck Converter (Rev. D) | Datasheet | Texas Instruments TPS50601A-SP Radiation Hardened 3-V to 7-V Input, 6-A Synchronous Buck Converter (Rev. D) Datasheet

Texas Instruments TPS50601A-SP Radiation Hardened 3-V to 7-V Input, 6-A Synchronous Buck Converter (Rev. D) Datasheet
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TPS50601A-SP
SLVSDF5D – SEPTEMBER 2017 – REVISED OCTOBER 2019
TPS50601A-SP Radiation Hardened 3-V to 7-V Input, 6-A Synchronous Buck Converter
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
5962-10221:
– Radiation hardened up to TID 100 krad(Si)
– ELDRS free 100 krad(Si) – 10 mrad(Si)/s
– Single lhup (SEL) Immune to
LET = 75 MeV-cm2/mg
– SEB and SEGR immune to 75 MeV-cm2/mg,
SOA Curve Available
– SET/SEFI Cross-section plot available
peak efficiency: 96.6% (VO = 3.3 V)
Integrated 58-mΩ/50-mΩ MOSFETs
Power rail: 3 to 7 V on VIN
6-A Maximum output current
Flexible switching frequency options:
– 100-kHz to 1-MHz Adjustable internal oscillator
– External sync capability: 100 kHz to 1 MHz
– Sync pin can be configured as a 500-kHz
output for master/slave applications
0.804-V ±1.5% Voltage reference
overtemperature, radiation, and line and load
regulation
Monotonic start-up into prebiased outputs
Adjustable soft start through external capacitor
Input enable and power-good output for power
sequencing
Power good output monitor for undervoltage and
overvoltage
Adjustable input undervoltage lockout (UVLO)
20-Pin Ultra-small, thermally-enhanced ceramic
flatpack package (hkh) for space applications
Efficiency at VIN = PVIN = 5 V
•
•
•
•
Space satellite point of load supply for FPGAs,
microcontrollers, data converters and ASICs
Space satellite payloads
Radiation hardened applications
Available in military (–55°C to 125°C) temperature
range
Engineering evaluation (/EM) Samples are
available
3 Description
The TPS50601A-SP is a radiation hardened, 7-V, 6-A
synchronous step-down converter, which is optimized
for small designs through high efficiency and
integrating the high-side and low-side MOSFETs.
Further space savings are achieved through current
mode control, which reduces component count, and a
high switching frequency, reducing the inductor's
footprint. The devices are offered in an ultra small,
thermally enhanced 20-pin ceramic flatpack package.
The output voltage startup ramp is controlled by the
SS/TR pin which allows operation as either a stand
alone power supply or in tracking situations. Power
sequencing is also possible by correctly configuring
the enable and the open drain power good pins. In
addition, the TPS50601A-SP can be configured in
master-slave mode to provide up to 12-A of output
current.
Cycle-by-cycle current limiting on the high-side FET
protects the device in overload situations and is
enhanced by a low-side sourcing current limit which
prevents current runaway. There is also a low-side
sinking current limit which turns off the low-side
MOSFET to prevent excessive reverse current.
Thermal shutdown disables the part when die
temperature exceeds thermal shutdown temperature.
100%
Device Information(1)
90%
PART NUMBER
80%
Efficiency
70%
60%
50%
40%
30%
VOUT = 1 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
20%
10%
0
0
0.5
1
1.5
2
2.5 3 3.5
Load (A)
4
4.5
5
5.5
6
D001
GRADE
5962-1022102VSC
QMLV
5962R1022102VSC
RHA - 100 krad(Si)
PACKAGE
CFP (20)(4)
(2)
TPS50601AHKH/EM
Engineering Evaluation
5962R1022102V9A
KGD RHA - 100 krad(Si)
Die(3)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) These units are intended for engineering evaluation only.
They are processed to a noncompliant flow. These units are
not suitable for qualification, production, radiation testing or
flight use. Parts are not warranted for performance over the
full MIL specified temperature range of –55°C to 125°C or
operating life.
(3) Bare die in waffle pack.
(4) Weight = 1.22g and is rounded to approximately ±10%
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS50601A-SP
SLVSDF5D – SEPTEMBER 2017 – REVISED OCTOBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
7
1
1
1
2
3
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2018) to Revision D
Page
•
added note: Weight = 1.22g to the Device Information table ................................................................................................. 1
•
Changed the Pin Configuration image.................................................................................................................................... 3
•
Changed SYNC out high level threshold MIN value From: 2 V To: VIN - 0.3 in the Electrical Characteristics table .............. 9
•
Deleted test Condition "Percent of program frequency" from SYNC in frequency range in the Electrical
Characteristics table ............................................................................................................................................................... 9
•
Changed "180° out of phase to the internal 500-kHz switching frequency." To: "180° in phase to the internal 500kHz switching frequency." in the Description of Table 3 ...................................................................................................... 18
•
Changed "180° out of phase respect to the internal oscillator.." To: "180° in phase respect to the internal oscillator.."
in the Parallel Operation section........................................................................................................................................... 27
•
Changed "(180° out of phase respect to the master device)." To: "(180° in phase respect to the master device).." in
the Parallel Operation section .............................................................................................................................................. 28
Changes from Revision B (June 2018) to Revision C
•
Page
Replaced all coordinates in Bond Pad Coordinates in Microns table with corrected values.................................................. 5
Changes from Revision A (March 2018) to Revision B
Page
•
Added Bare Die Information table .......................................................................................................................................... 4
•
Added Bond Pad Coordinates in Microns table...................................................................................................................... 5
Changes from Original (September 2017) to Revision A
•
2
Page
Changed the device status from Advance Information to Production Data............................................................................ 1
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SLVSDF5D – SEPTEMBER 2017 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
HKH Package
20-Pin CFP
Bottom View
GND
1
20
PWRGD
EN
2
19
SS/TR
RT
3
18
CO MP
SYNC
4
17
VSENSE
VIN
5
16
RE FCA P
15
PH
Th ermal
PVIN
6
PVIN
7
14
PH
PGND
8
13
PH
PGND
9
12
PH
PGND
10
11
PH
Pad
No t to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
GND
—
2
EN
I
EN pin is internally pulled up allowing for the pin to be floated to enable the device. Adjust the input undervoltage lockout (UVLO)
with two resistors.
3
RT
I/O
In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching frequency. Leaving this pin
floating sets the internal switching frequency to 500 kHz.
4
SYNC
I/O
Optional 100-kHz to 1-MHz external system clock input.
5
VIN
I
Input power for the control circuitry of the switching regulator.
PVIN
I
Input power for the output stage of the switching regulator.
PGND
—
Return for low-side power MOSFET.
PH
O
Switch phase node.
16
REFCAP
O
Required 470-nF external capacitor for internal reference.
17
VSENSE
I
Inverting input of the gm error amplifier.
18
COMP
I/O
Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.
19
SS/TR
I/O
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on
this pin overrides the internal reference. It can be used for tracking and sequencing.
20
PWRGD
O
Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or
during slow start.
6
7
Return for control circuitry.
(1)
8
9
10
11
12
13
14
15
(1)
GND (pin 1, analog ground) must be connected to PGND external to the package. Thermal pad must be connected to a heat dissipating
layer. Thermal pad is internally connected to the seal ring and GND.
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SLVSDF5D – SEPTEMBER 2017 – REVISED OCTOBER 2019
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Table 1. Bare Die Information
4
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD METALLIZATION
COMPOSITION
BOND PAD THICKNESS
15 mils
Silicon with backgrind
Ground
ALCU
1050 nm
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SLVSDF5D – SEPTEMBER 2017 – REVISED OCTOBER 2019
Table 2. Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
AVSS
1
938.16
5098.41
1064.16
5224.41
AVSS
2
759.06
5098.41
885.06
5224.41
N/C
3
579.96
5098.41
705.96
5224.41
AVSS
4
400.86
5098.41
526.86
5224.41
AVSS
5
221.76
5098.41
347.76
5224.41
EN
6
38.7
4843.98
164.7
4969.98
RT
7
38.7
4115.43
164.7
4241.43
SYNC
8
38.7
3936.33
164.7
4062.33
VIN
9
55.89
3473.865
181.89
3599.865
VIN
10
55.89
3285.765
181.89
3411.765
VIN
11
55.89
3097.665
181.89
3223.665
VIN
12
55.89
2909.565
181.89
3035.565
PVIN
13
360.045
2468.025
486.045
2594.025
PVIN
14
500.805
2468.025
626.805
2594.025
PVIN
15
643.905
2468.025
769.905
2594.025
PVIN
16
782.505
2468.025
908.505
2594.025
PVIN
17
360.045
2312.595
486.045
2438.595
PVIN
18
500.805
2312.595
626.805
2438.595
PVIN
19
643.905
2312.595
769.905
2438.595
PVIN
20
782.505
2312.595
908.505
2438.595
PVIN
21
360.045
1868.265
486.045
1994.265
PVIN
22
500.805
1868.265
626.805
1994.265
PVIN
23
643.905
1868.265
769.905
1994.265
PVIN
24
782.505
1868.265
908.505
1994.265
PVIN
25
360.045
1712.835
486.045
1838.835
PVIN
26
500.805
1712.835
626.805
1838.835
PVIN
27
643.905
1712.835
769.905
1838.835
PVIN
28
782.505
1712.835
908.505
1838.835
PGND
29
360
1004.625
486
1130.625
PGND
30
498.6
1004.625
624.6
1130.625
PGND
31
637.2
1004.625
763.2
1130.625
PGND
32
775.8
1004.625
901.8
1130.625
PGND
33
360
863.955
486
989.955
PGND
34
498.6
863.955
624.6
989.955
PGND
35
637.2
863.955
763.2
989.955
PGND
36
775.8
863.955
901.8
989.955
PGND
37
360
384.525
486
510.525
PGND
38
360
243.855
486
369.855
PGND
39
503.1
243.855
629.1
369.855
PGND
40
503.1
384.525
629.1
510.525
PGND
41
641.7
243.855
767.7
369.855
PGND
42
641.7
384.525
767.7
510.525
PGND
43
775.8
243.855
901.8
369.855
PGND
44
775.8
384.525
901.8
510.525
PH
45
1239.66
97.425
1365.66
223.425
PH
46
1374.66
529.965
1500.66
655.965
PH
47
1378.26
97.425
1504.26
223.425
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Table 2. Bond Pad Coordinates in Microns (continued)
6
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
PH
48
1516.86
97.425
1642.86
223.425
PH
49
1657.26
97.425
1783.26
223.425
PH
50
1790.46
529.965
1916.46
655.965
PH
51
1651.86
529.965
1777.86
655.965
PH
52
1513.26
529.965
1639.26
655.965
PH
53
1790.46
718.515
1916.46
844.515
PH
54
1651.86
718.515
1777.86
844.515
PH
55
1513.26
718.515
1639.26
844.515
PH
56
1374.66
718.515
1500.66
844.515
PH
57
1790.46
1150.065
1916.46
1276.065
PH
58
1651.86
1150.065
1777.86
1276.065
PH
59
1513.26
1150.065
1639.26
1276.065
PH
60
1374.66
1150.065
1500.66
1276.065
PH
61
1795.365
1565.1
1921.365
1691.1
PH
62
1655.865
1565.1
1781.865
1691.1
PH
63
1515.465
1565.1
1641.465
1691.1
PH
64
1376.865
1565.1
1502.865
1691.1
PH
65
1795.365
2016
1921.365
2142
PH
66
1655.865
2016
1781.865
2142
PH
67
1515.465
2016
1641.465
2142
PH
68
1376.865
2016
1502.865
2142
PH
69
1795.365
2164.86
1921.365
2290.86
PH
70
1655.865
2164.86
1781.865
2290.86
PH
71
1515.465
2164.86
1641.465
2290.86
PH
72
1376.865
2164.86
1502.865
2290.86
PH
73
1795.365
2615.76
1921.365
2741.76
PH
74
1655.865
2615.76
1781.865
2741.76
PH
75
1515.465
2615.76
1641.465
2741.76
PH
76
1376.865
2615.76
1502.865
2741.76
REFCAP_NU
77
1933.245
3572.46
2059.245
3698.46
VSENSE
78
1933.245
3770.415
2059.245
3896.415
COMP
79
1933.245
3949.515
2059.245
4075.515
SS
80
1933.2
4149.135
2059.2
4275.135
PWRGD
81
1933.2
4292.325
2059.2
4418.325
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature (unless otherwise noted) (1)
Input voltage
Output voltage
MIN
MAX
VIN
–0.3
7.5
PVIN
–0.3
7.5
EN
–0.3
5.5
VSENSE
–0.3
3.3
COMP
–0.3
3.3
PWRGD
–0.3
5.5
SS/TR
–0.3
5.5
RT
–0.3
5.5
SYNC
–0.3
7.5
REFCAP
–0.3
3.3
–1
7.5
–3
7.5
PH
PH 10-ns transient
Vdiff
(GND to exposed thermal pad)
V
0.2
V
Current limit
Current limit
A
±100
µA
PH
Current limit
Current limit
A
PVIN
Current limit
Current limit
A
RT
Sink current
V
–0.2
PH
Source current
UNIT
COMP
±200
µA
–0.1
5
mA
Operating junction temperature
–55
150
°C
Storage temperature, Tstg
–65
150
°C
PWRGD
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±750
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
TJ
Junction operating temperature
NOM
–55
MAX
UNIT
125
°C
6.4 Thermal Information
TPS50601A-SP
THERMAL METRIC
(1)
HKH (CFP)
UNIT
20 PINS
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
0.514
°C/W
Taken per Mil Standard 883 method 1012.1.
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6.5 Electrical Characteristics
TJ = –55°C to 125°C, VIN = PVIN = 3.0 V to 7.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage (VIN AND PVIN Pins)
PVIN operating input voltage
3
PVIN internal UVLO threshold
PVIN rising
PVIN internal UVLO hysteresis
VIN operating input voltage
7
V
450
mV
3
VIN internal UVLO threshold
VIN rising
7
2.75
VIN internal UVLO hysteresis
3
150
VIN shutdown supply current
VEN = 0 V
VIN operating – non switching supply current
VSENSE = VBG
V
2.50
V
V
mV
1.35
2.5
mA
5
10
mA
1.14
1.18
Enable and UVLO (EN Pin)
Rising
Enable threshold
Falling
1.05
1.11
V
Input current
VEN = 1.1 V
6.1
μA
Hysteresis current
VEN = 1.3 V
3
μA
Voltage Reference
Voltage reference
0 A ≤ Iout ≤ 6 A, –55 to 125°C
REFCAP voltage
470 nF
0.792
0.804
0.816
1.211
V
V
Mosfet
High-side switch resistance
PVIN = VIN = 3 V, lead length = 4 mm
50
mΩ
High-side switch resistance (1)
PVIN = VIN = 5 V, lead length = 4 mm
45
mΩ
(1)
High-side switch resistance
PVIN = VIN = 7 V, lead length = 4 mm
43
mΩ
Low-side switch resistance (1)
PVIN = VIN= 3 V, lead length = 4 mm
35
mΩ
Low-side switch resistance (1)
PVIN = VIN = 5 V, lead length = 4 mm
34
mΩ
Low-side switch resistance (1)
PVIN = VIN = 7 V, lead length = 4 mm
33
mΩ
Error Amplifier
Error amplifier transconductance (gm) (2)
–2 μA < ICOMP < 2 μA, V(COMP) = 1 V
Error amplifier dc gain (2)
VSENSE = 0.804 V
Error amplifier source/sink (2)
V(COMP) = 1 V, 100-mV input overdrive
1000
–250
Error amplifier output resistance
2000
±115
(2)
μS
V/V
250
7
Start switching threshold (2)
COMP to Iswitch gm
1400
10000
μA
MΩ
0.25
V
22
S
Current Limit
High-side switch current limit threshold
(3)
VIN = 7 V
11
A
Low-side switch sourcing current limit (3)
VIN = 7 V
10
A
Low-side switch sinking current limit
VIN = 7 V
3
A
170
°C
30
°C
Thermal Shutdown
Thermal shutdown
Thermal shutdown hysteresis
Internal Switching Frequency
Internally set frequency
Externally set frequency
RT = Open
395
500
585
RT = 100 kΩ (1%)
395
500
585
RT = 487 kΩ (1%)
85
100
120
RT = 47 kΩ (1%)
900
1000
1100
kHz
kHz
External Synchronization
(1)
(2)
(3)
8
Measured at pins.
Ensured by design only. Not tested in production.
Parameter is not tested in production.
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Electrical Characteristics (continued)
TJ = –55°C to 125°C, VIN = PVIN = 3.0 V to 7.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNC out low-to-high rise time (10%/90%)
CLOAD = 25 pF
70
111
ns
SYNC out high-to-low fall time (90%/10%)
CLOAD = 25 pF
6
15.5
ns
Falling edge delay time (4)
180
SYNC out high level threshold
IOH = 50 µA
SYNC out low level threshold
IOL = 50 µA
SYNC in low level threshold
PVIN = VIN = 3 V
SYNC in high level threshold
PVIN = VIN = 3 V
SYNC in low level threshold
PVIN = VIN = 7 V
SYNC in high level threshold
PVIN = VIN = 7 V
SYNC in frequency range (5)
°
VIN - 0.3
V
600
mV
900
mV
2.45
V
900
mV
1000
kHz
235
ns
4.25
V
100
PH (PH Pin)
Minimum on time
Measured at 10% to 90% of VIN,
25°C, IPH = 2 A
190
Slow Start and Tracking (SS/TR Pin)
SS charge current
SS/TR to VSENSE matching
2.5
3
μA
V(SS/TR) = 0.4 V
1.5
30
90
mV
VSENSE falling (fault)
91
VSENSE rising (good)
94
VSENSE rising (fault)
109
VSENSE falling (good)
106
Power Good (PWRGD Pin)
VSENSE threshold
Output high leakage
VSENSE = VREF, V(PWRGD) = 5 V
Output low
I(PWRGD) = 2 mA
Minimum VIN for valid output
V(PWRGD) < 0.5 V at 100 μA
Minimum SS/TR voltage for PWRGD
(4)
(5)
30
0.6
%
VREF
181
nA
0.3
V
1
V
1.55
V
Bench verified. Not tested in production.
Parameter is production tested at nominal voltage with VIN = PVIN = 5 V.
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6.6 Typical Characteristics
100%
0.816
90%
0.814
Voltage Reference (V)
80%
70%
50%
40%
30%
VOUT = 1 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
20%
10%
0.81
0.808
0.804
0.802
-55
0
0
0.5
1
1.5
2
2.5 3 3.5
Load (A)
4
4.5
5
5.5
VIN = 3 V & NL
VIN = 5 V & NL
VIN = 7 V & NL
VIN = 3 V & 6-A Load
VIN = 5 V & 6-A Load
VIN = 7 V & 6-A Load
0.806
6
VIN Shutdown Quiescent Current (mA)
Oscillator Frequency (kHz)
VIN = 3 V & No Load
VIN = 3 V & 6 A
VIN = 5 V & No Load
VIN = 5 V & 6 A
VIN = 7 V & No Load
VIN = 7 V & 6 A
-25
5
5
35
65
Temperature (qC)
95
35
65
Temperature (qC)
95
125
D006
Figure 2. Voltage Reference vs Temperature
Figure 1. Efficiency at VIN = PVIN = 5 V
525
520
515
510
505
500
495
490
485
480
475
470
465
460
-55
-25
D001
2.25
0.54
2
0.48
1.75
0.42
1.5
0.36
1.25
0.3
1
0.24
0.75
VIN = 3 V
0.18
PVIN = 3 V
VIN = 5 V
0.12
PVIN = 5 V
VIN = 7 V
0.06
PVIN = 7 V
0
95
125
0.5
0.25
0
-55
125
-25
5
D007
Figure 3. Internal Oscillator Frequency vs Temperature
35
65
Temperature (qC)
PVIN Shutdown Quiescent Current (mA)
Efficiency
60%
0.812
D008
Figure 4. Shutdown Quiescent Current vs Temperature
6.45
3.25
EN Pin Pull-Up Current (PA)
EN Pin Hysteresis Current (PA)
3.225
3.2
3.175
3.15
3.125
3.1
3.075
3.05
VIN = 3 V
VIN = 5 V
VIN = 7 V
3.025
3
-55
-25
5
35
65
Temperature (qC)
95
125
6.35
6.3
6.25
VIN = 3 V
VIN = 5 V
VIN = 7 V
6.2
6.15
-55
D009
Figure 5. EN Pin Hysteresis Current vs Temperature
10
6.4
-25
5
35
65
Temperature (qC)
95
125
D010
Figure 6. EN Pin Pull-Up Current vs Temperature
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1.15
EN Pin UVLO Threshold (V)
1.145
1.14
1.135
1.13
1.125
VIN = 3 V (Falling)
VIN = 5 V (Falling)
VIN = 7 V (Falling)
VIN = 3 V (Rising)
VIN = 5 V (Rising)
VIN = 7 V (Rising)
1.12
1.115
1.11
-55
-25
5
35
65
Temperature (qC)
95
125
Non-Switching Operating Quiscent Current (mA)
Typical Characteristics (continued)
3
2.7
2.4
2.1
1.8
1.5
-60
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D012
Figure 8. Non-Switching Operating Quiescent Current (VIN)
vs Temperature
2.28
35
30
Vsense) Offset (mV)
2.26
2.24
2.22
(SS
ISS Slow Start Charge Current (PA)
-40
D011
Figure 7. EN Pin UVLO Threshold vs Temperature
2.2
VIN = 3 V
VIN = 5 V
VIN = 7 V
2.18
-55
-25
5
35
65
Temperature (qC)
95
25
20
15
10
0
-55
125
-25
5
35
65
Temperature (qC)
D013
95
125
D014
Figure 10. (SS-VSENSE) Offset vs Temperature
50
VIN = 3 V
VIN = 5 V
VIN = 7 V
On-State Resistance (m:)
13
12.8
12.6
12.4
12.2
12
11.8
11.6
11.4
11.2
11
10.8
10.6
10.4
10.2
10
-60
VIN = 3 V
VIN = 5 V
VIN = 7 V
5
Figure 9. Slow Start Charge Current vs Temperature
Current Limit Threshold (A)
VIN = 3 V
VIN = 5 V
VIN = 7 V
45
40
35
30
VIN = 3 V
VIN = 5 V
VIN = 7 V
25
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
20
-55
-25
D015
Figure 11. High-Side Current Limit Threshold vs
Temperature
5
35
65
Temperature (qC)
95
125
D016
Figure 12. Low-Side RDS(ON) vs Temperature
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70
90%
65
80%
60
70%
Current Sharing
On-State Resistance (m:)
Typical Characteristics (continued)
55
50
45
VIN = 3 V
VIN = 5 V
VIN = 7 V
35
5
6
7
8
Load Current (A)
9
60%
50%
40%
20%
10%
-25
5
35
65
Temperature (qC)
95
125
0
1
2
D017
VIN = 5 V
Figure 13. High-Side RDS(ON) vs Temperature
12
Slave at 55°C
Slave at 25°C
Slave at 125°C
30%
40
30
-55
Master at 55°C
Master at 25°C
Master at 125°C
3
4
VOUT = 2.5 V
10
11
12
D018
ƒSW = 500 kHz
Figure 14. Current Sharing vs Load Current
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7 Detailed Description
7.1 Overview
The device is a 7-V, 6-A synchronous step-down (buck) converter with two integrated MOSFETs, a PMOS for the
high side and a NMOS for the low side. To improve performance during line and load transients, the device
implements a constant frequency, peak current mode control, which also simplifies external frequency
compensation. The wide switching frequency, 100 kHz to 1 MHz, allows for efficiency and size optimization when
selecting the output filter components.
The device is designed for safe monotonic startup into prebiased loads. The default start up is when VIN is
typically 3 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage UVLO
with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal
pullup current. The total operating current for the device is approximately 5 mA when not switching and under no
load. When the device is disabled, the supply current is typically less than 2.5 mA.
The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 6
A. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open-drain MOSFET which is pulled low when the VSENSE pin voltage
is less than 91% or greater than 109% of the reference voltage VREF and asserts high when the VSENSE pin
voltage is 94% to 106% of the VREF.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing
during power-up. A small-value capacitor or resistor divider should be coupled to the pin for slow start or critical
power-supply sequencing requirements.
The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 106% of the VREF. The device implements both high-side
MOSFET overload protection and bidirectional low-side MOSFET overload protections, which help control the
inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than
thermal shutdown trip point. The device is restarted under control of the slow-start circuit automatically when the
junction temperature drops 10°C typical below the thermal shutdown trip point.
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7.2 Functional Block Diagram
PWRGD
VIN
EN
PVIN PVIN
UVLO
Shutdown
Ip
UV
Enable
Comparator
Ih
Thermal
Shutdown
2.75 V
Shutdown
Logic
1.14 V
UVLO
OV
2.49 V
Current
Sense
Minimum Clamp
Pulse Skip
ERROR
AMPLIFIER
VIN
VSENSE
V/I
VSENSE
REFCAP
PVIN
SS/TR
SS/TR
Hysteretic
Control
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
& Deadtime
Control
Logic
PVIN
Slope
Compensation
Overload Recovery
and
Clamp
PH
Oscillator
RT Bias
LS MOSFET
Current Limit
Current
Sense
PGND
SYNC
Detect
COMP
SYNC
PH
PGND
RT
Thermal Pad/GND
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 VIN and Power VIN Pins (VIN and PVIN)
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system. Both pins have an input voltage range from 3 to 7 V. A voltage divider connected to
the EN pin can adjust the input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin
helps to provide consistent power-up behavior.
7.3.2 Voltage Reference
The voltage reference system produces a precise voltage reference as indicated in Electrical Characteristics.
14
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Feature Description (continued)
7.3.3 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. TI recommends to
use 1% tolerance or better resistors. Start with a 10 kΩ for RTOP and use Equation 1 to calculate RBOTTOM. To
improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is
more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
R BOTTOM =
VREF
× R TOP
VOUT F VREF
where
•
VREF = 0.804 V
(1)
7.3.4 Safe Start-Up Into Prebiased Outputs
The device is designed to prevent the low-side MOSFET from discharging a prebiased output. During monotonic
prebiased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is higher than
1.55 V.
7.3.5 Error Amplifier
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the
lower of the SS/TR pin voltage or the internal 0.804-V voltage reference. The transconductance of the error
amplifier is 1475 μA/V during normal operation. The frequency compensation network is connected between the
COMP pin and ground. The error amplifier DC gain is typically 20,000 V/V.
7.3.6 Slope Compensation
The device adds a compensating ramp to the switch current signal. This slope compensation prevents
subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.7 Enable and Adjust UVLO
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state. The EN pin has an internal pullup current source, allowing the user to
float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or opencollector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150-mV
typical.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN in
split-rail applications, then the EN pin can be configured as shown in Figure 15, Figure 16, and Figure 17. A
ceramic capacitor in parallel with the bottom resistor R2 is recommended to reduce noise on the EN pin as used
in the TPS50601A-SP Evaluation Module, SLVUB65.
The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. Calculate the UVLO thresholds
with Equation 2 and Equation 3.
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Feature Description (continued)
TPS50601A-SP
VIN
ip
ih
R1
EN
R2
Copyright © 2017, Texas Instruments Incorporated
Figure 15. Adjustable VIN UVLO
TPS50601A-SP
PVIN
ip
ih
R1
EN
R2
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Adjustable PVIN UVLO
TPS50601A-SP
PVIN
VIN
ip
ih
R1
EN
R2
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Adjustable VIN and PVIN UVLO
VENFALLING
F VST OP
VENRISING
V
Ip @1 F ENFALLING A + Ih
VENRISING
VSTART ×
R1 =
16
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Feature Description (continued)
R2 =
R1 × VENFALLING
VSTOP F VENFALLING + R1 kIp + Ih o
where
•
•
•
•
Ih = 3 μA
Ip = 6.1 μA
VENRISING = 1.14 V
VENFALLING = 1.11 V
(3)
7.3.8 Adjustable Switching Frequency and Synchronization (SYNC)
The switching frequency of the device supports three modes of operations. The modes of operation are set by
the conditions on the RT and SYNC pins. At a high level, these modes can be described as master, internal
oscillator, and external synchronization modes.
In master mode, the RT pin should be left floating; the internal oscillator is set to 500 kHz, and the SYNC pin is
set as an output clock. The SYNC output is in phase with respect to the internal oscillator. SYNC out signal level
is the same as VIN level with 50% duty cycle. SYNC signal feeding the slave module, which is in phase with the
master clock, gets internally inverted (180° out of phase with the master clock) internally in the slave module.
In internal oscillator mode, a resistor is connected between the RT pin and GND. The SYNC pin requires a 10kΩ resistor to GND for this mode to be effective. The switching frequency of the device is adjustable from 100
kHz to 1 MHz by placing a maximum of 510 kΩ and a minimum of 47 kΩ respectively. To determine the RT
resistance for a given switching frequency, use Equation 4 or the curve in Figure 18. To reduce the solution size,
the designer should set switching frequency as high as possible, but consider the tradeoffs of supply efficiency
and minimum controllable on-time.
-1.0549
RT(FSW) = 67009 x FSW
where
•
•
RT in kΩ
fSW in kHz
(4)
600
500
RT (k:)
400
300
200
100
0
100
200
300 400 500 600 700 800
Fsw - Switching Frequency (kHz)
900
1000
D001
Figure 18. RT vs Switching Frequency
When operating the converter in internal oscillator mode (internal oscillator determines the switching frequency
(500 kHz) default), the synchronous pin becomes the output and there is a phase inversion. When trying to
parallel with another converter, the RT pin of the second (slave) converter must have its RT pin populated such
that the converter frequency of the slave converter must be within ±5% of the master converter. This is required
because the RT pin also sets the proper operation of slope compensation.
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Feature Description (continued)
In external synchronization mode, a resistor is connected between the RT pin and GND. The SYNC pin requires
a toggling signal for this mode to be effective. The switching frequency of the device goes 1:1 with that of SYNC
pin. External system clock-user supplied sync clock signal determines the switching frequency. If no external
clock signal is detected for 20 µs, then TPS50601A-SP transitions to its internal clock, which is typically 500 kHz.
An external synchronization using an inverter to obtain phase inversion is necessary. RT values of the master
and slave converter must be within ±5% of the external synchronization frequency. This is necessary for proper
slope compensation. A resistance in the RT pin is required for proper operation of the slope compensation circuit.
To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 18.
These modes are described in Table 3.
Table 3. Switching Frequency, SYNC and RT Pin Usage Table
RT PIN
Float
47-kΩ to 510-kΩ
resistor to AGND
SWITCHING
FREQUENCY
SYNC PIN
DESCRIPTION AND NOTES
Generates an output signal
500 kHz
SYNC pin behaves as an output. SYNC output signal
is 180° in phase to the internal 500-kHz switching
frequency.
10-kΩ resistor to GND
100 kHz to 1 MHz
Internally generated switching frequency is based
upon the resistor value present at the RT pin.
User-supplied sync clock or
Internally synchronized to
TPS50601A-SP master device
external clock
sync output
Set value of RT that corresponds to the externally
supplied sync frequency.
7.3.9 Slow Start (SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow-start
time. Equation 5 shows the calculations for the slow-start time (tSS, 10% to 90%) and slow-start capacitor (CSS).
The voltage reference (VREF) is 0.804 V and the slow-start charge current (ISS) is 2 μA.
t SS :ms; =
CSS (nF) × VREF (V)
ISS (JA)
(5)
When any of the following 3 scenarios occur; the input UVLO is triggered, the EN pin is pulled below 1.05 V, or a
thermal shutdown event occurs; the device stops switching and enters low current operation. At the subsequent
power-up, when the shutdown condition is removed, the device does not start switching until it has discharged its
SS/TR pin to ground ensuring proper soft-start behavior.
7.3.10 Power Good (PWRGD)
The PWRGD pin is an open-drain output. When the VSENSE pin is between 94% and 106% of the internal
voltage reference, the PWRGD pin pull-down is deasserted and the pin floats. TI recommends to use a pullup
resistor between 10 kΩ to 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state
when the VIN input voltage is greater than 1 V but has reduced current sinking capability. The PWRGD achieves
full current sinking capability when the VIN input voltage is above 3 V.
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN
pin is pulled low or the SS/TR pin is below 1.55 V.
7.3.11 Sequencing (SS/TR)
Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins.
The sequential method is shown in Figure 19 using two TPS50601A-SP devices. The power good of the first
device is coupled to the EN pin of the second device, which enables the second power supply after the primary
supply reaches regulation.
18
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TPS50601A-SP
TPS50601A-SP
PWRGD
EN
EN
SS/TR
SS/TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Sequential Start-Up Sequence
Figure 20 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices
together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start
time, the pullup current source must be doubled in Equation 5.
TPS50601A-SP
EN
SS/TR
PWRGD
TPS50601A-SP
EN
SS/TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Ratiometric Start-Up Sequence
Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network
of R1 and R2 (shown in Figure 21) to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2
slightly before, after, or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and
VOUT2.
To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when
VOUT2 reaches regulation, use a negative number in Equation 6 and Equation 7 for ΔV. Equation 8 results in a
positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is
achieved.
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The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE
offset ( VSS-OFFSET, 30 mV) in the slow-start circuit and the offset created by the pullup current source (ISS = 2 μA)
and tracking resistors, the VSS-OFFSET and ISS are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the
value calculated in Equation 9.
VOUT2 + ¿V VSS FOFFSET
×
VREF
ISS
VREF × R1
R2 =
VOUT2 + ¿V F VREF
¿V = VOUT1 F VOUT2
R1 > 2800 × VOUT1 F 180 × ¿V
R1 =
(6)
(7)
(8)
(9)
TPS50601A-SP
EN
VOUT1
SS/TR
PWRGD
TPS50601A-SP
EN
VOUT 2
R1
SS/TR
R2
PWRGD
R4
R3
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Ratiometric and Simultaneous Start-Up Sequence
7.3.12 Output Overvoltage Protection (OVP)
The device incorporates an output OVP circuit to minimize output voltage overshoot. For example, when the
power supply output is overloaded, the error amplifier compares the actual output voltage to the internal
reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time,
the output of the error amplifier demands maximum output current. After the condition is removed, the regulator
output rises and the error amplifier output transitions to the steady-state voltage. In some applications with small
output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the
possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin
voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold, the high-side
MOSFET is turned off, preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next
clock cycle.
20
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7.3.13 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side and
low-side MOSFET.
7.3.13.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current
and the current reference generated by the COMP pin voltage are compared, when the peak switch current
intersects the current reference, the high-side switch is turned off.
7.3.13.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are
off until the start of the next cycle.
When the low-side MOSFET turns off, the switch node increases and forward biases the high-side MOSFET
parallel diode (the high-side MOSFET is still off at this stage).
7.3.14 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C (typical). The device reinitiates the power-up sequence when the junction temperature drops below 165°C
(typical).
7.3.15 Turn-On Behavior
Minimum on-time specification determines the maximum operating frequency of the design. As the unit starts up
and goes through its soft-start process, the required duty-cycle is less than the minimum controllable on-time.
This can cause the converter to skip pulses. Thus, instantaneous output pulses can be higher or lower than the
desired voltage. This behavior is only evident when operating at high frequency with high bandwidth. When the
minimum on-pulse is greater than the minimum controllable on-time, the turn-on behavior is normal.
7.3.16 Small Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used frequency compensation circuits shown in Figure 22. In Type 2A, one additional high-frequency pole is
added to attenuate high-frequency noise.
The following design guidelines are provided for advanced users who prefer to compensate using the general
method. The step-by-step design procedure described in Detailed Design Procedure may also be used.
VOUT
R1
VSENSE
COMP Type 2A
Vref
R2
gm ea
Roea
R3
Coea
C2
Type 2B
R3
C1
C1
Figure 22. Types of Frequency Compensation
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The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency fco. A good starting point is one-tenth of the switching frequency, ƒSW.
2. R3 can be determined by:
R3 =
tN × fco × VOUT × COUT
gmea × Vref × gmps
(10)
where gmea is the gm of the error amplifier (1400 μS), gmps is the gm of the power stage (22 S) and VREF is
the reference voltage (0.804 V).
3. Place a compensation zero at the dominant pole
C1 can be determined by
C1 =
fp =
COUT
1
× RL × tN using C1 and R3.
COUT × RL
R3
(11)
4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output
capacitor COUT.
C2 =
COUT × RESR
R3
(12)
7.4 Device Functional Modes
7.4.1 Fixed-Frequency PWM Control
The device uses fixed frequency, peak current mode control. The output voltage is compared through external
resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin.
An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted
into a current reference which compares to the high-side power switch current. When the power switch current
reaches the current reference generated by the COMP voltage level, the high-side power switch is turned off and
the low-side power switch is turned on.
7.4.2 Continuous Current Mode (CCM) Operation
As a synchronous buck converter, the device normally works in CCM under all load conditions.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS50601A-SP device is a highly-integrated synchronous step-down DC-DC converter. The device is used
to convert a higher DC-DC input voltage to a lower DC output voltage with a maximum output current of 6 A.
The TPS50601A-SP user's guide is available on the TI website, SLVUB65. The guide highlights standard EVM
test results, schematic, and BOM for reference.
8.2 Typical Application
VIN
VOUT
PVIN
PWRGD
VIN
L
PH
COUT
CIN
RTOP
R1
VSENSE
EN
R2
REFCAP
SS/TR
RT
CSS
RT
470 nF
PGND
GND
COMP
C2
RBOTTOM
TPS50601A-SP
THERMAL PAD
R3
C1
Copyright © 2017, Texas Instruments Incorporated
Figure 23. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
This example highlights a design using the TPS50601A-SP based on its evaluation module. For more details,
please refer to the EVM user's guide, SLVUB65. A few parameters must be known in order to start the design
process. These parameters are typically determined at the system level. For this example, we start with the
following known parameters:
Table 4. Design Parameters
DESIGN PARAMETER
Output voltage
EXAMPLE VALUE
2.5 V
Maximum output current
Transient response 1-A load step
Input voltage
6A
ΔVOUT = 5%
5-V nominal, 4.5 V to 7 V
Output voltage ripple
Start input voltage (rising VIN)
Stop input voltage (falling VIN)
Switching frequency
20 mVp-p
4.5 V
4.3 V
100 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Operating Frequency
The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and
thermal performance. In this design, a switching frequency of 100 kHz is selected. Based on Figure 18, the RT
value is set to a standard value of 487 kΩ.
8.2.2.2 Output Inductor Selection
To calculate the value of the output inductor, use Equation 13. KL is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current, IO. The inductor ripple current is filtered by the
output capacitor therefore, choosing high inductor ripple currents impact the selection of the output capacitor
since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer depending on specific system needs. Typical
values for KL range from 0.1 to 0.5. For low output currents, the value of KL could be increased to reduce the
value of the output inductor.
L=
VINMAX F VOUT
VOUT
×
IO × K L
VINMAX × fSW
(13)
For this design example, use KL = 0.45 and the inductor value is calculated to be 4.7 µH for nominal VIN = 5 V.
8.2.2.3 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The output capacitor must be sized to supply the extra current to the load until the control
loop responds to the load change. Equation 14 shows the minimum output capacitance, from the electrical point
of view, necessary to accomplish this.
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COUT >
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2 × IO
fSW × ¿VOUT
(14)
Where ΔIO is the change in output current, fSW is the regulator switching frequency and ΔVOUT is the allowable
change in the output voltage. For this example, the transient load response is specified as a 5% change in VOUT
for a load step of 1 A. For this example, ΔIO = 1 A and ΔVOUT = 0.05 × 2.5 = 0.125 V. Using these numbers
gives a minimum capacitance of 160 μF. This value does not take the ESR of the output capacitor into account in
the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
However, for space applications and large capacitance values, tantalum capacitors are typically used which have
a certain ESR value to take into consideration.
Equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, VOUTripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 20 mV. Under this requirement,
Equation 15 yields 168.75 µF.
COUT >
Iripple
1
×
8 × fSW VOUTripple
(15)
Equation 16 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 16 indicates the ESR should be less than 7.41 mΩ.
R ESR <
VOUTripple
Iripple
(16)
For this specific design, taking into consideration the stringent requirements for space applications, an output
capacitor of 330 µF with ESR = 6 mΩ has been selected.
8.2.2.4 Slow Start Capacitor Selection
The slow start capacitor CSS, determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS50601A-SP reach the current limit or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start
capacitor value can be calculated using Equation 5. The example circuit has the soft start time set to an arbitrary
value of about 4 ms which requires a 10-nF capacitor. In TPS50601A-SP, ISS is 2-µA typical, and VREF is 0.804
V.
8.2.2.5 Undervoltage Lockout (UVLO) Set Point
The UVLO can be adjusted using the external voltage divider network formed by R1 and R2. R1 is connected
between VIN and the EN pin of the TPS50601A-SP and R2 is connected between EN and GND. The UVLO has
two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when
the input voltage is falling. For the example design, the supply should turn on and start switching once the input
voltage increases above selected voltage (UVLO start or enable). After the regulator starts switching, it should
continue to do so until the input voltage falls below (UVLO stop or disable) voltage. Equation 2 and Equation 3
can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified in
Table 4, the nearest standard resistor value for R1 is 10 kΩ and for R2 is 3.4 kΩ.
8.2.2.6 Output Voltage Feedback Resistor Selection
The resistor divider network RTOP and RBOTTOM is used to set the output voltage. For the example design, 10 kΩ
was selected for RTOP. Using Equation 1, RBOTTOM is calculated as 4.77 kΩ. The nearest standard 1% resistor is
4.7 kΩ.
8.2.2.7 Compensation Component Selection
There are several industry techniques used to compensate DC-DC regulators. For this design, type 2B
compensation is used as shown in Small Signal Model for Frequency Compensation.
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First, the modulator pole, fpmod, and the RESR zero, fzmod must be calculated using Equation 17 and Equation 18.
Use Equation 19 and Equation 20 to estimate a starting point for the closed loop crossover frequency fco, then
the required compensation components may be derived. For this design example, fpmod is 1.16 kHz and fzmod is
80.38 kHz. Equation 19 is the geometric mean of the modulator pole and the ESR zero and Equation 20 is the
geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of
these two values as the intended crossover frequency fco. In this case Equation 19 yields 9.65 kHz and
Equation 20 yields 7.61 kHz. A frequency of 7.6 kHz is chosen as the intended crossover frequency.
IOUT
tN × VOUT × COUT
1
=
tN × R ESR × COUT
fpmod =
fzmod
(17)
(18)
fco = §fpmod × fzmod
(19)
fco = ¨fpmod ×
(20)
fSW
2
Now the compensation components can be calculated using Equation 10 and Equation 11. The standard values
for R3 and C1 are 1.6 kΩ and 82 nF, respectively.
26
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8.2.3 Parallel Operation
The TPS50601A-SP can be configured in master-slave mode to provide 12-A output current as shown in
Figure 24.
PVIN
VIN
VIN
Cin
EN
PH
Co
PWRGD
SYNC
SS/TR
COMP
C2
Css
R1
SYNC
SS
R3
C1
VOUT
2.5 V, 12 A
Lo
EN
VSENSE
VSNS
R2
REFCAP
RT/CLK GND
COMP
Exposed
Thermal
Pad
TPS50601A-SP
(Master)
PVIN
VIN
VIN
Cin
EN
SYNC
SS
COMP
Rt
EN
Lo
PH
PWRGD
SYNC
VSENSE
SS/TR
REFCAP
RT/CLK GND
COMP
Exposed
Thermal
Pad
Co
VSNS
TPS50601A-SP
(Slave)
Copyright © 2017, Texas Instruments Incorporated
Figure 24. Parallel Configuration Showing Master and Slave
The design procedure to configure the master-slave operation using the internal oscillator is as follows:
• The RT pin of the master device must be left floating. This achieves 2 purposes, to set the frequency to 500
kHz (typical) using the internal oscillator and to configure the SYNC pin of the master device as an output pin
with a 500-kHz clock, 180° in phase respect to the internal oscillator of the master device. For more details,
see Adjustable Switching Frequency and Synchronization (SYNC) section.
• The RT pin on slave device should be connected to a resistor such that the frequency of the slave device is
within 5% of the master's frequency, 500 kHz in this case. See Figure 18 for reference.
• SYNC pin of the master device must be connected to the SYNC pin of the slave device.
• Only a single feedback network is needed connected to the VSENSE pin of the master device. Therefore,
both VSENSE pins must be connected.
• Only a single compensation network is needed connected to the COMP pin of the master device. Therefore
both COMP pins must be connected.
• Only a single soft start capacitor is needed connected to the SS pin of the master device. Therefore both SS
pins must be connected.
• Only a single enable signal (or resistor divider) is needed connected to the EN pin of the master device.
Therefore, both EN pins must be connected.
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•
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Since the master device controls the compensation, soft start and enable networks, the factor of 2 must be
taken into account when calculating the components associated with these pins.
The master-slave mode can also be implemented using an external clock. In such case, a different frequency
other than 500 kHz can be used. When using an external clock, only the RT and SYNC pins configuration varies
as follows:
• RT pins of both master and slave device must be connected to a resistor matching the frequency of the
external clock being used. See Figure 18 for reference.
• The external clock is connected to the SYNC pin of the master device. A 10-kΩ resistor to GND should be
connected to the SYNC pin as well.
• An inverted clock (180° in phase respect to the master device) must be connected to the SYNC pin of the
slave device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well.
8.2.4 Application Curve
The evaluation module for the TPS50601A-SP was used to capture a load step response of the device. The
testing conditions were:
• VIN = PVIN = 5 V
• VOUT = 2.5 V
• Load step = 0 A to 5 A
• Switching frequency = 100 kHz
Figure 25. 5-A Step Response for 100-kHz Switching Operation
9 Power Supply Recommendations
The TPS50601A-SP is designed to operate from an input voltage supply range between 3 V and 7 V. This supply
voltage must be well regulated and proper local bypass capacitors should be used for proper electrical
performance from PVIN to GND and from VIN to GND. Due to stringent requirements for space applications,
typically additional input bypass capacitors are used. The TPS50601A-SP Evaluation Module uses 6, 22-µF
ceramic capacitors from PVIN to GND and a 4.7 µF and a 0.1 µF from VIN to GND.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. Standard good practices should be applied. Some basic
guidelines follow:
• The top layer contains the main power traces for PVIN, VIN, VOUT, and PHASE. Also on the top layer are
connections for the remaining pins of the TPS50601A-SP and a large top side area filled with ground.
• The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor and the output filter capacitor.
• Thermal pad can be electrically floating or connected externally. If electrically connected externally then it
must be connected to GND. Customer should evaluate their system performance when thermal pad is
electrically isolated and thermally conductive.
• Preferred approach is that GND pin should be tied directly to the power pad under the IC and the PGND.
• The PVIN and VIN pins should be bypassed to ground with ceramic capacitors placed as close as possible to
the pins.
• Since the PH connection is the switching node, the output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• The RT, REFCAP and COMP pins are sensitive to noise so the respective components should be located as
close as possible to the IC and routed with minimal lengths of trace.
• The feedback voltage signal VSENSE should be routed away from the switching node.
10.2 Layout Example
As close to the
device as
possible
GND
1
20
PWRGD
EN
2
19
SS/TR
RT
3
18
COMP
SYNC
4
17
VSENSE
16
REFCAP
Thermal Pad
(Bottom Side)
VIN
5
PVIN
6
15
PH
PVIN
7
14
PH
PGND
8
13
PH
PGND
9
12
PH
PGND
10
11
PH
Trace away from
switching node
VOUT
L
COUT
RTOP
Close to device
and loop as
small as possible
RBOTTOM
Figure 26. PCB Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TPS50601ASPEVM 6-A Regulator Evaluation Module
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-1022102VSC
ACTIVE
CFP
HKH
20
1
TBD
AU
N / A for Pkg Type
-55 to 125
5962-1022102VS
C
TPS50601AMHKHV
5962R1022102V9A
ACTIVE
XCEPT
KGD
0
25
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962R1022102VSC
ACTIVE
CFP
HKH
20
1
TBD
AU
N / A for Pkg Type
-55 to 125
5962R1022102VS
C
TPS50601AMHKHV
TPS50601AHKH/EM
ACTIVE
CFP
HKH
20
1
TBD
AU
N / A for Pkg Type
25 to 25
TPS50601AHKH/EM
EVAL ONLY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Feb-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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