Texas Instruments | UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI | Datasheet | Texas Instruments UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI Datasheet

Texas Instruments UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver for SiC/IGBT with Active Protection and High-CMTI Datasheet
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UCC21736-Q1
SLUSDM7 – OCTOBER 2019
UCC21736-Q1 10-A Source and Sink Reinforced Isolated Single Channel Gate Driver
for SiC/IGBT with Active Protection and High-CMTI
•
•
•
•
•
•
•
•
5.7-kVRMS single channel isolated gate driver
AEC-Q100 qualified for automotive applications
SiC MOSFETs and IGBTs up to 2121 Vpk
33-V maximum output drive voltage (VDD-VEE)
±10-A drive strength and split output
150-V/ns minimum CMTI
200-ns response time fast overcurrent protection
External active miller clamp
900-mA soft turn-off when fault happens
ASC input on isolated side to turn on power switch
during system fault
Alarm FLT on over current and reset from
RST/EN
Fast enable/disable response on RST/EN
Reject <40-ns noise transient and pulse on input
pins
12V VDD UVLO and -3V VEE UVLO with power
good on RDY
Inputs/outputs with over/under-shoot transient
voltage Immunity up to 5 V
130-ns (maximum) propagation delay and 30-ns
(maximum) pulse/part skew
SOIC-16 DW package with creepage and
clearance distance > 8 mm
Operating junction temperature –40°C to 150°C
2 Applications
•
•
•
Traction inverter for EVs
On-board charger and charging pile
DC-to-DC converter for HEV/EVs
3 Description
The UCC21736-Q1 is a galvanic isolated single
channel gate driver designed for SiC MOSFETs and
IGBTs up to 2121-V DC operating voltage with
advanced protection features, best-in-class dynamic
performance and robustness. UCC21736-Q1 has up
to ±10-A peak source and sink current.
The UCC21736-Q1 includes the state-of-art
protection features, such as fast overcurrent and
short circuit detection, shunt current sensing support,
fault reporting, active miller clamp, input and output
side power supply UVLO to optimize SiC and IGBT
switching behavior and robustness. The ASC feature
can be utilized to force ON power switch during
system failure events, further increasing the drivers'
versatility and simplifying the system design effort,
size and cost.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC21736-Q1
DW SOIC-16
10.3 mm × 7.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Device Pin Configuration
VCC 15
MOD
DEMOD
5
VDD
3
COM
8
VEE
7
CLMPE
4
OUTH
6
OUTL
VCC
Supply
GND
VDD
Supply
9
IN+ 10
PWM
Inputs
INÅ 11
RDY 12
FLT 13
Primary
Logic
Second ary Logic
Output
Stage
t
ON/OFF
Control
RST/EN 14
OCP
2
OC
APWM 16
ASC
Control
1
ASC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
•
•
•
•
•
•
•
•
•
•
1
The input side is isolated from the output side with
SiO2 capacitive isolation technology, supporting up to
1.5-kVRMS working voltage, 12.8-kVPK surge immunity
with longer than 40 years Isolation barrier life, as well
as providing low part-to-part skew, >150V/ns
common mode noise immunity (CMTI).
ISOLATION BARRIER
1 Features
UCC21736-Q1
SLUSDM7 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
ADVANCE INFORMATION
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Power Ratings........................................................... 6
Electrical Characteristics........................................... 7
Switching Characteristics .......................................... 9
Insulation Specifications.......................................... 10
Safety-Related Certifications................................... 10
Safety Limiting Values .......................................... 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 16
7.1
7.2
7.3
7.4
Propagation Delay...................................................
Input Deglitch Filter .................................................
Active Miller Clamp .................................................
Under Voltage Lockout (UVLO) ..............................
16
18
19
20
7.5 OC (Over Current) Protection ................................. 23
7.6 ASC Protection........................................................ 23
8
Detailed Description ............................................ 27
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
27
28
28
34
Applications and Implementation ...................... 35
9.1 Application Information............................................ 35
9.2 Typical Application .................................................. 35
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 48
12 Device and Documentation Support ................. 49
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
49
49
13 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2019
*
Advance Information release
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5 Pin Configuration and Functions
UCC21736-Q1
DW SOIC (16)
Top View
1
16
APWM
OC
2
15
VCC
COM
3
14
RST/EN
OUTH
4
13
FLT
VDD
5
12
RDY
OUTL
6
11
INÅ
CLMPE
7
10
IN+
VEE
8
9
GND
ADVANCE INFORMATION
ISOLATION BARRIER
ASC
Not to scale
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Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
ADVANCE INFORMATION
ASC
1
I
Active high to enable active short circuit function to force output high during system failure events
OC
2
I
Over current detection pin, support lower threshold for SenseFET, DESAT, and Shunt resistor sensing
COM
3
P
Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
OUTH
4
O
Gate driver output pull up
VDD
5
P
Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate
driver source peak current capability
OUTL
6
O
Gate driver output pull down
CLMPE
7
O
External Active miller clamp, connecting this pin to the gate of the external miller clamp MOSFET
VEE
8
P
Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate
driver sink peak current capability
GND
9
P
Input power supply and logic ground reference
IN+
10
I
Non-inverting gate driver control input
IN–
11
I
Inverting gate driver control input
RDY
12
O
Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other
RDY signals
FLT
13
O
Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be
paralleled with other faults
I
The RST/EN serves two purposes:
1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to
low;
2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A
reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The
FET is turned off by a general turn-off, if terminal EN is set to low.
RST/EN
14
VCC
15
P
Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND
APWM
16
O
Isolated PWM output monitoring ASC pin status
(1)
4
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
PARAMETER
MIN
MAX
UNIT
–0.3
6
V
–0.3
36
V
–17.5
0.3
V
36
V
VCC
VCC – GND
VDD
VDD – COM
VEE
VEE – COM
VMAX
VDD – VEE
–0.3
IN+, IN–, RST/EN
ASC
Reference to COM
OC
Reference to COM
OUTH, OUTL
CLMPE
DC
GND–0.3
VCC
V
Transient, less than 100 ns (2)
GND–5.0
VCC+5.0
V
–0.3
6
V
-0.3
6
DC
VEE–0.3
VDD
V
Transient, less than 100 ns (2)
VEE–5.0
VDD+5.0
V
–0.3
5
V
GND–0.3
Reference to VEE
RDY, FLT
VCC
V
IFLT, IRDY
FLT, and RDY pin input current
20
mA
IAPWM
APWM pin output current
20
mA
TJ
Junction temperature range
–40
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
ADVANCE INFORMATION
over operating free-air temperature range (unless otherwise noted) (1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Values are verified by characterization on bench.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
PARAMETER
MIN
MAX
VCC
VCC–GND
3.0
5.5
UNIT
V
VDD
VDD–COM
13
33
V
VMAX
VDD–VEE
V
–
33
High level input voltage
0.7×VCC
VCC
Low level input voltage
0
0.3×VCC
0
5
V
IN+, IN–, RST/EN
Reference to GND
V
ASC
Reference to COM
tRST/EN
Minimum pulse width that reset the fault
TA
Ambient Temperature
–40
125
°C
TJ
Junction temperature
–40
150
°C
1000
ns
6.4 Thermal Information
UCC21736-Q1
THERMAL METRIC
(1)
DW (SOIC)
UNIT
16
RθJA
(1)
Junction-to-ambient thermal resistance
68.3
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)
UCC21736-Q1
THERMAL METRIC (1)
DW (SOIC)
UNIT
16
RθJC(top)
Junction-to-case (top) thermal resistance
27.5
°C/W
RθJB
Junction-to-board thermal resistance
32.9
°C/W
ψJT
Junction-to-top characterization parameter
14.1
°C/W
ψJB
Junction-to-board characterization parameter
32.3
°C/W
6.5 Power Ratings
PARAMETER
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation by
transmitter side
PD2
Maximum power dissipation by
receiver side
TEST CONDITIONS
VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,
50% Duty Cycle for 10nF load, Ta=25oC
Value
UNIT
985
mW
20
mW
965
mW
ADVANCE INFORMATION
6
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6.6 Electrical Characteristics
VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,
CL=100pF, –40°C<TJ<150°C (unless otherwise noted) (1) (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.55
2.7
2.85
2.35
2.5
2.65
UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON
VVCC_OFF
VCC–GND
VVCC_HYS
V
0.2
tVCCFIL
VCC UVLO Deglitch time
tVCC+ to OUT
VCC UVLO on delay to output high
tVCC– to OUT
VCC UVLO off delay to output low
tVCC+ to RDY
VCC UVLO on delay to RDY high
tVCC– to RDY
VCC UVLO off delay to RDY low
10
37.8
IN+ = VCC, IN– = GND
10
µs
37.8
RST/EN = VCC
10
VDD UVLO THRESHOLD AND DELAY
VVDD_ON
VDD–COM
11.2
12.0
12.8
9.9
10.7
11.5
VVDD_HYS
V
0.8
tVDDFIL
VDD UVLO Deglitch time
tVDD+ to OUT
VDD UVLO on delay to output high
tVDD– to OUT
VDD UVLO off delay to output low
tVDD+ to RDY
VDD UVLO on delay to RDY high
tVDD– to RDY
VDD UVLO off delay to RDY low
5
ADVANCE INFORMATION
VVDD_OFF
5
IN+ = VCC, IN– = GND
5
µs
10
RST/EN = FLT=High
10
VEE UVLO THRESHOLD AND DELAY
VVEE_ON
VVEE_OFF
VEE–COM
–3.3
–3.0
–2.7
–2.9
–2.6
–2.3
VVEE_HYS
V
0.4
tVEEFIL
VEE UVLO Deglitch time
tVEE+ to OUT
VEE UVLO on delay to output high
tVEE– to OUT
VEE UVLO off delay to output low
tVEE+ to RDY
VEE UVLO on delay to RDY high
tVEE– to RDY
VEE UVLO off delay to RDY low
5
5
IN+ = VCC, IN– = GND
5
µs
10
RST/EN = FLT=High
10
VCC, VDD QUIESCENT CURRENT
IVCCQ
VCC quiescent current
IVDDQ
VDD quiescent current
OUT(H) = High, fS = 0Hz, AIN=2V
3
OUT(L) = Low, fS = 0Hz, AIN=2V
2
OUT(H) = High, fS = 0Hz, AIN=2V
mA
4
OUT(L) = Low, fS = 0Hz, AIN=2V
mA
3.7
LOGIC INPUTS — IN+, IN–, and RST/EN
VINH
Input high threshold
VCC=3.3V
VINL
Input low threshold
VCC=3.3V
1.85
VINHYS
Input threshold hysteresis
VCC=3.3V
0.33
V
IIH
Input high level input leakage current
VIN = VCC
90
µA
IIL
Input low level input leakage
VIN = GND
–90
µA
RIND
Input pins pull down resistance
see Detailed Description for more
information
55
RINU
Input pins pull up resistance
see Detailed Description for more
information
55
TINFIL
IN+, IN– and RST/EN deglitch (ON and
OFF) filter time
fS = 50kHz
TRSTFIL
Deglitch filter time to reset /FLT
0.99
2.31
1.52
V
V
kΩ
28
40
500
650
ns
800
ns
GATE DRIVER STAGE
IOUT, IOUTH
Peak source current
IOUT, IOUTL
Peak sink current
ROUTH
Output pull-up resistance
(1)
(2)
CL=0.18µF, fS=1kHz
IOUT = –0.1A
–10
A
10
A
2.5
Ω
Current are positive into and negative out of the specified terminal.
All voltages are referenced to COM unless otherwise notified.
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Electrical Characteristics (continued)
VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,
CL=100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2).
PARAMETER
TEST CONDITIONS
ROUTL
Output pull-down resistance
IOUT = 0.1A
VOUTH
High level output voltage
IOUT = –0.2A, VDD=15V
VOUTL
Low level output voltage
IOUT = 0.2A
MIN
TYP
MAX
0.3
UNIT
Ω
14.5
V
60
mV
ACTIVE PULLDOWN
VOUTPD
IOUTL or IOUT = 0.1×IOUT(L)(tpy),
VDD=OPEN, VEE=COM
Output active pull down on OUT, OUTL
2.5
V
2.5
V
EXTERNAL MILLER CLAMP
VCLMPTH
Miller clamp threshold voltage
Reference to VEE
1.5
2.0
VCLMPE
Output high voltage
Reference to VEE
4.4
4.8
V
ICLMPEH
Peak source current
0.12
0.25
A
ICLMPEL
Peak sink current
0.12
0.25
tCLMPER
Rising time
tDCLMPE
Miller clamp ON delay time
CCLMPE = 10nF
20
CCLMPE = 330pF
A
40
ns
40
ns
SHORT CIRCUIT CLAMPING
ADVANCE INFORMATION
VCLP-OUT(H)
VOUT–VDD, VOUTH–VDD
OUT = Low, IOUT(H) = 500mA, tCLP=10us
0.9
V
VCLP-OUT(L)
VOUT–VDD, VOUTL–VDD
OUT = High, IOUT(L) = 500mA, tCLP=10us
1.8
V
VCLP-CLMPI
VCLMPI–VDD
OUT = High, ICLMPI = -20mA, tCLP=10us
1.0
V
OC PROTECTION
IDCHG
OC pull down current when
VOCTH
Detection Threshold
VOC = 1V
VOCL
Voltage when OUT(L) = LOW, Reference
to COM
tOCFIL
tOCOFF
tOCFLT
40
0.63
IOC = 5mA
0.7
mA
0.77
V
0.13
V
OC fault deglitch filter
150
ns
OC propagation delay to OUT(L) 90%
200
ns
OC to FLT low delay
600
ns
900
mA
V
INTERNAL SOFT TURN-OFF
ISTO
Soft turn-off current on fault conditions
ASC - Active Short Circuit
VASCL
ASC Input low threshold
1.7
VASCH
ASC Input high threshold
3.2
V
tASC_r
ASC to output rising edge delay
660
ns
tASC_f
ASC to output falling edge delay
227
ns
ISOLATED ASC MONITOR (APWM)
fAPWM
DAPWM
APWM output frequency
APWM Dutycycle —
360
400
440
VASC = 0.5V
7
10
13
VASC = 2.5V
47
50
53
VASC = 4.5V
87
90
93
kHz
%
FLT AND RDY REPORTING
tRDYHLD
VDD UVLO RDY low minimum holding
time
tFLTMUTE
Output mute time on fault
Reset fault through RST/EN
RODON
Open drain output on resistance
IODON = 5mA
VODL
Open drain low output voltage
IODON = 5mA
0.55
0.55
1
ms
1
ms
30
Ω
0.3
V
COMMON MODE TRANSIENT IMMUNITY
CMTI
8
Common-mode transient immunity
150
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6.7 Switching Characteristics
VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, CL=100pF,
–40°C<TJ<150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPDHL
Propagation delay time – High to Low
90
tPDLH
Propagation delay time – Low to High
90
PWD
Pulse width distortion |tPDHL – tPDLH|
tsk-pp
Part to Part skew
Rising or Falling Propagation Delay
30
tr
Driver output rise time
CL=10nF
28
tf
Driver output fall time
CL=10nF
24
fMAX
Maximum switching frequency
25
ns
MHz
ADVANCE INFORMATION
1
UNIT
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6.8 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (Internal clearance) of the
double insulation (2 × 0.0085 mm)
> 17
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664–1
CLR
Overvoltage Category per IEC 60664–1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage AC voltage (bipolar)
VIOWM
Maximum isolation working voltage
ADVANCE INFORMATION
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
Insulation resistance, input to output (5)
RIO
2121
VPK
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
1500
VRMS
DC voltage
2121
VDC
VTEST=VIOTM, t = 60 s (qualification test)
8000
VTEST=1.2 x VIOTM, t = 1 s (100% production test)
9600
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Method a: After I/O safety test subgroup 2/3, Vini =
VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK,
tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394
VPK, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 sin (2πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
≥ 1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
≥ 1011
VIO = 500 V at TS = 150°C
≥ 109
Pollution degree
2
Climatic category
40/125/21
VPK
VPK
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
5700
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
6.9 Safety-Related Certifications
VDE
UL
Plan to certify according to DIN V VDE V 0884-11 (VDE V 088411):2017-01;
DIN EN 61010-1 (VDE 0411-1):2011-07
10
Plan to certify according to UL 1577 Component Recognition
Program
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Safety-Related Certifications (continued)
VDE
UL
Reinforced insulation
Maximum transient isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage, 2121 VPK;
Maximum surge isolation voltage, 8000 VPK
Single protection, 5700 VRMS
Certification Planned
Certification Planned
6.10 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
TBD
RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
TBD
RθJA =68.3°C/W, VDD = 20V, VEE=-5V, TJ = 150°C, TA
= 25°C
TBD
mW
150
°C
mA
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
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ADVANCE INFORMATION
PARAMETER
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6.11 Insulation Characteristics Curves
1.E+12
1.E+11
1.E+10
54 Yrs
1.E+09
Time to Fail (sec)
1.E+08
TDDB Line (< 1 ppm Fail Rate)
1.E+07
1.E+06
VDE Safety Margin Zone
ADVANCE INFORMATION
1.E+05
1.E+04
1.E+03
1.E+02
1800VRMS
1.E+01
200
1200
2200
3200
4200
5200
6200
Applied Voltage (VRMS)
Figure 1. Reinforced Isolation Capacitor Life Time Projection
2000
100
80
Safety Limiting Power (mW)
Safety Limitting Current (mA)
VDD=15V; VEE=-5V
VDD=20V; VEE=-5V
60
40
20
0
1000
500
0
0
25
50
75
100
125
Ambient Temperature (oC)
150
0
Safe
Figure 2. Thermal Derating Curve for Limiting Current per
VDE
12
1500
25
50
75
100
125
Ambient Temperature (oC)
150
Safe
Figure 3. Thermal Derating Curve for Limiting Power per
VDE
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6.12 Typical Characteristics
22
20
18
16
14
12
10
8
6
4
-60
-40
-20
0
20 40 60 80
Temperature (qC)
18
16
14
12
10
8
6
4
-60
100 120 140 160
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D017
Figure 5. Output Low Driver Current vs. Temperature
6
4
VCC = 3.3V
VCC = 5V
5.5
VCC = 3.3V
VCC = 5V
3.5
5
IVCCQ (mA)
3
4.5
2.5
4
2
3.5
1.5
3
-60
-40
-20
0
IN+ = High
20 40 60 80
Temperature (qC)
1
-60
100 120 140 160
-40
-20
0
D015
IN- = Low
IN+ = Low
Figure 6. IVCCQ Supply Current vs. Temperature
20 40 60 80
Temperature (qC)
100 120 140 160
D014
IN- = Low
Figure 7. IVCCQ Supply Current vs. Temperature
5
6
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
4.5
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
5.5
5
IVDDQ (mA)
4
IVCCQ (mA)
-40
D016
Figure 4. Output High Drive Current vs. Temperature
IVCCQ (mA)
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
20
ADVANCE INFORMATION
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
Peak Output Current Low, I OUTL (A)
Peak Output Current High, I OUTH (A)
22
3.5
4.5
3
4
2.5
3.5
2
30
70
110
150
190
230
Frequency (kHz)
270
3
-60
310
-40
-20
D018
Figure 8. IVCCQ Supply Current vs. Input Frequency
IN+ = High
0
20 40 60 80
Temperature (qC)
100 120 140 160
D012
IN- = Low
Figure 9. IVDDQ Supply Current vs. Temperature
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Typical Characteristics (continued)
6
10
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
5.5
VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V
9
8
IVDDQ (mA)
IVDDQ (mA)
5
4.5
4
7
6
5
4
3.5
3
3
-60
-40
-20
0
IN+ = Low
20 40 60 80
Temperature (qC)
2
30
100 120 140 160
270
310
D019
ADVANCE INFORMATION
VDD UVLO Threshold, VDD_ON (V)
14
3.5
3
2.5
2
1.5
-60
-40
-20
0
20 40 60 80
Temperature (qC)
13.5
13
12.5
12
11.5
11
10.5
10
-60
100 120 140 160
-40
-20
0
D001
Figure 12. VCC UVLO vs. Temperature
20 40 60 80
Temperature (qC)
100 120 140 160
D002
Figure 13. VDD UVLO vs. Temperature
100
100
Propagation Delay High-Low, t PDHL (ns)
Propagation Delay Low-High, t PDLH (ns)
150
190
230
Frequency (kHz)
Figure 11. IVDDQ Supply Current vs. Input Frequency
4
90
80
70
60
50
-60
-40
-20
VCC = 3.3V
RON = 0Ω
0
20 40 60 80
Temperature (qC)
VDD=18V
ROFF = 0Ω
100 120 140 160
90
80
70
60
50
-60
-40
-20
D021
CL = 100pF
Figure 14. Propagation Delay tPDLH vs. Temperature
14
110
IN- = Low
Figure 10. IVDDQ Supply Current vs. Temperature
VCC UVLO Threshold, V CC_ON (V)
70
D013
VCC = 3.3V
RON = 0Ω
0
20 40 60 80
Temperature (qC)
VDD=18V
ROFF = 0Ω
100 120 140 160
D022
CL = 100pF
Figure 15. Propagation Delay tPDHL vs. Temperature
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60
60
50
50
Fall Time, t f (ns)
40
30
20
40
30
20
10
-60
-40
-20
0
20 40 60 80
Temperature (qC)
VCC = 3.3V
RON = 0Ω
10
-60
100 120 140 160
-40
VDD=18V
ROFF = 0Ω
CL = 10nF
0
20 40 60 80
Temperature (qC)
VCC = 3.3V
RON = 0Ω
Figure 16. tr Rise Time vs. Temperature
100 120 140 160
D024
VDD=18V
ROFF = 0Ω
CL = 10nF
Figure 17. tf Fall Time vs. Temperature
2.5
3
2.25
VCLP-OUT(H) (V)
2.75
2.5
VOUTPD (V)
-20
D023
2.25
2
2
1.75
1.5
1.25
1
-60
1.75
1.5
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D025
Figure 19. VCLP-OUT(H) Short Circuit Clamping Voltage vs. Temperature
D008
2
1.75
VCLP-OUT(L) (V)
1.5
1.25
1
0.75
0.5
0.25
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D026
Figure 20. VCLP-OUT(L) Short Circuit Clamping Voltage vs. Temperature
Miller Clamp Threshold Voltage, VCLMPTH (V)
Figure 18. VOUTPD Output Active Pulldown Voltage vs.
Temperature
3
2.75
2.5
2.25
2
1.75
1.5
50
70
90
110
Temperature (qC)
130
150 160
D009
Figure 21. VCLMPTH Miller Clamp Threshold Voltage vs.
Temperature
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Rise Time, t r (ns)
Typical Characteristics (continued)
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Typical Characteristics (continued)
Miller Clamp ON Delay Time, t DCLMPE (ns)
Peak Clamp Sink Current, I CLMPEL (mA)
400
350
300
250
200
150
100
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
70
60
50
40
30
-60
-40
D010
Figure 22. ICLMPEL Miller Clamp Sink Current vs.
Temperature
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D011
Figure 23. tDCLMPE Miller Clamp ON Delay Time vs.
Temperature
ADVANCE INFORMATION
1
VOCTH (V)
0.8
0.6
0.4
0.2
-60
-40
-20
0
20 40 60 80
Temperature (qC)
100 120 140 160
D003
Figure 24. VOCTH OC Detection Threshold vs. Temperature
7 Parameter Measurement Information
7.1 Propagation Delay
7.1.1 Regular Turn-OFF
Figure 25 shows the propagation delay measurement for non-inverting configurations. Figure 26 shows the
propagation delay measurement with the inverting configurations.
16
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Propagation Delay (continued)
50%
50%
tPDLH
tPDHL
IN+
,1Å
90%
ADVANCE INFORMATION
10%
OUT
Figure 25. Non-inverting Logic Propagation Delay Measurement
IN+
,1Å
50%
50%
tPDLH
tPDHL
90%
OUT
10%
Figure 26. Inverting Logic Propagation Delay Measurement
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7.2 Input Deglitch Filter
In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input
pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is no
faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the
input deglitch filter width, TINFIL, there will be no responses on OUT drive signal. Figure 27 and Figure 28 shows
the IN+ pin ON and OFF pulse deglitch filter effect. Figure 29 and Figure 30 shows the IN– pin ON and OFF
pulse deglitch filter effect.
IN+
tPWM < TINFIL
tPWM < TINFIL
IN+
,1Å
,1Å
ADVANCE INFORMATION
OUT
OUT
Figure 27. IN+ ON Deglitch Filter
Figure 28. IN+ OFF Deglitch Filter
IN+
IN+
,1Å
tPWM < TINFIL
tPWM < TINFIL
,1Å
OUT
OUT
Figure 29. IN– ON Deglitch Filter
18
Figure 30. IN– OFF Deglitch Filter
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7.3 Active Miller Clamp
7.3.1 External Active Miller Clamp
For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active
miller clamp can help add an additional low impedance path to bypass the miller current and prevent the high
dV/dt introduced unintentional turn-on through the miller capacitance. Different from the internal active miller
clamp, external active miller clamp function is used for applications where the gate driver may not be close to the
power device or power module due to system layout considerations. External active miller clamp function provide
a 5V gate drive signal to turn-on the external miller clamp FET when the gate driver voltage is less than miller
clamp threshold, VCLMPTH. Figure 31 shows the timing diagram for external active miller clamp function.
(µIN+¶ Å µINŶ)
IN
VDD
tDCLMPE
OUT
VCLMPTH
ADVANCE INFORMATION
COM
VEE
HIGH
90%
tCLMPER
CLMPE
LOW
10%
Figure 31. Timing Diagram for External Active Miller Clamp Function
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7.4 Under Voltage Lockout (UVLO)
UVLO is one of the key protection features designed to protect the system in case of bias supply failures on
VCC — primary side power supply, and VDD — secondary side power supply.
7.4.1 VCC UVLO
The VCC UVLO protection details are discussed in this section. Figure 32 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(µIN+¶ Å µINŶ)
tVCCFIL
tVCCÅ to OUT
VCC
VVCC_ON
VVCC_OFF
VDD
ADVANCE INFORMATION
COM
VEE
tVCC+ to OUT
90%
VCLMPTH
OUT
10%
tVCC+ to RDY
tVCCÅ to RDY
tRDYHLD
Hi-Z
RDY
Figure 32. VCC UVLO Protection Timing Diagram
20
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Under Voltage Lockout (UVLO) (continued)
7.4.2 VDD UVLO
The VDD UVLO protection details are discussed in this section. Figure 33 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.
IN
(µIN+¶ Å µINŶ)
tVDDFIL
VDD
tVDDÅ to OUT
VVDD_ON
VVDD_OF F
COM
VEE
ADVANCE INFORMATION
VCC
tVDD+ to OUT
VCLMPTH
OUT
90%
10%
tVDD+ to RDY
tVDDÅ to RDY
RDY
tRDYHLD
Hi-Z
Figure 33. VDD UVLO Protection Timing Diagram
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Under Voltage Lockout (UVLO) (continued)
7.4.3 VEE UVLO
The VEE UVLO protection details are discussed in this section. Figure 34 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, and RDY.
IN
(µIN+¶ Å µINŶ)
tVEEÅ to OUT
VDD
tVEEFIL
COM
VVEE_OF F
VVEE_ON
VEE
VCC
ADVANCE INFORMATION
90%
tVEE+ to OUT
OUT
VCLMPTH
10%
tVEEÅ to RDY
tVEE+ to RDY
tRDYHLD
RDY
Hi-Z
Figure 34. VEE UVLO Protection Timing Diagram
22
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7.5 OC (Over Current) Protection
7.5.1 OC Protection with Soft Turn-OFF
OC Protection is used to sense the current of SiC-MOSFETs and IGBTs under over current or shoot-through
condition. Figure 35 shows the timing diagram of OC operation with soft turn-off.
IN
(µ,1+¶ Å µ,1Ŷ)
tOCFIL
VOCTH
OC
tOCOFF
ADVANCE INFORMATION
90%
GATE
VCLMPTH
tOCFLT
tFLTMUTE
Hi-Z
FLT
tRSTFIL
tRSTFIL
RST/EN
HIGH
Hi-Z
OUTH
LOW
Hi-Z
OUTL
LOW
Figure 35. OC Protection with Soft Turn-OFF
7.6 ASC Protection
When ASC pin receives a logic high signal, the output will be forced high regardless of the input side pin
conditions. The ASC function has higher priority than the input signal and VCC UVLO. The priority of VDD and
VEE UVLO, and the overcurrent fault event are higher than ASC function.
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ASC Protection (continued)
(µIN+¶ Å µINŶ)
IN
VVCC_ON
VCC
VVCC_OF F
VDD
COM
VEE
tVCC- to RDY
tVCC+ to RDY
RDY
ADVANCE INFORMATION
ASC
tASC_r
tASC_f
OUT
Figure 36. ASC Protection with VCC UVLO
24
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ASC Protection (continued)
(µIN+¶ Å µINŶ)
IN
VCC
VDD
VVDD_ON
VVDD_OF F
COM
VEE
tVDD- to RDY
tVDD+ to RDY
ADVANCE INFORMATION
RDY
ASC
tASC_r
tVDD- to OUT
tVDD+ to OUT
tASC_f
OUT
Figure 37. ASC Protection with VDD UVLO
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ASC Protection (continued)
(µIN+¶ Å µINŶ)
IN
tOCF IL
VOCT H
OC
tOCF LT
FLT
ADVANCE INFORMATION
RST/EN
ASC
tOCOFF
90%
GATE
Figure 38. ASC Protection with OC Fault
26
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8 Detailed Description
8.1 Overview
The UCC21736-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features
for SiC MOSFETs and IGBTs. The device can support up to 2121V DC operating voltage based on SiC
MOSFETs and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor
drive, on-board and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the
capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage
DSP/MCU and high voltage side.
The device includes extensive protection and monitor features to increase the reliability and robustness of the
SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with
gate voltage ≥ 15V. The active miller clamp feature prevents the false turn on causing by miller capacitance
during fast switching. External miller clamp FET can be used, providing more versatility to the system design.
The device has the state-of-art overcurrent and short circuit detection time, and fault reporting function to the low
voltage side DSP/MCU. The soft turn off is triggered when the overcurrent or short circuit fault is detected,
minimizing the short circuit energy while reducing the overshoot voltage on the switches.
The active short circuit feature can create a phase to phase short circuit for a three-phase inverter, which is
useful for the motor drive applications to protect the battary if the microcontroller loses control.
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The ±10A peak sink and source current of UCC21736-Q1 can drive the SiC MOSFET modules and IGBT
modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel
modules with external buffer stage. The input side is isolated with the output side with a reinforced isolation
barrier based on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8kVPK surge immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the
device fast and reduce the switching loss. While the 150V/ns minimum CMTI guarantees the reliability of the
system with fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime
setting, so the conduction loss can be reduced.
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8.2 Functional Block Diagram
7
CLAMPE
4
OUTH
6
OUTL
5
VDD
IN+ 10
PWM Inputs
MOD
DEMOD
INt 11
Output Stage
t
ON/OFF Control
STO
VCC
VCC 15
VCC Supply
9
UVLO
RDY 12
FLT
Fault Decode
13
ISOLATION BARRIER
ADVANCE INFORMATION
GND
UVLO
LDO[s for VEE,
COM and channel
OCP
3 COM
8
VEE
2
OC
1
ASC
Fault Encode
RST/EN 14
ASC Circuit
APWM 16
PWM Driver
DEMOD
MOD
8.3 Feature Description
8.3.1 Power Supply
The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both
unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The
negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the
other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to
its fast switching speed.
28
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Feature Description (continued)
UCC21736-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength
can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.
UCC21736-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage.
Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an
important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW
state. The split output of the driver stage is depicted in . The driver has rail-to-rail output by implementing a
hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel
MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance RNMOS is the
same as ROL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed,
during the miller plateau region of the power semiconductor turn-on transient. The ROH in represents the onresistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than
ROH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the
pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V
below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x ROL .
Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up impedance results in
strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of
the power semiconductor and reduces the turn on switching loss.
The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. The onresistance of the N-Channel MOSFET ROL can be found in the . This MOSFET can ensure the OUTL voltage be
pulled down to VEE rail. The low pull-down impedance not only results in high sink current to reduce the turn-off
time, but also helps to increase the noise immunity considering the miller effect.
VDD
Input
Signal
Anti Shootthrough
Circuitry
Isolation Barrier
ROH
RNMOS
OUTH
OUTL
ROL
Figure 39. Gate Driver Output Stage
8.3.3 VCC, VDD and VEE Undervoltage Lockout (UVLO)
UCC21736-Q1 implements the internal UVLO protection feature for both input and output power supplies VCC
and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The
output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not
only reduces the power consumption of the driver itself during low power supply voltage condition, but also
increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the
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8.3.2 Driver Stage
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Feature Description (continued)
gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD
value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the
power stage. UCC21736-Q1 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis; -3V
threshold voltage of VEE UVLO, with 400mV hysteresis. This threshold voltage is suitable for both SiC MOSFET
and IGBT.
The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity
of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak
transient current from the power supply, which can result in sudden voltage drop of the power supply. With
hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal
switching transients.
The timing diagrams of the UVLO feature of VCC, VDD and VEE are shown in Figure 32, Figure 33 and
Figure 34.The RDY pin on the input side is used to indicate the power good condition. The RDY pin is open
drain. During UVLO condition, the RDY pin is held in low status and connected to GND. Normally the pin is
pulled up externally to VCC to indicate the power good.
8.3.4 Active Pulldown
ADVANCE INFORMATION
UCC21736-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the
VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature
can prevent the output be false turned on before the device is back to control.
VDD
OUTL
Ra
Control
Circuit
VEE
COM
Figure 40. Active Pulldown
8.3.5 Short Circuit Clamping
During short circuit condition, the miller capacitance can cause a current sinking to the OUTH/OUTL pin due to
the high dV/dt and boost the OUTH/OUTL voltage. The short circuit clamping feature of UCC21736-Q1 can
clamp the OUTH/OUTL pin voltage to be slightly higher than VDD, which can protect the power semiconductors
from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by an internal diode from
the OUTH/OUTL to VDD.
30
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Feature Description (continued)
VDD
D1
D2 D3
OUTH
Control
Circuitry
OUTL
Figure 41. Short Circuit Clamping
8.3.6 External Active Miller Clamp
Active miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In
applications which the device can be in synchronous rectifier mode, the body diode conducts the current during
the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same and
the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-down
impedance of UCC21736-Q1 can provide a strong pulldown to hold the OUTL to VEE. However, external gate
resistance is usually adopted to limit the dV/dt. The miller effect during the turn on transient of the other power
semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or gateemitter voltage. If the voltage on VGS or VGE is higher than the threshold voltage of the power semiconductor, a
shoot through can happen and cause catastrophic damage. The active miller clamp feature of UCC21736-Q1
drives an external MOSFET, which connects to the device gate. The external MOSFET is triggered when the
gate voltage is lower than VCLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the false
turn on issue.
VCLMPTH
VCC
3V to 5.5V
IN+
µC
MOD
Isolation barrier
+
±
OUTH
Control
Circuitry
CLMPI
OUTL
DEMOD
INVEE
COM
VCC
Figure 42. Active Miller Clamp
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Feature Description (continued)
8.3.7 Overcurrent and Short Circuit Protection
The UCC21736-Q1 implements a fast overcurrent and short circuit protection feature to protect the SiC MOSFET
or IGBT from catastrophic breakdown during fault. The OC pin of the device has a typical 0.7V threshold with
respect to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the
output is held in low state, the OC pin is pulled down by an internal MOSFET and held in LOW state, which
prevents the overcurrent and short circuit fault from false triggering. The OC pin is in high-impedance state when
the output is in high state, which means the overcurrent and short circuit protection feature only works when the
power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the voltage of OC pin
when the power semiconductor is turned off.
The overcurrent and short circuit protection feature can also be paired with desaturation circuit and shunt
resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device.
Detailed application diagrams of desaturation circuit and shunt resistor will be given in .
• High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on shunt
resistor’s parasitic inductance and board layout parasitic, which results in false trigger of OC pin. High
precision, low ESL and small value resistor must be used in this approach.
• Shunt resistor approach is not recommended for high power applications and short circuit protection of the
low power applications.
The detailed applications of the overcurrent and short circuit feature will be discussed in the Application and
Implementation section.
OUTL
FLT
DEMOD
MOD
150ns
Deglitch Filter
ROFF
Isolation barrier
ADVANCE INFORMATION
The overcurrent and short circuit protection feature can be used to SiC MOSFET module or IGBT module with
SenseFET, traditional desaturation circuit and shunt resistor in series with the power loop for lower power
applications. For SiC MOSFET module or IGBT module with SenseFET, the SenseFET integrated in the module
can scale down the drain current or collector current. With an external high precision sense resistor, the drain
current or collector current can be accurately measured. If the voltage of the sensed resistor higher than the
overcurrent threshold VOCTH is detected, the soft turn-off is initiated. A fault will be reported to the input side FLT
pin to DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin.
The state-of-art overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC
MOSFET and IGBT.
OC
RFLT
+
+
±
CFLT
VOCTH
RS
Control
Logic
GND
COM
VEE
Figure 43. Overcurrent and Short Circuit Protection
32
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Feature Description (continued)
8.3.8 Fault (FLT, Reset and Enable (RST/EN)
The FLT pin of UCC21736-Q1 is open drain and can report a fault signal to the DSP/MCU when the overcurrent
and short circuit fault is detected through OC pin. The FLT pin is pulled down to GND, and is held in low state
unless a reset signal is received from RST/EN. The device has a fault mute time tFLTMUTE, within which the device
ignores any reset signal.
The RST/EN is pulled down internally. The device is disabled by default if the RST/EN pin is floating. The pin has
two purposes:
• Resets the overcurrent and short circuit fault signaled on FLT pin. The RST/EN pin is active low, if the pin is
set and held in low state for more than tRSTFIL, the fault signal is reset andFLT is reset back to the high
impedance status at the rising edge of RST/EN pin.
• Enable and shutdown the device. If the RST/EN pin is pulled low, the driver is disabled and shut down by the
regular turn off. The pin must be pulled up externally to enable the part, otherwise the device is disabled by
default.
When VCC loses power, or MCU is malfunctional, the motor can lose control and reversely charging the battery.
Overvoltage of the battery can cause battery break down, or even the fire hazard. In this case, the active short
circuit (ASC) function is used to protect the system by forcing the output signal high, turning on the switch and
creating an active short circuit loop between the phases to bypass the battery. The timing diagram of ASC
protection with VCC UVLO, VDD UVLO and OC fault are shown in Figure 36, Figure 37, and Figure 38.
The UCC21736-Q1 encodes the voltage signal VASC to a PWM signal, passing through the reinforced isolation
barrier, and output to APWM pin on the input side. Thus the ASC pin status can be monitored. The PWM signal
can either be transferred directly to DSP/MCU to calculate the duty cycle, or filtered by a simple RC filter as an
analog signal. The ASC input voltage varies from 0V to 5V, and the corresponding duty cycle of the APWM
output ranges from 95% to 5% with 400kHz frequency.
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8.3.9 ASC Protection and APWM Monitor
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8.4 Device Functional Modes
lists the device function.
Table 1. Function Table
Input
Output
ADVANCE INFORMATION
VCC
VDD
VEE
IN+
IN-
RST/EN
ASC
RDY
FLT
OUTH/OUTL
CLMPE
X
PU
PU
X
X
X
High
X
X
High
Low
PU
PD
PU
X
X
High
X
Low
HiZ
Low
High
PU
PU
PD
X
X
High
X
Low
HiZ
Low
High
PU
PD
X
X
X
X
Low
Low
HiZ
Low
Low
PD
PU
X
X
X
X
Low
HiZ
HiZ
Low
High
PU
PU
X
X
X
Low
Low
HiZ
HiZ
Low
High
PU
Open
X
X
X
X
Low
Low
HiZ
HiZ
HiZ
PU
PU
Open
X
X
X
Low
Low
HiZ
Low
High
PU
PU
X
Low
X
High
Low
HiZ
HiZ
Low
High
PU
PU
X
X
High
High
Low
HiZ
HiZ
Low
High
PU
PU
X
High
Low
High
Low
HiZ
HiZ
HiZ
Low
PU: Power Up (VCC ≥ 3V, VDD ≥ 12.8V; VEE ≤ -3.3V); PD: Power Down (VCC ≤ 2.2V, VDD ≤ 10.4V, VEE ≥
-2.3V); X: Irrelevant; P*: PWM Pulse; HiZ: High Impedance
34
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The UCC21736-Q1 device is very versatile because of the strong drive strength, wide range of output power
supply, high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working
voltage and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus
voltage up to 2121V. The device can be used in both low power and high power applications such as the traction
inverter in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies
and etc. The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device
directly without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which
allows the driver to have more control to the power semiconductor and saves the cost and space of the board
design. UCC21736-Q1 can also be used to drive very high power modules or paralleled modules with external
buffer stage. The input side can support power supply and microcontroller signal from 3.3V to 5V, and the device
level shifts the signal to output side through reinforced isolation barrier. The device has wide output power supply
range from 13V to 33V and support wide range of negative power supply. This allows the driver to be used in
SiC MOSFET applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor
with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the
device can be used to drive either a low-side or high-side driver.
UCC21736-Q1 device features extensive protection and monitoring features, which can monitor, report and
protect the system from various fault conditions.
• Fast detection and protection for the overcurrent and short circuit fault. The feature is preferable in a split
source SiC MOSFET module or a split emitter IGBT module. For the modules with no integrated current
mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement
short circuit protection. The semiconductor is shutdown when the fault is detected and FLTb pin is pulled
down to indicate the fault detection. The device is latched unless reset signal is received from the RST/EN
pin.
• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and
short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is
limited.
• UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to
be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is
back to normal operation mode once the power supply is out of the UVLO status. The power good status can
be monitored from the RDY pin.
• Active short circuit feature creates phase to phase short circuit in three-phase inverter to protect the battery
from overvoltage breakdown.
• The active miller clamp feature protects the power semiconductor from false turn on by driving an external
MOSFET. This feature allows the flexibility of the board layout design and the pulldown strength of miller
clamp FET.
• Enable and disable function through the RSTb/EN pin.
• Short circuit clamping.
• Active pulldown.
9.2 Typical Application
shows the typical application of a half bridge using two UCC21736-Q1 isolated gate drivers. The half bridge is a
basic element in various power electronics applications such as traction inverter in HEV/EV to convert the DC
current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion system. The
topology can also be used in motor drive applications to control the operating speed and torque of the AC
motors.
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9.1 Application Information
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Typical Application (continued)
PWM
3-Pha se
Input
µC
1
2
3
4
5
6
UCC
217 36-Q1
UCC
217 36-Q1
UCC
217 36-Q1
UCC
217 36-Q1
UCC
217 36-Q1
UCC
217 36-Q1
M
ASC
ADVANCE INFORMATION
4
5
6
FLT
Figure 44. Typical Application Schematic
9.2.1 Design Requirements
The design of the power system for end equipment should consider some design requirements to ensure the
reliable operation of UCC1736-Q1 through the load range. The design considerations include the peak source
and sink current, power dissipation, overcurrent and short circuit protection and etc.
A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show
in .
Table 2. Design Parameters
Parameter
36
Value
Input Supply Voltage
5V
IN-OUT Configuration
Non-inverting
Positive Output Voltage VDD
15V
Negative Output Voltage VEE
-5V
DC Bus Voltage
800V
Peak Drain Current
300A
Switching Frequency
50kHz
Switch Type
IGBT Module
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9.2.2 Detailed Design Procedure
9.2.2.1 Input filters for IN+, IN- and RST/EN
In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With
the strong drive strength of UCC21736-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise can not
only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal
PCB layout and coupled capacitance.
UCC21736-Q1 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can
be filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input
pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and
increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be
tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is
to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter
resistors and capacitors, both the noise immunity effect and delay time should be considered according to the
system requirements.
UCC21736-Q1 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg
shoot through issue. As shown in , the output is logic low while both IN+ and IN- are logic high. When only IN+ is
used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in the
phase leg can be sent to the IN- pin. As shown in , the PWM_T is the PWM signal to top side switch, the
PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is given to the
IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B signal is
given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B signals are
high, the outputs of both gate drivers are logic low to prevent the shoot through condition.
IN+
IN-
RON
OUTH
Microcontroller
OUTL
ROFF
PWM_T
PWM_B
RON
IN+
OUTH
INOUTL
ROFF
Figure 45. PWM Interlock for a Half Bridge
9.2.2.3 FLT, RDY and RST/EN Pin Circuitry
Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩ internal pulldown resistor, so the driver
is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for
the FLT, RDY and RST/EN pins.
To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be
added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to
300pF can be added.
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9.2.2.2 PWM Interlock of IN+ and IN-
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3.3V to 5V
VCC
15
0.1µF
1µF
GND
9
IN+
10
INt
ADVANCE INFORMATION
Micro-controller
(MCU)
11
5kQ
100pF
5kQ
5kQ
12
13
FLT
RDY
100pF
100pF
14
RST/EN
APWM
16
Figure 46. FLT, RDY and RST/EN Pins Circuitry
9.2.2.4 RST/EN Pin Control
RST/EN pin has two functions. It can be used to enable and shutdown the outputs of the driver, and reset the
fault signaled on the FLT pin. RST/EN pin needs to be pulled up to enable the device; when the pin is pulled
down, the device is in disabled status. With a 50kΩ pulldown resistor existing, the driver is disabled by default.
When the driver is latched after overcurrent or short circuit fault is detected, the FLT pin and output are latched
low and need to be reset byRST/EN pin. RST/EN pin is active low. The microcntroller needs to send a signal to
RST/EN pin after the fault mute time tFLTMUTE to reset the driver. This pin can also be used to automatically reset
the driver. The continuous input signal IN+ or IN- can be applied to RST/EN pin, so the microcontroller does not
need to generate another control signal to reset the driver. If non-inverting input IN+ is used, then IN+ can be tied
to RST/EN pin. If inverting input IN- is used, then a NOT logic is needed between the inverting PWM signal from
the microcontroller and the RST/EN pin. In this case, the driver can be reset in every switching cycle without an
extra control signal from microcontroller to RST/EN pin.
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3.3V to 5V
3.3V to 5V
VCC
VCC
15
15
1µF
0.1µF
0.1µF
1µF
GND
9
9
INt
5kQ
11
FLT
12
13
100pF
10
INt
5kQ
5kQ
11
FLT
100pF
12
13
RDY
100pF
RDY
100pF
14
16
RST/EN
14
APWM
16
RST/EN
APWM
Figure 47. Automatic Reset Control
9.2.2.5 Turn on and turn off gate resistors
UCC21736-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn on and
turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which
controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to
ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:
Is ource _ pk
Isink _ pk
min(10A,
min(10A,
VDD VEE
)
ROH _ EFF RON RG _ Int
VDD VEE
)
ROL ROFF RG _ Int
(1)
Where
• ROH_EFF is the effective internal pull up resistance of the hybrid pull-up structure, which is approximately 2 x
ROL, about 0.7 Ω
• ROL is the internal pulldown resistance, about 0.3 Ω
• RON is the external turn on gate resistance
• ROFF is the external turn off gate resistance
• RG_Int is the internal resistance of the SiC MOSFET or IGBT module
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5kQ
IN+
Micro-controller
(MCU)
Micro-controller
(MCU)
IN+
10
GND
UCC21736-Q1
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VDD
ROH_EFF
Cies=Cgc+Cge
+
t
Cgc
VDD
OUTH
RON
RG_Int
OUTL
ROFF
+
ROL
Cge
VEE
t
VEE
COM
ADVANCE INFORMATION
Figure 48. Output Model for Calculating Peak Gate Current
For example, for an IGBT module based system with the following parameters:
• Qg = 3300 nC
• RG_Int = 1.7 Ω
• RON=ROFF= 1 Ω
The peak source and sink current in this case are:
Is ource _ pk
Isink _ pk
min(10A,
min(10A,
VDD VEE
) | 5.9A
ROH _ EFF RON RG _ Int
VDD VEE
) | 6.7A
ROL ROFF RG _ Int
(2)
Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The
collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the miller
plateau voltage. The hybrid pullup structure ensures the peak source current at the miller plateau voltage, unless
the turn on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the
turn on switching loss is. The dV/dt can be estimated as Qgc/Isource_pk. For the turn off switching transient, the
drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After Vce
reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled
by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If
using relatively large turn off gate resistance, the Vce overshoot can be limited. The overshoot can be estimated
by:
'Vce
Lstray ˜ Iload / ((ROFF ROL RG _Int ) ˜ Cies ˜ ln(Vplat / Vth ))
(3)
Where
• Lstray is the stray inductance in power switching loop, as shown in Figure 49
• Iload is the load current, which is the turn off current of the power semiconductor
• Cies is the input capacitance of the power semiconductor
• Vplat is the plateau voltage of the power semiconductor
• Vth is the threshold voltage of the power semiconductor
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LDC
Lstray=LDC+Le1+Lc1+Le1+Lc1
Lc1
RG
Lload
t
+
+
t
VDC
Lc2
VDD
OUTH
Cgc
Cies=Cgc+Cge
RG
OUTL
Cge
COM
Le2
Figure 49. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration
The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The
power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:
PDR
PQ
PSW
(4)
PQ is the quiescent power loss for the driver, which is Iq x (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent
power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic
circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the
charging and discharing current of the internal circuit when the driver is switching. The power dissipation when
the driver is switching can be calculated as:
PSW
ROH _ EFF
1
˜(
2 ROH _ EFF RON RG _ Int
ROL
ROL
) ˜ (VDD VEE) ˜ fsw ˜ Qg
ROFF RG _ Int
(5)
Where
• Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD
• fsw is the switching frequency
In this example, the PSW can be calculated as:
PSW
ROH _ EFF
1
˜(
2 ROH _ EFF RON RG _ Int
ROL
ROL
) ˜ (VDD VEE) ˜ fsw ˜ Qg
ROFF RG _ Int
0.505W
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Thus, the total power loss is:
PDR
PQ PSW
0.10W 0.505W 0.605W
(7)
When the board temperature is 125°C, the junction temperature can be estimated as:
Tj
Tb
\ jb ˜ PDR | 150 o C
(8)
Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency
is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing
external gate resistance, the gate driver can be operated at a higher switching frequency.
9.2.2.6 External Active Miller Clamp
ADVANCE INFORMATION
External active miller clamp feature allows the gate driver to stay at the low status when the gate voltage is
detected below VCLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through
the parasitic miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative
voltage drop on the turn off gate resistance, and bumps up the gate voltage to cause a false turn on. The
external active miller clamp features allows flexibility of board layout and active miller clamp pulldown strength.
Limited by the board layout, if the driver cannot be placed close enough to the switch, external active miller
clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak
current needed. Caution must be exercised when the driver is place far from the power semiconductor. Since the
device has high peak sink and source current, the high dI/dt in the gate loop can cause a ground bounce on the
board parasitics. The ground bounce can cause a positive voltage bump on CLMPE pin during the turn off
transient, and results in the external active miller clamp MOSFET to turn on shortly and add extra drive strength
to the sink current. To reduce the ground bounce, a 2Ω resistance is recommended to the gate of the external
active clamp MOSFET.
When the VOUTH is detected to be lower than VCLMPTH above VEE, the CLMPE pin outputs a 5V voltage with
respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak
drain current, unless the on-resistance of the external clamp FET is large.
ICLMPE _ PK
min(ID _ PK ,
VDS
RDS _ ON
)
(9)
Where
• ID_PK is the peak drain current of the external clamp FET
• VDS is the drain-to-source voltage of the clamp FET when the CLMPE is activated
• RDS_ON is the on-resistance of the external clamp FET
The total delay time of the active miller clamp circuit from the gate voltage detection threshold VCLMPTH can be
calculated as tDCLMPE+tCLMPER. tCLMPER depends on the parameter of the external active miller clamp MOSFET.
As long as the total delay time is longer than the deadtime of high side and low side switches, the driver can
effectively protect the switch from false turn on issue caused by miller effect.
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VCLMPTH
VCC
3V to 5.5V
IN+
µC
MOD
Isolation barrier
+
±
OUTH
Control
Circuitry
CLMPE
OUTL
DEMOD
INVEE
COM
VCC
9.2.2.7 Overcurrent and Short Circuit Protection
Fast and reliable overcurrent and short circuit protection is important to protect the catastrophic break down of
the SiC MOSFET and IGBT modules, and improve the system reliability. The UCC21736-Q1 features a state-ofart overcurrent and short circuit protection, which can be applied to both SiC MOSFET and IGBT modules with
various detection circuits.
9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
The overcurrent and short circuit protection function is suitable for the SiC MOSFET and IGBT modules with
integrated SenseFET. The SenseFET scales down the main power loop current and outputs the current with a
dedicated pin of the power module. With external high precision sensing resistor, the scaled down current can be
measured and the main power loop current can be calculated. The value of the sensing resistor RS sets the
protection threshold of the main current. For example, with a ratio of 1:N = 1:50000 of the integrated current
mirror, by using the RS as 20Ω, the threshold protection current is:
IOC _ TH
VOCTH
˜ N 1750A
RS
(10)
The overcurrent and short circuit protection based on integrated SenseFET has high precision, as it is sensing
the current directly. The accuracy of the method is related to two factors: the scaling down ratio of the main
power loop current and the SenseFET, and the precision of the sensing resistor. Since the current is sensed
from the SenseFET, which is isolated from the main power loop, and the current is scaled down significantly with
much less dI/dt, the sensing loop has good noise immunity. To further improve the noise immunity, a low pass
filter can be added. A 100pF to 10nF filter capacitor can be added. The delay time caused by the low pass filter
should also be considered for the protection circuitry design.
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Figure 50. External Active Miller Clamp Configuration
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OUTL
DEMOD
MOD
150ns
Deglitch Filter
FLT
Isolation barrier
ROFF
OC
Kelvin
Connection
RFLT
+
VOCTH
±
Control
Logic
GND
SenseFET
+
CFLT
RS
COM
VEE
ADVANCE INFORMATION
Figure 51. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET
9.2.2.7.2 Protection Based on Desaturation Circuit
For SiC MOSFET and IGBT modules without SenseFET, desaturation (DESAT) circuit is the most popular circuit
which is adopted for overcurrent and short circuit protection. The circuit consists of a current source, a resistor, a
blanking capacitor and a diode. Normally the current source is provided from the gate driver, when the device
turns on, a current source charges the blanking capacitor and the diode forward biased. During normal operation,
the capacitor voltage is clamped by the switch VCE voltage. When short circuit happens, the capacitor voltage is
quickly charged to the threshold voltage which triggers the device shutdown. For the UCC21736-Q1, the OC pin
does not feature an internal current source. The current source should be generated externally from the output
power supply. When UCC21736-Q1 is in OFF state, the OC pin is pulled down by an internal MOSFET, which
creates an offset voltage on OC pin. By choosing R1 and R2 significantly higher than the pulldown resistance of
the internal MOSFET, the offset can be ignored. When UCC21736-Q1 is in ON state, the OC pin is high
impedance. The current source is generated by the output power supply VDD and the external resistor divider
R1, R2 and R3. The overcurrent detection threshold voltage of the IGBT is:
VDET
VOCTH ˜
R2 R3
R3
VF
(11)
The blanking time of the detection circuit is:
tBLK
R1 R2 R3 VOCTH
R1 R2
˜ R3 ˜ CBLK ˜ ln(1
˜
)
R1 R2 R3
R3
VDD
(12)
Where:
• VOCTH is the detection threshold voltage of the gate driver
• R1, R2 and R3 are the resistance of the voltage divider
• CBLK is the blanking capacitor
• VF is the forward voltage of the high voltage diode DHV
The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has
negligible power loss, and is easy to implement. The detection threshold voltage of IGBT and blanking time can
be programmed by external components. Different with the conventional desaturation circuit, the overcurrent
detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the
detection threshold voltage of the driver. A parallel schottky diode can be connected between OC and COM pins
to prevent the negative voltage on the OC pin in noisy system. Since the desaturation circuit measures the VCE
of the IGBT or VDS of the SiC MOSFET, not directly the current, the accuracy of the protection is not as high as
the SenseFET based protection method. The current threshold cannot be accurately controlled in the protection.
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ROFF
RDESAT
VDD
DHV
DEMOD
150ns
Deglitch Filter
FLT
Isolation barrier
R1
MOD
OC
R2
+
+
±
CBLK
VOCTH
R3
Control
Logic
GND
COM
Figure 52. Overcurrent and Short Circuit Protection Based on Desaturation Circuit
9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
In lower power applications, to simplify the circuit and reduce the cost, a shunt resistor can be used in series in
the power loop and measure the current directly. Since the resistor is in series in the power loop, it directly
measures the current and can have high accuracy by using a high precision resistor. The resistance needs to be
small to reduce the power loss, and should have large enough voltage resolution for the protection. Since the
sensing resistor is also in series in the gate driver loop, the voltage drop on the sensing resistor can cause the
voltage drop on the gate voltage of the IGBT or SiC MOSFET modules. The parasitic inductance of the sensing
resistor and the PCB trace of the sensing loop will also cause a noise voltage source during switching transient,
which makes the gate voltage oscillate. Thus, this method is not recommended for high power application, or
when dI/dt is high. To use it in low power application, the shunt resistor loop should be designed to have the
optimal voltage drop and minimum noise injection to the gate loop.
DEMOD
MOD
150ns
Deglitch Filter
FLT
Isolation barrier
ROFF
OC
RFLT
+
+
±
VOCTH
CFLT
RS
Control
Logic
GND
COM
VEE
Figure 53. Overcurrent and Short Circuit Protection Based on Shunt Resistor
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9.2.2.8 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in
Figure 54) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/
D45VH10 pair is up to 20 A peak.
In the case of a over-current detection, the soft turn off (STO) is activated. External components must be added
to implement STO instead of normal turn off speed when an external buffer is used. CSTO sets the timing for soft
turn off and RSTO limits the inrush current to below the current rating of the internal FET (10A). RSTO should be at
least (VDD-VEE)/10. The soft turn off timing is determined by the internal current source of 400mA and the
capacitor CSTO. CSTO is calculated using .
CSTO
•
•
ISTO ˜ t STO
VDD VEE
(13)
ISTO is the the internal STO current source, 400mA
tSTO is the desired STO timing
VDD
VDD
ADVANCE INFORMATION
ROH
RNMOS
Cies=Cgc+Cge
OUTH
Cgc
Cgc
RG_1
RG_2
RG_Int
RG_Int
OUTL
Cge
Cge
ROL
CSTO
COM
RSTO
VEE
Figure 54. Current Buffer for Increased Drive Strength
10 Power Supply Recommendations
During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and
VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a
voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of
decoupling capacitors are recommended at the power supplies. Considering UCC21736-Q1 has ±10A peak drive
strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE and
COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with output
side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out high
frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and
should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system
parasitics of PCB layout.
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11 Layout
Due to the strong drive strength of UCC21736-Q1, careful considerations must be taken in PCB design. Below
are some key points:
• The driver should be placed as close as possible to the power semiconductor to reduce the parasitic
inductance of the gate loop on the PCB traces
• The decoupling capacitors of the input and output power supplies should be placed as close as possible to
the power supply pins. The peak current generated at each switching transient can cause high dI/dt and
voltage spike on the parasitic inductance of PCB traces
• The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If
the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close
as possible to the source or emitter terminal of the power device package to separate the gate loop from the
high power switching loop
• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the
high frequency noise generated by the output side switching transients. The ground plane provides a lowinductance filter for the return current flow
• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the
ground plane on the output side to shield the output signals from the noise generated by the switch node; if
the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground
plane is not recommended
• If ground plane is not used on the output side, separate the return path of the OC and AIN ground loop from
the gate loop ground which has large peak source and sink current
• No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise
coupling between the input and output side which can contaminate the isolation barrier
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11.1 Layout Guidelines
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11.2 Layout Example
ADVANCE INFORMATION
Figure 55. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
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PACKAGE OPTION ADDENDUM
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12-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PUCC21736QDWQ1
ACTIVE
SOIC
DW
16
40
TBD
Call TI
Call TI
-40 to 125
PUCC21736QDWRQ1
ACTIVE
SOIC
DW
16
2000
TBD
Call TI
Call TI
-40 to 125
UCC21736QDWQ1
PREVIEW
SOIC
DW
16
40
TBD
Call TI
Call TI
-40 to 125
UCC21736QDWRQ1
PREVIEW
SOIC
DW
16
2000
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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