Texas Instruments | TPS54540B 4.5-V to 42-V Input, 5-A step-down dc/dc converter with Eco-mode™ | Datasheet | Texas Instruments TPS54540B 4.5-V to 42-V Input, 5-A step-down dc/dc converter with Eco-mode™ Datasheet

Texas Instruments TPS54540B 4.5-V to 42-V Input, 5-A step-down dc/dc converter with Eco-mode™ Datasheet
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TPS54540B
SLVSEZ9 – JANUARY 2019
TPS54540B 4.5-V to 42-V Input, 5-A step-down dc/dc converter with Eco-mode™
1 Features
3 Description
•
The TPS54540B is a 42-V, 5-A step-down regulator
with an integrated high side MOSFET. Current-mode
control provides simple external compensation and
flexible component selection. A low-ripple pulse-skip
mode reduces no-load-supply current to 146 μA.
Shutdown supply current is reduced to 2 μA when the
EN (enable) pin is pulled low.
1
•
•
•
•
•
•
•
•
•
•
High efficiency at light loads with pulse skipping
Eco-mode™
92-mΩ high-side MOSFET
146-μA operating quiescent current and
2-μA shutdown current
100-kHz to 2.5-MHz Fixed switching frequency
Synchronizes to external clock
Low dropout at light loads with integrated BOOT
recharge FET
Adjustable UVLO and hysteresis
0.8 V 1% Internal voltage reference
8-Pin HSOIC with PowerPAD™ package
–40°C to 150°C TJ operating range
Create a custom design using the TPS54540B
with the WEBENCH® Power Designer
Undervoltage lockout is internally set at 4.3 V but can
be increased using the EN pin. Output voltage startup ramp is internally controlled to provide a controlled
start-up and eliminate overshoot.
A wide switching frequency range allows either
efficiency or external component size to be optimized.
Output current is limited cycle-by-cycle. Frequency
foldback and thermal shutdown protects internal and
external components during an overload condition.
The TPS54540B is available in an 8-pin thermally
enhanced HSOIC PowerPAD package.
2 Applications
•
•
•
Industrial automation and motor control
USB dedicated charging ports and battery
chargers
12-V and 24-V Industrial and communications
power systems
Device Information(1)
PART NUMBER
PACKAGE
TPS54540B
BODY SIZE (NOM)
HSOIC (8)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
Simplified Schematic
Efficiency vs Load Current
100
VIN
VIN
36 V to 12 V
BOOT
95
EN
SW
COMP
Efficiency (%)
90
VOUT
85
12 V to 3.3 V
80
12 V to 5 V
75
70
VOUT = 12 V, fsw = 800 kHz
VOUT = 5 V and 3.3 V, fsw = 400 kHz
65
RT/CLK
FB
60
0
0.5
1
1.5
2
2.5
3
3.5
IO - Output Current (A)
4
4.5
5
C024
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54540B
SLVSEZ9 – JANUARY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 23
8
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 24
8.3 Other System Examples ......................................... 37
9 Power Supply Recommendations...................... 38
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Examples................................................... 39
10.3 Estimated Circuit Area .......................................... 39
11 Device and Documentation Support ................. 40
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description ................................................ 11
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
40
40
40
40
40
12 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
January 2019
*
Initial release
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5 Pin Configuration and Functions
DDA Package
8-Pin HSOIC With PowerPAD
Top View
BOOT
1
VIN
2
8
SW
7
GND
PowerPAD
EN
3
6
COMP
RT/CLK
4
5
FB
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
BOOT
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below
the minimum required to operate the high side MOSFET, the output is switched off until the
capacitor is refreshed.
2
VIN
I
Input supply voltage with 4.5-V to 42-V operating range.
3
EN
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust
the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage
Lockout section.
4
RT/CLK
I
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using
an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking
edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency
programming.
5
FB
I
Inverting input of the transconductance (gm) error amplifier.
6
COMP
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
7
GND
—
Ground
8
SW
I
—
Thermal pad
—
The source of the internal high-side power MOSFET and switching node of the converter.
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
–0.3
45
EN
–0.3
8.4
BOOT
Input voltage
53
3
UNIT
V
FB
–0.3
COMP
–0.3
3
RT/CLK
–0.3
3.6
–0.6
45
–2
45
Operating junction temperature
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
BOOT-SW
Output voltage
8
SW
SW, 10-ns transient
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VO + VDO
42
V
Output voltage
0.8
41.1
V
IO
Output current
0
5
A
TJ
Junction Temperature
–40
150
°C
VIN
Supply input voltage
VO
(1)
(1)
UNIT
See Equation 1
6.4 Thermal Information
TPS54540B
THERMAL METRIC (1)
DDA (HSOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
42
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.8
°C/W
RθJB
Junction-to-board thermal resistance
23.4
°C/W
ψJT
Junction-to-top characterization parameter
5.9
°C/W
ψJB
Junction-to-board characterization parameter
23.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to +150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
42
V
4.3
4.48
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
4.5
Rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
2.25
4.5
Operating: nonswitching supply current
FB = 0.9 V, TA = 25°C
146
175
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
1.1
Enable threshold +50 mV
Enable threshold –50 mV
Hysteresis current
–4.6
V
μA
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
μA
0.792
0.8
0.808
V
92
190
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current transconductance
50
nA
10,000
V/V
2500
kHz
±30
μA
17
A/V
CURRENT LIMIT
Current limit test
All VIN and temperatures, open loop (1)
6.3
7.9
9.5
All temperatures, VIN = 12 V, open loop (1)
6.3
7.9
9.5
7
7.9
8.8
VIN = 12 V, TA = 25°C, Open Loop (1)
A
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
°C
12
°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode
fSW
Switching frequency
100
RT = 200 kΩ
Switching frequency range using CLK mode
450
550
kHz
2300
kHz
1.55
RT/CLK low threshold
(1)
kHz
500
160
RT/CLK high threshold
2500
0.5
2
1.2
V
V
Open loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ENABLE AND UVLO (EN PIN)
Enable to COMP active
VIN = 12 V, TA = 25°C
340
µs
INTERNAL SOFT-START TIME
Soft-start time
fSW = 500 kHz, 10% to 90%
2.1
ms
Soft-start time
fSW = 2.5 MHz, 10% to 90%
0.42
ms
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
350
μs
77
μs
60
ns
15
ns
ERROR AMPLIFIER
Error amplifier transconductance (gM)
Error amplifier transconductance (gM) during
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
soft start
CURRENT LIMIT
Current limit threshold delay
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum CLK input pulse width
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
6.7 Typical Characteristics
0.814
VFB - Voltage Referance ( V)
RDSON - On-State Resistance ( )
0.25
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
0.809
0.804
0.799
0.794
0.789
BOOT-SW = 6 V
0
0.784
±50
±25
0
25
50
75
100
125
±50
150
TJ - Junction Temperature (ƒC)
25
50
75
100
125
150
C026
VIN = 12 V
Figure 1. On Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
9.5
9
4.5
12
9
High Side Switch Current (A)
High Side Switch Current (A)
0
TJ - Junction Temperature (ƒC)
VIN = 12 V
8.5
8
7.5
7
6.5
6
-40
±25
C025
8.5
8
7.5
7
-40 qC
25 qC
150 qC
6.5
6
-10
20
50
80
110
Temperature Junction (Tj)
140
170
0
10
D001
20
30
40
Input Voltage (V)
50
60
D002
VIN = 4.5 and 12 V
Figure 3. Switch Current Limit vs Junction Temperature
6
Figure 4. Switch Current Limit vs Input Voltage
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550
500
540
450
FSW - Switching Frequency (kHz)
FS - Switching Frequency (kHz)
Typical Characteristics (continued)
530
520
510
500
490
480
470
460
450
350
300
250
200
150
100
50
0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
VIN = 12 V
150
200
300
400
500
600
700
800
900
RT/CLK - Resistance (k )
C029
1000
C030
ƒsw (kHz) = 92471 x RT (kΩ)-0.991
RT (kΩ) = 101756 x ƒsw (kHz)-1.008
RT = 200 kΩ
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
2500
500
2300
450
2100
1900
400
gm (µA/V)
FSW - Switching Frequency (kHz)
400
1700
1500
1300
350
300
1100
900
250
700
500
200
0
50
100
150
±50
200
RT/CLK - Resistance (k )
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C031
150
C032
VIN = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
120
110
EN - Threshold (V)
100
gm (µA/V)
90
80
70
60
50
40
30
20
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
±50
±25
VIN = 12 V
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C033
150
C034
VIN = 12 V
Figure 9. EA Transconductance During Soft Start vs
Junction Temperature
Figure 10. EN Pin Voltage vs Junction Temperature
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±3.5
±0.5
±3.7
±0.7
±3.9
±0.9
±4.1
±1.1
±4.3
±1.3
IEN (µA)
IEN (uA)
Typical Characteristics (continued)
±4.5
±4.7
±1.7
±4.9
±1.9
±5.1
±2.1
±5.3
±2.3
±5.5
±2.5
±50
±25
0
25
50
75
100
125
VIN = 12 V
±50
150
TJ - Junction Temperature (ƒC)
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C035
IEN = Threshold +50 mV
VIN = 12 V
Figure 11. EN Pin Current vs Junction Temperature
150
C036
IEN = Threshold –50 mV
Figure 12. EN Pin Current vs Junction Temperature
100
% of Nominal Switching Frequency
±2.5
±2.7
±2.9
IEN - Hysteresis (µA)
±1.5
±3.1
±3.3
±3.5
±3.7
±3.9
±4.1
±4.3
Series2
VSENSE
Falling
VSENSE
Rising
Series4
75
50
25
0
±4.5
±50
±25
0
25
50
75
100
125
0.0
150
TJ - Junction Temperature (ƒC)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VSENSE (V)
C037
0.8
C038
VIN = 12 V
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
Figure 14. Switching Frequency vs VSENSE
3
3
Shutdown Supply Current (µA)
TJ = 25°C
2.5
IVIN (µA)
2
1.5
1
0.5
2
1.5
1
0.5
0
0
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
0
5
C039
10
15
20
25
30
VIN − Input Voltage (V)
35
40
45
G016
TA = 25°C
VIN = 12 V
Figure 15. Shutdown Supply Current vs Junction
Temperature
8
2.5
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
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Typical Characteristics (continued)
210
210
190
190
170
170
IVIN (µA)
IVIN (µA)
TJSeries2
= 25ƒC
150
130
150
130
110
110
90
90
70
70
±50
±25
0
25
50
75
100
125
0
150
TJ - Junction Temperature (ƒC)
28
35
42
C042
Figure 18. VIN Supply Current vs Input Voltage
4.5
BOOT-PH UVLO Falling
BOOT-PH UVLO Rising
UVLO Start Switching
UVLO Stop Switching
4.4
2.4
4.3
2.3
4.2
VIN (V)
VI - BOOT-PH (V)
21
TJ = 25°C
Figure 17. VIN Supply Current vs Junction Temperature
2.5
14
VIN - Input Voltage (V)
VIN = 12 V
2.6
7
C041
2.2
4.1
2.1
4.0
2.0
3.9
1.9
3.8
3.7
1.8
±50
±25
0
25
50
75
100
125
±50
150
TJ - Junction Temperature (ƒC)
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C043
Figure 19. BOOT-SW UVLO vs Junction Temperature
150
C044
Figure 20. Input Voltage UVLO vs Junction Temperature
10
9
Soft-Start Time (ms)
8
7
6
5
4
3
2
1
0
2500
2300
2100
1900
1700
1500
1300
1100
900
700
500
300
100
C045
Switching Frequency (kHz)
VIN = 12 V
TJ = 25°C
Figure 21. Soft-Start Time vs Switching Frequency
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7 Detailed Description
7.1 Overview
The TPS54540B is a 42-V, 5-A step-down (buck) regulator with an integrated high-side n-channel MOSFET. The
device implements constant frequency, current-mode control that reduces output capacitance and simplifies
external frequency compensation. The wide switching-frequency range of 100 kHz to 2500 kHz allows either
efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted
using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL)
connected to the RT/CLK pin that synchronizes the power switch turn on to a falling edge of an external clock
signal.
The TPS54540B has a default input start-up voltage of approximately 4.3 V. The EN pin can be used to adjust
the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current
source enables operation when the EN pin is floating. The operating current is 146 μA under no-load condition
(not switching). When the device is disabled, the supply current is 2 μA.
The integrated 92-mΩ high-side MOSFET supports high efficiency power supply designs capable of delivering 5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54540B reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit that turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset threshold.
An automatic BOOT capacitor recharge circuit allows the TPS54540B to operate at high duty cycles approaching
100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The
minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an overvoltage transient protection (OVP) comparator. When the
OVP comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less
than 106% of the desired output voltage.
The TPS54540B includes an internal soft-start circuit that slows the output rise time during start-up to reduce inrush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
10
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7.2 Functional Block Diagram
EN
VIN
Thermal
Shutdown
UVLO
Enable
Comparator
OV
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012 A 0192789
GND
POWERPAD
RT/ CLK
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7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54540B uses fixed-frequency, peak-current-mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier
output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54540B adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
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Feature Description (continued)
7.3.3 Pulse Skip Eco-mode
The TPS54540B operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate-drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV, and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse-skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54540B senses and controls peak switch current, not the average load
current. Therefore, the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 32 enters Eco-mode at about 25.3-mA output current. As the load current approaches
zero, the device enters a pulse-skip mode during which it draws only 146 μA input quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54540B provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating
of 10 V or higher for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54540B
operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the voltage
from BOOT to SW drops below 2.1 V, the high-side MOSFET is turned off, and an integrated low side MOSFET
pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high
output voltages, it is disabled at 24-V output and re-enabled when the output reaches 21.5 V.
Because the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus, the effective duty
cycle of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during
dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the lowside diode voltage, and the printed-circuit-board resistance.
Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal
operation of the device. This calculation must include tolerance of the component specifications and the variation
of these specifications at their maximum operating temperature in the application.
VOUT VF Rdc u IOUT
VIN min
RDS on u IOUT VF
0.99
where
•
•
•
12
VF = Schottky diode forward voltage
Rdc = DC resistance of inductor and PCB
RDS(on) = High-side MOSFET RDS(on)
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Feature Description (continued)
At heavy loads, the minimum input voltage must be increased to ensure a monotonic start-up. Equation 2 can be
used to calculate the minimum input voltage for this condition.
V OUT(max) = D (max) x (V IN(min) - I OUT(max) x R DS(on) + VF) - VF + I OUT(max) x R dc
where
•
•
•
•
•
•
D(max) ≥ 0.9
IB2SW = 100 µA
tSW = 1 / fSW(MHz)
VB2SW = VBOOT + VF
VBOOT = (1.41 × VIN – 0.554 – VF / tSW – 1.847 × 103 × IB2SW) / (1.41 + 1 / tSW)*
RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)
*VBOOT is clamped by the IC. If VBOOT calculates to greater than 6 V, set VBOOT = 6 V
(2)
7.3.5 Error Amplifier
The TPS54540B voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation,
the transconductance is reduced to 78 μA/V, and the error amplifier is referenced to the internal soft-start
voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V, ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. TI recommends using 1% tolerance or better divider resistors. Select
the low side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise, and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(3)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54540B is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54540B is disabled when the VIN pin voltage falls below 4 V or when the EN
pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA that enables operation
of the TPS54540B when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4μA Ihys current is removed. This additional current facilitates adjustable input-voltage UVLO hysteresis. Use
Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (for example, from 4.5 V to 9 V) and withstand
high input voltages (for example, from 40 V or 42 V), the EN pin may experience a voltage greater than the
absolute maximum voltage of 8.4 V during the high input voltage condition. It is recommended to use a zener
diode to clamp the pin voltage below the absolute maximum rating.
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Feature Description (continued)
VIN
TPS54540
i1
ihys
RUVLO1
EN
V EN
RUVLO2
Copyright © 2017, Texas Instruments Incorporated
Figure 22. Adjustable Undervoltage Lockout (UVLO)
- VSTOP
V
RUVLO1 = START
IHYS
(4)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1
(5)
7.3.8 Internal Soft Start
The TPS54540B has an internal digital soft start that ramps the reference voltage from zero volts to its final value
in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6.
1024
tSS (ms) =
fSW (kHz)
(6)
If the EN pin is pulled below the stop threshold of 1.2 V, switching stops, and the internal soft-start resets. The
soft start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) pin)
The switching frequency of the TPS54540B is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 7 or Equation 8 or the curves in Figure 6 and Figure 7. To reduce the solution size one
would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage, and minimum controllable on time should be considered. The minimum controllable ontime is typically 135 ns, which limits the maximum operating frequency in applications with high input-to-output
step-down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in Accurate Current-Limit Operation and
Maximum Switching Frequency.
101756
RT (kW) =
f sw (kHz)1.008
(7)
f sw (kHz) =
14
92417
RT (kW)0.991
(8)
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Feature Description (continued)
7.3.10 Accurate Current-Limit Operation and Maximum Switching Frequency
The TPS54540B implements peak-current-mode control in which the COMP pin voltage controls the peak current
of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side switch is
turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets the
peak switch-current limit. The TPS54540B provides an accurate current limit threshold with a typical current limit
delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The relationship
between the inductor value and the peak inductor current is shown in Figure 23.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 23. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54540B implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin
voltage falls from 0.8 V to 0 V. The TPS54540B uses a digital frequency foldback to enable synchronization to an
external clock during normal start-up and fault conditions. During short-circuit events, the inductor current can
exceed the peak current limit because of the high input voltage and the minimum controllable on-time. When the
output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off-time.
The frequency foldback effectively increases the off-time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 10 calculates the maximum switching frequency at
which the inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating
frequency must not exceed the calculated value.
Equation 9 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required at maximum input voltage.
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Feature Description (continued)
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
fSW (max skip ) =
fSW(shift) =
1
tON
(9)
where
•
•
•
•
•
•
•
•
•
•
IO — Output current
ICL — Current limit
Rdc — inductor resistance
VIN — maximum input voltage
VOUT — output voltage
VOUTSC — output voltage during short
Vd — diode voltage drop
RDS(on) — switch on resistance
tON — controllable on time
ƒDIV — frequency divide equals (1, 2, 4, or 8)
(10)
7.3.11 Synchronization to RT/CLK pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 24. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 1.7 V and
have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW is synchronized to the falling edge of RT/CLK pin signal. Design the external synchronization
circuit so that the default frequency set resistor is connected from the RT/CLK pin to ground when the
synchronization signal is off. When using a low impedance-signal source, the frequency set resistor is connected
in parallel with an AC-coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 24. The
two resistors in series provide the default frequency setting resistance when the signal source is turned off. The
sum of the resistance must set the switching frequency close to the external CLK frequency. TI recommends
accoupling the synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin.
The first time the RT/CLK is pulled above the PLL threshold the TPS54540B switches from the RT resistor freerunning frequency mode to the PLL synchronized mode. The internal 0.5-V voltage source is removed, and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency
can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor
mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then
increases or decreases to the resistor-programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 volts. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 25, Figure 26, and Figure 27 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse-skip mode (Eco-Mode).
SPACER
16
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Feature Description (continued)
RT/CLK
TPS54540B
TPS54540B
RT/CLK
PLL
RT
PLL
Hi-Z
Clock
Source
Clock
Source
RT
Copyright © 2019, Texas Instruments Incorporated
Figure 24. Synchronizing to a System Clock
SW
SW
EXT
EXT
IL
IL
Figure 25. Plot of Synchronizing in CCM
Figure 26. Plot of Synchronizing in DCM
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Feature Description (continued)
SW
EXT
IL
Figure 27. Plot of Synchronizing in Eco-mode
7.3.12 Overvoltage Protection
The TPS54540B incorporates an output OVP circuit to minimize voltage overshoot when recovering from output
fault conditions or strong unload transients in designs with low output capacitance. For example, when the power
supply output is overloaded the error amplifier compares the actual output voltage to the internal reference
voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of
the error amplifier increases to a maximum voltage corresponding to the peak-current-limit threshold. When the
overload condition is removed, the regulator output rises, and the error amplifier output transitions to the normal
operating level. In some applications, the power-supply-output voltage can increase faster than the response of
the error-amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin
voltage to the rising OVP threshold, which is nominally 109% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54540B provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power-up sequence controlled
by the internal soft-start circuitry.
7.3.14 Small Signal Model for Loop Response
Figure 28 shows an equivalent model for the TPS54540B control loop that can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current source. The resistor Ro
and capacitor Co model the open-loop gain and frequency response of the amplifier. The 1-mV ac voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is
only valid for CCM operation.
18
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Feature Description (continued)
SW
VO
Power Stage
gmps 17 A/V
a
b
RESR
R1
RL
COMP
c
0.8 V
R3
CO
C2
RO
FB
COUT
gmea
R2
350 mA/V
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Small Signal Model for Loop Response
7.3.15 Simple Small Signal Model for Peak-Current-Mode Control
Figure 29 describes a simple small signal model that can be used to design frequency compensation. The
TPS54540B power stage can be approximated by a voltage-controlled current source (duty-cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 11 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP pin voltage (node c in Figure 28) is the power stage transconductance,
gmPS. The gmPS for the TPS54540B is 17 A/V. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 12.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of
Figure 29. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14).
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Feature Description (continued)
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 29. Simple Small Signal Model and Frequency Response for Peak-Current-Mode Control
æ
s ö
ç1 +
÷
2p ´ fZ ø
VOUT
= Adc ´ è
VC
æ
s ö
ç1 +
÷
2
p
´ fP ø
è
Adc = gmps ´ RL
20
(11)
(12)
1
fP =
COUT ´ RL ´ 2p
(13)
1
fZ =
COUT ´ RESR ´ 2p
(14)
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Feature Description (continued)
7.3.16 Small Signal Model for Frequency Compensation
The TPS54540B uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 30. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to the small
signal model in Figure 30. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 30. See Application and Implementation for a design example using a Type 2A network with a low-ESR
output capacitor.
Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power-supply requirements.
VO
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
R3
C2
C1
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 31. Frequency Response of the Type 2A and Type 2B Frequency Compensation
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Feature Description (continued)
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
Ro =
CO
(15)
(16)
æ
ö
s
ç1 +
÷
2
p
´
f
Z1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea
A1 = gmea
P1 =
Z1 =
P2 =
P2 =
P2 =
22
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(18)
(19)
1
2p ´ Ro ´ C1
(20)
1
2p ´ R3 ´ C1
(21)
1
2p ´ R3 | | RO ´ (C2 + CO )
type 2a
(22)
1
type 2b
2p ´ R3 | | RO ´ CO
2p ´ R O
(17)
(23)
1
type 1
´ (C2 + C O )
(24)
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7.4 Device Functional Modes
7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
TI recommends operating the device with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V,
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device does not switch. If EN is externally pulled up to VIN or left floating, when VIN passes the
UVLO threshold the device becomes active. Switching is enabled, and the soft-start sequence is initiated. The
TPS54540B starts at the soft-start time determined by the internal soft-start timer.
7.4.2 Operation with EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft-start sequence is initiated. The TPS54540B starts at the soft-start time
determined by the internal soft-start timer.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54540B is a 42-V, 5-A step-down regulator with an integrated high-side MOSFET. Ideal applications
are: 12-V and 24-V industrial and communications power systems.
8.2 Typical Application
L1
5.5 µH
C4
U1
TPS54540BDDA
VIN
6 V to 42 V
C10
4.7 …F
C3
4.7 …F
C1
2
3
C2
4.7 …F
R1
365k
4
4.7 …F
R2
88.7
BOOT
VIN
GND
COMP
EN
RT/CLK
D1
SW
PWRPD
1
FB
8
PDS760
C6
C7
100 …F
100 …F
7
R5
31.6k
6
5
FB
GND
C8
R4
16.9k
9
R3
243k
FB
47 pF
C5
R6
10.2k
4700 pF
GND
VOUT
3.3 V, 5 A
0.1 …F
GND
GND
GND
GND
Copyright © 2019, Texas Instruments Incorporated
Figure 32. 3.3 V Output TPS54540B Design Example
8.2.1 Design Requirements
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. Calculations can be done with the aid of WEBENCH or the Excel® spreadsheet located on this
product's landing page. For this example, start with the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETERS
24
EXAMPLE VALUES
Output voltage
3.3 V
Transient response 1.25 A to 3.75 A load step
ΔVOUT = 4%
Maximum output current
5A
Input voltage
12 V nom. 6 V to 42 V
Output voltage ripple
0.5% of VOUT
Start input voltage (rising VIN)
5.75 V
Stop input voltage (falling VIN)
4.5 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54540B device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because this produces the smallest solution size. High switching frequency allows
for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Use Equation 9 and Equation 10 to calculate the upper limit of the switching frequency for the regulator. Choose
the lower value result from the two equations. Switching frequencies higher than these values results in pulse
skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54540. For this example, the output voltage is 3.3 V,
and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 mΩ,
typical switch resistance of 92 mΩ, and 5-A load, using Equation 25 the maximum switch frequency to avoid
pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits use Equation 26
to determine the maximum switching frequency for frequency foldback protection. With a current limit value of 6.3
A and short-circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 27 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 32. For 400 kHz operation, the closest
standard value resistor is 243 kΩ.
1
æ 5 A x 10.3 mW + 3.3 V + 0.52 V ö
fSW(max skip) =
´ ç
÷ = 680 kHz
135ns
è 42 V - 5 A x 92 mW + 0.52 V ø
(25)
8
æ 6.3 A x 10.3 mW + 0.1 V + 0.52 V ö
´ ç
÷ = 960 kHz
135 ns
è 42 V - 6.3 A x 92 mW + 0.52 V ø
101756
RT (kW) =
= 242 kW
400 (kHz)1.008
fSW(shift) =
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8.2.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current must always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS
current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can
be found from Equation 30 and Equation 31. For this design, the RMS inductor current is 5 A, and the peak
inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A
and an RMS current rating of 10 A. This also has a typical inductance of 5.5 µH at no load and 4.8 µH at 5-A
load. Lastly, it has a DCR of 10.3 mΩ.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor-current level
previously calculated. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative design approach is to choose an inductor with a saturation
current rating equal to or greater than the switch current limit of the TPS54540 which is nominally 7.5 A.
VIN(max ) - VOUT
VOUT
42 V - 3.3 V
3.3 V
´
=
´
= 5.1 mH
LO(min ) =
IOUT ´ KIND
VIN(max ) ´ fSW
5 A x 0.3
42 V ´ 400 kHz
(28)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
3.3 V x (42 V - 3.3 V)
= 1.58 A
42 V x 4.8 mH x 400 kHz
(29)
spacer
IL(rms ) =
(IOUT )
2
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
+
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)÷ö
2
÷ =
÷
ø
2
(5 A )
2
æ 3.3 V ´ (42 V - 3.3 V ) ö
1
+
´ ç
÷ =5A
ç
÷
12
è 42 V ´ 4.8 mH ´ 400 kHz ø
(30)
spacer
IL(peak ) = IOUT +
IRIPPLE
1.58 A
= 5A +
= 5.79 A
2
2
(31)
8.2.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
26
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The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. A regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 32 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒSW
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,
ΔIOUT is 3.75 A – 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. Using these numbers gives a minimum
capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage
change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and
tantalum capacitors have higher ESR that must be included in load-step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load-step response is
shown in Figure 37. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33
calculates the minimum capacitance required to keep the output-voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and VI is the initial voltage. For this example, the worst-case load step is from 3.75 A to
1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is
4% of the output voltage. This makes Vf = 1.04 × 3.3 V = 3.43 V. VI is the initial capacitor voltage, which is the
nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 68 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒSW is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 34 yields 30 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the equivalent ESR should be less than 10 mΩ.
The most stringent criteria for the output capacitor is the 95 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature, and dc bias increases this minimum value. For this example, 2 ×
100-μF, 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR are used. The derated capacitance is 130 µF, well
above the minimum required capacitance of 95 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability, especially non ceramic capacitors. Some capacitor data sheets specify the root mean square (RMS)
value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current that the output
capacitor must support. For this example, Equation 36 yields 460 mA.
2 ´ DIOUT
2 ´ 2.5 A
COUT >
=
= 95 mF
fSW ´ DVOUT 400 kHz x 0.13 V
(32)
((I ) - (I ) ) = 4.8 mH x (3.75 A - 1.25 A ) = 68 mF
x
(3.43 V - 3.3 V )
((V ) - (V ) )
2
OH
COUT > LO
2
2
f
2
2
2
2
OL
2
I
1
1
1
1
x
´
=
= 30 mF
8 ´ fSW æ VORIPPLE ö 8 x 400 kHz
æ 16 mV ö
ç 1.58 A ÷
ç
÷
è
ø
è IRIPPLE ø
V
16 mV
RESR < ORIPPLE =
= 10 mW
IRIPPLE
1.58 A
(33)
COUT >
(34)
(35)
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ICOUT(rms) =
www.ti.com
(
VOUT ´ VIN(max ) - VOUT
)=
12 ´ VIN(max ) ´ LO ´ fSW
3.3 V ´
(42 V
- 3.3 V )
12 ´ 42 V ´ 4.8 mH ´ 400 kHz
= 460 mA
(36)
8.2.2.5 Catch Diode
The TPS54540B requires an external catch diode between the SW pin and GND. The selected diode must have
a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater
than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their
low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540.
For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 volts
at 5 A and 25°C.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode at the
nominal input voltage is 1.9 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD
(V
=
IN(max ) - VOUT
(12 V
)´ I
OUT
VIN
- 3.3 V ) ´ 5 A x 0.52 V
12 V
2
´ Vf d
+
C j ´ fSW ´ (VIN + Vf d)
+
2
=
300 pF x 400 kHz x (12 V + 0.52 V)2
= 1.9 W
2
(37)
8.2.2.6 Input Capacitor
The TPS54540B requires a high-quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input-current ripple of the TPS54540B. The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching-regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients
up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V,
16 V, 25 V, 50 V, or 100 V. For this example, four 4.7-μF, 50-V capacitors in parallel are used. Table 2 shows
several choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage
ripple occurs at 50% duty cycle and can be calculated using Equation 39. Using the design example values, IOUT
= 5 A, CIN = 18.8 μF, ƒSW = 400 kHz, yields an input voltage ripple of 170 mV and an RMS input ripple current of
2.5 A.
28
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ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 5A
3.3 V
´
6V
(6 V
- 3.3 V )
6V
= 2.5 A
(38)
I
´ 0.25
5 A ´ 0.25
DVIN = OUT
=
= 170 mV
CIN ´ fSW
18.8 mF ´ 400 kHz
(39)
Table 2. Capacitor Types
VALUE (μF)
1 to 2.2
1 to 4.7
1
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
1 to 4.7
1 to 2.2
EIA Size
VOLTAGE
DIALECTRIC
100 V
1210
GRM32 series
50 V
100 V
1206
COMMENTS
GRM31 series
50 V
50 V
2220
100 V
VJ X7R series
50 V
2225
100 V
100 V
1812
X7R
C series C4532
50 V
100 V
1210
C series C3225
50 V
50 V
1210
100 V
X7R dielectric series
50 V
1812
100 V
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. TI
recommends a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or higher
voltage rating.
8.2.2.8 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54540. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brownouts when the input voltage is falling. For the example design, the supply must turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN terminal. Equation 4 and Equation 5 calculate the resistance values necessary. For
the example application, a 365-kΩ resistor between VIN and EN (RUVLO1) and a 88.7-kΩ resistor between EN
and GND (RUVLO2) are required to produce the 5.75 V and 4.5 V start and stop voltages.
V
- VSTOP
5.75 V - 4.5 V
RUVLO1 = START
=
= 368 kW
IHYS
3.4 mA
(40)
RUVLO2 =
VENA
1.2 V
=
= 88.7 kW
VSTART - VENA
5.75 V - 1.2 V
+ 1.2 mA
+ I1
365 kW
RUVLO1
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8.2.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 3, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the
output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
V
- 0.8 V
æ 3.3 V - 0.8 V ö
RHS = RLS x OUT
= 10.2 kW x ç
÷ = 31.9 kW
0.8 V
0.8 V
è
ø
(42)
8.2.2.10 Minimum VIN
To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the
device must be above the value calculated with Equation 43. Using the typical values for the RHS, RDC and VF in
this application example, the minimum input voltage is 5.56 V. The BOOT-SW = 3 V curve in Figure 1 was used
for RDS(on) = 0.12 Ω because the device operates with low dropout. When operating with low dropout, the BOOTSW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed every switching
cycle. In the final application, the values of RDS(on), Rdc, and VF used in Equation 43 must include tolerance of the
component specifications and the variation of these specifications at their maximum operating temperature in the
application. In this application example, the calculated minimum input voltage is near the input voltage UVLO for
the TPS54540B so the device may turn off before going into dropout.
VOUT
VIN min
VF
Rdc u IOUT
RDS on u I OUT VF
0.99
3.3 V 0.5 V 0.0103 : u 5 A
0.12 : u 5 A 0.5 V
0.99
VIN min
3.99 V
(43)
8.2.2.11 Compensation
There are several methods to design compensation for dc/dc regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Becausae the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 44 and
Equation 45. For COUT, use a derated value of 130 μF. Use equations Equation 46 and Equation 47 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz.
Equation 45 is the geometric mean of the modulator pole and the ESR zero, and Equation 47 is the mean of
modulator pole and half of the switching frequency. Equation 46 yields 34 kHz and Equation 47 gives 19 kHz.
Use the geometric mean value of Equation 46 and Equation 47 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
5A
fP(mod) =
=
= 1850 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 130 mF
(44)
f Z(mod) =
30
1
2 ´ p ´ RESR ´ COUT
fco1 =
fp(mod) x f z(mod) =
fco2 =
fp(mod) x
fSW
2
=
=
1
= 610 kHz
2 ´ p ´ 1 mW ´ 130 mF
1850 Hz x 610 kHz
= 34 kHz
400 kHz
2
= 19 kHz
1850 Hz x
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(45)
(46)
(47)
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To determine the compensation resistor, R4, use Equation 48. The typical power stage transconductance, gmps,
is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8
V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use
Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5100 pF for
compensating capacitor C5. 4700 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
3.3V
æ 2 ´ p ´ 30 kHz ´ 130 mF ö æ
R4 = ç
xç
÷ = ç
÷ x ç
÷ = 17 kW
÷
gmps
17 A / V
è
ø è 0.8 V x 350 mA / V ø
è
ø è VREF x gmea ø
(48)
1
1
C5 =
=
= 5100 pF
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 16.9 kW x 1850 Hz
(49)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
130 mF x 1 mW
=
= 15 pF
C8 = OUT
R4
16.9 kW
(50)
1
1
C8 =
=
= 47 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
(51)
8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters DCM when the output current is less than 560 mA. The
power supply enters Eco-mode when the output current is lower than 18 mA. The input current draw is 241 μA
with no load.
8.2.2.13 Power Dissipation Estimate
The following formulas show how to estimate the TPS54540 power dissipation under CCM operation. Do not use
these equations if the device is operating in DCM.
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.
æV
ö
3.3 V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 92 mW ´
= 0.633 W
V
12 V
è IN ø
(52)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
(53)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W
(54)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(55)
Where:
IOUT
is the output current (A).
RDS(on)
is the on-resistance of the high-side MOSFET (Ω).
VOUT
is the output voltage (V).
VIN
is the input voltage (V).
fSW
is the switching frequency (Hz).
trise
is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG
is the total gate charge of the internal MOSFET
IQ
is the operating nonswitching supply current
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Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.633 W + 0.118 W + 0.014 W + 0.0018 W = 0.77 W
(56)
For given TA,
TJ = TA + RTH ´ PTOT
(57)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(58)
Where:
PTOT
is the total device power dissipation (W).
TA
is the ambient temperature (°C).
TJ
is the junction temperature (°C).
RTH
is the thermal resistance of the package (°C/W)
TJMAX
is maximum junction temperature (°C).
TAMAX
is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch
diode, and PCB trace resistance impacting the overall efficiency of the regulator.
8.2.2.14 Safe Operating Area
90
90
80
80
70
70
60
60
TA (ƒC)
TA (ƒC)
The safe operating area (SOA) of the device is shown in Figure 33, through Figure 36 for 3.3 V, 5 V, and 12 V
outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at
which the internal and external components are at or below the manufacturer’s maximum operating
temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar
to the EVM. Pay careful attention to the other components chosen for the design, especially the catch diode. In
most of these test conditions, the thermal performance is limited by the catch diode. When operating at high duty
cycles or at higher switching frequency the TPS54540B thermal performance can become the limiting factor.
50
50
6V
40
8V
40
12 V
24 V
30
36 V
20
0.0
0.5
12 V
24 V
30
36 V
20
1.0
1.5
2.0
2.5
3.0
3.5
IOUT (Amps)
4.0
4.5
5.0
0.0
C056
Figure 33. 3.3-V Outputs
32
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IOUT (Amps)
4.0
4.5
5.0
C057
Figure 34. 5-V Outputs
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90
90
80
80
70
70
60
TA (ƒC)
TA (ƒC)
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fsw = 800 kHz
50
18 V
40
60
50
400 LFM
40
200 LFM
30
100 LFM
24 V
30
36 V
Nat Conv
20
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IOUT (Amps)
ƒSW = 800 kHz
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
IOUT (Amps)
C058
ƒsw = 800 kHz
Figure 35. 12-V Outputs
VIN = 36 V
5.0
C048
VO = 12 V
Figure 36. Air Flow Conditions
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8.2.3 Application Curves
10 V/div
1 A/div
Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.
IOUT
VIN
100 mV/div
10 mV/div
VOUT ±3.3V offset
VOUT ±3.3V offset
Time = 4 ms/div
Time = 100 Ps/div
Figure 38. Line Transient (8 V to 40 V)
Figure 37. Load Transient
5 V/div
VIN
VOUT
2 V/div
EN
EN
2 V/div
2 V/div
2 V/div
5 V/div
VIN
VOUT
Time = 2 ms/div
Time = 20 ms/div
Figure 40. Start-up With EN
Figure 39. Start-up With VIN
10 V/div
SW
500 mA/div
IL
10 mV/div
IL
10 mV/div
1 A/div
10 V/div
SW
VOUT ± AC Coupled
VOUT ± AC Coupled
IOUT = 100 mA
Time = 4 Ps/div
Time = 4 Ps/div
Figure 41. Output Ripple CCM
34
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Figure 42. Output Ripple DCM
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Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.
10 V/div
IL
1 A/div
10 V/div
200 mA/div
SW
SW
200 mV/div
10 mV/div
IL
VOUT ± AC Coupled
No Load
VIN ± AC Coupled
Time = 1 ms/div
Time = 4 Ps/div
Figure 43. Output Ripple PSM
Figure 44. Input Ripple CCM
10 V/div
2 V/div
SW
SW
VIN ± AC Coupled
IOUT = 100 mA
IL
VOUT = 5 V
20 mV/div
10 mV/div
200 mA/div
500 mA/div
IL
No Load
EN Floating
VIN = 5.5 V
Time = 4 Ps/div
Time = 40 Ps/div
Figure 45. Input Ripple DCM
Figure 46. Low Dropout Operation
100
100
90
95
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
VOUT = 5 V, fsw = 400 kHz
70
65
60
0
0.5
1
1.5
Series4
VIN = 7 V
12V
VIN = 12 V
VIN = 24 V
24V
VIN = 36 V
36V
2
2.5
3
3.5
4
IO - Output Current (A)
4.5
60
50
30
V
VIN=12V
IN = 12 V
20
VIN=24V
V
IN = 24 V
10
5
VIN=6V
V
IN = 7 V
40
0
0.001
C024
Figure 47. Efficiency vs Load Current
VIN=24V
V
IN = 36 V
VOUT = 5 V, fsw = 400 kHz
0.01
0.1
IO - Output Current (A)
Figure 48. Light Load Efficiency
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C024
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Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.
100
100
95
90
80
70
Efficiency (%)
85
80
75
65
VOUT = 3.3 V, fsw = 400 kHz
0
0.5
1
1.5
2
2.5
50
40
30
VIN
V
IN ==66VV
V
VIN
12VV
IN ==12
V
VIN
24VV
IN ==24
V
VIN
36VV
IN ==36
70
60
60
3
3.5
4
4.5
Load Current (A)
10
VOUT = 3.3 V, fsw = 400 kHz
0
0.001
5
0.01
Figure 49. Efficiency vs Load Current
95
85
Gain (dB)
Efficiency (%)
90
80
V
18in
IN = 18 V
60
180
50
150
40
120
30
90
20
60
10
30
0
0
±10
±30
±20
±60
±30
70
Series1
V
IN = 24 V
65
VOUT = 12 V, fsw = 800 kHz
0
0.5
1
1.5
2
2.5
±50
Series3
V
IN = 36 V
3
3.5
4
4.5
IO - Output Current (A)
±90
±40
VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A
±120
Phase
±150
±180
10
5
100
1k
10k
100k
1M
Frequency (Hz)
C024
C053
Figure 52. Overall Loop Frequency Response
Figure 51. Efficiency vs Output Current
0.20
0.4
0.15
Output Voltage Normalized (%)
0.5
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
Gain
±60
60
Output Voltage Normalized (%)
1
C051
Figure 50. Light Load Efficiency
100
VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz
-0.4
VIN = 12 V, IOUT = 5 A, fsw = 400 kHz
0.10
0.05
0.00
±0.05
±0.10
±0.15
±0.20
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Current (A)
4.5
5
0
C054
Figure 53. Regulation vs Load Current
36
0.1
Load Current (A)
C050
75
VIN
V
IN ==66VV
V
VIN
12VV
IN ==12
V
VIN
24VV
IN ==24
V
VIN
36VV
IN ==36
20
Phase (£)
Efficiency (%)
90
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5
10
15
20
25
30
35
40
Input Voltage (V)
45
C055
Figure 54. Regulation vs Input Voltage
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Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise noted.
8.3 Other System Examples
8.3.1 Inverting Power
The TPS54540B can be used to convert a positive input voltage to a negative output voltage. Idea applications
are amplifiers requiring a negative power supply. For a more detailed example see SLVA317.
VIN
+
Cin
Cboot
Lo
BOOT
VIN
Cd
GND
SW
TPS54540B
R1
GND
+
Co
FB
R2
VOUT
EN
COMP
RT/CLK
Rcomp
RT
Czero
Cpole
Copyright © 2019, Texas Instruments Incorporated
Figure 55. TPS54540B Inverting Power Supply from SLVA317 Application Note
8.3.2 Split-Rail Power Supply
The TPS54540B can be used to convert a positive input voltage to a split-rail positive and negative output
voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and negative
voltage power supply. For a more detailed example see TI application report, Creating a split-rail power supply
with a wide input voltage buck regulator.
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Other System Examples (continued)
VIN
+
VOPOS
Cin
Cboot
+
GND
Copos
BOOT
VIN
Cd
GND
SW
TPS54540B
R1
GND
+
Coneg
FB
R2
VONEG
EN
COMP
RT/CLK
Rcomp
RT
Czero
Cpole
Copyright © 2019, Texas Instruments Incorporated
Figure 56. TPS54540B Split-Rail Power Supply
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 42 V. If the input
supply is located more than a few inches from the TPS54540B converter. Additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical
choice.
38
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance.
• To reduce parasitic effects, bypass the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R
or X7R dielectric.
• Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode
of the catch diode.
• Tie the GND pin directly to the power pad under the IC and the PowerPAD.
• Connect the PowerPAD to internal PCB ground planes using multiple vias directly under the IC.
• Route the SW pin to the cathode of the catch diode and to the output inductor.
• Because the SW connection is the switching node, place the catch diode and output inductor close to the SW
pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• For operation at full-rated load, the top side ground area must provide adequate heat dissipating area.
• The RT/CLK pin is sensitive to noise; therefore, place the RT resistor as close as possible to the IC and
routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has
been shown to produce good results and is meant as a guideline.
10.2 Layout Examples
Vout
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT/CLK
Frequency
Set Resistor
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 57. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of Typical Application the estimated printed circuit board area is 1.025
in2 (661 mm2). This area does not include test points or connectors.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54340B device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Excel is a registered trademark of Microsoft Corporation.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
40
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54540BDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 150
54540C
TPS54540BDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 150
54540C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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26-Jan-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54540BDDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54540BDDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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