Texas Instruments | TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller (Rev. A) | Datasheet | Texas Instruments TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller (Rev. A) Datasheet

Texas Instruments TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller (Rev. A) Datasheet
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TPS23755
SLVSDW2A – DEC 2018 – REVISED JANUARY 2019
TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller
1 Features
3 Description
•
The TPS23755 device combines a Power over
Ethernet (PoE) powered device (PD) interface, a 150V switching power FET, and a current-mode DC-DC
controller optimized for flyback topology. The high
level of integration along with primary side regulation
(PSR), spread spectrum frequency dithering (SSFD),
and advanced startup makes the TPS23755 an ideal
solution for size-constrained applications. The PoE
implementation supports the IEEE 802.3at standard
as a 13-W, Type 1 PD.
Complete IEEE 802.3at PD Solution for Type 1
PoE
– Ethernet Alliance (EA) Logo Certified Designs
Available
– Robust 100-V, 0.36-Ω (typ) Hotswap MOSFET
– Programmable Classification Level
Integrated PWM Controller with 0.77-Ω (typ) 150V Power MOSFET
– Flyback Controller with PSR
– Supports CCM Operation with Secondary
Side Diode Rectifier
– ±3% (typ, 12-V Output) Load Regulation
(5%-100% range)
– Supports Low-side Switch Buck Topology
– Adjustable Switching Frequency with
Synchronization
– Advanced Startup
– Programmable Slew Rate and Frequency
Dithering for Enhanced EMI Reduction
Secondary Side Adapter Priority Control with
Smooth Transition
–40°C to 125°C Junction Temperature Range
Small 6-mm x 4-mm VSON Package
1
•
•
•
•
SFFD and slew rate control helps to minimize the
size and cost of the EMI filter. Advanced Startup
allows the use of minimal bias capacitor while
simplifying converter startup and hiccup design.
Secondary auxiliary power detect capability provides
priority for a secondary side power adapter, while
ensuring smooth transition to and from PoE input
power, with no efficiency or thermal trade-off.
The DC-DC controller features internal soft-start,
slope compensation, and blanking. For non-isolated
applications, the buck topology is also supported by
the TPS23755.
2 Applications
•
•
•
•
The PSR feature of the DC-DC controller uses
feedback from an auxiliary winding for control of the
output voltage, eliminating the need for external shunt
regulator and optocoupler. It is optimized for
operation with secondary side diode rectifier (typically
12-V output or higher). Typically, the converter
operates in continuous conduction mode (CCM) at a
switching frequency of 250 kHz.
IEEE 802.3at Compliant Powered Devices
Security Cameras
IP Phones
Access Points
Table 1. Device Information(1)
PART NUMBER
PACKAGE
TPS23755
VSON (24)
BODY SIZE (NOM)
6.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Simplified Application
T1
+
CBULK
RCL
DOUT
From Ethernet
Transformers
Figure 2. Efficiency Vs. Load Current, 12 V
Output
COUT
TPS23755
DCL
VDD
RDEN
12V
CCL
100
VPD
DRAIN
DEN
RCS
0.1 F
CLS
RCLS
R1
CCC2
70
COMP
CCOMP
FRS
RCOMP
Efficiency (%)
From Spare Pairs
or Transformers
CCC
VCC
R2
FB
RAUX
RDTR
AUX_V
CP
DTHR
CDTR
AUX_D
RTN
VB
GND
80
CS
VSS
RFRS
90
DCC
RSNS
58V
SRR
SRF
CVB
RSRF
RSRR
Optional
(For secondary side Aux
Supply Detection)
60
50
PoE
DC-DC
40
30
20
10
0
0
0.2
0.4
0.6
0.8
Load Current (A)
1
1.2
D025
Exce
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS23755
SLVSDW2A – DEC 2018 – REVISED JANUARY 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Product Information...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: DC-DC Controller
Section ....................................................................... 7
7.6 Electrical Characteristics: PoE and Control .............. 9
7.7 Typical Characteristics ............................................ 10
8
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application .................................................. 30
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
Changes from Original (December 2018) to Revision A
•
2
Page
Changed device status to Production Data ........................................................................................................................... 1
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5 Product Information
6 Pin Configuration and Functions
RJJ Package
24-Pin VSON
Top View
A1
A4
RSNS
1
24
DRAIN
CP
2
23
NC
GND
3
SRR
4
21
VCC
SRF
5
20
AUX_V
VB
6
19
COMP
AUX_D
7
18
FB
CS
8
17
NC
DTHR
9
16
CLS
FRS
10
15
DEN
RTN
11
14
VPD
12
13
VDD
VSS
A2
A3
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
RSNS
O
Switching Power FET source connection. Connect to the external power current sense resistor.
2
CP
O
CP provides the clamp for the primary side regulation loop. Connect this pin to the lower end of
the second primary side winding of the transformer.
3
GND
—
Power ground used by the flyback power FET gate driver and CP. Connect to RTN.
4
SRR
I
Switching FET Gate sinking current input, used for EMI control. Connect a resistance from SRR to
GND to control the Vds rate of rise.
5
SRF
I
Switching FET Gate sourcing current input, used for EMI control. Connect a resistance from SRF
to VB to control the Vds rate of fall.
6
VB
O
5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF
ceramic capacitor to GND pin.
7
AUX_D
I
Auxiliary supply detect, internally pulled-up to approximately 5V. Pull this pin low, typically through
an optocoupler from the secondary side, to step down the output voltage of the DC-DC converter
when a secondary side auxiliary supply is connected.
8
CS
I
DC-DC controller current sense input. Connect directly to the external power current sense
resistor.
9
DTHR
O
Used for spread spectrum frequency dithering. Connect a capacitor from DTHR to RTN and a
resistor from DTHR to FRS. If dithering is not used, short DTHR to VB pin.
10
FRS
I/O
This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to
RTN to set the frequency.
11
RTN
—
RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.
12
VSS
—
Negative power rail derived from the PoE source.
13
VDD
—
Source of DC-DC converter start-up current. Connect to VPD for most applications.
14
VPD
—
Positive input power rail for PoE interface circuit. Derived from the PoE source. Bypass with a 0.1
µF to VSS and protect with a TVS.
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Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
15
DEN
I/O
Connect a 24.9-kΩ resistor from DEN to VPD to provide the PoE detection signature. Pulling this
pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.
16
CLS
O
Connect a resistor from CLS to VSS to program the classification current.
17
NC
—
No connect pin. Leave open.
18
FB
I
Converter error amplifier inverting (feedback) input. It is typically driven by a voltage divider from
the auxiliary winding. Also connect to the COMP compensation network.
19
COMP
O
Compensation output of the DC-DC convertor error amplifier. Connect the compensation networks
from this pin to the FB pin to compensate the converter.
20
AUX_V
O
AUX_V works with AUX_D to step down the output voltage setting of the DC-DC converter when
an auxiliary supply is detected. Typically connected to FB pin through a resistor which defines the
new voltage setting.
21
VCC
I/O
DC/DC converter bias voltage. The internal startup current source and converter bias winding
output power this pin. Connect a 1µF minimum ceramic capacitor to RTN.
23
NC
—
No connect pin. Leave open.
24
DRAIN
O
Drain connection to the internal switching power MOSFET of the DC/DC controller.
PAD
—
The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat
dissipation.
ANCHORS
—
Should be soldered to PCB for mechanical performance. These pins are not connected internally.
A1-A4
4
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7 Specifications
7.1 Absolute Maximum Ratings
Voltage are with respect to VVSS (unless otherwise noted) (1)
Input voltage
MIN
MAX
VDD, VPD, DEN, GND, RTN (2)
–0.3
100
VDD to RTN
–0.3
100
AUX_D, FB, CS, all to RTN
–0.3
6.5
SRF to GND
–0.3
6.5
CLS
Voltage
(3)
–0.3
6.5
FRS (3), COMP (3), VB (3), SRR (3), DTHR (3), RSNS (3), AUX_V (3), all to
RTN
–0.3
6.5
VCC to RTN
–0.3
19
DRAIN to GND
–0.3
150
CP to GND
–0.3
60
GND to RTN
–0.3
0.3
VB, VCC
Sourcing current
Sinking current
Internally limited
RTN
Internally limited
DEN
1
AUX_V
5
mA
mA
Internally limited
Switching DRAIN peak current limit
2
Switching DRAIN peak current limit, Buck topology with 16% dutycycle
3
CP
TJ(max)
Maximum junction temperature
Tstg
Storage temperature
(2)
(3)
V
35
COMP
Peak sourcing
current
(1)
V
Internally limited
CLS
COMP
IDRAIN
UNIT
A
1.5
A
Internally Limited
–65
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
IRTN = 0 for VRTN > 80 V.
Do not apply voltage to these pins.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
IEC 61000-4-2 contact discharge
(3)
IEC 61000-4-2 air-gap discharge (3)
(1)
(2)
(3)
±8000
UNIT
V
±15000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
ESD per EN61000-4-2, applied between RJ-45 and output ground of the TPS23755EVM-894 evaluation module. These were the test
levels, not the failure threshold.
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7.3 Recommended Operating Conditions
Voltage with respect to VVSS (unless otherwise noted)
MIN
Input voltage range
Sinking current
Peak current limit
Peak sourcing
current
Capacitance
Resistance
NOM
MAX
VDD, VPD, RTN, GND
0
VCC to RTN
0
16
AUX_D to RTN
0
VB
CS to RTN
0
2
DRAIN to GND
0
125
CP to GND
0
57
V
45
RTN
350
DRAIN, RSNS
1.6
DRAIN, RSNS, Buck topology with 16% duty-cycle
2.5
CP
500
VB (1)
0.08
0.1
VCC
0.8
1
CLS (1)
30
mA
A
mA
μF
SRF to VB
100
SRR to GND
Ω
15
Synchronization
pulse width input
(when used)
FRS
TJ
Operating junction temperature
(1)
UNIT
35
ns
–40
125
°C
Voltage should not be externally applied to this pin.
7.4 Thermal Information
TPS23755
THERMAL METRIC
(1)
RJJ (VSON)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
34.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.5
°C/W
RθJB
Junction-to-board thermal resistance
14.5
°C/W
ψJT
Junction-to-top characterization parameter
6.4
°C/W
ψJB
Junction-to-board characterization parameter
14.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.4
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: DC-DC Controller Section
Unless otherwise noted, VVDD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,
and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; 8.5 V
≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN and VVPD = VVDD] or [VVSS = VRTN = VVPD], all voltages referred to VRTN and VGND unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVCC rising
8
8.25
8.6
V
VVCC falling
5.85
6.1
6.25
V
2
2.15
2.5
V
2.0
2.35
mA
DC-DC SUPPLY (VCC)
VCUVR
VCUVF
Undervoltage lockout
VCUVH
Hysteresis
IRUN
Operating current, converter
switching
tST
Start-up time, CCC = 1 μF
VVC_ST
VCC startup voltage
(1)
VVCC = 10 V, VFB = VRTN = VRSNS ,
DRAIN with 2-kΩ pull up to 95 V
VDD = 10.2 V, VVCC(0) = 0 V
0.5
1.0
2.5
ms
VDD = 35 V, VVCC(0) = 0 V
0.5
0.80
1.5
ms
Measure VVCC during startup, IVCC =
0 mA
11
13
15.5
V
kHz
DC-DC TIMING (FRS)
fSW
Switching frequency
VFB = VRSNS = VRTN, Measure at
DRAIN
223
248
273
DMAX
Duty cycle
VFB = VRSNS = VRTN, Measure at
DRAIN
75%
77.5%
80%
VSYNC
Synchronization
Input threshold
2
2.2
2.4
V
FREQUENCY DITHERING RAMP GENERATOR (DTHR)
IDTRCH
Charging (sourcing) current
0.5 V < VDTHR < 1.38 V
3 x IFRS
47.2
49.6
µA
52.1
µA
3 x IFRS
µA
IDTRDC
Discharging (sinking) current
0.6 V < VDTHR < 1.5 V
47.2
49.6
52.1
µA
VDTUT
Dithering upper threshold
VDTHR rising until IDTHR > 0
1.41
1.513
1.60
V
VDTLT
Dithering lower threshold
VDTHR falling until IDTHR < 0
0.43
0.487
0.54
V
VDTPP
Dithering pk-pk amplitude
1.005
1.026
1.046
V
1.723
1.75
1.777
V
0.5
μA
ERROR AMPLIFIER (FB, COMP)
VREFC
Feedback regulation voltage
IFB_LK
FB leakage current (source or sink)
GBW
Small signal unity gain bandwidth
0.9
1.2
MHz
AOL
Open loop voltage gain
70
90
dB
1.35
1.5
VFB-RTN = 1.75 V
VZDC
0% duty-cycle threshold
VCOMP falling until DRAIN switching
stops
ICOMPH
COMP source current
VFB = VRTN , VCOMP = 3 V
ICOMPL
COMP sink current
VFB = VVB , VCOMP = 1.25 V
VCOMPH
COMP high voltage
VFB = VVB , 15 kΩ from COMP to
RTN
VCOMPL
COMP low voltage
VFB = VVB , 15 kΩ from COMP to VB
COMP to CS gain
ΔVCS / ΔVCOMP , 0 V < VCS < 0.5 V
1.65
1
2.1
V
mA
6
4
mA
5
1.1
V
V
0.475
0.5
0.525
V/V
SOFT-START
tSS
Soft-start period
tCD
Cool-down period
8
16
24
ms
15
20
26
ms
V
CURRENT SENSE (CS)
VCSMAX
VFB = VRTN, VCS rising
0.5
0.55
0.6
tOFFDEL_ILM Current limit turnoff delay
Maximum threshold voltage
VCS = 0.65 V
25
41
60
tOFFDEL_PW PWM comparator turnoff delay
VCS = 0.4 V
25
41
60
56.5
75
93.5
Blanking delay
(1)
In addtition to tOFFDEL
ns
ns
The hysteresis tolerance tracks the rising threshold for a given device.
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Electrical Characteristics: DC-DC Controller Section (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,
and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; 8.5 V
≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN and VVPD = VVDD] or [VVSS = VRTN = VVPD], all voltages referred to VRTN and VGND unless otherwise noted.
PARAMETER
TEST CONDITIONS
VSLOPE
Internal slope compensation voltage
Peak voltage at maximum duty
cycle, referred to CS
ISL_EX
Peak slope compensation current
VFB = VRTN, ICS at maximum duty
cycle (ac component)
Bias current
DC component of CS current
MIN
TYP
MAX
UNIT
120
155
185
mV
30
42
54
μA
-6.7
-5
-3.3
μA
0.77
1.28
Ω
1
1.1
V
2
2.3
V
SWITCHING POWER FET (DRAIN, RSNS)
BVDSS
Power FET break-down voltage
RDS(ON)
Power FET on resistance
VSD
Source-to-drain diode forward
voltage
150
IRSNS = 500mA
0.6
V
SECONDARY SIDE AUXILIARY POWER (AUX_D, AUX_V)
VAUXEN
VAUXH
Ipullup
VAVL
AUX_D threshold voltage
VAUX_D rising
Hysteresis
AUX_D pullup current
AUX_V output low voltage
1.7
(1)
0.15
70
100
VAUX_D = VVB , 5 KΩ from AUX_V to
VB
V
130
µA
50
mV
165
°C
THERMAL SHUTDOWN
Turnoff temperature
145
Hysteresis (2)
(2)
8
159
13
°C
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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7.6 Electrical Characteristics: PoE and Control
Unless otherwise noted, VVPD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D,
and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF;
–40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
Unless otherwise noted, VVPD = VVDD , VVCC = VRTN. All voltages referred to VVSS unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
8.3
13.9
µA
0.1
5
µA
Measure IVPD + IVDD + IDEN + IRTN , VVPD = 1.4 V
55.5 56.3
60
μA
Measure IVPD + IVDD + IDEN + IRTN , VVPD = 10 V
400
407
414.5
μA
3
4
5
V
PD DETECTION (DEN)
Ilkg
Detection bias current
DEN open, VVPD = 10 V, Measure IVPD + IVDD + IDEN + IRTN
DEN leakage current
VDEN = VVPD = 57 V, Measure IDEN
Detection current
VPD_DIS
3.5
Hotswap disable threshold
PD CLASSIFICATION (CLS)
RCLS = 649 Ω
RCLS = 121 Ω
13 V ≤ VDD ≤ 21 V, Measure
IVPD + IVDD + IDEN + IRTN
1.8 2.14
2.4
9.9 10.6
11.3
17.6 18.6
19.4
29.3
ICLS
Classification current
RCLS = 45.3 Ω
26.5 27.9
VCL_ON
Classification regulator lower
threshold
Regulator turns on, VVPD rising
10.7 12.1
13
V
Hysteresis (1)
0.6
1.1
1.55
V
Regulator turns off, VVPD rising
21
22
23
V
VCU_HYS
Classification regulator upper
threshold
Hysteresis (1)
0.5 0.77
1
V
Ilkg
Leakage current
VVPD = 57 V, VCLS = 0 V, VDEN = VVSS, Measure ICLS
1
μA
VCL_HYS
VCU_OFF
RCLS = 68.1 Ω
mA
RTN (PASS DEVICE)
0.36
0.68
Ω
Current limit
VRTN = 1.5 V, pulsed measurement
405
550
800
mA
Inrush current limit
VRTN = 2 V, VVPD: 0 V → 48 V, pulsed measurement
100
140
220
mA
Foldback voltage threshold
VRTN rising
11 12.3
13.6
V
Foldback deglitch time
VRTN rising to when current limit changes to inrush current limit
600
µs
Leakage current
VVPD = VRTN = 100 V, VDEN = VVSS
40
μA
36.7
V
4.5
4.7
V
300
580
ON-resistance
Ilkg
150
387
PD INPUT SUPPLY (VPD, VDD)
UVLO_R
UVLO_H
IVPD_VDD
Undervoltage lockout threshold
VVPD rising
Hysteresis
34.7 35.5
(1)
4.1
Operating current
VCC open, 40 V ≤ VVPD = VVDD ≤ 57 V, Startup completed, Measure IVPD + IVDD
Off-state current
RTN, GND and VCC open, VVPD = 30 V, Measure IVPD
330
µA
THERMAL SHUTDOWN
Turnoff temperature
145
Hysteresis (2)
(1)
(2)
159
165
13
°C
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only.
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7.7 Typical Characteristics
12.5
570
TJ = -40qC
TJ = 25qC
TJ = 125qC
568
Current Limit (mA)
VPD Bias Current (PA)
10
7.5
5
2.5
1
2
3
4
5
6
7
VPD-VSS Voltage (V)
8
9
560
-50
10
0.55
Pass FET Resistance (:)
0.6
158
156
154
152
150
-25
0
25
50
75
Junction Temperature (qC)
100
D004
0.5
0.4
0.35
-25
0
25
50
75
Junction Temperature (qC)
D005
100
125
D003
Figure 7. Pass FET Resistance vs Temperature
1.25
650
TJ = -40qC
TJ = 25qC
TJ = 125qC
CCC = 1 PF
VVDD = 10.2 V
VVDD = 35 V
Converter Start Time (ms)
1.2
550
500
450
400
350
300
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
30
35
40
45
50
VPD-VSS Voltage (V)
55
0.7
-50
60
-25
0
25
50
75
Junction Temperature (qC)
D002
Figure 8. VPD and VDD Supply Current vs Voltage
100
125
D007
Figure 9. Converter Startup Time vs Temperature
4
18
RFRS = 37.4 k:
RFRS = 60.4 k:
RFRS = 301 k:
3.75
17.5
VCC Operating Current (mA)
Soft-Start Time Period (ms)
125
0.45
0.25
-50
125
Figure 6. PoE Inrush Current Limit vs Temperature
250
25
100
0.3
148
600
0
25
50
75
Junction Temperature (qC)
Figure 5. PoE Current Limit vs Temperature
160
146
-50
-25
D001
Figure 4. Detection Bias Current vs Voltage
Inrush Current Limit (mA)
564
562
0
VPD and VDD Total Supply Current (PA)
566
17
16.5
16
15.5
3.5
3.25
3
2.75
2.5
2.25
2
1.75
1.5
1.25
15
-50
1
-25
0
25
50
75
Junction Temperature (qC)
100
D021
Figure 10. Converter Soft-Start Time vs Temperature
10
9
125
10
11
12
VCC Voltage (V)
13
14
D006
Figure 11. Controller Bias Current vs Voltage
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Typical Characteristics (continued)
800
400
Switching Frequency (kHz)
Switching Frequency (kHz)
350
300
250
200
RFRS = 37.4 k:
RFRS = 60.4 k:
RFRS = 301 k:
150
100
600
400
200
50
0
-50
0
-25
0
25
50
75
Junction Temperature (qC)
100
0
125
D008
Figure 12. Switching Frequency vs Temperature
10
15
20
25
30
35
40
45
Programmable Conductance, 106/RFRS (:-1)
50
D009
Figure 13. Switching Frequency vs Programmed Resistance
51
51
50.5
50
49.5
49
0.5
0.75
1
DTHR Voltage (V)
1.25
TJ = 25qC
DTHR Discharging Current (PA)
TJ = 25qC
DTHR Charging Current (PA)
5
50.5
50
49.5
49
0.5
1.5
0.75
D015
Figure 14. Frequency Dithering Charging Current
1
DTHR Voltage (V)
1.25
1.5
D016
Figure 15. Frequency Dithering Discharging Current
1.76
1.022
FB Regulation Voltage (V)
DTHR pk-pk Amplitude (V)
1.021
1.02
1.019
1.018
1.017
1.016
1.755
1.75
1.745
1.015
1.014
-50
-25
0
25
50
75
Junction Temperature (qC)
100
1.74
-50
125
Figure 16. Frequency Dithering Peak-to-Peak Amplitude
0
25
50
75
Junction Temperature (qC)
100
125
D020
Figure 17. Feedback Regulation Voltage vs Temperature
50
80
48
78
46
Blanking Period (ns)
Slope Compensation Current (PA)
-25
D017
44
42
40
76
74
72
38
36
-50
-25
0
25
50
75
Junction Temperature (qC)
100
70
-50
125
D010
Figure 18. Current Slope Compensation Current vs
Temperature
-25
0
25
50
75
Junction Temperature (qC)
100
125
D011
Figure 19. Blanking Period vs Temperature
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Typical Characteristics (continued)
50
Converter Current Limit Delay (ns)
Converter PWM Comparator Delay (ns)
50
48
46
44
42
40
-50
-25
0
25
50
75
Junction Temperature (qC)
100
44
42
-25
0
25
50
75
Junction Temperature (qC)
D013
100
125
D012
Figure 21. Converter Current Limit Delay vs Temperature
12
4
TJ = -40qC
TJ = 25qC
TJ = 125qC
COMP Sinking Current (mA)
COMP Sourcing Current (mA)
46
40
-50
125
Figure 20. Converter PWM Comparator Delay vs
Temperature
3
2
1
0
0.8
1.6
2.4
3.2
COMP Voltage (V)
4
4.8
10
8
6
4
TJ = -40qC
TJ = 25qC
TJ = 125qC
2
0
0.5
0
5.6
1
1.5
D018
Figure 22. Error Amplifier Source Current
2
2.5
COMP Voltage (V)
3
3.5
4
D019
Figure 23. Error Amplifier Sink Current
100
135
TJ = -40qC
TJ = 25qC
TJ = 125qC
90
80
TJ = -40qC
TJ = 25qC
TJ = 125qC
120
105
70
Phase Margin (q)
Gain Amplitude (dB)
48
60
50
40
30
20
10
90
75
60
45
30
0
15
-10
-20
100
1k
10k
100k
Frequency (Hz)
0
100
1M
1k
D023
Figure 24. Error Amplifier Gain vs Frequency
10k
100k
Frequency (Hz)
1M
D024
Figure 25. Error Amplifier Phase vs Frequency
Switching FET Resistance (:)
1.4
1.2
1
0.8
0.6
0.4
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
D014
Figure 26. Switching FET Resistance vs Temperature
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8 Detailed Description
8.1 Overview
The TPS23755 device is a 24-pin integrated circuit that contains all of the features needed to implement an
IEEE802.3at Type-1 powered device (PD), combined with a fully integrated 150-V switching power FET and a
current-mode DC-DC controller optimized for flyback switching regulator designs using primary side control. The
TPS23755 applies to single-output flyback converter applications where a secondary side diode rectifier is used.
Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during
startup. DC-DC converter features include startup function and current mode control operation. The TPS23755
device integrates a low 0.36-Ω internal switch to support Type-1 applications.
The TPS23755 features secondary auxiliary power detect (AUX_D) capability, providing priority for a secondary
side power adapter, while ensuring smooth transition (via AUX_V) to and from the PoE power input.
The TPS23755 device contains several protection features such as ƒ, current limit foldback, and a robust 100-V
internal return switch.
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8.2 Functional Block Diagram
VDD
COMP
VCC
Regulator
FB
50k
Vrefc
(1.75V)
t
+ E/A
+
t
50k
+
chrg
disch
0.25 V
Converter off
from PD
RTN
Soft Start
uvlo
Control
disch
chrg
VB
Regulator
Reference
Current Ramp
+
40 A (pk)
t
SRF
0.75 V
CS
DRAIN
3.75k
1 D
Q
CLRB
+
0.55 V
Timing
Blanking
Control
RSNS
CLK
t
SRR
FRS
CP
Oscillator
CP
DTHR
GND
AUX V
5V
AUX_D
RTN
RTN
12.1V &
11V
VPD
22V &
21.2V
Detection
Comp.
Class
Comp.
4V
Class
Comp.
VSS
1.25V
REG.
400µS
12.3V
& 1V
DEN
CLS
800Ps
Converter OFF
S
Q
R
Inrush latch
35.5V &
31V
OTSD
UVLO
Comp.
Inrush limit
threshold 1
Current limit
0
threshold
High if over
temperauture
1
IRTN sense
0
VSS
Signals referenced to VSS unless
otherwise noted
Hotswap
MOSFET
RTN
IRTN sense,1 if < 90% of inrush and current limit
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8.3 Feature Description
See Figure 38 for component reference designators (RCS for example ), and Electrical Characteristics: DC-DC
Controller Section for values denoted by reference (VCSMAX for example). Electrical Characteristic values take
precedence over any numerical values used in the following sections.
8.3.1 CLS Classification
An external resistor (RCLS in Figure 38 ) connected between the CLS pin and VSS provides a classification
signature to the PSE. The controller places a voltage of approximately 1.25 V across the external resistor
whenever the voltage differential between VPD and VSS lies from about 11 V to 22 V. The current drawn by this
resistor, combined with the internal current drain of the controller and any leakage through the internal pass
MOSFET, creates the classification current. Table 2 lists the external resistor values required for each of the PD
power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power supplied
to the downstream load, should not exceed the maximum power indicated in Table 2. The TPS23755 supports
class 0 – 3 power levels.
Table 2. Class Resistor Selection
CLASS
POWER AT PD PI
RESISTOR (Ω)
MINIMUM (W)
MAXIMUM (W)
0
0.44
12.95
649
1
0.44
3.84
121
2
3.84
6.49
68.1
3
6.49
12.95
45.3
8.3.2 DEN Detection and Enable
DEN pin implements two separate functions. A resistor (RDEN in Figure 38) connected between VPD and DEN
generates a detection signature whenever the voltage differential between VPD and VSS lies from approximately
1.4 to 11 V. Beyond this range, the controller disconnects this resistor to save power. The IEEE 802.3at standard
specifies a detection signature resistance, RDEN from 23.75 kΩ to 26.25 kΩ, or 25 kΩ ± 5%. TI recommends a
resistor of 24.9 kΩ ± 1% for RDEN.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turn
off. If the resistance connected between VDD and DEN is divided into two roughly equal portions, then the
application circuit can disable the PD by grounding the tap point between the two resistances, while
simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.
8.3.3 Internal Pass MOSFET
RTN pin provides the negative power return path for the load. It is internally connected to the drain of the PoE
hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground
plane) for the DC-DC controller and converter primary to maintain signal integrity.
Once VVPD exceeds the UVLO threshold, the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents
the RTN current from exceeding a nominal value of about 140 mA until the bulk capacitance (CBULK in Figure 38)
is fully charged. Inrush ends when the RTN current drops below about 125 mA. The RTN current is subsequently
limited to about 0.45 A
If RTN ever exceeds about 12.3 V for longer than 400 μs, then the PD returns to inrush limiting.
8.3.4 DC-DC Controller Features
The TPS23755 device DC-DC controller implements a typical current-mode control as shown in Functional Block
Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, gate
driver and switching power FET. In addition, an internal current-compensation ramp generator, frequency
synchronization logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source
with control are provided.
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The TPS23755 is optimized for isolated converters, and it includes an internal error amplifier. The voltage
feedback is from the bias winding. The COMP output of the error amplifier is directly fed to a 2:1 internal resistor
divider and an offset of VZDC/2 (approximately 0.75 V) which defines a current-demand control for the pulse width
modulator (PWM). A VCOMP below VZDC stops converter switching, while voltages above (VZDC + 2 × (VCSMAX +
VSLOPE)) does not increase the requested peak current in the switching MOSFET.
The internal start-up current source and control logic implement a bootstrap-type startup. The startup current
source charges CCC from VDD and maintain its voltage when the converter is disabled or during the soft-start
period, while operational power must come from a converter (bias winding) output.
The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual
power loss of external resistors.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 28 to increase
slope compensation. This makes it easier to design the current limit to a fixed value.
The DC-DC controller has an OTSD that can be triggered by heat sources including the power switching FET
and GATE driver. The controller OTSD turns off the switching FET and resets the soft-start generator.
8.3.4.1 VCC, VB and Advanced PWM Startup
The VCC pin connects to the auxiliary bias supply for the DC-DC controller. The switching MOSFET gate driver
draws current directly from the VB pin, which is the output of an internal 5V regulator fed from VCC. A startup
current source from VDD to VCC implements the converter bootstrap startup. VCC must receive power from an
auxiliary source, such as an auxiliary winding on the flyback transformer, to sustain normal operation after
startup.
The startup current source is turned on during the inrush phase, charging CCC and maintaining its voltage, and it
is turned off only after the DC-DC soft-start cycle has been completed, which occurs when the DC-DC converter
has ramped up its output voltage, as shown in Figure 27. Internal loading on VCC and VB is initially minimal
while CCC charges, to allow the converter to start. Due to the high current capability of the startup source, the
recommended capacitance at VCC is relatively small, typically 1 μF in most applications.
Once VVCC falls below its UVLO threshold, the converter shuts off and the startup current source is turned back
on, initiating a new PWM startup cycle.
High current startup is ON for the whole soft-start
cycle to allow low VCC capacitance
VCC Startup Source ON
End of Soft-Start, Startup source
turned off
PD + Power Supply Fully
Operational
HSW cap
recharge
Soft Start
Figure 27. Advanced Startup
8.3.4.2 CS, Current Slope Compensation and blanking
The current-sense input for the DC-DC converter should be connected to the high side of the current-sense
resistor of the switching MOSFET. The current-limit threshold, VCSMAX, defines the voltage on CS above which
the switching FET ON-time is terminated regardless of the voltage on COMP output.
Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy
traces such as DRAIN and CP, and to a lower degree to SRR and SRF.
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Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)
current for stability at duty cycles near and over 50%. The TPS23755 has a maximum duty cycle limit of 78.5%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 78.5%, converters may be designed that run at duty cycles well below this for a
narrower, 36-V to 57-V range. The TPS23755 provides a fixed internal compensation ramp that suffices for most
applications. RS (see Figure 28) may be used if the internally provided slope compensation is not enough. It
works with ramp current (IPK = ISL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on.
The IPK specification does not include the approximately 5-μA fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp
voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section specifies the slope
peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is
based on the full period, compute RS per Equation 1 where VSLOPE, DMAX, and ISL-EX are from Electrical
Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is unitless (for
example, DMAX = 0.78).
R S :3; =
VSLOPE (mV)
WD
AC
MAX
× 1000
ISL EX (JA)/DMAX
BVSLOPE _D :mV; F @
(1)
DRAIN
GND
RTN
RSNS
CS
RS
CS
RCS
Figure 28. Additional Slope Compensation
Blanking provides an interval between the FET gate drive going high and the current comparator on CS actively
monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the
comparator is active, preventing undesired short duty cycles and premature current limiting.
The TPS23755 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach, for example if the presence of RS causes increased noise,
due to adjacent noisy signals, to appear at CS pin. The TPS23755 provides a pulldown on CS (approximately
400 Ω) during the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-tocycle carry-over voltage on CS.
8.3.4.3 COMP, FB, CP and Opto-less Feedback
The TPS23755 DC-DC controller implements current-mode control, using a voltage control loop error amplifier
(pins FB and COMP) to define the input reference voltage of the current mode control comparator which
determines the switching MOSFET peak current. Loop compensation components are connected between
COMP and FB.
VCOMP below VZDC causes the converter to stop switching. The maximum (peak) current is requested at
approximately (VZDC + 2 × (VCSMAX + VSLOPE)). The AC gain from COMP to the PWM comparator is 0.5.
The TPS23755 DC-DC controller can operate with feedback from an auxiliary winding of the flyback power
transformer, eliminating the need for external shunt regulator and optocoupler. It also operates with continuously
connected feedback, enabling better optimization of the power supply, and resulting in significantly lower noise
sensitivity.
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The TPS23755 applies to single-output flyback converter applications where a secondary side diode rectifier is
used. In typical 12 V output application and when combined with a correctly designed power transformer, ±5%
load regulation over a wide (5% to 100%) output current range can be achieved.
8.3.4.4 FRS Frequency Setting and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23755 converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the
current-compensation ramp circuit, making the ramp height independent of frequency. RFRS must be selected per
Equation 2.
R FRS (k3) =
15000
fSW (kHz)
(2)
The TPS23755 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse ( > 35 ns) of magnitude VSYNC to FRS as shown in Figure 29. RFRS must be chosen so
that the maximum free-running frequency is just below the desired synchronization frequency. The
synchronization pulse terminates the potential ON-time period, and the OFF-time period does not begin until the
pulse terminates. A short pulse is preferred to avoid reducing the potential ON-time.
TSYNC
RFRS
FRS
47pF
TSYNC
1000pF
VSYNC
RTN
47pF
Synchronization
Pulse
RFRS
FRS
RT
Synchronization
Pulse
RTN
Figure 29 shows examples of nonisolated and transformer-coupled synchronization circuits. RT reduces noise
susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because
it is high impedance.
1:1
VSYNC
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Synchronization
8.3.4.5 Frequency Dithering for Spread Spectrum Applications
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 have
requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.
A technique referred to as frequency dithering can also be used to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements.
Frequency dithering is a built-in feature of the TPS23755. The oscillator frequency can be dithered by connecting
a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor, CDTR (Figure 38), is
selected to define the modulation frequency fm. This capacitor is being continuously charged and discharged
between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink equivalent to approximately 3x
the current through FRS pin. CDTR value is defined according to:
CDTR =
3W
R FRS (3)
2.052 × fm (Hz)
(3)
fm should always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission
measurement. Typically, fm should be set to around 11 kHz to account for component variations.
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The resistor RDTR is used to determine ∆f, which is the amount of dithering, and its value is determined according
to:
R DTR (3) =
0.513 × R FRS (3)
%DTHR
(4)
For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of
±33 kHz.
8.3.4.6 SST and Soft-Start of the Switcher
Converters require a soft-start on the voltage error amplifier to prevent output overshoot on startup. In PoE
applications, the PD also needs soft-start to limit its input current at turnon below the limit allocated by the power
source equipment (PSE).
The TPS23755 provides primary side closed loop controlled soft-start, which applies a slowly rising ramp voltage
to a second control input of the error amplifier. The lower of the reference input and soft-start ramps controls the
error amplifier, allowing the output voltage to rise in a smooth monotonic fashion.
The soft-start period of the TPS23755 is internally set to a nominal value of 16 ms.
8.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing
The TPS23755’s unique auxiliary power detect capability provides priority for a secondary side power adapter,
while ensuring smooth transition to and from the PoE power. This can be applied for example in applications
where the auxiliary power is the main power, while the PoE input acts as the backup power. The auxiliary voltage
is “Ore’d” directly at the output of flyback transformer, on secondary side. See Figure 30 below where the output
voltage is nominally 12 V.
When the auxiliary is present, a signal (AUX_D) tells the PD PWM to lower its output voltage slightly below the
auxiliary voltage to ensure the auxiliary has priority to power the main output. When the auxiliary power goes
away, the DC-DC converter increases back its output voltage, to ensure seamless transition. One significant
advantage of this approach is that the efficiency of the PoE-powered flyback power stage can be optimized
independently of the need for seamless transition. The adjustability of the lower voltage level allows the use of
highly inaccurate auxiliary voltage sources. Such feature eases the thermal design, in particular when secondary
diode rectification is used, since when PoE powered, the flyback stage can deliver power at a higher output
voltage, and hence at a lower output current.
In Figure 30 below, ROUT1 ensures that the PSE maintains power while the auxiliary is present, ensuring there
will be no power interruption when the auxiliary power is removed.
The lower voltage level is programmable with the RAUX resistor, which impacts the feedback network division
ratio. Note however that the flyback power transformer design and resistor selection must be such that VVCC will
remain above nominally 6.1 V (VCUVF) while the auxiliary power is present.
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DOUT
TPS23755
VOUT
12V
COUT
VCC
COMP
CCC
R1
CCC2
RAUX
FB
AUX_V
R2
Vout Flyback
ROUT1
RTN
Secondary
Adapter
(VADAPTER)
AUX_D
Secondary side Aux
Supply Detection
12V
< VADAPTER
Vout Flyback
~12V
VADAPTER
0V
VOUT
12V
~12V
Figure 30. Secondary Side Priority Control with Smooth Transition
8.3.5 Internal Switching FET - DRAIN, RSNS, SRF and SRR
The DRAIN and RSNS provide connection to the drain and source of the integrated switching power FET. RSNS
pin is a high current pin and it must have a short connection to the current sense resistor which other end is
directly tied to a plane referenced to the GND pin. Current sensing is done with CS pin, which should be
connected directly to the high side of the current sense resistor.
The internal FET gate driver is powered from VB voltage rail and the return path is through the GND pin. SRF
and SRR pins provide slew rate control of the switching FET. The gate sourcing current is drawn through the
SRF pin which is tied to VB pin through a resistor (0-100 Ω). The gate sinking current circulates through the SRR
pin which is externally tied to the GND pin either via a low-value resistor (0-15 Ω) or a direct connection.
8.3.6 VPD Supply Voltage
VPD pin connects to the positive side of the input supply. It provides operating power to the PD controller and
allows monitoring of the input line voltage. If VVPD falls below its UVLO threshold and goes back above it, or if a
thermal shutdown resumes while VVPD is already above its UVLO threshold, the TPS23755 returns to inrush
limiting.
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8.3.7 VDD Supply Voltage
VDD connects to the source of DC-DC converter startup current. It is connected to VPD for most applications. It
may also be isolated by a diode from VPD to support some PoE priority operation.
8.3.8 GND
GND is the power ground used by the flyback power FET gate driver and CP pin. Connect to the RTN plane. VB
bypassing capacitor should be directly connected to the GND pin.
8.3.9 VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited
hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. The
exposed thermal PAD must be connected to this pin to ensure proper operation.
8.3.10 Exposed Thermal PAD
The exposed thermal PAD is internally connected to VSS pin. It should be tied to a large VSS copper area on the
PCB to provide a low resistance thermal path to the circuit board. TI recommends maintaining a clearance of
0.025” between VSS and high-voltage signals such as VPD and VDD.
8.4 Device Functional Modes
8.4.1 PoE Overview
The following text is intended as an aid in understanding the operation of the TPS23755, but it is not a substitute
for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33
(PoE), adding high-power options and enhanced classification.
Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a Type 1 device, and devices with
high power or enhanced classification is referred to as Type 2 devices. The TPS23755 is intended to power Type
1 devices (up to 13 W), and is fully compliant to IEEE 802.3at for hardware classes 0 - 3. Standards change and
must always be referenced when making design decisions.
Detect
0
2.7
10.1 14.5
20.5
30
Maximum Input
Voltage
Must Turn On byVoltage Rising
Shutdown
Classify
3/06/08
Lower Limit Proper Operation
Must Turn Off by Voltage Falling
Classification
Upper Limit
Classification
Lower Limit
Detection
Upper Limit
Detection
Lower Limit
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then
removing power if a PD is disconnected. The process proceeds through an idle state and three operational states
of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically
looks to see if something has been plugged in; this is referred to as detection. The low power levels used during
detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may
inquire how much power the PD requires; this is referred to as (hardware) classification. Only Type 2 PSEs are
required to do hardware classification. The PD may return the default 13-W current-encoded class, or one of four
other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD must present
the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a
valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 31
shows the operational states as a function of PD input voltage.
Normal Operation
36
42
57
PI Voltage (V)
Figure 31. Operational States
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Device Functional Modes (continued)
The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the cable and operating
margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω for Type 1 devices to derive the voltage
limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power
of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE
can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between
the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000baseT systems is
recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair
terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to
accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges
create a difference between the standard limits at the PI and the TPS23755 specifications.
The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second
interval. A Type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and 450 mA
during powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0
and 3 PDs may draw up to 400-mA peak currents for up to 50 ms. The PSE may set lower output current limits
based on the declared power requirements of the PD.
8.4.2 Threshold Voltages
The TPS23755 has a number of internal comparators with hysteresis for stable switching between the various
states as shown in Figure 31. Figure 32 relates the parameters in Electrical Characteristics: DC-DC Controller
Section and Electrical Characteristics: PoE and Control to the PoE states. The mode labeled idle between
classification and operation implies that the DEN, CLS, and RTN pins are all high impedance.
Functional
State
PD Powered
Idle
Classification
VVPD-VVSS
Detection
VCL_HYS
1.4 V
VCL_ON
VCU_HYS
VUVLO_H
VCU_OFF
VUVLO_R
Note: Variable names refer to Electrical Characteristic
Table parameters
Figure 32. Threshold Voltages
8.4.3 PoE Start-Up Sequence
The waveforms of Figure 33 demonstrate detection, classification, and start-up from a Type 1 PSE. The key
waveforms shown are VVPD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels;
however, four levels are shown in this example. Four levels guard against misdetection of a device when plugged
in during the detection sequence.
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Device Functional Modes (continued)
Figure 33. PoE Start-Up Sequence
8.4.4 Detection
The TPS23755 is in detection mode whenever VVPD-VSS is below the lower classification threshold. When the
input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS.
An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only
sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and
26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and the TPS23755 bias loading. The incremental resistance of the input diode
bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge
resistance is partially cancelled by the effective resistance of the TPS23755 during detection.
8.4.5 Hardware Classification
Hardware classification allows a PSE to determine the power requirements of a PD before starting, and helps
with power management once power is applied. The maximum power entries in Table 2 determine the class the
PD must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than
its stated Class power. The standard permits the PD to draw limited current peaks; however, the average power
requirement always applies.
Voltage from 14.5 V to 20.5 V is applied to the PD for up to 75 ms during hardware classification. A fixed output
voltage is sourced by the CLS pin, causing a fixed current to be drawn from VPD through RCLS. The total current
drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured and
decoded by the PSE to determine which of the five available classes is advertised (see Table 2). The TPS23755
disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off during PD
thermal limit or when DEN is active. The CLS output is inherently current-limited, but should not be shorted to
VSS for long periods of time.
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Device Functional Modes (continued)
8.4.6 Maintain Power Signature (MPS)
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (at a duty cycle of at least 75 ms on
every 225 ms) and an AC impedance lower than 26.25 kΩ in parallel with 0.05 μF. The AC impedance is usually
accomplished by the minimum CBULK requirement of 5 μF. When DEN is used to force the hotswap switch off, the
DC MPS is not met. A PSE that monitors the DC MPS will remove power from the PD when this occurs. A PSE
that monitors only the AC MPS may remove power from the PD.
8.4.7 Start-Up and Converter Operation
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full
voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits discharges CDD, CCC, and CVB while the PD is unpowered. Thus VVDD-RTN will
be a small voltage until just after full voltage is applied to the PD, as seen in Figure 33.
The PSE drives the PD input voltage to the operating range once it has decided to power up the PD. When VPD
rises above the UVLO turnon threshold (VUVLO-R, approximately 35.5 V) with RTN high, the TPS23755 enables
the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 34 for
an example. Converter switching is disabled while CDD charges and VRTN falls from VVDD to nearly VVSS;
however, the converter start-up circuit is allowed to charge CCC. Once the inrush current falls about 10% below
the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter
switching is permitted.
Converter switching is allowed if the PD is not in inrush current limit and the VCC under-voltage lockout (VCUVR)
circuit permits it. Continuing the start-up sequence shown in Figure 34, VVCC rises as the start-up current source
charges CCC and the converter switching is inhibited by the status of the VCC UVLO. The VB regulator powers
the internal converter circuits as VVCC rises.
Once VVCC goes above its UVLO (nominally 8.25 V), the converter switching is enabled following the closed loop
controlled soft-start sequence. Note that the startup current source capability is such that it can fully maintain
VVCC during the converter soft-start without requiring any significant CCC capacitance, in 48 V input applications.
At the end of the soft-start period, the startup current source is turned off. VVCC falls as it powers the internal
circuits including the switching MOSFET gate. If the converter control-bias output rises to support VVCC before it
falls to VCUVF (nominally 6.1 V), a successful start-up occurs. Figure 34 shows a small droop in VVCC while the
output voltage rises smoothly and a successful start-up occurs.
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Device Functional Modes (continued)
50V/div
VVDD-RTN
Converter
starts
PI powered
Inrush
100mA/div
IPI
VVCC-RTN
Startup turn off
5V/div
10V/div
VOUT
OUTPUT VOLTAGE
SOFT START
Time: 10ms/div
Figure 34. Power Up and Start
The converter shuts off when VVCC falls below its lower UVLO. This can happen when power is removed from the
PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including
the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off. A restart
initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is sometimes referred
to as hiccup mode, which when combined with the soft-start provides robust output short protection by providing
time-average heating reduction of the output rectifier.
Figure 35 illustrates the situation when there is severe overload at the main output which causes VCC hiccup.
After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start
cycle is reinitiated, introducing a short pause before the output voltage is ramped up.
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Device Functional Modes (continued)
VOUT overload
Converter
Turn off then restart
IPI
100mA/div
Startup turn off
VVCC-RTN
VCC
UVLO
5V/div
10V/div
VOUT
OUTPUT VOLTAGE
SOFT START
COOL DOWN
Time: 10ms/div
Figure 35. Restart Following Severe Overload at Main Output of Flyback DC-DC Converter
If VVPD-VSS drops below the lower PoE UVLO (UVLO_R – UVLO_H, approximately 31 V), the hotswap MOSFET
is turned off, but the converter still runs. The converter stops if VVCC falls below the VCUVF (nominally 6.1 V), the
hotswap is in inrush current limit, the SST pin is pulled to ground, VVDD-RTN falls below typically 7.7 V
(approximately 0.75 V hysteresis) or the converter is in thermal shutdown.
8.4.8 PD Self-Protection
The PD section has the following self-protection functions.
• Hotswap switch current limit
• Hotswap switch foldback
• Hotswap thermal protection
The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The
PSE output cannot be relied on to protect the PD MOSFET against transient conditions, requiring the PD to
provide fault protection. High stress conditions include converter output shorts, shorts from VDD to RTN, or
transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a
result. If VRTN rises above approximately 12.3 V for longer than approximately 400 μs, the current limit reverts to
the inrush limit, and turns the converter off. The 400-μs deglitch feature prevents momentary transients from
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Device Functional Modes (continued)
causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 36
shows an example of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current
limit, overshooting to a relatively low current, recovers to 420-mA, full-current limit, and charges the input
capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VSS was
below 12 V after the 400-μs deglitch.
IPI
200mA/div
CBULK completes
charge while converter
operates
VVSS-RTN § -15V
10V/div
VVPD-VSS
20V/div
Time: 200us/div
Figure 36. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or
operation into a VPD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD
restarts in inrush current limit when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature
allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous
converter topologies that can deliver power in both directions.
The hotswap switch is forced off under the following conditions:
• VDEN ≤ VPD_DIS when VVPD-VSS is in the operational range
• PD over temperature
• VVPD-VSS < PoE UVLO (approximately 31 V).
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Device Functional Modes (continued)
8.4.9 Adapter ORing
VSS
VDD
VPD
DEN
CLS
Low Voltage
Output
Power
Circuit
TPS23755
RCLS
58V
From Spare
Pairs or
Transformers
0.1uF
RDEN
From Ethernet
Transformers
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
installation. While most applications only require that the PD operate when both sources are present, the
TPS23755 device supports forced operation from either of the power sources. Figure 37 illustrates three options
for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1
applies power to the device input, option 2 applies power between the device PoE section and the power circuit,
and option 3 applies power to the output side of the converter. Each of these options has advantages and
disadvantages. Many of the basic ORing configurations and much of the discussion contained in the application
note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306), apply to the TPS23755.
RTN
Adapter
Option 1
Adapter
Option 2
Adapter
Option 3
Figure 37. ORing Configurations
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary
for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the
combinations. However, the TPS23755 device offers several built-in features that simplify some combinations.
Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE
(option 1) presents the problem that either source might be higher. A blocking switch would be required to assure
which source was active. A second example is combining a 12-V adapter with PoE using option 2. The converter
draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition
from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be
turned off while CBULK capacitance charges, with a subsequent converter restart at the higher voltage and lower
input current. A third example is use of a 12-V adapter with ORing option 1. The PD hotswap would have to
handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal power. A
fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the
PD. If adapter power is then lost, the PD stops operating until the PSE detects and powers the PD.
The TPS23755 has a unique feature that can be used to achieve seamless transition while applying option 3. It
provides adapter priority by reducing the DC-DC output voltage when the adapter voltage is present. An
optocoupler is typically driven from the secondary side of the converter when the adapter voltage is present,
which commands the converter voltage to go down to a predetermined voltage level, by use of pins AUX_D and
AUX_V. This voltage level is lower than the minimum adapter voltage to ensure priority. The DC-DC converter
stays in operation, which with appropriate minimum loading can ensure the PSE power will be maintained, to
ensure there will be no output power interruption next time the adapter voltage goes down.
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Device Functional Modes (continued)
The IEEE standards require that the PI conductors be electrically isolated from ground and all other system
potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test
between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option
3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS23755 supports power supply topologies that require a single PWM gate drive with current-mode
control. Figure 38 provides an example of a simple diode rectified primary-side-regulated flyback converter.
9.2 Typical Application
CBULK
DOUT
+
TPS23755
From Ethernet
Transformers
CCL
RCL
12 V
COUT
DCL
VDD
VPD
RDEN
DRAIN
DEN
RCS
DCC
RSNS
D1
C1
T1
CLS
From Spare Pairs
or Transformers
RVCC
RS
CS
R1
RCLS
VCC
VSS
CCC
COMP
CCOMP
FRS
CCC2
R2
RCOMP
FB
RAUX
RDTR
AUX_V
CP
DTHR
RFRS
AUX_D
RTN
CDTR
VB
GND
SRR
Optional
(For secondary side aux
supply detection)
SRF
RSRF
CVB
RSRR
Figure 38. Basic TPS23755 Implementation
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Typical Application (continued)
VOUT
CD
+
CBULK
RS
COUT
From Ethernet
Transformers
TPS23755
RD
LOUT
VDD
RDEN
VPD
DRAIN
DEN
RCS
RSNS
0.1 F
RFB2
CLS
CS
RCLS
From Spare Pairs
or Transformers
58V
Q1
CCC
VCC
VSS
CCOMP2
COMP
CCOMP1
FRS
RCOMP
FB
RDTR
CP
DTHR
RFB
AUX_D
CDTR
RFRS
RTN
GND
VB
SRR
CVB
SRF
RSRF
RSRR
Figure 39. Simplified Buck Application
9.2.1 Design Requirements
Selecting a converter topology along with a design procedure is beyond the scope of this applications section.
The TPS23755 is optimized for primary-side-regulated diode rectified flyback topologies for 12 V outputs or
higher due to its good balance of high efficiency and output regulation. Typical applications use post regulation to
power the system load's lower voltage rails. The TPS23755 can also be used in non-isolated buck topology
application like shown in Figure 39.
Examples to help in programming the TPS23755 in a primary-side regulated flyback are shown below. For more
specific converter design examples refer to the TPS23755EVM-894 EVM: Evaluation Module for TPS23755.
Table 3. Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER INTERFACE
Input voltage
Applied to the PoE Input
37
Applied to the Secondary Input
57
12
V
V
Detection voltage
At device terminals
2.7
10.1
Classification voltage
At device terminals
14.5
20.5
V
V
Classification current
RCLASS = 45.3 Ω
26.5
29.3
mA
Inrush current-limit
140
mA
Operating current-limit
550
mA
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Typical Application (continued)
Table 3. Design Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-TO-DC CONVERTER
Output voltage
VIN = 48 V, ILOAD ≤ ILOAD (max)
Output current
37 V ≤ VIN ≤ 57 V
Output ripple voltage peak-to-peak
Efficiency, end-to-end
12
V
1
A
VIN = 48 V, ILOAD = 1 A
50
mV
VIN = 48 V, ILOAD= 100mA
78
VIN = 48 V, ILOAD = 500mA
86
VIN = 48 V, ILOAD = 1 A
87
Switching frequency
250
%
kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Input Bridges and Schottky Diodes
Using Schottky diodes instead of PN junction diodes for the PoE input bridges reduces the power dissipation in
these devices by about 30%. There are, however, some things to consider when using them. The IEEE standard
specifies a maximum backfeed voltage of 2.8 V. A 100-kΩ resistor is placed between the unpowered pairs and
the voltage is measured across the resistor. Schottky diodes often have a higher reverse leakage current than
PN diodes, making this a harder requirement to meet. To compensate, use conservative design for diode
operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by
using packaged bridges.
Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting
reasonable expectations for the temperature range over which the detection signature is accurate is the simplest
solution. Increasing RDEN slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After
exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate
protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors.
As a general recommendation, use 0.8A-1A, 100-V rated discrete or bridge diodes for the input rectifiers.
9.2.2.2 Protection, D1
A TVS, D1 , across the rectified PoE voltage per Figure 38 must be used. A SMAJ58A, or equivalent, is
recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient
voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional
protection.
9.2.2.3 Capacitor, C1
The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF.
Typically a 0.1 μF, 100 V, 10% ceramic capacitor is used.
9.2.2.4 Detection Resistor, RDEN
The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.7 kΩ and 26.3 kΩ, or 25
kΩ ± 5%. Typically a 24.9 kΩ ± 1% is used.
9.2.2.5 Classification Resistor, RCLS
Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at
standard. The class power assigned should correspond to the maximum average power drawn by the PD during
operation. Select RCLS according to Table 2. For example, Class 3 applications should use a 45.3 Ω resistor for
RCLS.
32
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9.2.2.6 Bulk Capacitance, CBULK
The bulk capacitance, CBULK must furnish input transients during heavy loads and long cable length conditions. It
also helps with stability on the DC/DC converter. It is recommended to use a minimum 10 uF, electrolytic
capacitor.
9.2.2.7 Output Voltage Feedback Divider, RAUX, R1,R2
R1, R2 and RAUX set the output voltage of the bias winding of the converter. For applications that do not use
AUX_D functionality, RAUX should not be populated and Equation 5 should be used.
V VCC
VREFC R1 R 2
R2
(5)
For secondary side adapter priority applications, the DC/DC output voltage can be set lower than the adapter
voltage by pulling AUX_D to RTN. Equation 6 should be used first to determine the lower output voltage when
adapter is present.
V VCC
VREFC R1 R 2
R2
when Aux_D is LOW.
(6)
Then Raux can be calculated using Equation 7 to set the nominal output voltage of the bias winding.
V VCC
VREFC R1 R AUX
R1 R 2
R 2 R Aux
R 2 R AUX
when Aux_D is HIGH.
(7)
When transitioning from the normal operating output voltage to a lower output voltage when Aux_D is pulled
LOW, switching may stop until the VCC voltage can reduce its voltage to the lower VCC voltage. The output
voltage may drop during this time due to the loss of switching. Typically this is not a concern since the adapter is
providing power to the load. A combination of adding a dummy load in parallel with CCC and increasing the
secondary output capacitance can minimize the time that switching stops.
In applications that use smooth transition between adapter the PoE, circuitry should be added to keep the PSE
connected to the PD and the converter operational while maintaining adapter priority. It is recommended to refer
to the TPS23755EVM-894.
9.2.2.8 Setting Frequency, RFRS
The converter switching frequency in PWM mode is set by connecting resistor, RFRS from the FRS pin to RTN.
For a converter that requires a 250 kHz switching frequency and using Equation 8
R FRS k:
15000
f SW kHz
15000
250 kHz
60 k:
(8)
A standard 60.4 kΩ resistor should be used.
9.2.2.9 Frequency Dithering, RDTR and CDTR
For optimum EMI performance, CDTR and RDTR should be selected as described in Frequency Dithering for
Spread Spectrum Applications in Equation 9 and Equation 10.
3
C DTR nF
R DTR :
3
R FRS :
2.052 u f m Hz
0.513 u R FRS :
%DTHR
60.4 k:
2.052 u 11000 Hz
0.513 u 60.4k:
0.132
2.2 nF
(9)
235 k:
(10)
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A standard 237 kΩ resistor should be used.
9.2.2.10 Transformer design, T1
The turns ratio and primary inductance are important parameters to consider in a flyback transformer. The turns
ratio act to limit the max duty cycle and reduce stress on the secondary components while the primary
inductance sets the current ripple. In CCM operation, the higher inductance allows for a reduced current ripple
which can help with EMI performance and noise.
For primary-side regulated flyback converters, the transformer construction is important to maintain good
regulation on the secondary output. It is recommended to use LDT0950 for 12 V applications.
9.2.2.11 Current Sense Resistor, RCS
RCS should be chosen based on the peak primary current at the desired output current limit.
R CS
V CSMAX
I Pk
Pr imary
(11)
9.2.2.12 Current Slope Compensation, RS
RS may be used if the internally provided slope compensation is not enough. The down slope of the reflected
secondary current through the current sense resistor at each switching period is determined and a percentage
(typically 50%-75%) of it will define Vslope. Using LDT0950, it is recommended to start with 251 mV and use
Equation 12.
RS :
ª
« V SLOPE mV
D
«¬
I SL
EX
§ V SLOPE mV
¨
¨
D MAX
©
PA
·º
¸»
¸
¹ ¼»
D MAX
u 1000
ª
§ 155 mV · º
«251 mV ¨
¸»
© 78.5% ¹ ¼
¬
u 1000
42 PA
78.5%
1 k:
(12)
9.2.2.13 Bias Supply Requirements, CCC, DCC
Advanced startup in the TPS23755 allows for relatively low capacitance on the bias circuit. It is recommended to
use a 1 uF 10% 25 V ceramic capacitors on CCC. DCC can be a low cost, general-purpose diode. It is
recommended to use MMSD4148 diode (100 V, 200 mA).
9.2.2.14 Switching Transformer Considerations, RVCC and CCC2
RVCC helps to reduce peak charging from the bias winding. Reduced peak charging becomes especially
important when tuning hiccup mode operation during output overload. A typical value for RVCC in Class 3 PoE PD
applications while maintaining a suitable load regulation is 10 ohms.
9.2.2.15 Primary FET Clamping, RCL, CCL, and DCL
The stored energy in the leakage inductance of the power transformer can cause ringing during the primary FET
turnoff. The snubber must be chosen to mitigate primary FET overshoot and oscillation while maintaining high
overall efficiency.
It is recommended to use 39 kΩ (125 mW) for RCL and 0.1 uF (100 V) for CCL.
DCL should be an ultra-fast diode with a short forward recovery recovery time allowing the snubber to turn on
quickly. The 200 V / 1 A rated diode with a recovery time approximately 25 ns or better is recommended.
9.2.2.16 Converter output capacitance, COUT
The output capacitor is considered as part of the overall stability of the converter, the output voltage ripple, and
the load transient response. The output capacitor needs to be selected based on the most stringent of these
criteria. The minimum capacitance is typically determined by the output voltage ripple shown in Equation 13.
34
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C OUT !
I OUT A u D max
VRipple V u f SW Hz
where Dmax is the calculated operating max duty cycle shown in Equation 14
D max
V OUT
VIN min
(13)
VDiode u N PS
V OUT
VDiode u N PS
(14)
For strict load transient requirements, the COUT cap may need to be increased. The TPS23755EVM-894 uses
two 22 uF ceramic capacitors for an optimized load transient response.
9.2.2.17 Secondary Output Diode Rectifier, DOUT
The output rectifier diode must provide low forward voltage drop at the secondary peak current. Consideration
must be given to a safe operating area during output overload conditions.
For a 12 V output, PDS360-13 in a high thermal performance package (60 V reverse voltage, 3-A continuous
current max, Vf = =0.62 V max at 3A ) is used in the TPS23755EVM-894.
9.2.2.18 Slew rate control, RSRF and RSRR
RSRF and RSRR minimize primary drain-source oscillations and help optimize EMI performance at high
frequencies, the value chosen should be within the recommend operating conditions table in Recommended
Operating Conditions. It is recommended to start with 10 ohms for RSRF and 10 ohms for RSRR then adjust
accordingly during bench and EMI testing.
9.2.2.19
Shutdown at Low Temperatures, DVDD and CVDD
For applications operating near –10°C or less, there may be some extra switching cycles during removal of the
PoE input or during shutdown. It is acceptable for most applications; however, for a more monotonic shutdown of
the output voltage during power removal, it is recommended to use DVDD and CVDD as shown in Figure 40. DVDD
can be MMSD4148 and CVDD can be 0.22 uF 100 V capacitor.
From Ethernet
Transformers
DVDD
CBULK
+
CVDD
VDD
VPD
From Spare Pairs
or Transformers
C1
D1
TPS23755
VSS
Figure 40. DVDD and CVDD Configuration for Low Temperature Conditions
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9.2.3 Application Curves
VDD-VSS
RTN-VSS
IIN
Figure 41. TPS23755 Startup to TPS23861 PSE
Figure 42. TPS23755 PSR Flyback Startup to Full Load
Figure 43. TPS23755 Output Short and Recovery
Figure 44. Slew Rate Adjust SRR = 15 Ω
Figure 45. Slew Rate Adjust SRR = 0 Ω
Figure 46. Slew Rate Adjust SRF = 0 Ω
12.4
IL = 100 mA
IL = 1A
Output Voltage (V)
12.3
12.2
12.1
12
11.9
11.8
11.7
-40
-20
0
20
40
Temperature (qC)
60
80
100
D027
Figure 47. Output Regulation vs. Ambient Temperature
36
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Figure 48. Slew Rate Adjust SRF = 100 Ω
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10 Power Supply Recommendations
The TPS23755 converter should be designed such that the input voltage of the converter is capable of operating
within the IEEE802.3at recommended input voltage as shown in Figure 31 and the minimum operating voltage of
the adapter if applicable.
11 Layout
11.1 Layout Guidelines
The TPS23755 IC’s layout footprint shown in the Example Board Layout should be strictly followed. The below
list are key highlights for layout consideration around the TPS23755.
•
•
•
Pin 22 of the TPS23755 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN).
Therefore, the Pin 22 footprint should be removed when laying out the TPS23755.
It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer
plane (2 oz copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal
dissipation.
The Pin24 of the TPS23755 should be near the power transformer and the current sense resistor should be
close to Pin 1 of the TPS23755 to minimize the primary loop.
The layout of the PoE front end should follow power and EMI or ESD best-practice guidelines. A basic set of
recommendations includes:
• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode
bridges, TVS and 0.1 μF capacitor, and TPS23755 converter input bulk capacitor.
• Make all leads as short as possible with wide power traces and paired signal and return.
• No crossovers of signals from one part of the flow to another are allowed.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48 V input voltage
rails and between the input and an isolated converter output.
• Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper
fills in the power path.
The DC-to-DC converter layout benefits from basic rules such as:
• Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes
to help with thermal dissipation of the power transformer.
• Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground
through multiple layer planes to help with thermal dissipation of the power transformer.
• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include
the power semiconductors and magnetics.
• Minimize the trace length of high current power semiconductors and magnetic components.
• Where possible, use vertical pairing.
• Use the ground plane for the switching currents carefully.
• Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside
the power supply.
• Maintain proper spacing around the high-voltage sections of the converter.
11.2 Layout Example
Figure 49 and Figure 50 show the top and bottom layer and assemblies of the TPS23755EVM-894 as a
reference for optimum parts placement.
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Layout Example (continued)
Figure 49. Top Side and Routing
38
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Layout Example (continued)
Figure 50. Bottom Side Placement and Routing
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V.
Comiskey, TI, SLUA469
• TPS23755EVM-894: Evaluation Module for TPS23755, SLUG
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RJJ0023B
VSON - 1 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
6.1
5.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
4X (0.4)
4X ( 0.25)
20X 0.4
(0.2) TYP
1.9 0.1
A3
A2
4X (0.45)
12
13
EXPOSED
THERMAL PAD
5.5 0.1
2X
4.4
SYMM
25
23X
24
1
A1
PIN 1 ID
0.25
0.15
0.1
0.05
C B A
A4
SYMM
23X
10X (0.2)
0.5
0.3
8X (0.4)
2X (1.6)
4223621/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RJJ0023B
VSON - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
(1.9)
10X (0.2)
SYMM
4X ( 0.25)
23X (0.6)
A1
23X (0.2)
A4
1
24
4X (2.675)
( 0.2) TYP
VIA
20X (0.4)
25
SYMM
(5.5)
(1.32)
TYP
SOLDER MASK
OPENING
(R0.05) TYP
ALL PAD CORNERS
13
12
METAL UNDER
SOLDER MASK
A2
A3
(0.45) TYP
8X
(0.4)
4X (1.725)
(0.6)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223621/B 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RJJ0023B
VSON - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
8X (0.85)
4X ( 0.25)
23X (0.6)
A1
23X (0.2)
A4
1
24
8X (1.12)
4X (2.675)
20X (0.4)
SOLDER MASK
OPENING
25
SYMM
(5.94)
(0.66) TYP
(R0.05) TYP
(1.32) TYP
METAL UNDER
SOLDER MASK
12
13
A3
A2
10X (0.46)
(0.525) TYP
4X (1.725)
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
THERMAL PAD 25: 73%
SCALE:20X
4223621B 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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24-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS23755RJJR
ACTIVE
VSON
RJJ
23
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TPS23755
TPS23755RJJT
ACTIVE
VSON
RJJ
23
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TPS23755
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS23755RJJR
VSON
RJJ
23
3000
330.0
12.4
4.25
6.25
1.15
8.0
12.0
Q1
TPS23755RJJT
VSON
RJJ
23
250
180.0
12.4
4.25
6.25
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS23755RJJR
VSON
RJJ
23
3000
370.0
355.0
55.0
TPS23755RJJT
VSON
RJJ
23
250
195.0
200.0
45.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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