Texas Instruments | TPS55340-Q1 Integrated 5-A, Wide Input Range Boost, SEPIC, or Flyback DC/DC Converter (Rev. B) | Datasheet | Texas Instruments TPS55340-Q1 Integrated 5-A, Wide Input Range Boost, SEPIC, or Flyback DC/DC Converter (Rev. B) Datasheet

Texas Instruments TPS55340-Q1 Integrated 5-A, Wide Input Range Boost, SEPIC, or Flyback DC/DC Converter (Rev. B) Datasheet
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TPS55340-Q1
SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
TPS55340-Q1 Integrated 5-A, Wide Input Range
Boost, SEPIC, or Flyback DC/DC Converter
1 Features
2 Applications
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
Internal 5-A, 40-V Low-Side MOSFET Switch
2.9 to 38-V Input Voltage Range
±0.7% Reference Voltage
0.5-mA Operating Quiescent Current
2.7-µA Shutdown Supply Current
Fixed-Frequency Current Mode PWM Control
Frequency Adjustable from 100 kHz to 2.5 MHz
(see Switching Frequency)
Synchronization Capability to External Clock
Adjustable Soft-Start Time
Pulse-Skipping for Higher Efficiency at Light
Loads
Cycle-by-Cycle Current-Limit, Thermal Shutdown,
and UVLO Protection
WQFN-16 (3 mm × 3 mm) Package with
PowerPad™
Wide –40°C to +150°C Operating TJ Range
Create a Custom Design Using the TPS55340-Q1
with the WEBENCH Power Designer
•
•
Boost, SEPIC, and Flyback Topologies
Automotive Pre-Boost Applications to Support
Start-Stop Requirements
USB Power Delivery
Industrial Power Systems
3 Description
The TPS55340-Q1 device is a monolithic nonsynchronous switching converter with integrated 5-A,
40-V power switch. The device can be configured in
several standard switching-regulator topologies,
including boost, SEPIC and isolated flyback. The
device has a wide input voltage range to support
applications with input voltage from 2.9 to 38-V.
The TPS55340-Q1 device regulates the output
voltage with current mode PWM (pulse width
modulation) control, and has an internal oscillator.
The switching frequency of PWM is set by either an
external resistor or by synchronizing to an external
clock signal. The user can program the switching
frequency from 100 kHz to 2.5 MHz.
The device features a programmable soft-start
function to limit inrush current during start-up and has
other built-in protection features including cycle-bycycle over current-limit and thermal shutdown.
The TPS55340-Q1 device is available in a small 3mm × 3-mm 16-pin WQFN package with PowerPad
for enhanced thermal performance.
Device Information(1)
PART NUMBER
PACKAGE
TPS55340-Q1
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application for Boost
L
VI
D
Efficiency vs Output Current
VO
100
VIN
SW
EN
SW
FREQ
SW
SS
R(FREQ)
CSS
R(C)
C(C)
90
R(SH)
FB
COMP
PGND
SYNC
PGND
AGND
PGND
95
CO
TPS55340-Q1
85
Efficiency (%)
CI
R(SL)
80
75
70
65
60
55
VO = 24 V
VI
VI =
=5
5V
V
VI
12 V
V
VI == 12
ƒS = 600 kHz
VI == 15
VI
15 V
V
50
0.0
0.4
0.8
1.2
Output Current (A)
1.6
2.0
2.4
C021
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS55340-Q1
SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2016) to Revision B
Page
•
Added links for Webench ....................................................................................................................................................... 1
•
Added text note under pin configuration diagram. ................................................................................................................ 3
Changes from Original (June 2014) to Revision A
Page
•
Changed the Applications section .......................................................................................................................................... 1
•
Changed title from DC-DC Regulator to DC-DC Converter ................................................................................................... 1
•
Changed the Handling Ratings table to ESD Ratings and moved the storage temperature to the Absolute Maximum
Ratings table........................................................................................................................................................................... 4
•
Changed the Switching Frequency section to add recommendation for using an external synchronous clock when
setting the switching frequency higher than 1.2 MHz........................................................................................................... 10
•
Changed the equation to calculate R3 in the Compensating the Control Loop (R3, C4, and C5) section .......................... 22
•
Added the Receiving Notification of Documentation Updates and Community Resources sections .................................. 30
2
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SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
5 Pin Configuration and Functions
SW
SW
NC
PGND
16-Pin QFN With PowerPAD
RTE Package
Top View
16
15
14
13
SW
1
12
PGND
VIN
2
11
PGND
EN
3
10
NC
SS
4
PowerPAD
5
6
7
8
SYNC
AGND
COMP
FB
9
FREQ
TI recommends connecting NC with AGND.
Pin Functions
PIN
NAME
DESCRIPTION
NO.
AGND
6
Signal ground of the IC
COMP
7
Output of the transconductance error amplifier. An external RC network connected to this pin compensates the regulator
feedback loop.
EN
3
Enable pin. When the voltage of this pin falls below the enable threshold for more than 1 ms, the IC turns off.
FB
8
Error amplifier input and feedback pin for positive voltage regulation. Connect the FB pin to the center tap of a resistor divider
to program the output voltage.
FREQ
9
Switching frequency program pin. An external resistor connected between the FREQ pin and the AGND pin sets the switching
frequency.
NC
10
14
This pin is reserved and must be connected to ground.
11
PGND
12
Power ground of the IC. The PGND pin is connected to the source of the internal power MOSFET switch.
13
SS
4
Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing.
1
SW
15
SW is the drain of the internal power MOSFET. Connect the SW pin to the switched side of the boost or SEPIC inductor or the
flyback transformer.
16
SYNC
5
Switching-frequency synchronization pin. An external clock signal can set the switching frequency between 200 kHz and 1
MHz. If this pin is not used, it must be tied to AGND.
VIN
2
The input supply pin to the IC. Connect the VIN pin to a supply voltage between 2.9 V and 32 V. The voltage on the VIN pin
can be different from the boost power-stage input.
PowerPAD
The PowerPAD must be soldered to the AGND. If possible, use thermal vias to connect the PowerPAD to PCB ground-plane
layers for improved power dissipation.
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SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)
VIN (2)
EN
(2)
MIN
MAX
UNIT
–0.3
40
V
–0.3
40
V
FB, FREQ, and COMP (2)
–0.3
3
V
SS (2)
–0.3
5
V
–0.3
7
V
–0.3
40
V
–5
40
V
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Input voltage
SYNC
SW (2)
Output voltage
(1)
(2)
(2)
SW (<10 ns transient) (2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VI
Input voltage
VO
Output voltage
V(EN)
EN voltage
VSYN
External switching-frequency logic input
TA
TJ
NOM
MAX
UNIT
2.9
38
V
VI
38
V
0
38
V
0
5
V
Operating free-air temperature
–40
125
°C
Operating junction temperature
–40
150
°C
6.4 Thermal Information
TPS55340-Q1
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
43.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.7
°C/W
RθJB
Junction-to-board thermal resistance
14.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
14.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
6.5 Electrical Characteristics
VI = 5 V, TJ = –40°C to 150°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range
IQ
Operating quiescent current into VIN
Device non-switching, V(FB) = 2 V
2.9
0.5
38
IL(sd)
Shutdown current
EN = GND
2.7
V(UVLO)
Under-voltage lockout threshold
VI(f)
Vhys
Under-voltage lockout hysteresis
V
mA
10
µA
2.5
2.7
V
120
140
160
mV
ENABLE AND REFERENCE CONTROL
V(EN)(r)
EN threshold voltage
EN rising input
0.9
1.08
1.3
V
V(EN)(f)
EN threshold voltage
EN falling input
0.74
0.92
1.125
V
V(EN)(hys)
EN threshold hysteresis
R(EN)
EN pull down resistor
toff
Shutdown delay, SS discharge
V(SYNC)H
SYN logic high voltage
V(SYNC)L
SYN logic low voltage
0.16
400
EN high to low
950
V
1600
1
kΩ
ms
1.2
0.4
V
VOLTAGE AND CURRENT CONTROL
Vref
Voltage feedback regulation voltage
IIB(FB)
Voltage feedback input bias current
I(COMP_sink)
COMP-pin sink current
IS(COMP)
COMP-pin source current
VC(COMP)
COMP pin Clamp Voltage
V(COMP_th)
COMP pin threshold
gm(ea)
Error amplifier transconductance
RO(ea)
Error amplifier output resistance
ƒ(ea)
Error amplifier crossover frequency
1.204
1.229
1.254
1.22
1.229
1.238
TA = 25°C
1.6
20
V(FB) = Vref + 200 mV, V(COMP) = 1 V
42
µA
V(FB) = Vref – 200 mV, V(COMP) = 1 V
42
µA
TA = 25°C
High Clamp, V(FB) = 1 V
3.1
Low Clamp, V(FB) = 1.5 V
1.04
240
360
nA
V
0.75
Duty cycle = 0%
V
V
440
µmho
10
MΩ
500
kHz
FREQUENCY
ƒ
Frequency
Dmax
Maximum duty cycle
V(FREQ)
FREQ pin voltage
tW(on)min
Minimum on pulse width
R(FREQ) = 480 kΩ
75
94
R(FREQ) = 80 kΩ
460
577
130
740
R(FREQ) = 40 kΩ
920
1140
1480
R(FREQ) = 18 kΩ
2261
2549
2837
V(FB) = 1 V, R(FREQ) = 80 kΩ
89%
96%
1.25
kHz
V
R(FREQ) = 80 kΩ
77
107
VI = 5 V
60
110
VI = 3 V
70
120
ns
POWER SWITCH
rDS(on)
N-channel MOSFET on-resistance
ILN_NFET
N-channel leakage current
VDS = 25 V, TA = 25°C
ILIM
N-Channel MOSFET current limit
D = Dmax
IB(SS)
Soft-start bias current
V(SS) = 0 V
mΩ
2.1
µA
7.75
A
OCP AND SS
5.25
6.6
6
µA
165
°C
15
°C
THERMAL SHUTDOWN
Tsd
Thermal shutdown threshold
Thys
Thermal shutdown threshold hysteresis
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6.6 Typical Characteristics
VI = 5 V, TA = 25°C (unless otherwise noted)
8
Current-Limit Threshold (A)
Transconductance (µA/V)
400
380
360
340
320
7
6
5
4
3
2
1
300
±50
±25
0
25
50
75
100
125
Temperature (°C )
±50
150
120
1.228
100
Resistance (m
Voltage Reference (V)
25
50
75
100
125
150
C002
Figure 2. Switch Current-Limit vs Temperature
1.230
1.226
1.224
1.222
80
60
40
VI
VI==33VV
20
VI
VI==55VV
VI==12
12VV
VI
1.220
0
±50
±25
0
25
50
75
100
125
Temperature (°C)
150
±50
2300
Switching Frequency (kHz)
450
400
350
300
250
200
125
150
C004
1500
1300
1100
900
700
0
20
D003
Figure 5. Frequency vs FREQ Resistance
Low Frequency Range
100
1700
500
500
75
1900
100
100
450
50
2100
150
250
300
350
400
FREQ Resistance (k:)
25
Figure 4. Static Drain-Source On-State Resistance (rDS(on))
vs Temperature
2500
200
0
Temperature (°C)
500
150
±25
C003
Figure 3. Feedback Voltage Reference vs Temperature
Switching Frequency (kHz)
0
Temperature (°C)
Figure 1. Error Amplifier Transconductance vs Temperature
6
±25
C001
40
60
FREQ Resistance (k:)
80
100
D005
Figure 6. Frequency vs FREQ Resistance
High Frequency Range
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Typical Characteristics (continued)
VI = 5 V, TA = 25°C (unless otherwise noted)
400
1400
350
1200
Frequency (kHz)
Frequency (kHz)
300
250
200
150
100
1000
800
600
RFREQ
40 kΩ
k
R(FREQ)=
= 40
400
R(FREQ)=
= 80
RFREQ
80 kΩ
k
R(FREQ) = 480 kΩ
RFREQ
= 480 k
200
50
0
0
0
5
10
15
20
25
30
Voltage on the VIN Pin (V)
35
±50
40
±25
0
25
50
75
100
125
150
Temperature (°C)
D006
C006
TA = 25°C
Figure 8. Frequency vs Temperature
700
4
600
3
500
400
COMP Voltage (V)
Frequency (kHz)
Figure 7. Minimum Switching Frequency for Quick Recovery
from Frequency Foldback
Non-foldback
300
Foldback
200
3
COMP-Terminal Clamp High
2
COMP-Terminal Clamp Low
2
1
100
1
0
±50
±25
0
25
50
75
100
125
±50
150
Temperature (°C)
±25
0
25
50
75
100
125
150
Temperature (°C)
C007
C008
R(FREQ) = 80 kΩ
Figure 9. Non-Foldback Frequency vs Foldback Frequency
Figure 10. COMP Clamp Voltage vs Temperature
1
2.70
EN Voltage Rising
2.68
Enable Voltage (V)
2.66
Input Voltage (V)
EN Voltage Falling
1
2.64
2.62
2.60
UVLO Start
2.58
UVLO Stop
2.56
2.54
1
1
1
1
2.52
1
2.50
±50
±25
0
25
50
75
100
Temperature (°C)
125
150
±50
±25
Figure 11. Input Voltage UVLO vs Temperature
0
25
50
75
100
125
Temperature (°C)
C009
150
C010
Figure 12. Enable Voltage vs Temperature
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Typical Characteristics (continued)
VI = 5 V, TA = 25°C (unless otherwise noted)
99
95
Minimum On Time (ns)
100
Maximum Duty Cycle (%)
100
98
97
96
95
90
85
80
75
94
70
±50
±25
0
25
50
75
100
125
150
Temperature (°C)
±50
R(FREQ) = 80 kΩ
7
1.8
Supply Current (mA)
Shutdown Current (µA)
50
75
100
125
150
C012
Figure 14. Minimum On Time vs Temperature
2.1
6
5
4
3
1.5
1.2
0.9
2
0.6
1
0.3
0
25
50
75
Temperature (°C)
100
125
150
Switching
Non-switching
±50
±25
0
25
50
75
100
125
Temperature (°C)
C013
Figure 15. Shutdown Current vs Temperature
8
25
R(FREQ) = 80 kΩ
Figure 13. Maximum Duty Cycle vs Temperature
±25
0
Temperature (°C)
8
±50
±25
C011
150
C014
Figure 16. Supply Current vs Temperature
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7 Detailed Description
7.1 Overview
The TPS55340-Q1 device is a monolithic non-synchronous switching converter with an integrated 5-A, 40-V
power switch. The device can be configured in several standard switching-regulator topologies, including boost,
SEPIC, and isolated flyback. The device has a wide input voltage range to support applications with input voltage
from multi-cell batteries or regulated 3.3-V, 5-V, 12-V, and 24-V power rails.
7.2 Functional Block Diagram
VIN
SW
FB
Error
Amp
EN
1.229-V
Reference
COMP
PWM
Control
Ramp
Generator
Gate
Driver
Lossless
Current Sense
S
Oscillator
SS
FREQ
SYNC
AGND
PGND
7.3 Feature Description
7.3.1 Operation
If designed as a boost converter, the TPS55340-Q1 device regulates the output with current-mode pulse-widthmodulation (PWM) control. The PWM-control circuitry turns on the switch at the beginning of each oscillator clock
cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up.
During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor
current reaches a threshold level set by the error amplifier output, the power switch turns off and the external
Schottky diode is forward biased to allow the inductor current to flow to the output. The inductor transfers stored
energy to replenish the output capacitor and supply the load current. This operation repeats every switching
cycle. The duty cycle of the converter is determined by the PWM-control comparator which compares the error
amplifier output and the current signal. The oscillator frequency is programmed by the external resistor or
synchronized to an external clock signal.
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Feature Description (continued)
A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope
compensation is required to avoid sub-harmonic oscillation that is intrinsic to peak-current mode control at duty
cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate
to maintain stability.
The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error
amplifier. The output of the error amplifier is connected to the COMP pin. An external RC-compensation network
connected to the COMP pin is chosen for feedback loop stability and optimum transient response.
7.3.2 Switching Frequency
The switching frequency is set by a resistor (R(FREQ)) connected to the FREQ pin of the TPS55340-Q1 device.
The relationship between the resistance of R(FREQ) and frequency is shown in the Figure 5. Do not leave this pin
open. A resistor must always be connected from the FREQ pin to ground for proper operation. Use Equation 1 to
calculate the resistor value required for a desired frequency.
R(FREQ) (kΩ) = 57500 × ƒS
–1.03
(kHz)
(1)
For the given resistor value, use Equation 2 to calculate the corresponding frequency.
ƒS (kHz) = 41600 × R(FREQ) –0.97 (kΩ)
(2)
The TPS55340-Q1 switching frequency can synchronized to an external clock signal that is applied to the SYNC
pin. The required logic levels of the external clock are shown in the Electrical Characteristics table. The
recommended duty cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the
FREQ pin to ground when the converter is synchronized to the external clock and the external clock frequency
must be within ±20% of the corresponding frequency set by the resistor. For example, if the frequency
programmed by the FREQ pin resistor is 600 kHz, the external clock signal must be in the range of 480 to 720
kHz.
With a switching frequency below 280 kHz (typical) after the TPS55340-Q1 enters frequency foldback as
described in the Overcurrent Protection and Frequency Foldback section, if a load remains when the overcurrent
condition is removed the output may not recover to the set value. For the output to return to the set value the
load must be removed completely or the TPS55340-Q1 power cycled with the EN pin or VIN pin. Select a
nominal switching frequency of 350 kHz for quicker recovery from frequency foldback.
When setting the switching frequency higher than 1.2 MHz, TI recommends using an external synchronous clock
as the switching frequency to ensure that the pulse-skipping function works at a light load. When using the
internal switching frequency above 1.2 MHz, the TPS55340-Q1 device might not pulse skip as described in the
Minimum On Time and Pulse Skipping section. When the pulse-skipping function does not work at light loads,
the TPS55340-Q1 device always operates in PWM mode with a minimum ON pulse width. This causes the
output voltage to be higher than the set value with the resistor divider at the FB pin. This occurs in minimum duty
cycle conditions such as when there is light output load or when the input voltage is close to the set output
voltage in a boost topology. In the light load condition a minimum output load will keep the output voltage at the
set value in a boost topology. The minimum load needed can be estimated with Equation 3 or Equation 4 using
the maximum minimum on time of 107 ns and a parasitic C(SW) capacitance of 150 pF. For example when
boosting 5 V to 12 V with 2.5 MHz switching frequency and 2-µH inductor the worst case minimum output load is
36 mA.
IO min
IO min
10
VI u t W(on) min
VO
VI u L u CSW
2 u L u VO
VI
VI
u fs
when VO – VI < VI
VI u t W(on) min VI u L u CSW
2 u L u VO
2
2
(3)
u fs
when VO – VI > VI
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Feature Description (continued)
7.3.3 Overcurrent Protection and Frequency Foldback
The TPS55340-Q1 device provides cycle-by-cycle over-current protection that turns off the power switch when
the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets at the beginning of the next
switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on the
output. When the FB voltage through the feedback resistors, drops lower than 0.9 V, the switching frequency is
automatically reduced to ¼ of the normal value. Figure 9 shows the non-foldback frequency with an 80-kΩ timing
resistor and the corresponding foldback frequency. The switching frequency does not return to normal until the
overcurrent condition is removed and the FB voltage increases above 0.9 V. The frequency foldback feature is
disabled during soft-start.
7.3.3.1 Minimum On Time and Pulse Skipping
The TPS55340-Q1 PWM control system has a minimum PWM pulse width of 77 ns (typical). This minimum ontime determines the minimum duty cycle of the PWM, for any set switching frequency. When the voltage
regulation loop of the TPS55340-Q1 device requires a minimum on-time pulse width less than 77 ns, the IC
enters pulse-skipping mode. In this mode, the device power switches off for several switching cycles to prevent
the output voltage from rising above the desired regulated voltage. This operation typically occurs in light load
conditions when the PWM operates in discontinuous conduction mode. Pulse skipping increases the output ripple
as shown in Figure 23.
7.3.4 Voltage Reference and Setting Output Voltage
An internal voltage reference provides a precise 1.229-V voltage reference at the error amplifier non-inverting
input. To set the output voltage, select the FB pin resistor R(SH) and R(SL) as shown in Equation 5.
æ R(SH)
ö
VO = 1.229 V ´ ç
+ 1÷
ç R(SL )
÷
è
ø
(5)
7.3.5 Soft-Start
The TPS55340-Q1 device has a built-in soft-start circuit that significantly reduces the start-up current spike and
output voltage overshoot. When the IC is enabled, an internal bias current source (6 µA typical) charges a
capacitor (C(SS)) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that
determines the peak current and duty cycle of the PWM controller. Limiting the peak switch current during startup with a slow ramp on the SS pin reduces in-rush current and output voltage overshoot. When the capacitor
reaches 1.8 V, the soft-start cycle is complete and the soft-start voltage no longer clamps the error amplifier
output. When the EN is pulled low for at least 1 ms, the IC enters the shutdown mode and the SS capacitor is
discharged through a 5-kΩ resistor to prepare for the next soft-start sequence.
7.3.6 Slope Compensation
To prevent sub-harmonic oscillations, the TPS55340-Q1 device uses internal slope compensation. Use
Equation 6 to calculate the sensed current slope of boost converter.
V
S
= I ´R
n
( ) L (SENSE )
(6)
Use Equation 7 to calculate the slope compensation dv/dt.
æ
ö
ç 0.32 V ÷
çR
÷
ç (FREQ ) ÷
0.5 µA
è
ø
S
(e ) = 16 ´ (1 - D) ´ 6 pF + 6 pF
(7)
In a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop
including the inductor current sampling effect as well as the slope compensation on the small-signal response
must be taken into account as calculated in Equation 8.
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Feature Description (continued)
He (s) =
1
éæ
ù
S(e ) ö
÷ ´ (1 - D) - 0.5 ú
s ´ êç 1 +
êç
ú
S(n ) ÷
ø
ëè
û+
1+
ƒS
s2
(p ´ ƒS )
2
where
•
•
•
R(SENSE) (15 mΩ) is the equivalent current-sense resistor
R(FREQ) is the timing resistor used to set frequency
D is the duty cycle
(8)
NOTE
If S(n) << S(e), the converter operates in voltage mode control rather than operating current
mode control, and Equation 8 is no longer valid.
7.3.7 Enable and Thermal Shutdown
The TPS55340-Q1 device enters shutdown when the EN voltage is less than 0.68 V (minimum) for more than
1ms. In shutdown, the input supply current for the device is less than 10 µA (maximum). The EN pin has an
internal 950-kΩ pulldown resistor to disable the device if the pin is floating.
An internal thermal shutdown turns off the device when the junction temperature exceeds 165°C (typical). The
device restarts when the junction temperature drops by 15°C.
7.3.8 Undervoltage Lockout (UVLO)
An undervoltage-lockout circuit prevents misoperation of the device at input voltages below 2.5 V (typical). When
the input voltage is below the UVLO threshold, the device remains off and the internal power MOSFET turns off.
The UVLO threshold is set below the minimum operating voltage of 2.9 V to ensure that a transient VIN dip does
not cause the device to reset. For the input voltages between UVLO threshold and 2.9 V, the device attempts to
operate, but the electrical specifications are not ensured.
7.3.9 Thermal Considerations
The maximum IC junction temperature must be restricted to 150°C under normal operating conditions. This
restriction limits the power dissipation of the TPS55340-Q1 device. The TPS55340-Q1 device features a
thermally enhanced QFN package. This package includes a PowerPad that improves the thermal capabilities of
the package. The thermal resistance of the QFN package in any application greatly depends on the PCB layout
and the PowerPad connection. The PowerPad must be soldered to the analog ground on the PCB. Use thermal
vias underneath the PowerPad to achieve good thermal performance.
7.4 Device Functional Modes
7.4.1 Operation With VI < 2.9 V (Minimum VI)
The TPS55340-Q1 device operates with input voltages above 2.9 V. The typical UVLO voltage (turning off) is 2.5
V and the TPS55340-Q1 device remains off at input voltages lower than that point. For the input voltages
between UVLO threshold and 2.9 V, the device attempts to operate, but the electrical specifications are NOT
ensured.
7.4.2 Operation With EN Control
The enable rising-edge threshold voltage is 1.08 V (typical) with 0.16 V hysteresis (typical). With the EN pin held
below the turn-off voltage the device is disabled and switching is inhibited. The IC quiescent current is reduced in
this state. When the input voltage is above the UVLO threshold and the EN pin voltage increases above the
rising edge threshold, the device becomes active. Switching enables and the soft-start sequence initiates. The
TPS55340-Q1 device starts at the soft-start time determined by the external soft-start capacitor.
12
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Device Functional Modes (continued)
7.4.3 Operation at Light Loads
The device is designed to operate in high-efficiency pulse-skipping mode under light load conditions.
Discontinuous-conduction-mode (DCM) operation initiates when the switch current falls to 0 A. During DCM
operation, the catch diode stops conducting when the switch current falls to 0 A. The switching node (the SW
pin) waveform takes on the characteristics of discontinuous-conduction-mode (DCM) operation as shown in
Figure 22. As the load decreases further and when the voltage-regulation loop of TPS55340-Q1 device requires
an on-time pulse width less than the minimum PWM pulse width of 77 ns (typical), the IC enters pulse-skipping
mode. In this mode, the device holds the power switch off for several switching cycles to prevent the output
voltage from rising too much above the desired regulated voltage.
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8 Application and Implementation
8.1 Application Information
The TPS55340-Q1 device can be configured in several standard switching-regulator topologies, including boost,
SEPIC, and isolated flyback. For example, the device configured in boost topology is widely used to convert a
lower DC voltage to a higher DC voltage with a maximum available switching current of 5.25 A. Use the following
design procedure to select component values for a boost converter design or SEPIC design for the TPS55340Q1 device. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. This section presents a simplified discussion of the design process.
8.2 Typical Applications
The following section provides a step-by-step design approach for configuring the TPS55340-Q1 device as a
voltage regulating boost converter, as shown in Figure 17. When configured as SEPIC or flyback converter, a
different design approach is required. A design example of SEPIC converter is provided in the TPS55340-Q1
SEPIC Converter section.
8.2.1 TPS55340-Q1 Boost Converter
TP1
SW
L1
10uH
VIN
J1
TP4
J2
D1
VIN
VOUT
24V, 1.9A
5V - 12V
C1
J6
C2
10uF
R6
0
C8
4.7uF
C9
4.7uF
C10
4.7uF
1
VIN
C6
J7
1
VOUT
GND
GND
1 SW
GND
14
NC
13
PGND
SW
PWPD
C7
0.1uF
J3
15
SW
16
17
2 VIN
3 EN
OFF
COMP
FB
C3
0.047uF
AGND
VIN
EN
R5
J4
GND
50
R4
78.7k
NC 10
FREQ 9
SYNC
JP1
TP2
LOOP
PGND 11
TPS55340-Q1
4 SS
ON
TP5
PGND 12
U1
5
6
7
8
R1
187k
SYNC
J5
TP3
COMP
SYNC
SYNC
R2
GND
R3
2.55k
10.0k
C5
100pF
1
Not Populated
C4
0.1uF
Figure 17. Boost Converter Application Schematic
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Typical Applications (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1. These parameters are typically determined at the
system level.
Table 1. Key Parameters of Boost Converter Example
DESIGN PARAMETER
EXAMPLE VALUE
Output Voltage
24 V
Input Voltage
5 V to 12 V
Maximum Output Current
800 mA
Transient Response 50% load step (ΔVO = 3%)
960 mV
Output Voltage Ripple (0.5% of VO)
120 mV
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS55340-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Selecting the Switching Frequency (R4)
The first step of this design procedure is to determine the switching frequency of the regulator. Consider the
tradeoffs of a higher switching frequency versus a lower switching frequency. A higher switching frequency
allows for the use of a lower-valued inductor and smaller output capacitors which leads to the smallest solution
size. A lower switching frequency results in a larger solution size but better efficiency. In general, the selected
switching frequency allows for the minimum tolerable efficiency to avoid excessively large external components.
A switching frequency of 600 kHz is a good trade-off between efficiency and solution size. The appropriate
resistor value is selected based on the resistance versus frequency graph (see Figure 5) or calculated using
Equation 1. The value of R4 is calculated to be 78.4 kΩ and the nearest standard value resistor of 78.7 kΩ is
selected. A resistor must be placed from the FREQ pin to ground, even if an external oscillation is applied for
synchronization.
8.2.1.2.3 Determining the Duty Cycle
The input-to-output voltage-conversion ratio of the TPS55340-Q1 device is limited by the worst-case maximum
duty cycle of 89% and the minimum duty cycle which is determined by the minimum on-time of 77 ns and the
switching frequency. Use Equation 9 to calculate the minimum duty cycle. Selecting a 600-kHz switching
frequency, the minimum duty cycle is calculated as 4%.
D(PS) = tonmin × ƒS
(9)
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The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the
converter is running in discontinuous conduction mode (DCM), where the inductor current ramps to zero at the
end of each cycle, the duty cycle varies with changes of the load much more than when running in continuous
conduction mode (CCM). In continuous conduction mode, where the inductor maintains a minimum DC current,
the duty cycle is related primarily to the input and output voltages as calculated with Equation 10. Assume a 0.5V drop (V(D)) across the Schottky rectifier. At the minimum input of 5 V, the duty cycle is 80%. At the maximum
input of 12 V, the duty cycle is 51%.
VO + V(D ) - VI
D=
VO + V
(D )
(10)
At light loads the converter operates in DCM. In this case the duty cycle is a function of the load, input voltage,
output voltages, inductance, and switching frequency as calculated in Equation 11. The light-load duty cycle can
be calculated only after an inductance is selected (see the Selecting the Inductor (L1) section). While operating in
DCM with very-light load conditions the duty cycle demand forces the TPS55340-Q1 device to operate with the
minimum on time. The converter then begins pulse skipping which can increase the output ripple.
2 ´ (VO + V(D ) - VI ) ´ L ´ IO ´ ƒS
D=
VI
(11)
All converters using a diode as the freewheeling or catch component have a load-current level at which the
converters transition from DCM to CCM. The transit from DCM to CCM is the point when the inductor current
falls to zero during the off-time of the power switch. At higher load currents, the inductor current does not fall to
zero and the diode and switch current assume a trapezoidal wave-shape as opposed to a triangular wave-shape.
The load current boundary between discontinuous conduction and continuous conduction is calculated for a set
of converter parameters as shown in Equation 12.
(V + V( ) - V )´ V
=
2 ´ (V + V( ) ) ´ ƒ ´ L
2
IO(cr )
O
I
D
I
2
O
D
S
where
•
•
•
•
•
•
VO is the output voltage of the converter in volts (V)
V(D) is the forward conduction voltage drop across the rectifier or catch diode in volts (V)
VI is the input voltage to the converter in volts (V)
IO is the output current of the converter in amperes (A)
L is the inductor value in henries (H)
ƒS is the switching frequency in hertz (Hz)
(12)
For loads higher than the result of the Equation 12, the duty cycle is given by Equation 10. For loads less than
the results of Equation 12, the duty cycle is given Equation 11.
Unless otherwise stated, the design equations that follow assume that the converter is running in continuous
conduction mode, which typically results in a higher efficiency for the power levels of this converter.
8.2.1.2.4 Selecting the Inductor (L1)
The selection of the inductor affects steady state operation as well as transient behavior and loop stability.
Because of these factors, the inductor is the most important component in the power-regulator design. There are
three important inductor specifications: inductor value, DC resistance, and saturation current. Considering
inductor value alone is not enough. Inductor values can have ±20% tolerance with no current bias. When the
inductor current approaches saturation level, the effective inductance can fall to a fraction of the zero current
value.
The minimum value of the inductor must meet the inductor current ripple (ΔIL) requirement at worst case. In a
boost converter, the maximum inductor-current ripple occurs at 50% duty cycle. For applications where duty
cycle is always smaller or larger than 50%, use Equation 14 to calculate the minimum inductance with the duty
cycle as close to 50% as possible and corresponding input voltage. For applications that must operate with 50%
duty cycle when input voltage is somewhere between the minimum and the maximum input voltage, use
Equation 15. K(IND) is a coefficient that represents the amount of inductor ripple current relative to the maximum
16
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input current (I(M_DC) = ILavg). Use Equation 13 to calculate the maximum input current, with an estimated
efficiency based on similar applications (η(EST)). The inductor ripple current is filtered by the output capacitor.
Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the
output capacitor must have a ripple-current rating equal-to or greater-than the inductor ripple current. In general,
the inductor ripple value (K(IND)) is at the discretion of the designer. However, the following guidelines can be
used for selecting the value for K(IND).
For CCM operation, TI recommends to use K(IND) values in the range of 0.2 to 0.4. Selecting a value for K(IND)
that is closer to 0.2 results in a larger inductance value, maximizes the potential output current of the converter,
and minimizes electromagnetic interference (EMI). Selecting a value for K(IND) that is closer to 0.4 results in a
smaller inductance value, a physically smaller inductor, and improved transient response. However, a K(IND) value
close to 0.4 can result in potentially worse EMI and lower efficiency. Using an inductor with a smaller inductance
value can result in the converter operating in DCM. Operating in DCM reduces the maximum output current of
the boost converter, causes larger input voltage and output voltage ripple, and reduces efficiency. For this
design, a value of 0.3 for K(IND) was selected along with a conservative efficiency estimate of 85% with the
minimum input voltage and maximum output current. Use Equation 14 to calculate the minimum output
inductance with the maximum input voltage because this equation corresponds to duty cycle closest to 50%. The
maximum input current is estimated at 4.52 A and the minimum inductance is 7.53 µH. A standard value of 10
µH is selected.
VO ´ IO
I(M _ DC ) =
h(EST ) ´ VI min
(13)
VI
D
LO min ³
´
, D ≠ 50%, VI with D closest to 50%
I(M _ DC ) ´ K (IND ) ƒS
LO min ³
(V
O
+ V(D )
)
I(M _ DC ) ´ K (IND )
´
(14)
1
, D = 50%
4 ´ ƒS
(15)
After selecting the inductance, the required current ratings can be calculated. Use Equation 16 to calculate the
ripple using the selected inductance. At a minimum input voltage, the inductor has the largest current ripple,
therefore VImin is used in Equation 16. Use Equation 17 and Equation 18 to calculate the root mean square
(RMS) and peak inductor current. For this design the current ripple is 663 mA, the RMS inductor current is 4.52
A, and the peak inductor current is 4.85 A. TI recommends that the peak inductor current rating of the selected
inductor be 20% higher to account for transients during power up, faults, or transient load conditions. The most
conservative approach is to specify an inductor with a saturation current greater than the maximum peak currentlimit of the TPS55340-Q1 device. This approach helps to avoid saturation of the inductor. The selected inductor
for this design was a Würth Elektronik 74437368100. This inductor has a saturation current rating of 12.5 A,
RMS current rating of 5.2 A, and typical DCR of 27 mΩ.
V min Dmax
DIL = I
´
ƒS
LO
(16)
IL(RMS) =
(II(DC) )2 + æçè D12IL ö÷ø
IL(peak) = II(DC)
2
(17)
DI
+ L
2
(18)
The TPS55340-Q1 device has built-in slope compensation to avoid subharmonic oscillation associated with
current mode control. If the inductor value is too small, the slope compensation may not be adequate, and the
loop can be unstable.
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8.2.1.2.5 Computing the Maximum Output Current
The overcurrent limit for the integrated power MOSFET limits the maximum input current and thus the maximum
input power for a given input voltage. Maximum output power is less than maximum input power because of
power conversion losses. Therefore, the current-limit setting, input voltage, output voltage, and efficiency can all
change the maximum current output (IOmax). The current-limit clamps the peak inductor current and therefore
the ripple must be subtracted to derive maximum DC current. Decreasing the K(IND) value or designing for a
higher efficiency increases the maximum output current. Use the selected inductance or the selected K(IND) value
to calculate the maximum output current. Use Equation 19, the minimum input voltage, and minimum peak
current-limit (I(LIM)) of 5.25 A to calculate the maximum output current.
æ K (IND ) ö
DIL ö
æ
÷ ´ h(EST )
VI min ´ I(LIM) ´ ç 1 ´
h
VI min ´ ç I(LIM) ÷
ç
2 ÷
(EST )
2
è
ø
è
ø
=
IO max =
VO
VO
(19)
For this design, with a 5-V input boosted to 24-V output, a 10-μH inductor with an assumed the Schottky forward
voltage of 0.5 V, and estimated efficiency of 85%, the maximum output current is calculated to be 871 mA. With
a 12-V input and increased estimated efficiency of 90%, the maximum output current calculated value increases
to 2.13 A. This circuit was evaluated to the maximum output currents with both the minimum and maximum input
voltage.
8.2.1.2.6 Selecting the Output Capacitor (C8 through C10)
At least 4.7 µF of ceramic type X5R or X7R capacitance is recommended at the output. This output capacitance
was selected to meet the requirements for the output ripple (Vrip) and voltage change during a load transient. The
loop is then compensated for the selected output capacitor. The output capacitance must be selected based on
the most stringent of these criteria. The output-ripple voltage is related to the capacitance and equivalent series
resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, use Equation 20 to calculate the
minimum capacitance required for a given ripple. Using high ESR capacitors causes additional ripple. Use
Equation 21 to calculate the maximum ESR for a specified ripple. ESR ripple can be neglected for ceramic
capacitors but must be considered if tantalum or electrolytic capacitors are used. Use Equation 22 to calculate
the minimum ceramic output capacitance required to meet a load transient requirement. Use Equation 23 to
calculate the RMS current required by the output capacitor for support.
Dmax ´ IO
CO ³
ƒS ´ Vrip
(20)
æ
Dmax ´ IO ö
ç Vrip ÷
ƒ S ´ CO ø
è
ESR £
DIL
CO ³
(21)
DI(TRAN)
2 ´ p ´ ƒBW ´ DV(TRAN)
ICO(RMS) = IO
(22)
Dmax
1
( Dmax )
(23)
Using Equation 20 for this design, the minimum output capacitance for the specified 120-mV output ripple is 8.8
µF. For a maximum transient-voltage change (ΔV(TRAN)) of 960 mV with a 400 mA load transient (ΔI(TRAN)), and a
6 kHz control loop bandwidth (ƒBW) with Equation 22, the minimum output capacitance is calculated as 11.1 µF.
The most stringent criteria is the 11.1 µF for the required load transient. Equation 23 calculates a 1.58-A RMS
current in the output capacitor. The capacitor must also be properly rated for the desired output voltage.
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Care must be taken when evaluating ceramic capacitors that derate under DC bias, aging, and AC signal
conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the range
of converter switching frequency. Self-resonance significantly decreases the effective capacitance. The DC bias
also significantly reduces capacitance. Ceramic capacitors can lose as much as 50% of the capacitance when
operated at the rated voltage. Therefore, leave a margin when selecting the capacitor voltage rating to ensure
adequate capacitance at the required output voltage. For this example, three 4.7-µF, 50-V 1210 X7R ceramic
capacitors are used in parallel leading to a negligible ESR. Selecting 50-V capacitors instead of 35-V capacitors
reduces the effects of DC bias and allows this example circuit to be rated for the maximum output voltage range
of the TPS55340-Q1 device.
8.2.1.2.7 Selecting the Input Capacitors (C2 and C7)
At least 4.7-µF of ceramic input capacitance is recommended. Additional input capacitance may be required to
meet ripple requirements, transient requirements, or both. High-quality ceramic-type X5R or X7R capacitors are
recommended to minimize capacitance variations over temperature. The capacitor must also have an RMScurrent rating greater than the maximum RMS-input current of the TPS55340-Q1 device as calculated with
Equation 24. The input capacitor must also be rated greater than the maximum input voltage. Use Equation 25 to
calculate the input voltage ripple.
DI
ICI(RMS) = L
12
(24)
DIL
VI(rip) =
+ DIL ´ R(CI)
4 ´ ƒS ´ CI
(25)
In the design example, the input RMS current is calculated to be 191 mA. The selected input capacitor is a 10µF, 35-V 1210 X7R with 3 mΩ ESR. Although a capacitor with a lower voltage rating can be used, a 35-V rated
capacitor was selected to limit the affects of DC bias and to allow the circuit to be rated for the entire input range
of the TPS55340-Q1 device. The input ripple is calculated to be 30 mV. An additional 0.1-µF, 50-V 0603 X5R is
located close to the VIN pin and the GND pin for additional decoupling.
8.2.1.2.8 Setting the Output Voltage (R1 and R2)
To set the output voltage in either DCM or CCM, use Equation 26 and Equation 27 to calculate the values of R1
and R2.
æ R1 ö
VO = 1.229 V ´ ç
+ 1÷
è R2 ø
(26)
æ VO
ö
R1 = R2 ´ ç
- 1÷
è 1.229 V
ø
(27)
Considering the leakage current through the resistor divider and noise decoupling into FB pin, an optimum value
for R2 is around 10 kΩ. The output voltage tolerance depends on the V(FB) accuracy and the tolerance of R1 and
R2. In this example, with a 24 V output, R1 is calculated to 185.3 kΩ using Equation 27. The nearest standard
value of 187 kΩ is used.
8.2.1.2.9 Setting the Soft-Start Time (C7)
Select the appropriate capacitor to set soft-start time and avoid overshoot. Increasing the soft-start time reduces
the overshoot during start-up. A 0.047 µF ceramic capacitor is used in this example.
8.2.1.2.10 Selecting the Schottky Diode (D1)
The high switching frequency of the TPS55340-Q1 device demands high-speed rectification for optimum
efficiency. Ensure that the average current rating and peak current rating of the diode exceed the average output
current and peak inductor current. In addition, the reverse breakdown voltage of the diode must exceed the
regulated output voltage. The diode must also be rated for the power dissipated which is calculated using
Equation 28.
PD = V(D) × IO
(28)
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In this conservative design example, the selected diode is rated for the maximum output current of 2.13 A.
During normal operation with 800-mA output current and assuming a Schottky diode drop of 0.5 V, the diode
must be capable of dissipating 400 mW. The recommended minimum ratings for this design are a 40-V, 3-A
diode. However to improve the flexibility of this design, a Diodes Inc B540-13-F in an SMC package with voltage
and current ratings of 40 V and 5 A was selected for this desigh.
8.2.1.2.11 Compensating the Control Loop (R3, C4, and C5)
The TPS55340-Q1 device requires external compensation which allows the loop response to be optimized for
each application. The COMP pin is the output of the internal error amplifier. An external resistor (R3) and
ceramic capacitor (C4) are connected to the COMP pin to provide a pole and a zero as shown in the application
circuit (see Figure 17). This pole and zero, along with the inherent pole and zero of a boost converter, determine
the closed loop frequency response which is important for converter stability and transient response. Loop
compensation must be designed for the minimum operating voltage.
The following equations summarize the loop equations for the TPS55340-Q1 device configured as a CCM boost
converter. The equations include the power stage output pole (ƒO) and the right-half-plane zero (ƒ(RHPZ)) of a
boost converter calculated using Equation 29 and Equation 30 respectively. When calculating ƒO, including the
derating of ceramic output capacitors is important. In the example with an estimated 10.2-µF capacitance, these
frequencies are calculated to be 980 kHz and 22.1 kHz respectively. Use Equation 29 to calculate the DC gain
(A) of the power stage which is 39.9 dB in this design. Use Equation 32 and Equation 33 to calculate the
compensation pole (ƒ(P)) and zero (ƒ(Z)) generated by R3, C4, and the internal transconductance amplifier
(respectively).
20
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Most CCM boost converters have a stable control loop if ƒ(Z) is set slightly above ƒ(P) through proper sizing of R3
and C4. To start, select a value of 0.1 µF for C4 and a value of 2 kΩ for R3. Increasing R3 or reducing C4
increases the closed loop bandwidth and therefore improves the transient response. Adjusting R3 and C4 in
opposite directions increases the phase and gain margin of the loop, which improves loop stability. TI
recommends to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency (ƒS) or 1/3 the
RHPZ frequency (ƒ(RHPZ)) which is calculated using Equation 30. Use the spreadsheet tool located as an aid in
compensation design. See the TPS55340-Q1 product folder at www.TI.com.
2
ƒO »
2p ´ RO ´ CO
where
•
•
CO is the equivalent output capacitor (CO = C8 + C9 + C10)
RO is the equivalent load resistance (VO / IO)
ƒ(RHPZ ) »
æ V ö
RO
´ç I ÷
2p ´ L è VO ø
(29)
2
(30)
VI
1.229
1
A=
´ gM(ea ) ´ 10 MW ´
´ RO ´
VO
VO ´ R(SENSE )
2
where
•
•
gea is the error amplifier transconductance located in the Electrical Characteristics table
R(SENSE) (15 mΩ, typical) is the sense resistor in the current control loop
1
ƒ(P ) =
2p ´ 10 MW ´ C4
1
ƒ(Z ) =
2p ´ R3 ´ C4
ƒ
ƒCO(1) = S
5
(31)
(32)
(33)
where
•
ƒCO(1) is possible bandwidth
ƒCO(2 ) =
(34)
ƒ(RHPZ )
3
where
•
ƒCO(2) is possible bandwidth
(35)
An additional capacitor from the COMP pin to the GND pin (C5) can be used to place a high frequency pole in
the control loop. Using this additional capacitor is not always required when using ceramic output capacitors. If a
non-ceramic output capacitor is used, an additional zero (ƒ(ZESR)) is located in the control loop. Use Equation 37
to calculate ƒ(ZESR). Use Equation 38 and Equation 36 to calculate the value of C5 and the pole created by C5
(respectively). Finally if additional phase margin is required, add an additional zero (f(ZFF)) by placing a capacitor
(C(FF)) in parallel with the top feedback resistor (R1). TI recommends to place the zero at the target cross-over
frequency or higher. The feed forward capacitor also adds a pole at a higher frequency. Use Equation 39 to
calculate the recommended value of C(FF).
1
ƒ(P2 ) =
2p ´ R3 ´ C5
(36)
1
ƒ(ZESR ) »
2p ´ R(ESR ) ´ CO
(37)
R(ESR ) ´ CO
C5 =
R3
where
•
R(ESR) is the ESR of the output capacitor
(38)
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C(FF ) =
www.ti.com
1
Vref
VO
2p ´ R1 ´ ƒ(ZFF ) ´
(39)
If a network measurement tool is available, the most accurate compensation design can be achieved following
this procedure. The power stage frequency response is first measured using a network analyzer at the minimum
5-V input and maximum 800-mA load. Figure 18 shows this measurement. In this design only one pole and one
zero are used and therefore the maximum phase increase from the compensation is 180 degrees. For a 60
degree phase margin, the power stage phase must be –120 degrees at the lowest point. Based on the target
6-kHz bandwidth, the measured power stage gain, K(PS) (ƒBW), is 24.84 dB and the phase is –110.3 degrees.
Gain
Phase
Gain (dB)
40
0.0
±30.0
20
±60.0
0
±90.0
Phase (°)
60
±20
±120.0
±40
±150.0
±60
100
1000
10000
Frequency (Hz)
±180.0
100000
C015
Figure 18. Power Stage Gain and Phase of the Boost Converter
The value of R3 is then selected to set the compensation gain as the reciprocal of the power stage gain at the
target bandwidth using Equation 40. The value of C4 is then selected to place a zero at 1/10 the target
bandwidth using Equation 41. In this case R3 is calculated to be 2.56 kΩ, the nearest standard value 2.55 kΩ is
used. The value of C4 is calculated to be 0.104 µF and the nearest standard value of 0.100 µF is used. A 100-pF
capacitor is selected for C5 to add a high frequency pole at a frequency 100 times the target bandwidth, however
adding 100 pF for C5 is not necessary because this design uses all ceramic capacitors.
1
R3 =
K (PS ) (ƒBW )
æ
ö
20
R2
ç
÷
ç gM(ea ) ´ (R1 + R2 ) ´ 10
÷
ç
÷
è
ø
(40)
1
C4 =
ƒ
2p ´ R3 ´ BW
10
(41)
22
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8.2.1.3 Application Curves
The following application curves are characteristics of the boost converter.
100
95
VO
90
Efficiency (%)
85
80
75
70
65
IO
VI
VI==55VV
60
55
VI
VI==12
12VV
50
0.0
0.4
0.8
1.2
1.6
Output Current (A)
2.0
C016
Time — 1 ms/div
VO (AC-coupled) = 500 mV/div
IO = 200 mA/div
Figure 20. Load Transient Response
Figure 19. Efficiency Versus Output Current
IL
IL
VO
VO
SW
SW
Time — 1 µs/div
IL = 1 A/div
VO (AC-coupled) = 10 mV/div
V(SW) = 20 V/div
Time — 1 ms/div
IL = 1 A/div
VO (AC-coupled) = 100 mV/div
V(SW) = 20 V/div
Figure 21. CCM PWM Operation
Figure 22. DCM PWM operation
VI
IL
VO
EN
SW
SW
VO
Time — 50 µs/div
IL = 200 mA/div
VO (AC-coupled) = 20 mV/div
V(SW) = 20 V/div
VI = 1 V/div
VO = 10 V/div
Figure 23. Pulse Skipping
Time — 500 µs/div
V(EN) = 2 V/dvi
V(SW) = 10 V/div
Figure 24. Startup
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180
40
120
20
60
Gain (dB)
60
0
Phase (°)
SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
0
-20
-60
5-V Gain
5-V Phase
15-V Gain
15-V Phase
-40
-60
100
-120
-180
100000
1000
10000
Frequency (Hz)
D001
IO = 800 mA
Figure 25. Closed Loop Gain and Phase of the Boost Converter
8.2.2 TPS55340-Q1 SEPIC Converter
L1
12uH
C6
VIN
VIN
1
6-18V
2
2
C1
C8
22uF
1
2
1
1
2
3
4
C10
22uF
1
EN
2
OFF
3
NC
PGND
PGND
VIN
EN
TPS55340-Q1
NC
FREQ
SS
C3
0.047uF
TP5
1
GND
2
2
VOUT
1
GND
5
6
7
8
J4
2
12
R5
11
R4
95.3k
10
TP2
1
GND
49.9
9
R1
86.6k
SYNC
SYNC
J7
PGND
SW
U1
SW
VIN
J5
C11
13
14
FB
JP1
15
SW
PWPD
J3
ON
16
17
C7
0.1uF
GND
C9
22uF
1
COMP
2
R6
0
1
AGND
GND
C2
10uF
VOUT
12V, 1A
1
SYNC
1
J2
D1
TP1
J6
VIN
TP4
2.2uF
J1
SYNC
TP3
R3
2.37k
R2
10k
C5
1
C4
0.1uF
1
Not Populated
Copyright © 2016, Texas Instruments Incorporated
Figure 26. SEPIC-Converter Application Schematic
24
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8.2.2.1 Design Requirements
The parameters listed in Table 2 are used for a SEPIC converter design. These calculations are performed only
for CCM operation. The use of a coupled inductor is assumed.
Table 2. Key Parameters of SEPIC Converter Example
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage
12 V
Input voltage
6 V to 18 V, 12 V nominal
Maximum output current
1A
Transient response 50% load step (ΔVO = 4%)
480 mV
Output voltage ripple (0.5% of VO)
60 mV
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Selecting the Switching Frequency (R4)
A 500-kHz switching frequency (ƒS) was selected for this design. Use Equation 1 and the nearest standard value
95.3 kΩ to calculate the value of R4.
8.2.2.2.2 Duty Cycle
Use Equation 42 to calculate the duty cycle of a SEPIC converter. Selecting the 6-V minimum input the duty
cycle is calculated as 68%. Selecting the 18-V maximum input voltage the duty cycle is calculated as 41%.
VO + V(D )
D=
VO + V(D ) + VI
(42)
8.2.2.2.3 Selecting the Inductor (L1)
With an estimated 85% efficiency, the input current is calculated to be 2.35 A using Equation 11. The minimum
inductance is calculated to be 10.5 µH using Equation 43 with a K(IND) value of 0.3 and a maximum input value of
18-V. The nearest standard value of 12 µH is used. This equation assumes that a coupled inductor is used.
VI max ´ Dmin
L³
2 ´ ƒS ´ II(DC) ´ K (IND )
(43)
The inductor ripple current is recalculated to be 615 mA using Equation 44. The peak current is calculated to be
3.69 A. For the saturation rating of the selected inductor, use the typical current-limit. The RMS current for La is
approximately the average input current 2.35 A. The RMS current for Lb is approximately the output current of 1
A. For this design a CoilCraft MSD1260-123 was used with 6.86-A saturation, 74-mΩ DCR, and 3.12-A RMS
current rating for one winding.
V max ´ Dmin
DIL = I
2 ´ ƒS ´ L
(44)
DI ö æ
DI ö
æ
IL(peak) = IL(a _ peak) + IL(b _ peak) = ç II(DC) + L ÷ + ç IO + L ÷
2
2 ø
è
ø è
(45)
8.2.2.2.4 Calculating the Maximum Output Current
The maximum output current is calculated to be 1.47 A using Equation 46 with the minimum input voltage of 6 V,
selected inductance of 12 µH, 5.25-A minimum current-limit, and estimated 85% efficiency.
IO max =
(I(
LIM) - DIL
)
æ
ö
VO
ç
+ 1÷
ç VI min ´ h(EST )
÷
è
ø
=
(I(
LIM) - II(DC)
´ K (IND )
)
æ
ö
VO
ç
+ 1÷
ç VI min ´ h(EST )
÷
è
ø
(46)
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8.2.2.2.5 Selecting the Output Capacitor (C8 through C10)
To meet the 60-mV ripple specification, the minimum output capacitance is calculated to be 22.5 µF with
Equation 47. This design uses ceramic output capacitors and the effects of ESR are ignored. To meet the
transient response of 500 mA with less than 480-mV voltage change and a 7-kHz control loop bandwidth, the
minimum output capacitance is calculated to be 23.7µF using Equation 48. The RMS current is calculated to be
1.44 A using Equation 24. The output capacitors used in this design is three 22-µF, 25-V X7R 1210 ceramic
capacitors. With voltage derating, the effective total output capacitance is estimated to be 30.4 µF.
Dmax ´ IO
CO ³
ƒS ´ Vrip
(47)
CO ³
DI(TRAN)
2p ´ ƒBW ´ DV(TRAN)
(48)
8.2.2.2.6 Selecting the Series Capacitor (C6)
The series capacitor is chosen to limit the ripple current to 5% of the maximum input voltage. Using Equation 49
the minimum capacitance is 1.5 µF. Using Equation 50 the RMS current is calculated to be 1.63 A. A 2.2-µF
ceramic capacitor in a 1206 package was selected for this design.
IO ´ Dmax
C(P ) ³
0.05 ´ VI max ´ ƒS
(49)
I(CP _ RMS) = II(DC) ´
(1 - Dmax)
Dmax
(50)
8.2.2.2.7 Selecting the Input Capacitor (C2 and C7)
Based on the minimum 4.7-µF ceramic recommended for the TPS55340-Q1 device, a 10-µF X7R input capacitor
was used with an additional 0.1 µF placed close to the VIN pin and the GND pin. With an estimated 6-µF
capacitance after voltage derating, the input ripple voltage is calculated to be 39.9 mV using Equation 51. The
RMS current of the input capacitance is calculated to be 0.177 A using Equation 52.
DIL
VI(rip) =
4 ´ ƒS ´ CI
(51)
I(CI _ RMS) =
DIL
12
(52)
8.2.2.2.8 Selecting the Schottky Diode (D1)
The selected diode must have a minimum breakdown voltage (V(BR)). Use Equation 53 to calculate V(BR) which is
30.5 V in this design. The average current rating is recommended to be greater than the maximum output
current. With the maximum 18-V input, average current is calculated to be 2.6 A using Equation 19. The package
must also be capable of handling the power dissipation. With an estimated 0.5 V forward voltage, power
dissipation is calculated with Equation 28 to be 500 mW. Diodes Inc B340B was chosen for this design with a 40V, 3-A rating in a SMB package.
V(BR) = VO + VImax + VF
(53)
8.2.2.2.9 Setting the Output Voltage (R1 and R2)
With R2 fixed at 10 kΩ, use Equation 27 to calculate the nearest standard value of 86.6 kΩ for R1.
8.2.2.2.10 Setting the Soft-Start Time (C3)
The recommended 0.047-µF soft-start capacitor is used for C3.
8.2.2.2.11 Mosfet Rating Considerations
In this design, with the maximum input voltage of 18 V and output voltage of 12 V, the FET receives
approximately 30 V across drain and source. A 10% tolerance for the MOSFET VDS rating is recommended to
account for any ringing. The 40-V rating of the TPS55340-Q1 power MOSFET comfortably satisfies this
requirement.
26
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8.2.2.2.12 Compensating the Control Loop (R3 and C4)
This design was compensated by measuring the frequency response of the power stage at the lowest input
voltage of 6 V and choosing the components for the desired bandwidth. The lowest right-half plane zero (ƒ(RHPZ))
is calculated with Equation 54 to be 36.7 kHz. When using the recommendation of limiting the bandwidth to 1/3
of ƒ(RHPZ) or less, the recommended maximum bandwidth is 12.2 kHz.
VO
IO
ƒ(RHPZ ) =
2
æ D ö
2´ p ´ L ´ ç
ç (1 - D ) ÷÷
è
ø
(54)
This design also uses only one pole and one zero. To achieve approximately 60 degrees of phase margin, the
power stage phase must be no lower than approximately –120 degrees at the desired bandwidth. To ensure a
stable design, R3 was initially set to 1 kΩ and C4 was set to 1 µF. Figure 27 shows the measurement of the
power stage. At 7 kHz the power stage has a gain of 19.52 dB and phase of –118.1 degrees.
6-V Input Gain
6-V Input Phase
Gain (dB)
40
180
120
20
60
0
0
Phase (°)
60
±20
±60
±40
±120
±60
100
1000
10000
±180
100000
Frequency (Hz)
C018
Figure 27. SEPIC Power Stage Gain and Phase
Because no changes occur in the transconductance amplifier, the equations used to calculate the external
compensation components in a boost design can be used in the SEPIC design. Using the maximum gm(ea) from
the electrical specification of 440 µmho, Equation 40 calculates the nearest standard value of R3 to be 2.37 kΩ.
Using Equation 41, C4 is calculated to the nearest standard value of 0.1 µF.
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8.2.2.3 Application Curves
The following curves are characteristics of the SEPIC converter.
100
95
IO
90
Efficiency (%)
85
80
VO
75
70
65
VI
VI==66VV
60
VI==12
12VV
VI
55
VI==18
18VV
VI
50
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Output Current (A)
C019
IO = 500 mA/div
Figure 28. Efficiency Versus Output Current
SW
Time — 500 µs/div
VO (AC-coupled) = 200 mV/div
Figure 29. Load Transient Response
VI
IL(b)
EN
SW
IL(a)
VO
VO
IL(a) = 1 A/div
VI = 2 V/div
VO = 5 V/dvi
60
180
6-V Gain
6-V Phase
120
18-V Gain
18-V Phase
40
20
60
0
0
-20
-60
-40
-120
-60
100
V(SW) = 20 V/div
Figure 31. Output Voltage Soft-start
Figure 30. CCM PWM Operation
Gain (dB)
Time — 1 ms/div
V(EN) = 2 V/div
1000
10000
Frequency (Hz)
Phase (°)
Time — 2 µs/div
V(SW) = 10 V/div
IL(b) = 1 A/div
VO (AC-coupled) = 50 mV/div
-180
100000
D004
Figure 32. Closed Loop Gain and Phase of the SEPIC Converter
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.9 V and 32 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS55340-Q1 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those with high frequency and high switch current, printed circuit
board (PCB) layout is an important design step. If the layout is not carefully designed, the regulator can suffer
from instability as well as noise problems. The following guidelines are recommended for good PCB layout.
• To maximize efficiency, keep switch rise and fall times as short as possible.
• To prevent radiation of high frequency resonance problems, use proper layout of the high frequency switching
path.
• Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the
switching regulator to minimize inter-plane coupling.
• The high current path including the internal MOSFET switch, Schottky diode, and output capacitor, contains
nanosecond rise times and fall times. Keep these rise times and fall times as short as possible.
• Place the input capacitor as close to the VIN pin and the AGND pin as possible to reduce the IC supply
ripple.
10.2 Layout Example
LO
VI
VI
Bypass
Capacitor
VO
VI
High-Frequency
Bypass Capacitor
Output
Filter
Capacitor
SW
SW
NC
PGND
16
15
14
13
VIN 2
11 PGND
PowerPad
CI
Bypass capacitor
for TPS55340-Q1.
Put close to Pin 2
Power Ground
12 PGND
SW 1
Power Ground
Output
Filter
Capacitor
EN
3
10 NC
SS
4
9
5
C(SS)
6
7
SYNC AGND COMP
FREQ
Frequency
Set
Resistor
8
FB
UVLO
Resistors
Connect to VO on the
inner or bottom layer
Compensation
Network
Feedback
Resistors
Connect to AGND on the
inner or bottom layer
Figure 33. TPS55340-Q1 Example Board Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS55340-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPad, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
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Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS55340-Q1
TPS55340-Q1
www.ti.com
SLVSBV5B – JUNE 2014 – REVISED JANUARY 2019
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TPS55340-Q1
31
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS55340QRTERQ1
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
55340Q
TPS55340QRTETQ1
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
55340Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2019
OTHER QUALIFIED VERSIONS OF TPS55340-Q1 :
• Catalog: TPS55340
• Enhanced Product: TPS55340-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS55340QRTERQ1
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS55340QRTETQ1
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS55340QRTERQ1
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS55340QRTETQ1
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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