Texas Instruments | TPS23523: –48-V Hot Swap and Single OR-ing Controller (Rev. A) | Datasheet | Texas Instruments TPS23523: –48-V Hot Swap and Single OR-ing Controller (Rev. A) Datasheet

Texas Instruments TPS23523: –48-V Hot Swap and Single OR-ing Controller (Rev. A) Datasheet
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TPS23523
SLVSDF9A – DECEMBER 2017 – REVISED JANUARY 2019
TPS23523: –48-V Hot Swap and Single OR-ing Controller
1 Features
3 Description
•
The TPS23523 is an integrated hot swap and OR-ing
controller that enables high power telecom systems to
comply with stringent transient requirements. The
200-V absolute maximum rating makes it easier to
survive lightning surge tests (IEC61000-4-5). The soft
start cap disconnect allows for the use of smaller hot
swap FETs by limiting the inrush current, without
hurting the transient response. The dual hot swap
gate driver saves space and BOM cost in high power
applications that require multiple hot swap FETs.The
400-µA sourcing current allows fast recovery, which
helps to avoid system resets during lightning surge
tests. The dual current limit makes it easier to pass
brown outs and input steps such as required by the
ATIS 0600315.2013. Finally, it offers accurate
undervoltage and overvoltage protection with
programmable thresholds and hysteresis.
1
•
•
•
•
•
•
•
•
–10-V to –80-V DC Operation, –200-V Absolute
Maximum
Soft Start Cap Disconnect
Dual Hot Swap Gate Drive
400-µA Gate Sourcing Current
Dual Current Limit (based on VDS)
– 25 mV ±4% When Low VDS
– 3 mV ±25% When High VDS
Programmable UV(±1.5%) and OV (±2%)
– Programmable Hysteresis (±11%)
Integrated OR-ing Controller
– Regulation: 25 mV ±15 mV
– Fast Turn off: –6 mV ±4 mV
Retries After Time Out
16-Pin TSSOP
The TPS23523 integrates an OR-ing controller,
making it ideal for –48-V systems that require reverse
hook-up protection and reverse-current protection.
The OR-ing controller protects the output when the
input drops avoiding system resets.
2 Applications
•
•
•
•
•
Remote Radio Units
Baseband Units
Routers and Switchers
Small Cells
–48-V Telecommunications Infrastructure
Device Information(1)
PART NUMBER
TPS23523
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
RTN
VCC
R1
PGb
UVEN
R2
To
Load
COUT
Vref
OV
1 k:
R3
CSS
SS
-48 V_OUT
TPS23523 PW
D
100 :
Optional
RD
Neg48
GATE2
BGATE
Q1
GATE
Q3
SNS
TMR
VEE
PROG
RSNS
CTMR
CSS,VEE
Q2
-48 V_A
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS23523
SLVSDF9A – DECEMBER 2017 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
7.1 Relationship between Sense Voltage, Gate Current,
and Timer................................................................. 10
8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Original (December 2017) to Revision A
Page
•
Added a row for VD in the Absolute Maximum Ratings table ................................................................................................ 4
•
Added tablenote 2 to the Absolute Maximum Ratings table .................................................................................................. 4
•
Updated Equation 12 ........................................................................................................................................................... 20
•
Updated Equation 22 ........................................................................................................................................................... 22
2
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SLVSDF9A – DECEMBER 2017 – REVISED JANUARY 2019
5 Pin Configuration and Functions
PW Package
16-Pin (TSSOP)
Top View
Neg48
1
16
Vref
NC
2
15
PROG
GATE2
3
14
PGb
BGATE
4
13
VCC
VEE
5
12
UVEN
SNS
6
11
OV
GATE
7
10
TMR
SS
8
9
D
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Neg48
1
NC
2
GATE2
3
O
Gate driver for the 2nd hot swap FET. NC if feature isn’t used.
BGATE
4
O
Gate driver for the OR-ing FET.
VEE
5
GND
SNS
6
I
Sense pin, used to measure current and regulate it. Kelvin Sense to RSNS to ensure accurate
current limits.
GATE
7
O
Gate drive for the main hot swap FET.
SS
8
O
Pin used for soft starting the output. Connect a capacitor (CSS) between the SS pin and
-48V_OUT. The dv/dt rate on the -48V_OUT pin is proportional to the gate sourcing current
divided by CSS.
D
9
I
Pin used to sense the drain of the hot swap FET and to program the threshold where the hot
swap switches from the CL1 and CL2. Connect a resistor from this pin to the drain of the hot
swap FET (also called -48V_OUT) to program the threshold.
TMR
10
O
Timer pin used to program the duration when the hot swap FET can be in current limit.
Program this time by adding a capacitor between the TMR pin and VEE.
OV
11
I
Input overvoltage comparator. Tie a resistor divider to program the threshold where the
device turns off due to overvoltage event.
UVEN
12
I
Input undervoltage comparator. Tie a resistor divider to program the threshold where the
device turns on.
VCC
13
S
Clamped supply. Tie to RTN through resistor.
PGb
14
O
Power Good Bar, which is an open drain output that indicated when the power is good and
the load can start drawing full power. PGb goes low when the hot swap is fully on and the
DC/DC can draw full power.
PROG
15
I
Adjust current limit and fast trip threshold by tying to VEE, floating, or tying to VEE through
resistor.
Vref
16
O
5V reference output. Connect to the base of a BJT to generate a rail that can be used to
power current monitors and digital Isolators.
I
Input to the OR-ing controller for the –48 feed. The TPS23523 will regulate the drop from
VEE to Neg48 to 25 mV to mimic an ideal diode.
No connect to space high voltage pins.
This pin corresponds to the IC GND. Kelvin sense to the bottom of RSNS to ensure accurate
current limit.
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SLVSDF9A – DECEMBER 2017 – REVISED JANUARY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage
MIN
MAX
UNIT
VVCC (current into VCC <10 mA)
–0.3
20
V
VSNS, VOV
–0.3
6.5
V
VUVEN, , VSS
–0.3
30
V
VD (2)
–0.3
40
V
VNeg48
–0.3
200
V
VNeg48 through 100-Ω resistor
–1
200
V
VNeg48 through 1-kΩ resistor
–2
200
V
VGATE, VGATE2, VBGATE
–0.3
VCC
V
VTMR , VPROG, VVREF
–0.3
6.5
V
VPGb
–0.3
200
V
Operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–55
150
°C
Input voltage
Output voltage
Output voltage
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Current into the Pin D should be limited to < 1 mA through RD resistor
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VVCC
Supply voltage (current into VCC <10 mA)
0
20
V
VSNS, VOV
Input voltage
0
5.5
V
VUVEN, VD, VSS
Input voltage
VNeg48
Input voltage, through 100-Ω resistor
VGATE, VGATE2, VBGATE
0
18
V
–0.2
150
V
Output voltage
0
VCC
V
VTMR , VPROG, VVREF
Output voltage
0
5.5
V
VPGb
Output voltage
0
80
V
CSS
Capacitance
1
200
nF
RSS
Resistance
1
10
kΩ
RD
Resistance
120
2,000
kΩ
RNEG48V
Resistance
100
1
kΩ
4
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6.4 Thermal Information
TPS23523
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
98.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.3
°C/W
RθJB
Junction-to-board thermal resistance
44.3
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
43.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1
V < VNEG48Vx < 150 V, VVref = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
9
9.5
10
UNIT
VCC – Clamped Supply
V(UVLO_VCC)
UVLO on VCC
rising
V(UVLO_VCC,hyst)
UVLO hysteresis on VCC
hysteresis
VCC regulation
1.1< I(VCC) < 10 mA (current into
VCC)
V(VCC)
IQ
Quiescent Current
1
12
14.5
V
V
18
V
VVCC = 10 V. Off
1
mA
VVCC = 10 V. On
1
mA
1.1
mA
VVCC = 10 V, Gateand BGATE in
regulation
UVEN – Undervoltage and Enable
V(UVEN_T)
Threshold voltage for V(UVEN)
I(UV_hyst)
Hysteresis current, sourcing
from UV pin
VUV = 1.5 V
0.985
1
1.015
V
9
10
11.2
µA
0.98
1
1.02
V
9
10
11.2
µA
OV – Overvoltage
V(OV_T)
Threshold voltage for VOV
I(OV_hyst)
Hysteresis current, sourcing
from OV pin
VOV = 1.5 V
VTMR
Voltage on timer when part
times out.
VD = 0 V, TMR ↑, measure VTMR
when VGATE = 0
1.47
1.5
1.53
V
VTMR2
Voltage on timer when part
times out.
VD = 1 V, TMR ↑, measure VTMR
when VGATE = 0
0.735
0.75
0.765
V
VSNS = 0.1 V, VD = 0 V, VTMR = 0 V,
measure I out from TMR
9
10
11
µA
ITMR,SRs
Timer Sourcing current when
in fault condition or when
retrying.
VSNS = 0.1 V, VD = 2 V, VTMR = 0 V,
measure I out from TMR
45
50
55
µA
1.5
2
2.5
µA
0.475
0.5
0.525
V
15
µA
TMR – Timer
ITMR,SNC
Timer sinking current when
not in fault condition.
VSNS = 0 V, VD = 0 V, VTMR = 2 V,
VTMR,RETRY
Voltage on timer when the
timer starts going back up in
retry. Retry version only.
VSNS = 0 V, VD = 0 V, TMR ↑ = 2 V,
TMR ↓, measure VTMR when I into
TMR change polarity
NRETRY
Number of retry duty cycles.
Retry version only.
DRETRY
Retry duty cycle. Retry
version only.
IGATE,TIMER
Gate Sourcing Current
Threshold When timer starts
to run.
64
0.4%
VG = 5 V, VD = 2 V, VSNS ↑,
measure IGATE when TMR sources
current
5
10
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1
V < VNEG48Vx < 150 V, VVref = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSNS,TMR1
Sense Voltage when Timer
starts to run.
VD = 2 V, VTMR = 0 V, VG = 5 V;
VSNS ↑, measure VSNS when TMR
sources current
VSNS,TMR2
Sense Voltage when Timer
starts to run.
VD = 0 V, VTMR = 0 V , VG = 5 V;
VSNS ↑, measure VSNS when TMR
sources current
MIN
TYP
MAX
UNIT
1.5
2.5
mV
23.25
24.5
mV
SNS – Sense Pin For Current Limit
ISNS,LEAK
VSNS,CL1
Leakage current on sense
pin
PROG = Float
PROG = VEE
-2
VTMR = 0 V. VGATE = 5 V. VD = 0 V,
VSNS ↑, measure when IGATE = 0;
PROG = FLOAT
VSNS,FST
PROG = VEE
RPROG = 78.7kΩ
VTMR = 0 V. VGATE = 5 V. VD = 0 V,
VSNS ↑,measure when IGATE> 100
mA
RPROG = 162 kΩ
2
µA
24
25
26
mV
38
40
42
mV
45
50
55
mV
72
80
88
mV
110
120
130
mV
68
75
82
mV
VSNS,CL2
Fold Back Current Limit
VTMR = 0 V, VGATE = 5 V, VD = 5 V,
VSNS ↑, measure when IGATE = 0;
2.25
3
3.75
mV
VSNS,FST2
Fast Trip during start-up
VTMR = 0 V, VGATE = 5 V, VD = 5 V,
VSNS ↑, Measure when IGATE> 100
mA
6
9
12
mV
7.9
10.1
12
µA
0.48
V
1.51
V
PROG – Programing Pin to Set Current Limit (CL) and Fast Trip
iPROG
PROG pin current
VPROG,LOW
Prog pin voltage
Threshold on VPROG, where the fast
trip setting changes from 80mV to
120mV.
VPROG,MID
Prog pin voltage
Threshold on VPROG, where the
current limit setting changes from
25mV to 40mV.
VPROG,High
Prog pin voltage
Threshold on VPROG, where the fast
trip setting changes from 80mV to
120mV.
0.94
1.23
2.4
V
GATE – Gate Drive for Main Hot Swap FET
V(VCC-GATE)
Output gate voltage
V(SNS) = 0 V
1
V
I(GATE,SRS,NORM)
Sourcing Current during
normal operation.
V(TMR) = 0 V. V(GATE) = 8 V. VD = 0
V, V(SNS) = 0 V
250
400
I(GATE,SRS,START)
Sourcing Current during starup
V(TMR) = 0 V. V(GATE) = 5 V. VD = 0
V, V(SNS) = 0 V
15
20
25
µA
I(GATE,wkpd)
Weak pull down current
V(SNS) = 0 V. VUVEN = 0 V
3
5
7
mA
I(GATE,FST)
Fast Pull down current with
10mV overdrive
0.4
1
1.5
µA
A
GATE2 – Gate Drive for Auxiliary Hot Swap FET
V(VCC-GATE2)
Output gate voltage
V(SNS) = 0 V
I(GATE2,wkpd)
weak pull down
VGATE = 0 V
I(GATE2,SRC)
Sourcing Current
IGATE2,FST
Fast Pull down current with
10 mV overdrive
VGATE,TH
Threshold on VGATE when
GATE2 turns on
Raise VGATE, measure when VGATE2
comes up.
VGATE,TH,hyst
Hysteresis of threshold on
VGATE when GATE2 turns on
hysteresis
1
V
5
mA
50
µA
0.4
1
1.5
A
6.25
7.25
8
V
0.5
V
D – Drain Sense
6
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1
V < VNEG48Vx < 150 V, VVref = VPROG = Hi-Z; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
R(D,INT)
Resistance from the drain pin
to GND.
TEST CONDITIONS
28.5
30
31.5
kΩ
V(D,CL_SW)
Voltage on drain that
V(TMR) = 0 V, V(GATE) = 5 V, V(SNS) =
switches between two current 20 mV, D↑, measure V when I(GATE)
limits
=0
1.46
1.5
1.54
V
V(D,TMR_SW)
Voltage on drain that
switches the VTMR threshold.
V(TMR) = 1 V, V(GATE) = 5 V, V(SNS) =
20 mV, D↑, measure V when I(GATE)
=0
0.73
0.75
0.77
V
V(D,TMR_SW,hyst)
hysteresis for V(D,TMR,SW)
hysteresis
75
mV
SS (Soft Start)
I(SS,PD)
Pull down current when not in
VSS = 5 V
inrush
R(SS,GATE)
Resistance between GATE
and SS in the start-up phase
100
mA
80
Ω
Vref
VVref
Reference output
0 < IVref < 800 µA
IVref
VVref SC current
Vref ON, VVref (shorted)
4
4.9
5.5
2
V
mA
Neg48
I(lkg,Neg48)
Leakage current
VNeg48 = –50 mV, BGATE ON
-2
VNeg48 = –100 mV, BGATE ON
-7
VNeg48 = 150 V, BGATE off
V(FWD)
Forward regulation voltage of
the OR-ing controller. VFWD =
VEE – V(NEG48Vx)
V(FWD,FST)
Forward voltage where a fast
pull up is activated.
V(RV)
Fast reverse trip voltage.
VGATEx = 5 V. VVEE – VNeg48Vx ↑
measure when IGATEx = 100 µA
2
µA
7
µA
30
µA
10
25
40
mV
50
80
105
mV
2
6
10
mV
0.65
1.1
V
BGATE
VVCC-BGATE
Gate Output Voltage.
I(BGATE,SRS)
Gate sourcing current in
regulation
VVEE – VNeg48Vx = 50 mV
5
µA
I(BGATE,SINK)
Gate sinking current in
regulation
VVEE – VNeg48Vx = 0
5
µA
RGATE,SRC,FST
Pull up resistance in fast
sourcing mode.
VVEE – VNeg48Vx = 100 mV; Measure
current at VGATEx = 0 V. R = VVCC/I
10
kΩ
I(BGATE,FST)
Fast Gate pull down current
V(VEE) – VNeg48 = –15 mV
0.4
1
1.5
A
6.5
7.25
8
V
1.5
V
1
µA
175
°C
PGb (Power Good Bar)
V(GATE2,PGb)
Threshold on GATE2 that
triggers PGb to assert.
Raise VGATE2 until PGb asserts
V(PGb,PD)
Pull down strength on PGb
PGb sinking 1 mA
I(PGb,LEAK)
leakage current on PGb pin
OTSD (Over Temperature Shut Down)
TSD
Shutdown temperature
TSD,hyst
Shutdown temperature
Hysteresis
Temp Rising
135
155
8
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC – Clamped Supply
tID
Insertion Delay
VVCC: 0 V → 10 V, measure delay
before VGATE ↑
32
ms
Deglitch on UVEN
4
µs
Deglitch on OV
4
µs
VSNS steps from 0 mV to 60 mV.
Measure time for GATE and GATE2
to come down.
300
ns
VNEG48V steps from -40 mV to 15
mV. Measure time for BGATE to
come down.
300
ns
Power Good ↑ (V(GATE) 0 V → 10 V)
Look for PGb ↓
1
ms
Power Good ↓ (V(GATE) 10 V → 0 V)
Look for PGb ↑
32
ms
UVEN
TUV,degl
OV
TOV,degl
SNS
TSNS,FST,R
Response time to large over current
ESP
Neg48V
TNeg48V,FST Response time to large reverse
current
,RESP
PGb
tPGb,DEGL
8
Deglitch of PGb. (GATE2 =
unloaded, raise GATE, measure
delay between GATE and PGb)
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6.7 Typical Characteristics
Unless otherwise noted: –40°C ≤ TJ ≤125°C, 1.1 mA < IVCC < 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx
= Hi-Z , V(TMR) = 0 V, –1 V < VNEG48Vx < 150 V , VVref = VPROG = Hi-Z;
Ivcc injected into VCC pin
VVCC = 10 V, Regulation is current limit
Figure 1. VCC Regulation Voltage vs Current and
Temperature
Figure 2. Iq vs Temperature and Operating Condition
Figure 3. Isns Current Vs Temperature
Figure 4. VVref vs Temperature and IVREF
Figure 5. Vpgb vs Temperature
Figure 6. VVCC-GATE vs Temperature
In Power Good
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7 Parameter Measurement Information
7.1 Relationship between Sense Voltage, Gate Current, and Timer
The diagram below illustrates the relationship between the VSNS (voltage across RSNS), Gate current, and the
timer operation. The diagram is intended to help explain the various parameters in the electrical characteristic
table and is not drawn to scale.
Note that IGATE reduces as the sense voltage approaches the current limit threshold and it equals zero at the
current limit regulation point. To ensure that the timer always runs when the IC is in regulation the timer starts at
a slightly positive IGATE.
Figure 7. Relationship Between Timer, Gate Current, and Sense Voltage (VGATE = 5 V)
10
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8 Detailed Description
8.1 Overview
The TPS23523 is an integrated hot swap and Single OR-ing controller that enables high power telecom systems
to comply with stringent transient requirements. The soft start cap disconnect allows soft start at start-up and
disconnects the soft start cap during normal operation. This allows for the use of smaller hot swap FETs without
hurting the transient response. GATE2 is a second hot swap FET driver, which only turns ON when the main hot
swap FET is fully on. Thus the FETs driven by GATE2 don't need to have strong SOA. This saves space and
BOM cost in high power applications that require multiple hot swap FETs.The 400 µA sourcing current allows
fast recovery, which helps to avoid system resets during lightning surge tests. The dual current limit makes it
easier to pass brown outs and input steps such as required by the ATIS 0600315.2013. Finally, the TPS23523
offers accurate undervoltage and overvoltage protection with programmable thresholds and hysteresis.
The TPS23523 integrates an OR-ing controller, making it ideal for –48 V systems that require reverse hook-up
protection and reverse-current protection. The OR-ing controller protects the output when the input drops
avoiding system resets. The OR-ing controller will turn off if any reverse current is detected.
8.2 Functional Block Diagram
RTN
VCC
Vref
Internal
Regulator
& Band Gap
VINT
V1V
HS_ON
iHYST
R1
VINT,GD
PGb
DIS_RTN
UVEN
Time Out
VING
V1V
R2
Logic, Timing, and
Control
COUT
To
Load
PROG
OV_GD
OV
V1.5V
GATE2_Hi
SS_ON
VINT
iHYST
Hi_CL
R3
D
30k
SS CSS
RD
1k
SS
Disconnect
Neg48
BGATE
GATE2
ORing
Control
Time
Out
Timer
Block
IC_GND
VEE
-48V
Q3
Q2
VVCC
Current Limit
& Gate Drive
GATE
in ILIM
HS_ON
TMR
Q1
SNS
RSNS
CTMR
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8.3 Feature Description
8.3.1 Current Limit
The TPS23523 utilizes two current limit thresholds:
• ICL1 – also referred to as high current limit threshold, which is used when the VDS of the hot swap FET is low.
• ICL2 – lower current limit threshold, which is used when the VDS of the hot swap FET is high.
This dual level protection scheme ensures that the part has a higher chance of riding out voltage steps and other
transients due to the higher current limit at low VDS, while protecting the MOSFET during start into short and hotshort events, by setting a lower current limit threshold for conditions with high VDS. The transition threshold is
programmed with a resistor that is connected from the drain of the hot swap FET to the D pin of the TPS23523.
The figure below illustrates an example with a ICL1 set to 25 A and ICL2 set to 3 A. Note that compared to a
traditional SOA protection scheme this approach allows better utilization of the SOA in the 10 V < VDS. < 40-V
range, which is critical in riding through transients and voltage steps.
Note that in both cases the TPS23523 regulated the gate voltage to enforce the current limit. However, this
regulation is not very fast and doesn’t offer the best protection against hot-shorts on the output. To protect in this
scenario a fast comparator is used, which quickly pulls down the gate in case of severe over current events (2x
bigger than VCL1).
Figure 8. Dual Current Limit vs FET Power Limit
8.3.1.1 Programming the CL Switch-Over Threshold
The VDS threshold when the TPS23523 switches over from ICL1 to ICL2 (VD,SW) can be computed using
Equation 1. For example, if a 15-V switch over is desired, RD should be set to 270 kΩ.
V DS,SW
1.5 V u 30 kß R D
30 kß
(1)
8.3.1.2 Setting Up the PROG Pin
The PROG pin can be tied to VEE, left floating, or tied to VEE through a resistor to adjust VSNS,CL1 and the ratio
of fast trip to current limit. The options are set as follows:
●PROG = NC or Float: VSNS,CL1 = 25 mV, VSNS,FST is 2x VSNS,CL1
●RPROG = 196 kΩ (1%): VSNS,CL1 = 25 mV, VSNS,FST is 3x VSNS,CL1
12
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Feature Description (continued)
●RPROG = 66.5 kΩ (1%): VSNS,CL1 = 40 mV, VSNS,FST is 3x VSNS,CL1
●PROG = VEE: VSNS,CL1 = 40 mV, VSNS,FST is 2x VSNS,CL1
8.3.1.3 Programming CL1
The current limit at low VDS (ICL1) of the TPS23523 can be computed using Equation 2.
I CL1
V SNS,CL1
R SNS
(2)
To compute ICL1 for a 1-mΩ sense resistor use Equation 3 below.
I CL1
V SNS,CL1
R SNS
25 mV
1 mß
25 A
(3)
8.3.1.4 Programming CL2
The current limit at high VDS (ICL2) of the TPS23523 can be computed using Equation 4.
I CL2
V SNS,CL2
R SNS
(4)
To compute ICL2 for a 1-mΩ sense resistor use Equation 5.
I CL2
V SNS,CL2
R SNS
3 mV
3A
1 mß
(5)
8.3.2 Soft Start Disconnect
The inrush current into the output capacitor (COUT) can be limited by placing a capacitor between the SS (Soft
Start) pin and the drain of the hot swap MOSFET. In that case the inrush current can be computed using
Equation 6.
C OUT u I GATE,SRS,START
660 µF u 20 µA
I INR
0.4 A
C SS
33 nF
(6)
Note that with most hot swap the CSS pin is tied simply to the gate pin, but this can interfere with performance
during normal operation if transients or short circuits are encountered. In addition the CSS capacitor tends to pull
up the gate during hot plug and cause shoot through current if it is always tied to the gate. For that reason the
TPS23523 has a disconnect switch between the gate pin and the SS pin as well as a discharge resistor. During
the initial hot plug and during the insertion delay the switch between SS and GATE is open and SS is being
discharged to GND through a resistor. Then during start-up SS and GATE are connected to limit the slew rate.
Once in normal operation the SS pin is not tied to GATE and it is not shorted to GND, which prevents it from
interfering with the operation during transients.
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Feature Description (continued)
SS
1k
CSS
SS_Dis
CSS,GND
SS_ON
Q1
GATE
Figure 9. Implementation of SS Disconnect
8.3.3 Timer
Timer is a critical feature in the hot swap, which manages the stress level in the MOSFET. The timer will source
and sink current into the timer capacitor as follows:
• Not in current limit: sink 2 µA
• If the part is in current limit and VGATE < VGATE,TH, the timer sources current as follows:
– VD < VD,CL_SW: source 10 µA
– VD > VD,CL_SW: source 50 µA
The TPS23523 times out and shuts down the hot swap as follows.
• If VD < VD,TMR_SW then the hot swap times out when VTMR reaches 1.5 V.
• If VD > VD,TMR_SW then the hot swap times out when VTMR reaches 0.75 V.
The above behavior maximizes the ability of the hot swap to ride out voltage steps, while ensuring that the FET
remains safe even if the part can not ride out a voltage step.
A
•
•
•
•
cool down period follows after the part times out. During this time the timer performs the following:
Discharge CTMR with a 2-µA current source until 0.5 V
Charge CTMR with a 10-µA current source until it is back to 1.5 V.
Repeat the above 64 times
Discharge timer to 0 V.
The part attempts to restart after finishing the above. If the UVEN signal is toggled while the 64 cycles are in
progress the part restarts immediately after the 64 cycles are completed.
The timer operates as follows when recovering from POR:
• If VTMR < 0.5 V:
– Proceed to regular startup
– Do not discharge VTMR
• If VTMR > 0.5 V:
– Go through 64 charge/discharge cycles
– Discharge VTMR
– Proceed to startup
The Time Out (TTO) can be computed using the equations below. Note that the time out depends on the VDS of
the MOSFET.
14
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Feature Description (continued)
T TO
C TMR u V TMR
T TO (V D
I TMR,SRS
0.75 V)
T TO (0.75 V
VD
T TO (V D ! 1.5 V)
(7)
C TMR u 1.5 V
10 PA
1.5 V)
(8)
C TMR u 0.75 V
10 PA
(9)
C TMR u 0.75 V
50 PA
(10)
8.3.4 Gate 2
The TPS23523 features a second hot swap Gate drive, which can be used to save BOM cost and size in
applications that require multiple hot swap MOSFETs. The 2nd MOSFET is only turned ON when the main FET
is enhanced. As a result the 2nd MOSFET doesn't operate with large current and large voltage across it, thus
reducing the SOA requirements. In many cases a 5x6 QFN FET can replace a D2PACK FET. The following
figures show the operation during start-up and Hot Short event. It can be seen that the second FET is OFF
during stressful operation and turns on during normal operation to improve steady state efficiency and reduce
power losses.
Figure 10. Gate 2 Operation During Start-Up
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Feature Description (continued)
Figure 11. Gate2 Operation During Hot Short
8.3.5 OR-ing
The TPS23523 features integrated OR-ing that controls the external MOSFET in a way to emulate an ideal
diode. The TPS23523 will regulate the forward drop across the OR-ing FET to 25 mV. This is accomplished by
controlling the VGS of the MOSFET. As the current decreases the VGS is also decreased, which effectively
increases the RDSON of the MOSFET. This process is regulated with a low gain amplifier that is gate (OR-ing
FET) pole compensated. The lower gain helps ensure stability over various operating conditions. The regulating
amplifier ensures that there is no DC reverse current.
However, the amplifier is not very fast and thus it is paired with a fast comparator. This comparator quickly turns
off the FET if there is significant reverse current detected.
Figure 12. Simplified Diagram of OR-ing Block
16
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8.4 Device Functional Modes
Figure 13. Simplified Hot Swap State Machine
The Figure above shows a simplified state machine of the hot swap controller. It has 4 distinct operating states
and the controller switches between these states based on the following signals:
• Ving_rc: This means that both the input voltage is in the right range and the IC has power with Vcc. A 4-µs
delay is added for deglitching. If the input voltage is above the OV threshold, input voltage is below the UV
threshold, or VCC is below its internal UVLO, Ving_rc will be low.
• TimeOut: This signal comes from the timer block and will be asserted Hi if the IC has timed out due to an
over-current condition. This signal is also Hi while the timer is going through the restart cycles. Once the
cycles are completed this signal will go Low.
• ins_over: This signal states that the insertion delay has been completed and the hot swap is ready to start-up.
• FT: this is the fast trip signal coming from the fast trip comparator. It goes Hi if an extreme over current event
is detected.
• PG: Internal Power good signal. This is high when the hot swap is fully on and the load can draw full power.
For PG to be Hi, the GATE has to be Hi, GATE2 needs to be Hi, and the drain pin needs to be below 0.75 V.
• PG_degl: This is a deglitched version of the PG and is the signal used to move between states and controls
the external PGb pin.
8.4.1 OFF State
In this state the hot swap FET is turned off and the controller is waiting to start-up. The controller can be in this
state due to any of these scenarios:
• Input voltage is not in the valid range.
• The hot swap is in the cool down state and the timer is going through the retry cycle after a fault condition
such as output hot short or over current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
8.4.2 Insertion Delay State
In this state the hot swap FET is turned off and the controller is waiting for the insertion delay to finish. This
allows the input supply to settle after a Hot Plug. If any of the following occur, the controller will be kicked back to
the OFF state:
• Input voltage is not in the valid range.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
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Device Functional Modes (continued)
Once the insertion delay is finished, the controller will move to the Start-up state.
8.4.3 Start-up State
In this state the controller is turning on and charging the output cap. The operation is set as follows:
• The SS pin is internally connected to the GATE pin to allow for output dv/dt control.
• Lower gate sourcing current is applied to the GATE pin to allow for smaller SS caps.
• The lower current limit setting of VSNS,CL2 and a lower fast trip setting of VSNS,FST2 is used to minimize the
MOSFET stress in case of a fault condition.
If any of the following occur, the controller will be kicked back to the OFF state:
• Input voltage is not in the valid range.
• The timer times out due to over-current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
• Fast trip is triggered.
Once the PG_degl signal goes Hi, the controller will move to the Normal Operation state.
8.4.4 Normal Operation State
In this state the hot swap is fully on and the operation is set as follows:
• The SS pin is disconnected from the GATE pin to improve transient response.
• The full gate sourcing current is used to improve transient response.
• The current limit and fast trip threshold are a function of the D pin to optimize the transient response while
protecting the MOSFET.
If any of the following occur, the controller will be kicked back to the OFF state:
• PG_degl goes low.
• The timer times out due to over-current.
• VCC is below its UVLO threshold and the IC doesn’t have enough power to operate properly.
Note that if the input voltage is outside the valid range or the fast trip is triggered, the hot swap FET will turn off,
but the controller will not exit the Normal Operation state. In this case the PG signal would go low immediately. If
this condition persists, the PG_degl will go low as well and the controller would move to the OFF state. This
operation prevents the controller from re-starting the system during quick transients.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS23523 is a hot swap controller for –48-V applications and is used to manage inrush current and protect
downstream circuitry and the upstream bus in case of fault conditions. The following key scenarios should be
considered when designing a –48-V hot swap circuit:
• Start Up.
• Output of a hot swap is shorted to ground while the hot swap is on. This is often referred to as a Hot Short.
• Powering up a board when the output and ground are shorted. This is usually called a start-into-short.
• Input lightning surge. Here it is usually desired to avoid damage to downstream circuitry and to avoid system
restarts.
These scenarios place a lot of stress on the hot swap MOSFET and the board designer should take special care
to ensure that the MOSFET stays within it's Safe Operating Area (SOA) under all of these conditions. A detailed
design example is provided below and the key equations are written out. Note that solving all of these equations
by hand is cumbersome and can result in errors. Instead, TI recommends using the TPS2352X Design
Calculator provided on the product page.
9.2 Typical Application
RTN
RVCC
CVCC
10 Ÿ
VCC
RUV1
D3
0.1µF
D1
COV
ROV2
0.1µF
1µF
ROV1
CUV
UVEN
PGb
OV
Vref
CDCDC
LEMI
RUV2
CSS
1k
SS
TPS23523PW
RD
Part of DC/DC
D
Optional
10 Ÿ
Q2
GATE2
Neg48
10 Ÿ
BGATE
Q1
GATE
SNS
100 Ÿ
PROG
VEE
TMR
RSNS
CSS,VEE
10 Ÿ
-48V
RPROG
CTMR
Q3
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Figure 14. Application Diagram for Design Example
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Typical Application (continued)
9.2.1 Design Requirements
The table below summarizes the design parameters that must be known before designing a hot swap circuit.
When charging the output capacitor through the hot swap MOSFET, the FET’s total energy dissipation equals
the total energy stored in the output capacitor (1/2CV2). Thus both the input voltage and output capacitance will
determine the stress experienced by the MOSFET. The maximum load power will drive the current limit and
sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and the thermal
properties of the PCB (RθCA) will drive the selection of the MOSFET's RDSON and the number of MOSFETs used.
RθCA is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET.
Air cooling will also reduce RθCA substantially. Finally, it's important to know what transients the circuit has to
pass in order to size up the input protection accordingly.
Table 1. Design Requirements for a –38 V to –60 V, 400-W Protection Circuit
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
–38 V to –60 V
Maximum Load Power
400 W
Output Capacitance
660 µF
Location of Output Cap
After EMI filter with ~5 µH of inductance.
Maximum Ambient Temperature
85°C
MOSFET RθCA (function of layout)
20°C/W
Pass “Hot-Short” on Output?
Yes
Pass a “Start into short”?
Yes
Is the load off until PG asserted?
Yes
Max Input Inductance
10 µH
Level of IEC61000-4-5 to pass
2-kV Line to Line with 2-Ω series impedance
Pass Reverse Hook Up
Yes
9.2.2 Detailed Design Procedure
9.2.2.1 Selecting RSNS
Before selecting RSNS, first compute the maximum load current. For this example the worst case load current
happens at the minimum input voltage of 38 V. Thus the maximum current is 400 W/38 V = 10.5 A. To provide
some margin, set the target current limit to 12 A and compute RSNS using equation below:
R SNS,CLC
V SNS,CL1
I CL1
25 mV
12 A
2.08 m:
(11)
Use next available RSNS of 2 mΩ.
9.2.2.2 Selecting Soft Start Setting: CSS and CSS,VEE
First, compute the minimum inrush current where the timer will trip using equation below.
IINR,TMR
VSNS,TMR1
RSNS
1.5 mV
2 m:
0.75 A
(12)
To avoid running the timer the inrush current needs to be sufficiently low. Target 0.4 A of inrush current to allow
margin, and compute the target CSS using equation below.
c SS
20
c OUT,MAX u I GATE,SRS,START
I INR,TGT
792 µF u 20 µA
0.4 A
39.6 nF
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Next choose, the next available CSS greater than 39.6 nF. For this example 43 nF was used, which assumes a
33 nF and 10 nF cap in parallel. This results in an inrush current of 0.37 A at max COUT (792 µF) and inrush
current of 0.31 A at typical COUT (660 µF). Also it is recommended to add a capacitor between the soft start pin
and VEE (CSS,VEE) to improve immunity to input voltage noise during soft start. It's recommended to chose a
capacitor that's 3x larger than CSS. In this case a 150 nF capacitor was chosen.
Finally the start-up time at maximum input voltage can be computed using the equation below:
c SS u VIN,MAX
T START VIN,MAX
43nF u 60 V
20 µA
I GATE,SRS,START
129 ms
(14)
9.2.2.3 Selecting VDS Switch Over Threshold
The VDS threshold where the current limit switches from CL1 to CL2 can be programmed using RD. In general a
higher threshold improves ability to ride through voltage steps, brown outs, and other transients. However, a
larger setting can also expose the MOSFET to more stress, because the larger current limit is now allowed at
higher VDS voltages. If there are no specific voltage step requirements, 20 V is a good starting point. Use the
equation below to compute the target RD.
§ V DS,SW
·
R D 30 kß u ¨
1¸ 370 kß
© 1.5 V
¹
(15)
9.2.2.4 Timer Selection
The timer determines how long the hot swap can be in current limit before timing out and can be programmed
using CTMR. In general a longer time out (TTO) improves ability to ride through voltage steps, brown outs, and
other transients. However, a larger setting can also expose the MOSFET to more stress, because it takes longer
for the FET to shut down during fault conditions. If there are no specific voltage step or transient requirements, 2
ms is a good starting point. Use the equation below to compute the target CTMR. Choose the next available
capacitor value of 15 nF, which results in a 2.25 ms time out.
C TMR
T TO u I TMR,SRS
V TMR
2 ms u 10 PA
1.5 V
13.3nF
(16)
9.2.2.5 MOSFET Selection and SOA Checks
When selecting MOSFETs for the –48 V application the three key parameters are: VDS rating, RDSON, and safe
operating area (SOA). For this application the CSD19535KTT was selected to provide a 100 V VDS rating, low
RDSON, and sufficient SOA. After selecting the MOSFET, it is important to double check that it has sufficient SOA
to handle the key stress scenarios: start-up, output Hot Short, and Start into Short. MOSFET's SOA is usually
specified at a case temperature of 25°C and should be derated based on the maximum case temperature
expected in the application. Compute the maximum case temperature using the equation below. Note that the
RDSON will vary with temperature and solving the equation below could be a repetitive process. The
CSD19535KTT, has a maximum 3.4 mΩ RDSON at room temperature and is ~1.5x higher at 100°C. N stands for
the number of MOSFETs used in parallel.
T C,MAX
T C,MAX
T A,MAX
85 qC
§ I LOAD,MAX
R TCA u ¨¨
N
©
20q
C
u 10.5 A
W
2
2
·
¸¸ u R DSON TJ
¹
u 3.4 u 1.5 m:
(17)
96.3 qC
(18)
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Next the stress the MOSFET will experience during operation should be compared to the FETs capability. First,
consider the power up. The inrush current with max COUT will be 0.37 A and the inrush will last for 129 ms. Note
that the power dissipation of the FET will start at VIN,MAX × IINR and reduce to zero as the VDS of the MOSFET is
reduced. The SOA curve of a typical MOSFET assume the same power dissipation for a given time. A
conservative approach is to assume an equivalent power profile where PFET = VIN,MAX × IINR for t = Tstart-up /2. In
this instance, the SOA can be checked by looking at a 60 V, 0.4 A, 64.5 ms pulse. Based on the SOA of the
CSD19535KTT, it can handle 60 V, 1.8 A for 10 ms and it can handle 60 V, 1 A for 100 ms. The SOA at TC =
25°C for 64.5 ms can be extrapolated by approximating SOA vs time as a power function as shown in equations
below:
a u tm
I SOA t
m
a
(19)
ln (I SOA t 1 / I SOA t 2 )
ln t 1 / t 2
I SOA t 2
tm
2
§ 1.8 A ·
ln ¨
¸
© 1A ¹
§ 10 ms ·
ln ¨
¸
© 100 ms ¹
1A
100 ms
ISOA 64.5 ms,25 qC
0.25
3.16 A u ms
0.25
(20)
0.25
(21)
3.16 A u ms
0.25
u 64.5 ms
0.25
1.12 A
(22)
Finally, the FET SOA needs to be derated based on the maximum case temperature as shown below. Note that
the FET can handle 0.59 A, while it will have 0.37 A during start-up. Thus there is a lot of margin during this test
condition.
I SOA 64.5 ms, T C,MAX
1.12 A u
175 qC 96.3 qC
175 qC 25 qC
0.59 A
(23)
A similar approach should be taken to compute the FETs SOA capability during a Hot Short and start into short.
As shown in the following figure, during a start into short the gate is coming up very slowly due to a large
capacitance tied to the gate through the SS pin. Thus it is more stressful than a Hot Short and should be used for
worst case SOA calculations. To compare the FET stress during start-up into short to the SOA curves the stress
needs to be approximated as a square pulse as showing in the figure below. In this example, the stress is
approximated with a 1.1 ms (Teq), 1.5 A, 60 V pulse. The FET can handle 6 A, 60 V for 1 ms and 1.8 A, 60 V for
10 ms. Using approximation and temp derating as shown earlier, the FET's capability can be computed as 3 A,
60 V, for 1.1 ms at 96°C. 3 A is significantly larger than 1.5 A implying good margin.
22
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Figure 15. Teq During a Start Into a Short
The final operating point to check is the operation with high current and VDS just below the VDS,SW threshold. In
this example, the time out would be 1.1ms (one half of the time out at Vd = 0 V), the current will be 12.5 A, and
the voltage would be 20 V. Looking up the SOA curve, the FET can handle 30 A, 20 V for 1 ms and 10 A, 20 V
for 10 ms. Repeating previously shown approximations and temp derating, the FET's capability is computed to be
16 A, 20 V, for 1.1 ms at 96°C. Again this is below the worst case operating point of 12.5 A and 20 V suggesting
good margin.
9.2.2.6 Input Cap, Input TVS, and OR-ing FET selection
This design example is sized for an application that needs to pass a 2 kV, 2Ω lightning strike per IEC61000-4-5.
This equates to almost 1000 A of input current that needs to be clamped. In addition, the design needs to pass
reverse hook up and thus the TVS needs to be bi directional. A ceramic transient voltage suppressor (2x
B72540T6500S162) CT2220K50E2G was used to clamp this huge surge of current. According to it's datasheet it
can clamp 500 A of current to 150 V. Note that the lightning strike can be positive or negative. The worst case
voltage is dropped across the OR-ing FETs when the strike is positive (–48 V line goes above RTN). If the output
of the OR-ing is –48 V and the input goes to +150 V that is a 200 V drop. Thus BSC320N20NS3 was chosen for
the OR-ing FETs. This is a 200 V FET with a 32 mΩ RDSON at room temperature. 2 of these were used in parallel
to minimize power loss and manage thermal. Finally a 0.1 µF input bypass cap is recommended.
9.2.2.7 EMI Filter Consideration
In this example it is assumed that the EMI filter is right after the hot swap and the bulk cap is after the EMI filter.
The EMI filter adds significant inductance and needs to be accounted for. During a Hot Short, the inductor builds
up significant current that needs to go somewhere after the FET opens. For that a free wheeling diode should be
used along with a snubber. For this example a 150 V, SMA diode was used: STPS1150A. The snubber
consisted of a 10-Ω resistor in series with a 1-µF ceramic capacitor. In addition a 0.1-µF ceramic cap was tied
directly on the output.
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9.2.2.8 Undervoltage and Overvoltage Settings
Both the threshold and hysteresis can be programmed for undervoltage and overvoltage protection. In general
the rising UV threshold should be set sufficiently below the minimum input voltage and the falling OV threshold
should be set sufficiently above the maximum input voltage to account for tolerances. For this example a rising
UV threshold of 37 V and a falling UV threshold of 35 V was chosen as the target. First, choose RUV1 based on
the 2 V UV hysteresis as shown below.
V UV,hyst,tgt
2V
R UV1
200 kßG
i UV,hyst
10 µA
(24)
Once RUV1 is known RUV2 can be computed based on the target rising UV threshold as shown below.
R UV1
200 kß
R UV2
5.56 kß
V UV,TGT,Risin g 1 V
37 V 1 V
The OV setting can be programmed in a similar fashion as shown in equations below.
V OV,hyst,tgt
3V
R OV1
300 kß
i OV,hyst
10 µA
R OV2
R OV1
V OV,TGT,Ri sing 1 V
300 kß
65 V 1 V
(25)
(26)
(27)
4.68 kß
(28)
Optional filtering capacitors can be added to the UV and OV to improve immunity to noise and transients on the
input bus. These should be tuned based on system requirements and input inductance. In this example place
holders were added to the PCB, but the components were not populated.
9.2.2.9 Choosing RVCC and CVCC
The VCC is used as internal supply rail and is a shunt regulator. To ensure stability of internal loop a minimum of
0.1 µF is required for CVCC. To ensure reasonable power on time it is recommended to keep CVCC below 1 µF.
RVCC should be sized in such a way to ensure that sufficient current is supplied to the IC at minimum operating
voltage corresponding to the falling UV threshold. To allow for some margin it is recommended that the current
through RVCC is at least 1.2x of IQ,MAX when RTN = Falling UV threshold and VCC = 10 V (minimum
recommended operating voltage on VCC). For this example RVCC of 16.2 kΩ was used.
9.2.2.10 Power Good Interface to Downstream DC/DC
It's critical to keep the downstream DC/DC off while the hot swap is charging the bulk capacitor. This can be
accomplished through the PGb pin. Note that the VEE of the hot swap and the DC/DC are different and the
Power Good can not be directly tied to the EN or UV of the DC/DC. The application circuit below provides a
simple way to control the downstream converter with the PGb pin of the hot swap.
Figure 16. Interface to DC/DC
24
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9.2.3 Application Curves
Figure 17. Start Up (Vin = 54 V)
Figure 18. Start Up (Vin = 54 V)
Figure 19. Start Up (Vin = 54 V)
Figure 20. Start Up (Vin = 38 V)
Figure 21. Start Up (Vin = 60 V)
Figure 22. Hot Short (Vin = 54 V)
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Zoomed In
26
Figure 23. Hot Short (Vin = 54 V)
Figure 24. Gradual Over Current
Figure 25. Load Step Into Current Limit
Figure 26. Load Step Into Current Limit
Figure 27. Start Into Short
Figure 28. Start Into Short
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5-A load
5-A load
Figure 29. Short on Vin
Figure 30. Short on Vin
Figure 31. Reverse Hook Up
Figure 32. Reverse Hook Up
5-A load
6-A load, per IEC61000-4-5
Figure 33. 1-ms Brown Out
Figure 34. 2 kV (2 Ω) Lightning Surge
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6-A load, per IEC61000-4-5
6-A load, per IEC61000-4-5
Figure 35. 2 kV (2 Ω) Lightning Surge
Figure 36. -2 kV (2 Ω) Lightning Surge
6-A load, per IEC61000-4-5
Figure 37. -2 kV (2 Ω) Lightning Surge
28
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10 Power Supply Recommendations
In general, the TPS23523 is designed to have robust operation from a non-ideal –48 V bus with various
transients such as the lightning surge. The IC is powered through RVCC making it more immune to supply drop
outs and high voltage spikes. Regardless, TI recommends following several key precautions:
• Always test the solution with the various transients that can be encountered in the systems. This especially
applies to transients that were not tested with TI’s EVM.
• If large input ripple is expected during start-up, increase the ratio of CSS, VEE to CSS to reduce input current
ripple at start-up.
• Operating from large input inductance (>40 µH) can cause instability to the current limit loop or oscillations
during start-up. Add a capacitor from Gate to VEE to help stabilize the current limit loop. Add an input
snubber if oscillations are observed at start-up.
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11 Layout
11.1 Layout Guidelines
There are several things to keep in mind during layout of the TPS23523 circuit:
● The VEE and SNS pin need to have a Kelvin Sense connection to the sense resistor.
● The VEE trace carries current and needs to be thick and short in order to minimize IR drop and to avoid
introducing current sensing error.
● It is recommended to use a net-tie to separate the power plane coming into the RSNS and the Kelvin connection
to VEE.
● Connect the Neg48Vx filtering caps, UVEN resistor divider, OV resistor divider, and TMR cap to the "VEE" to
insure maximum accuracy.
● The filtering caps on Neg48V and SNS should be placed as close to the IC as possible.
11.2 Layout Example
Figure 38. Layout Example
30
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• TPS23525EVM-815 Evaluation Module User's Guide (SLVUB36)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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31
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS23523PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
23523
TPS23523PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
23523
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS23523PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TPS23523PWT
TSSOP
PW
16
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS23523PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TPS23523PWT
TSSOP
PW
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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