Texas Instruments | TPS745 500-mA, High Accuracy, Adjustable LDO With Power-Good in a Small Size Package (Rev. A) | Datasheet | Texas Instruments TPS745 500-mA, High Accuracy, Adjustable LDO With Power-Good in a Small Size Package (Rev. A) Datasheet

Texas Instruments TPS745 500-mA, High Accuracy, Adjustable LDO With Power-Good in a Small Size Package (Rev. A) Datasheet
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TPS745
SBVS326A – APRIL 2018 – REVISED DECEMBER 2018
TPS745 500-mA, High Accuracy, Adjustable LDO With Power-Good in a Small Size
Package
1 Features
3 Description
•
•
The TPS745 is an adjustable 500-mA low-dropout
(LDO) regulator with power-good functionality. This
device is available in a small, 6-pin, 2-mm × 2-mm
WSON package and consumes very low quiescent
current and provides fast line and load transient
performance. The TPS745 features an ultra-low
dropout of 130 mV at 500 mA that can help improve
the power efficiency of the system.
1
•
•
•
•
•
•
•
Input Voltage Range: 1.5 V to 6.0 V
Adjustable Output Voltage:
– 0.55 V to 5.5 V
Very Low Dropout:
– 130 mV (max) at 500 mA (3.3 VOUT)
High Output Accuracy: 0.7% (Typical) and 1%
(Maximum Over Temperature)
Open-Drain Power-Good Output
IQ: 25 µA (Typical)
Built-In Soft-Start With Monotonic VOUT Rise
Package:
– 2-mm × 2-mm WSON-6 (DRV)
Active Output Discharge
The TPS745 is optimized for a wide variety of
applications by supporting an input voltage range
from 1.5 V to 6.0 V and an externally adjustable
output range of 0.55 V to 5.5 V. The low output
voltage enables this LDO to power the modern
microcontrollers with lower core voltages.
The TPS745 has a power-good (PG) output that
monitors the voltage at the feedback pin to indicate
the status of the output voltage. The EN input and PG
output can be used for the sequencing multiple power
sources in the system.
2 Applications
•
•
•
•
•
•
•
Set-Top Boxes, Gaming Consoles
Home Theater and Entertainment
Desktops, Notebooks, Ultrabooks
Printers
Servers
Thermostat and Lighting Control
Electronic Point of Sale (EPOS)
The TPS745 is stable with small ceramic output
capacitors, allowing for a small overall solution size.
A precision band-gap and error amplifier provides
high accuracy of 0.7% (max) at 25°C and 1% (max)
over temperature (85ºC). This device includes
integrated thermal shutdown, current limit, and
undervoltage lockout (UVLO) features. The TPS745
has an internal foldback current limit that helps
reduce the thermal dissipation during short-circuit
events.
Device Information(1)
PART NUMBER
TPS745
PACKAGE
WSON (6)
BODY SIZE (NOM)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VIN
IN
CIN
VOUT
OUT
R1
TPS745
GND
COUT
FB
R2
VEN
RPG
VPG
EN
PG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS745
SBVS326A – APRIL 2018 – REVISED DECEMBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (April 2018) to Revision A
•
2
Page
Changed document status from Advance Information to Production Data ........................................................................... 1
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SBVS326A – APRIL 2018 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
DRV Package
6-Pin Adjustable WSON
Top View
OUT
1
FB
2
GND
3
6
IN
5
PG
4
EN
Thermal
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
EN
4
Input
FB
2
—
This pin is used as an input to the control loop error amplifier and is used to set the
output voltage of the LDO.
GND
3
—
Ground pin
IN
6
Input
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground as listed in the
Recommended Operating Conditions table and the Input and Output Capacitor Selection
section. Place the input capacitor as close to the output of the device as possible.
1
Output
Regulated output voltage pin. A capacitor is required from OUT to ground for stability.
For best transient response, use the nominal recommended value or larger ceramic
capacitor from OUT to ground; see the Recommended Operating Conditions table and
the Input and Output Capacitor Selection section. Place the output capacitor as close to
output of the device as possible.
5
Output
Power-good output
Pad
—
OUT
PG
Thermal pad
Connect the thermal pad to a large area GND plane for improved thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage
Current
(2)
MAX
–0.3
6.5
Enable, VEN
–0.3
6.5
Feedback, VFB
–0.3
2
Power-good, VPG
–0.3
6.5
Output, VOUT
–0.3
VIN + 0.3 (2)
Power-good current
Temperature
(1)
MIN
Supply, VIN
±10
Operating junction, TJ
–40
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
The absolute maximum rating is VIN + 0.3V or 6.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM ispossible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM ispossible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
NOM
MAX
UNIT
1.5
6.0
V
Output voltage
0.55
5.5
V
IOUT
Output current
0
500
mA
CIN
Input capacitor
1
COUT
Output capacitor (1)
1
220
µF
VEN
Enable voltage
0
6.0
V
fEN
Enable toggle frequency
10
kHz
VPG
PG voltage
0
6.0
V
TJ
Junction temperature
–40
125
°C
(1)
4
µF
Minimum derated capacitance of 0.47 µF is required for stability
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6.4 Thermal Information
TPS745
THERMAL METRIC (1)
DRV (WSON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
80.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
98.7
°C/W
RθJB
Junction-to-board thermal resistance
44.8
°C/W
ψJT
Junction-to-top characterization parameter
6.1
°C/W
ψJB
Junction-to-board characterization parameter
45.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
20.8
°C/W
(1)
For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA,
VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
VFB
Feedback voltage
TEST CONDITIONS
MIN
TJ = 25°C
–0.7%
–40°C ≤ TJ ≤ +85°C
–40°C ≤ TJ ≤ +125°C
Line regulation
VOUT(NOM) + 0.5 V (2) ≤ VI N ≤ 6.0 V
Load regulation
0.1 mA ≤ IOUT ≤ 500 mA, VIN ≥ 2.0 V
IGND
Ground current
IGND
Ground current
ISHDN
Shutdown current
IFB
Feedback pin current
ICL
Output current limit
ISC
Short-circuit current limit
VDO
Dropout voltage
PSRR
Power-supply rejection ratio
IOUT = 0 mA
–1%
1%
–1.5%
1.5%
10
25
VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V
VIN = VOUT(NOM) + 1.0 V
IOUT = 500 mA,
–40°C ≤ TJ ≤ +125°C,
VOUT = 0.95 × VOUT(NOM)
VIN = VOUT(NOM) + 1.0 V,
IOUT = 50 mA
7.5
mV
V/A
31
µA
35
µA
0.1
1
µA
0.01
0.1
µA
–40°C ≤ TJ ≤ +125°C
VIN = VOUT(NOM) + 1.0 V
V
0.030
TJ = 25°C
UNIT
0.7%
2
VOUT = VOUT(NOM) – 0.2 V,
VOUT < 1.5 V
530
720
865
VOUT = 0.9 V × VOUT(NOM),
VOUT ≥ 1.5 V
530
720
865
mA
VOUT = 0 V
350
0.65 V ≤ VOUT < 0.8 V
720
880
0.8 V ≤ VOUT < 1.0 V
585
750
1.0 V ≤ VOUT < 1.2 V
420
570
1.2 V ≤ VOUT < 1.5 V
285
400
1.5 V ≤ VOUT < 1.8 V
180
235
1.8 V ≤ VOUT < 2.5 V
140
185
2.5 V ≤ VOUT < 3.3 V
102
140
3.3 V ≤ VOUT ≤ 5.5 V
95
130
f = 1 kHz
50
f = 100 kHz
45
f = 1 MHz
30
Vn
Output noise voltage
VUVLO
Undervoltage lockout
VUVLO,
HYST
Undervoltage lockout
hysteresis
VIN Hysteresis
tSTR
Startup time
From EN low-to-high transition to VOUT = VOUT(NOM) × 95%
(1)
(2)
MAX
0.55
TJ = 25°C
Output accuracy (1)
TYP
BW = 10 Hz to 100 kHz, VOUT = 0.9 V
mA
mV
dB
53
µVRMS
VIN rising
1.21
1.33
1.47
V
VIN falling
1.17
1.29
1.42
V
40
mV
500
µs
When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included
VIN = 1.5V for VOUT < 1.0 V
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Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA,
VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.0
UNIT
VEN(HI)
EN pin high voltage
VEN(LO)
EN pin low voltage
IEN
Enable pin current
VIN = EN = 6.0 V
10
nA
RPULL
Pulldown resistance
VIN = 6.0 V
95
Ω
PGHTH
PG high threshold
VOUT increasing
89
94
95
%VOUT
PGLTH
PG low threshold
VOUT decreasing
87
92
93
%VOUT
VOL(PG)
PG pin low-level output
voltage
VIN ≥ 1.5 V, ISINK = 1 mA
300
VOL(PG)
PG pin low-level output
voltage
VIN ≥ 2.75 V, ISINK = 2 mA
300
Ilkg(PG)
PG pin leakage current
VOUT > PGHTH, VPG = 6.0 V
0.3
DOWN
TSD
V
Thermal shutdown
V
mV
300
Shutdown, temperature increasing
170
Reset, temperature decreasing
155
nA
°C
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
tPGDH
PG delay time rising (1)
tPGDL
(1)
(1)
6
PG delay time falling
MIN
NOM
MAX
UNIT
Time from 92% VOUT to 20% of PG
135
165
178
µs
Time from 90% VOUT to 80% of PG
1.5
7
10
µs
Output overdrive = 10%
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6.7 Typical Characteristics
0.6
0.6
0.45
0.45
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
3.8
±
±
4
4.2
qC
qC
4.4
4.6
TJ
± qC
0qC
4.8
5
25qC
85qC
5.2
5.4
125qC
150qC
5.6
5.8
0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
1.5
6
±
±
2
Input Voltage (V)
VOUT = 3.3 V, IOUT = 1 mA
Figure 1. 3.3-V Line Regulation vs VIN
3
3.5
4
4.5
125qC
150qC
5
5.5
6
0.45
0.5
Figure 2. 0.55-V Line Regulation vs VIN
160
140
0.2
Dropout Voltage (mV)
Output Voltage Accuracy (%)
2.5
25qC
85qC
Input Voltage (V)
VOUT = 0.55 V, IOUT = 1 mA
0.3
0.1
0
-0.1
TJ
± qC
0qC
-0.2
±
±
qC
qC
25qC
85qC
±
±
qC
qC
0.05
0.1
TJ
± qC
0qC
25qC
85qC
125qC
150qC
120
100
80
60
40
20
125qC
150qC
0
-0.3
5.5
5.6
5.7
5.8
5.9
0
6
Figure 3. 5.5-V Line Regulation vs VIN
870
140
Dropout Voltage (mV)
160
840
810
780
750
720
690
±
±
qC
qC
0.2
0.25
0.3
0.35
0.4
Figure 4. 3.3-V Dropout Voltage vs IOUT
900
TJ
± qC
0qC
0.15
Output Current (A)
Input Voltage (V)
VOUT = 5.5 V, IOUT = 1 mA
Dropout Voltage (mV)
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
660
±
±
qC
qC
0.05
0.1
TJ
± qC
0qC
25qC
85qC
125qC
150qC
120
100
80
60
40
20
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
Output Current (A)
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Output Current (A)
Figure 5. 0.55-V Dropout Voltage vs IOUT
Figure 6. 5.5-V Dropout Voltage vs IOUT
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Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
1,000
800
±
±
800
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
700
Ground Pin Current (PA)
Dropout Voltage (mV)
900
700
600
500
400
300
200
600
500
400
300
200
100
100
0
0.5
±
±
1.5
2
2.5
3
3.5
4
4.5
5
0
0.05
0.1
0.15
Figure 7. VDO vs VOUT
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Figure 8. IGND vs IOUT
560
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
±
±
480
Ground Pin Current (PA)
±
±
1,800
Shutdown Current (nA)
125qC
150qC
Output Current (A)
2,100
1,500
1,200
900
600
300
0
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
400
320
240
160
80
0
-300
-80
0
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
0
0.6
Input Voltage (V)
VEN = 0 V
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
Input Voltage (V)
VOUT = 3.3 V, IOUT = 0 mA
Figure 9. ISHDN vs VIN
Figure 10. IQ vs VIN
1
0.6
±
±
0.75
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
0.5
0.25
0
-0.25
-0.5
-0.75
±
±
0.45
Change in VOUT (%)
Change in VOUT (%)
25qC
85qC
0
1
Output Voltage (V)
IOUT = 500 mA
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
0.3
0.15
0
-0.15
-0.3
-0.45
-1
-0.6
0
0.05
0.1
VIN
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
Output Current (A)
= 3.8 V, VOUT = 3.3 V
0.05
0.1
0.15
VIN
Figure 11. 3.3-V Load Regulation vs IOUT
8
TJ
± qC
0qC
qC
qC
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0.2
0.25
0.3
0.35
0.4
0.45
0.5
Output Current (A)
= 2 V, VOUT = 0.55 V
Figure 12. 0.55-V Load Regulation vs IOUT
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Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
640
1
±
±
qC
qC
25qC
85qC
125qC
150qC
±
±
560
0.5
Output Voltage (mV)
Change in VOUT (%)
0.75
TJ
± qC
0qC
0.25
0
-0.25
-0.5
125qC
150qC
480
400
320
240
160
0
-1
0
0.05
0.1
0.15
VIN
0.2
0.25
0.3
0.35
0.4
0.45
0
0.5
1
1.5
3.5
4
4.5
5
35
PGLTH
-30
-10
10
30
50
70
90
PGHTH
110
130
30
25
20
15
10
5
0
-5
-10
-50
150
PG = 3.3 V
-25
0
25
50
75
PG = 5.5 V
100
125
150
Temperature (qC)
Figure 15. PGLTH and PGHTH vs Temperature
Figure 16. IIkg(PG) vs Temperature and PG Pin Voltage
210
qC
qC
TJ
± qC
0qC
25qC
85qC
125qC
150qC
PG Pin Voltage Low (mV)
±
±
210
180
150
120
90
60
30
0
0.2
3
Figure 14. VOUT vs IOUT Pulldown Resistor
300
240
2.5
40
Temperature (qC)
270
2
Pulldown Current (mA)
PG Leakage Current (nA)
92.5
92.25
92
91.75
91.5
91.25
91
90.75
90.5
90.25
90
89.75
89.5
89.25
89
-50
0.5
Output Current (A)
= 6 V, VOUT = 5.5 V
Figure 13. 5-V Load Regulation vs IOUT
PG Pin Voltage Low (mV)
25qC
85qC
80
-0.75
PG Pin Thresholds (%)
TJ
± qC
0qC
qC
qC
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
180
±
±
TJ
± qC
0qC
qC
qC
25qC
85qC
125qC
150qC
150
120
90
60
30
0
0.2
PG Pin Sink Current (mA)
VIN = 3.8 V, VOUT = 3.3 V
0.3
0.4
VIN
Figure 17. VOL(PG) vs PG Pin Sink Current
0.5
0.6
0.7
0.8
0.9
Figure 18. VOL(PG) vs PG Pin Sink Current
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PG Pin Sink Current (mA)
= 1.5 V, VOUT = 0.55 V
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Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
166
6.5
tPGDL
6.1
164
PG Delay Time Falling (Ps)
162
160
158
156
154
152
5.7
5.3
4.9
4.5
4.1
3.7
3.3
2.9
150
-50
-25
0
25
50
75
100
125
2.5
-50
150
-25
0
25
Temperature (qC)
Figure 19. tPGDH vs Temperature
100
125
150
300
VEN(LO)
800
VEN(HI)
±
±
250
760
Enable Pin Current (PA)
Enable Threshold (mV)
75
Figure 20. tPGDL vs Temperature
840
720
680
640
600
560
520
TJ
± qC
0qC
qC
qC
125qC
85qC
125qC
150qC
200
150
100
50
0
480
440
-50
-50
-25
0
25
50
75
100
125
150
0
0.5
1
Temperature (qC)
Figure 21. VEN(HI) and VEN(LO) vs Temperature
4.5
TJ
-20qC
0qC
-50qC
-40qC
4
25qC
85qC
125qC
Input Voltage (V)
3
2.5
2
1.5
1
0.5
0
100
200
300
400
2
2.5
3
3.5
4
4.5
5
5.5
Figure 22. IEN vs VIN
3.5
0
1.5
Input Voltage (V)
VEN = 5.5 V
5
Output Voltage (V)
50
Temperature (qC)
500
600
700
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0.5
Output Current (mA)
1
Time (ms)
1.5
25
Vin
20
Vout 15
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
2
AC-coupled Output Voltage (mV)
PG Delay Time Rising (Ps)
tPGDH
VOUT = 0.55 V, IOUT = 1 mA, VIN slew rate = 1 V/µs
Figure 23. 3.3-V Foldback Current Limit vs IOUT
10
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Typical Characteristics (continued)
0
0.2
0.4
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
4
200
Iout
Vout 150
100
3.5
3
2.5
50
2
0
1.5
-50
1
-100
0.5
-150
0
-200
-0.5
-250
-1
0
50
Iout
Vout 150
100
3.5
Output Current (A)
3
2.5
50
2
0
1.5
-50
1
-100
0.5
-150
0
-200
-0.5
-1
150
200 250 300
Time (us)
350
400
350
400
450
450
4
AC-coupled Output Voltage (mV)
Output Current (A)
200
100
200 250 300
Time (us)
-300
500
Figure 26. 3.3-V, 1-mA to 500-mA Load Transient
Figure 25. 3.3-V Line Transient
4
50
150
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs
VOUT = 3.3 V, IOUT = 1 mA, VIN slew rate = 1 V/µs
0
100
AC-coupled Output Voltage (mV)
120
Vin
100
Vout 80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
1.8
2
200
Iout
Vout 150
100
3.5
3
2.5
50
2
0
1.5
-50
1
-100
0.5
-150
0
-200
-250
-0.5
-250
-300
500
-1
0
50
VIN = 2 V, VOUT = 0.55 V, IOUT slew rate = 1 A/µs
100
150
200 250 300
Time (us)
350
400
450
AC-coupled Output Voltage (mV)
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
AC-coupled Output Voltage (mV)
Output Current (A)
Input Voltage (V)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
-300
500
VIN = 5.5 V, VOUT = 5 V, IOUT slew rate = 1 A/µs
Figure 27. 0.55-V, 1-mA to 500-mA Load Transient
Figure 28. 5-V, 1-mA to 500-mA Load Transient
5
5
4.5
4
4
3.5
3
Voltage (V)
Voltage (V)
3
2.5
2
1.5
1
2
1
0.5
0
Vout
Vin
-0.5
-1
Vout
Venable
Vin
0
-1
0
200
400
600
Time (us)
800
1,000
0
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
200
400
600
Time (us)
800
1,000
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
Figure 29. VIN Power-Up
Figure 30. Startup With EN
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Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
90
VIN = 3.5 V
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V
80
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
90
80
70
60
50
40
30
VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V
20
10
0
10
10M
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF
100
Figure 31. PSRR vs Frequency and VIN
70
60
50
40
30
20
10
100
1k
10k
100k
Frequency (Hz)
1M
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
VIN = 3.5 V
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V
80
70
60
50
40
30
VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V
20
10
0
10
10M
100
1k
10k
100k
Frequency (Hz)
1M
10M
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF
Figure 33. PSRR vs Frequency and VIN
Figure 34. PSRR vs Frequency and VIN
90
VIN = 1.9 V, VOUT = 0.9 V
VIN = 2.8 V, VOUT = 1.8 V
VIN = 4.3 V, VOUT = 3.3 V
80
70
60
50
40
30
20
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Power-Supply Rejection Ratio (dB)
90
Power-Supply Rejection Ratio (dB)
10M
Figure 32. PSRR vs Frequency and VIN
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF
COUT = 1 PF
COUT = 2.2 PF
COUT = 4.7 PF
COUT = 47 PF
80
70
60
50
40
30
20
10
0
10
IOUT = 500 mA, COUT = 2.2 µF
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA
Figure 35. PSRR vs Frequency
12
1M
90
80
0
10
10k
100k
Frequency (Hz)
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF
90
0
10
1k
Figure 36. PSRR vs Frequency and COUT
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Typical Characteristics (continued)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
90
CFF = 0 nF
CFF = 1 nF
CFF = 10 nF
CFF = 100 nF
80
70
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
90
60
50
40
30
20
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
80
70
60
50
40
30
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
20
10
0
10
10M
100
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA
Figure 37. PSRR vs Frequency and CFF
1M
10M
Figure 38. PSRR vs Frequency and ILOAD
20
IOUT= 10mA, 159PVRMS
IOUT= 100mA, 160PVRMS
IOUT= 500mA, 160PVRMS
10
5
CFF = 0 nF, 160 PVRMS
CFF = 1 nF, 108 PVRMS
CFF = 10 nF, 74 PVRMS
CFF = 100 nF, 44 PVRMS
10
5
2
Noise (PV/—Hz)
2
Noise (PV/—Hz)
10k
100k
Frequency (Hz)
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF
20
1
0.5
0.2
0.1
1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0.005
10
0.005
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF,
VRMS BW = 10 Hz to 100 kHz
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF,
VRMS BW = 10 Hz to 100 kHz
Figure 39. Output Spectral Noise Density
Figure 40. Output Spectral Noise Density vs
Frequency and CFF
20
20
COUT = 2.2PF, 160 PVRMS
COUT = 4.7PF, 170 PVRMS
COUT = 47PF, 138 PVRMS
10
5
VIN=1.9V, VOUT=0.9V, 53PVRMS
VIN=2.8V, VOUT=1.8V, 96PVRMS
VIN=3.8V, VOUT=3.3V, 160PVRMS
10
5
2
Noise (PV/—Hz)
2
Noise (PV/—Hz)
1k
1
0.5
0.2
0.1
1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
0.01
0.005
10
0.005
10
100
1k
10k
100k
Frequency (Hz)
1M
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CFF = 0 µF,
VRMS BW = 10 Hz to 100 kHz
Figure 41. Output Spectral Noise Density vs
Frequency and COUT
10M
100
1k
10k
100k
Frequency (Hz)
1M
10M
IOUT = 500 mA, COUT = 2.2 µF, VRMS BW = 10 Hz to 100 kHz
Figure 42. Output Spectral Noise Density vs Frequency
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7 Detailed Description
7.1 Overview
The TPS745 low-dropout regulators (LDO) consumes low quiescent current and delivers excellent line and load
transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage,
make this device ideal for portable consumer applications. The internal power-good detection circuit allows the
down-stream supplies to be sequenced and alerts if the output voltage is below a regulation threshold.
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
for this device is –40°C to +125°C.
7.2 Functional Block Diagram
OUT
IN
Current
Limit
–
+
Thermal
Shutdown
95 FB
UVLO
PG
+
0.90 x VREF
EN
–
Band Gap
GND
Logic
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS745 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When
VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN). When the device
enters UVLO, the PG output is pulled low.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN.When the
device is disabled, the PG output pin is pulled low.
The TPS745 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device
is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor (RPULLDOWN). Equation 1 calculates the time constant:
τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL)
14
(1)
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Feature Description (continued)
7.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the shortcircuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.4 V × VOUT(NOM).
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 43 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
IOUT
0V
0 mA
ISC
IRATED
ICL
Figure 43. Foldback Current Limit
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
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Feature Description (continued)
The TPS745 internal protection circuitry protects against overload conditions but is not intended to be activated
in normal operation. Continuously running the TPS745 into thermal shutdown degrades device reliability.
7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
Dropout operation
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < IOUT(max)
TJ < TSD(shutdown)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
Disabled
(any true condition
disables the device)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
Figure 44 shows that the output voltage of the TPS745 can be adjusted from 0.55 V to 5.5 V by using a resistor
divider network.
VIN
IN
CIN
VOUT
OUT
R1
TPS745
GND
COUT
FB
R2
RPG
VEN
VPG
EN
PG
Figure 44. Adjustable Operation
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(2)
For this device, VFB = 0.55 V.
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(3)
For this device, IFB = 10 nA.
8.1.2 Input and Output Capacitor Selection
The TPS745 requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over
temperature. When choosing a capacitor for a specific application, pay attention to the dc bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
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Application Information (continued)
8.1.3 Dropout Voltage
The TPS745 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation.
8.1.4 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up, as shown in Figure 45, when the slew rate and voltage levels are in the correct
range. Use an enable signal to avoid this condition.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Voltage
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 45. Startup Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 46 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a
line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Application Information (continued)
Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
Figure 46. Line Transients From Dropout
8.1.5 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply
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Application Information (continued)
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 47 shows one approach of protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 47. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit
board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no
other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. Equation 4 calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(4)
NOTE
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use the
minimum input voltage required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to Equation 5, power dissipation and junction temperature are most often related by the junction-toambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA).
TJ = TA + (RθJA × PD)
(5)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.7 Power-Good Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.
When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages
and pulls the PG pin close to GND. When the output voltage exceeds PGHTH, the PG pin becomes high
impedance. By connecting a pullup resistor to an external supply, any downstream device can receive powergood as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results
in a valid logic signal for the receiving device. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended.
20
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Application Information (continued)
When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas the
power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output.
To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO startup
and the power-good output match, which can be done by adding a capacitor in parallel with the power-good
pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a LowDropout Regulator application report.
The state of PG is only valid when the device operates above the minimum input voltage of the device and
power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO
threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not
enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output
pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.
8.1.8 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF
can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and
Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
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8.2 Typical Application
Figure 48 shows the typical application circuit for the TPS745. Input and output capacitances must be at least
1 µF.
VIN
IN
CIN
VOUT
OUT
R1
TPS745
GND
COUT
FB
R2
RPG
VEN
VPG
EN
PG
Figure 48. TPS745 Typical Application
8.2.1 Design Requirements
Use the parameters listed in Table 2 for typical linear regulator applications.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
3.8 V
Output voltage
3.3 V, ±1%
Input current
500 mA (maximum)
Output load
500-mA DC
Maximum ambient temperature
70°C
8.2.2 Detailed Design Procedure
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 2.2 µF are selected to give the maximum output capacitance in a small, low-cost package; see the
Input and Output Capacitor Selection section for details.
Figure 44 illustrates the output voltage of the TPS745. Set the output voltage using the resistor divider; see the
section for details.
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 6 to calculate the current through the input.
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(6)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 7 to calculate the power dissipation. Multiply PD by RθJA as Equation 8
shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).
22
PD = (IGND+ IOUT) × (VIN – VOUT)
TJ = RθJA × PD + TA
(7)
(8)
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Calculate the maximum ambient temperature as Equation 9 shows if the (TJ(MAX)) value does not exceed 125°C.
Equation 10 calculates the maximum ambient temperature with a value of 104.93°C.
TA(MAX) = TJ(MAX) – RθJA × PD
TA(MAX) = 125°C – 80.3°C/W × (3.8 V – 3.3 V) × (0.5 A) = 104.93°C
(9)
(10)
8.2.3 Application Curve
Power-Supply Rejection Ratio (dB)
90
80
70
60
50
40
30
20
10
0
10
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
100
1k
10k
100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF
Figure 49. PSRR vs Frequency and ILOAD
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9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TPS745.
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections, in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DRV package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Example
COUT
Cff
CIN
1
6
2
5
3
4
RPG
R1
R2
GND PLANE
Signal to Pin1
Figure 50. DRV Package Layout Example
24
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS74501PDRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1MEH
TPS74501PDRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1MEH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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20-Dec-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS74501PDRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS74501PDRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS74501PDRVR
WSON
DRV
6
3000
210.0
185.0
35.0
TPS74501PDRVT
WSON
DRV
6
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1 0.1
EXPOSED
THERMAL PAD
3
2X
1.3
4
7
1.6 0.1
6
1
4X 0.65
PIN 1 ID
(OPTIONAL)
6X
6X
0.3
0.2
0.35
0.25
0.1
0.05
C A
C
B
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
(1)
1
7
6
6X (0.3)
(1.6)
SYMM
(1.1)
4X (0.65)
4
3
SYMM
(R0.05) TYP
( 0.2) VIA
TYP
(1.95)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
1
SYMM
METAL
7
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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