Texas Instruments | TPS51200A-Q1 Sink and Source DDR Termination Regulator (Rev. A) | Datasheet | Texas Instruments TPS51200A-Q1 Sink and Source DDR Termination Regulator (Rev. A) Datasheet

Texas Instruments TPS51200A-Q1 Sink and Source DDR Termination Regulator (Rev. A) Datasheet
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TPS51200A-Q1
SLUSD58A – JUNE 2018 – REVISED DECEMBER 2018
TPS51200A-Q1 Sink and Source DDR Termination Regulator
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications:
– Device Temperature Grade 1:
–40°C ≤ TA ≤ 125°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Extended Reliability Testing
Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
VLDOIN Voltage Range: 1.1 V to 3.5 V
Sink and Source Termination Regulator Includes
Droop Compensation
Requires Minimum Output Capacitance of 20-μF
(typically 3 × 10-μF MLCCs) for Memory
Termination Applications (DDR)
PGOOD to Monitor Output Regulation
EN Input
REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider
Remote Sensing (VOSNS)
±10-mA Buffered Reference (REFOUT)
Built-in Soft-Start, UVLO and OCL
Thermal Shutdown
Meets DDR, DDR2 JEDEC Specifications;
Supports DDR3 and Low-Power DDR3 and DDR4
VTT Applications
VSON-10 Package With Exposed Thermal Pad
•
•
Memory Termination Regulator for DDR, DDR2,
DDR3, and Low Power DDR3/DDR4
Notebook, Desktop, Server
Telecom and Datacom, GSM Base Station, LCDTV and PDP-TV, Copier and Printer, Set-Top Box
3 Description
The TPS51200A-Q1 device is a sink and source
double-data-rate
(DDR)
termination
regulator
specifically designed for low input voltage, low-cost,
low-noise systems where space is a key
consideration.
The device maintains a fast transient response and
only requires a minimum output capacitance of 20 μF.
The device supports a remote sensing function and
all power requirements for DDR, DDR2, DDR3, and
Low Power DDR3 and DDR4 VTT bus termination.
In addition, the device provides an open-drain
PGOOD signal to monitor the output regulation and
an EN signal that can be used to discharge VTT
during S3 (suspend to RAM) for DDR applications.
The device is available in the thermally-efficient
VSON-10 package, and is rated both green and Pbfree. The device is specified from –40°C to 125°C.
Device Information(1)
PART NUMBER
TPS51200A-Q1
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified DDR Application
VDDQ
1
REFIN
VIN 10
3.3 VIN
TPS51200A-Q1
VLDOIN
2
VLDOIN
VTT
3
VO
4
PGND
5
VOSNS
PGOOD
PGOOD
9
GND
8
EN
7
SLP_S3
REFOUT
6
VTTREF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51200A-Q1
SLUSD58A – JUNE 2018 – REVISED DECEMBER 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview ................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
10.3 Thermal Considerations ........................................ 27
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2018) to Revision A
Page
•
Added Extended Reliability Testing to Features list ............................................................................................................... 1
•
Changed document status from Advance Information to Production Data ........................................................................... 1
•
Updated device number error in schematic illustrations ...................................................................................................... 14
2
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
REFIN
1
10
VIN
VLDOIN
2
9
PGOOD
VO
3
8
GND
PGND
4
7
EN
VOSNS
5
6
REFOUT
Thermal
Pad
Pin Functions
PIN
NAME
EN
GND
NO.
I/O
7
I
DESCRIPTION
For DDR VTT application, connect EN to SLP_S3. For any other applications, use EN as the ON/OFF
function. Keep EN voltage equal or lower than VIN voltage at all times.
8
—
Ground. Signal ground. Connect to negative pin of the output capacitor.
(1)
4
—
Power ground output for the LDO
PGOOD
9
O
PGOOD output. Indicates regulation.
REFIN
1
I
Reference input
REFOUT
6
O
Reference output. Connect to GND through 0.1-μF ceramic capacitor. If there is REFOUT capacitor at DDR
side, keep the total capacitance on REFOUT pin below 1 μF. The REFOUT pin can not be open.
VIN
10
I
2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is
required.
VLDOIN
2
I
Supply voltage for the LDO.
VO
3
O
Power output for the LDO. Minimum 20-μF capacitance is required. No maximum capacitance limit.
VOSNS
5
I
Voltage sense output for the LDO. Connect to positive pin of the output capacitor or the load.
PGND
(1)
Thermal pad connection. See Figure 35 in the Thermal Considerations section for additional information.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
Input voltage (2)
Output voltage (2)
MIN
MAX
VIN, VLDOIN, VOSNS, REFIN
–0.3
3.6
EN
–0.3
6.5
PGND to GND
–0.3
0.3
VO, REFOUT
–0.3
3.6
PGOOD
–0.3
6.5
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–55
UNIT
V
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground pin unless otherwise noted.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per
AEC Q100-011
(1)
UNIT
±2000
Corner pins (1, 5, 6, and 10)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Supply voltage
MIN
MAX
2.375
3.500
–0.1
3.5
0.5
1.8
VO, PGOOD
–0.1
3.5
REFOUT
–0.1
1.8
PGND
–0.1
0.1
–40
125
VIN
EN, VLDOIN, VOSNS
REFIN
Voltage range
Operating free-air temperature, TA
UNIT
V
°C
6.4 Thermal Information
TPS51200A-Q1
THERMAL METRIC
(1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
55.7
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
62.2
°C/W
RθJB
Junction-to-board thermal resistance
28.0
°C/W
ψJT
Junction-to-top characterization parameter
3.1
°C/W
ψJB
Junction-to-board characterization parameter
27.9
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
12.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 μF and circuit shown in the Simplified DDR Application section (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
Supply current
TA = 25 °C, VEN = 3.3 V, No Load
0.7
1
TA = 25 °C, VEN = 0 V, VREFIN = 0, No Load
65
80
200
400
1
50
μA
0.1
50
μA
1
μA
15
mV
15
mV
15
mV
15
mV
15
mV
–25
25
mV
3
4.5
A
3.5
5.5
A
18
25
Ω
IIN(SDN)
Shutdown current
ILDOIN
Supply current of VLDOIN
TA = 25 °C, VEN = 3.3 V, No Load
ILDOIN(SDN)
Shutdown current of VLDOIN
TA = 25 °C, VEN = 0 V, No Load
TA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, No Load
mA
μA
INPUT CURRENT
IREFIN
Input current, REFIN
VEN = 3.3 V
VO OUTPUT
1.25
VREFOUT = 1.25 V (DDR1), IO = 0 A
–15
0.9
VREFOUT = 0.9 V (DDR2), IO = 0 A
VVOSNS
Output DC voltage, VO
–15
–15
-15
–2A < IVO < 2A
VO source current Limit
With reference to REFOUT, VOSNS = 90% × VREFOUT
IVOSNCL
VO sink current Limit
With reference to REFOUT, VOSNS = 110% × VREFOUT
IDSCHRG
Discharge current, VO
VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25°C
V
0.6
VREFOUT = 0.6 V (DDR4), IO = 0 A
Output voltage tolerance to REFOUT
V
0.675
VREFOUT = 0.675 V (DDR3L), IO = 0 A
IVOSRCL
V
0.75
VREFOUT = 0.75 V (DDR3), IO = 0 A
VVOTOL
V
-15
V
POWERGOOD COMPARATOR
VTH(PG)
VO PGOOD threshold
PGOOD window lower threshold with respect to REFOUT
–23.5%
–20%
–17.5%
PGOOD window upper threshold with respect to REFOUT
17.5%
20%
23.5%
PGOOD hysteresis
VPGOODLOW
IPGOODLK
Output low voltage
Leakage current
(1)
5%
ISINK = 4 mA
VOSNS = VREFIN (PGOOD high impedance), PGOOD = VIN
+ 0.2 V
0.4
V
1
μA
REFIN AND REFOUT
VREFIN
REFIN voltage range
VREFINUVLO
REFIN undervoltage lockout
VREFINUVHYS
REFIN undervoltage lockout hysteresis
VREFOUT
REFOUT voltage
0.5
REFIN rising
360
390
1.8
V
420
mV
20
mV
REFIN
V
–10 mA ≤ IREFOUT ≤ 10 mA, 0.6 V ≤ VREFIN ≤ 1.25 V
–15
15
–1 mA ≤ IREFOUT ≤ 1 mA, 0.6 V ≤ VREFIN ≤ 1.25 V
-12
12
VREFOUTTOL
REFOUT voltage tolerance to VREFIN
mV
IREFOUTSRCL
REFOUT source current limit
VREFOUT = 0.5 V
10
40
mA
IREFOUTSNCL
REFOUT sink current limit
VREFOUT = 1.5 V
10
40
mA
Wake up, TA = 25°C
2.2
2.3
UVLO / EN LOGIC THRESHOLD
VVINUVLO
UVLO threshold
VENIH
High-level input voltage
Enable
VENIL
Low-level input voltage
Enable
VENYST
Hysteresis voltage
Enable
IENLEAK
Logic input leakage current
EN, TA = 25°C
Hysteresis
2.375
50
V
mV
1.7
V
0.3
V
1
μA
0.5
–1
V
THERMAL SHUTDOWN
TSDN
(1)
Thermal shutdown threshold (1)
Shutdown temperature
Hysteresis
150
25
°C
Ensured by design. Not production tested.
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6.6 Switching Characteristics
Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT
= 3 × 10 μF and circuit shown in the Simplified DDR Application section (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWERGOOD COMPARATOR
TPGSTUPDLY
PGOOD startup delay
Startup rising edge, VOSNS within
15% of REFOUT
TPBADDLY
PGOOD bad delay
VOSNS is outside of the ±20%
PGOOD window
2
ms
10
μs
6.7 Typical Characteristics
For Figure 1 through Figure 18, 3 × 10-μF MLCCs (0805) are used on the output.
1.3
± 40°C
0°C
25°C
85°C
1.26
TA
± 40°C
0°C
25°C
85°C
930
Output Voltage (mV)
1.28
Output Voltage (V)
940
TA
1.24
1.22
1.2
920
910
900
890
880
1.18
870
±3
±2
±1
0
1
Output Current (A)
2
3
VVIN = 3.3 V
±3
DDR
±2
Figure 1. Load Regulation
700
Output Voltage (mV)
Output Voltage (mV)
TA
±40°C
0°C
25°C
85°C
710
750
740
730
720
710
690
680
670
660
650
700
±3
±2
±1
0
1
Output Current (A)
2
VVIN = 3.3 V
3
640
±3
DDR3
Figure 3. Load Regulation
6
DDR2
Figure 2. Load Regulation
± 40°C
0°C
25°C
85°C
760
3
720
TA
770
2
VVIN = 3.3 V
790
780
±1
0
1
Output Current (A)
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±2
±1
0
1
Output Current (mA)
VVIN = 3.3 V
2
3
DDR3L
Figure 4. Load Regulation
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Typical Characteristics (continued)
For Figure 1 through Figure 18, 3 × 10-μF MLCCs (0805) are used on the output.
670
± 40°C
0°C
25°C
85°C
630
1.25
1.2
Output Voltage (V)
650
Output Voltage (mV)
1.3
TA
610
590
1.15
1.1
1.05
TA
1
570
± 40°C
0°C
25°C
85°C
0.95
550
0.9
±3
±1
0
1
Output Current (A)
±2
VVIN = 3.3 V
2
3
±3
±2
LP DDR3 or DDR4
±1
0
1
Output Current (A)
2
3
VVIN =2.5 V
DDR
Figure 5. Load Regulation
1
800
0.95
825
Output Voltage (mV)
Output Voltage (V)
Figure 6. Load Regulation
0.9
0.85
0.8
TA
± 40°C
0°C
25°C
85°C
0.75
0.8
±3
±2
TA
± 40°C
0°C
25°C
85°C
750
725
700
675
650
±1
0
1
Output Current (A)
2
VVIN = 2.5 V
3
±3
DDR2
±2
±1
0
1
Output Current (A)
2
VVIN = 2.5 V
3
DDR3
Figure 8. Load Regulation
Figure 7. Load Regulation
720
750
TA
±40°C
0°C
25°C
85°C
Output Voltage (mV)
700
690
TA
± 40°C
0°C
25°C
85°C
700
Output Voltage (mV)
710
680
670
660
650
650
600
550
640
630
500
620
±3
±2
±1
0
1
Output Current (mA)
2
VVIN = 2.5 V
3
±3
DDR3L
Figure 9. Load Regulation
±2
±1
0
1
Output Current (A)
VVIN = 2.5 V
2
LP DDR3 or DDR4
Figure 10. Load Regulation
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Typical Characteristics (continued)
For Figure 1 through Figure 18, 3 × 10-μF MLCCs (0805) are used on the output.
1.255
± 40°C
25°C
85°C
1.253
1.252
1.251
1.25
1.249
1.248
1.247
±15
TA
± 40°C
25°C
85°C
904
Output Voltage (mV)
1.254
Output Voltage (V)
905
TA
903
902
901
900
899
898
±10
±5
0
5
REFOUT Output Current (mA)
10
897
±15
15
±10
±5
0
5
REFOUT Output Current (mA)
10
DDR
DDR2
Figure 11. REFOUT Load Regulation
755
680
± 40°C
25°C
85°C
753
678
752
751
750
749
748
747
±15
TA
±40°C
25°C
85°C
679
Output Voltage (mV)
Output Voltage (mV)
Figure 12. REFOUT Load Regulation
TA
754
677
676
675
674
673
672
±10
±5
0
5
REFOUT Output Current (mA)
10
15
-15
-10
DDR3L
Figure 13. REFOUT Load Regulation
Figure 14. REFOUT Load Regulation
1.4
605
TA
± 40°C
25°C
85°C
603
1.2
DROPOUT Voltage (V)
604
Output Voltage (mV)
15
-5
0
5
10
REFOUT Output Current (mA)
DDR3
602
601
600
599
1
0.8
0.6
0.4
VOUT (V)
0.6
0.75
0.9
1.25
0.2
598
597
±15
15
0
±10
±5
0
5
REFOUT Output Current (mA)
10
15
0
0.5
1
2
2.5
1.5
Output Current (A)
3
3.5
LP DDR3 or DDR4
Figure 15. REFOUT Load Regulation
8
Figure 16. DROPOUT Voltage vs Output Current
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Typical Characteristics (continued)
For Figure 1 through Figure 18, 3 × 10-μF MLCCs (0805) are used on the output.
50
40
60
200
150
50
150
±50
0
±10
±30
1k
Gain
Phase
10 k
100 k
Frequency (Hz)
1M
Phase (°)
0
10
100
30
Phase (°)
50
20
±20
40
100
30
Gain (dB)
200
0
10
±50
0
±100
±10
±150
±20
±200
10 M
50
20
±100
Gain
Phase
±30
1k
10 k
DDR2
Figure 17. Gain and Phase vs Frequency
Gain (dB)
60
±150
100 k
Frequency (Hz)
1M
±200
10 M
DDR3
Figure 18. Gain and Phase vs Frequency
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7 Detailed Description
7.1 Overview
The TPS51200A-Q1 device is a sink and source, double data-rate (DDR) termination regulator specifically
designed for low-input voltage, low-cost, and low-noise systems where space is a key consideration.
The TPS51200A-Q1 device is designed to provide proper termination voltage and a 10-mA buffered reference
voltage for DDR memory which includes the following DDR specifications (core voltage, reference voltage) with
minimal external components: DDR (2.5 V, 1.25 V), DDR2 (1.8 V, 0.9 V), DDR3 (1.5 V, 0.75 V), LP DDR3 or
DDR4 (1.2 V, 0.6 V).
7.2 Functional Block Diagram
REFIN
+
1
2.3 V
VIN 10
VOSNS
2
VLDOIN
6
REFOUT
3
VO
4
PGND
9
PGOOD
UVLO
+
Gm
DchgREF
5
+
EN
8
DchgVTT
Gm
REFINOK
+
+
+
GND
ENVTT
7
Start-up
Delay
+
UDG-08019
7.3 Feature Description
7.3.1 Sink and Source Regulator (VO Pin)
The TPS51200A-Q1 device is a sink and source (sink/source) tracking termination regulator specifically designed
for low input voltage, low-cost, and low external-component count systems where space is a key application
parameter. The TPS51200A-Q1 device integrates a high-performance, low-dropout (LDO) linear regulator that is
capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing pin, VOSNS, must be connected to the positive pin of the
output capacitors as a separate trace from the high current path from the VO pin.
7.3.2 Reference Input (REFIN Pin)
The output voltage, VO, is regulated to the REFOUT pin. When the REFIN pin is configured for standard DDR
termination applications, the REFIN pin can be set by an external equivalent ratio voltage divider connected to
the memory supply bus (VDDQ). The TPS51200A-Q1 device supports the REFIN voltage from 0.5 V to 1.8 V,
making the device versatile and ideal for many types of low-power LDO applications.
10
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Feature Description (continued)
7.3.3 Reference Output (REFOUT Pin)
When the device is configured for DDR termination applications, the REFOUT pin generates the DDR VTT
reference voltage for the memory application. The device is capable of supporting both a sourcing and sinking
load of 10 mA. The REFOUT pin becomes active when the REFIN voltage rises to 0.390 V and the VIN pin is
above the UVLO threshold. When the REFOUT pin is less than 0.375 V, it is disabled and subsequently
discharges to the GND pin through an internal 10-kΩ MOSFET. The REFOUT pin is independent of the EN pin
state.
7.3.4 Soft-Start Sequencing
The soft-start function of the VO pin is achieved through a current clamp. The current clamp allows the output
capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When
the VO pin is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit
(OCL) level. When the VO pin rises or falls within the PGOOD window, the current clamp level switches to the
full OCL level. The soft-start function is completely symmetrical and works not only from GND to the REFOUT
voltage, but also from the VLDOIN pin to the REFOUT voltage.
7.3.5 Enable Control (EN Pin)
When the EN pin is driven high, the TPS51200A-Q1 VO-regulator begins normal operation. When the EN pin is
driven low, the VO pin discharges to the GND pin through an internal 18-Ω MOSFET. The REFOUT pin remains
on when the EN pin is driven low.
7.3.6 Powergood Function (PGOOD Pin)
The TPS51200A-Q1 device provides an open-drain PGOOD output that goes high when the VO output is within
±20% of the REFOUT pin. The PGOOD pin deasserts within 10 μs after the output exceeds the size of the
powergood window. During initial VO startup, the PGOOD pin asserts high 2 ms (typ) after the VO pin enters
power good window. Because the PGOOD pin is an open-drain output, a 100-kΩ, pullup resistor between the
PGOOD pin and a stable active supply voltage rail is required.
7.3.7 Current Protection (VO Pin)
The LDO has a constant overcurrent limit (OCL). Note that the OCL level reduces by one-half when the output
voltage is not within the powergood window. This reduction is a non-latch protection.
7.3.8 UVLO Protection (VIN Pin)
For the VIN undervoltage-lockout (UVLO) protection, the device monitors the VIN voltage. When the VIN voltage
is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown
is a non-latch protection.
7.3.9 Thermal Shutdown
The TPS51200A-Q1 device monitors the junction temperature. If the device junction temperature exceeds the
threshold value, (typically 150°C), the VO and REFOUT regulators are both shut off, discharged by the internal
discharge MOSFETs. This shutdown is a non-latch protection.
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7.4 Device Functional Modes
The TPS51200A-Q1 device can be used in an application system where either a 2.5-V rail or a 3.3-V rail is
available. The minimum input voltage requirement is 2.375 V. If a 2.5-V rail is used, ensure that the absolute
minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a
2.5-V rail input is between –5% and 5% accuracy, or better.
7.4.1 S3 and Pseudo-S5 Support
The TPS51200A-Q1 device provides S3 support by an EN function. The EN pin can be connected to an SLP_S3
signal in the end application. Both the REFOUT and VO pin are on when EN = high (S0 state). The REFOUT pin
is maintained while the VO pin is turned off and discharged through an internal discharge MOSFET when EN =
low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, the TPS51200A-Q1 device enters
pseudo-S5 state. Both the VO and REFOUT outputs are turned off and discharged to the GND pin through
internal MOSFETs when pseudo-S5 support is engaged (S4/S5 state). Figure 19 shows a typical startup and
shutdown timing diagram for an application that uses S3 and pseudo-S5 support. It is also allowed to turn on
VLDOIN earlier than VIN during power on, and turn off VIN earlier than VLDOIN during power off.
7.4.2 Tracking Startup and Shutdown
The TPS51200A-Q1 device also supports tracking startup and shutdown when the EN pin is tied directly to the
system bus and not used to turn on or turn off the device. During tracking startup, the VO pin follows the
REFOUT pin when the REFIN voltage is greater than 0.39 V. The REFIN pin follows the rise of the VDDQ rail
though a voltage divider. The typical soft-start time for the VDDQ rail is approximately 3 ms, however this softstar time can vary depending on the system configuration. The SS time of the VO output no longer depends on
the OCL setting, but is a function of the SS time of the VDDQ rail. PGOOD is asserted 2 ms after the VO pin is
within ±20% of the REFOUT pin. During tracking shutdown, the VO pin falls following the REFOUT pin until the
REFOUT pin reaches 0.37 V. When the REFOUT pin falls below 0.37 V, the internal discharge MOSFETs are
turned on and quickly discharge both the REFOUT and VO pins to GND. The PGOOD pin is deasserted when
the VO pin is beyond the ±20% range of the REFOUT pin. Figure 20 shows the typical timing diagram for an
application that uses tracking startup and shutdown.
3.3VIN
VVDDQ = 1.5 V
VLDOIN
REFIN
REFOUT
(VTTREF)
EN
(S3_SLP)
VVO = 0.75 V
tSS .
VO
tSS =
PGOOD
COUT x VO
IOOCL
2 ms
Figure 19. Typical Timing Diagram for S3 and Pseudo-S5 Support
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Device Functional Modes (continued)
3.3VIN
EN
VLDOIN
REFIN
REFOUT
(VTTREF)
VO
tSS determined
by the SS time
of VLDOIN
VVO = 0.75 V
PGOOD
2 ms
Figure 20. Typical Timing Diagram of Tracking Startup and Shutdown
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51200A-Q1 device is specifically designed to power up the memory termination rail (as shown in
Figure 21). The DDR memory termination structure determines the main characteristics of the VTT rail, which is
to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 22 for typical
characteristics for a single memory cell.
8.2 Typical Application
8.2.1 VTT DIMM Applications
VTT
SPD
DQ
CA
VDD
VTT
CA
VDD
VDD
DQ
DDR3 240 Pin Socke t
VO
TPS512 00A-Q1
10 µF
10 µF
10 µF
UDG-08022
Figure 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200A-Q1
8.2.1.1 Design Parameters
Use the information listed in Table 1 as the design parameters.
Table 1. DDR, DDR2, DDR3, LP DDR3 and DDR4 Termination Technology and Differences
PARAMETER
DDR
DDR2
DR3
LP DDR3 or
DDR4
FSB Data Rates
200, 266, 333 and 400 MHz
400, 533, 677 and 800 MHz
800, 1066, 1330 and 1600 MHz
Same as DDR3
Termination
On-die termination for data group. VTT
Motherboard termination to VTT
termination for address, command and
for all signals
control signals
On-die termination for data group. VTT
termination for address, command and
control signals
Same as DDR3
Termination Current
Demand
Max source/sink transient
currents of up to 2.6 A to 2.9 A
Not as demanding
•
Only
34
signals
(address,
command, control) tied to VTT
•
ODT handles data signals
Less than 1 A of burst current
Not as demanding
•
Only
34
signals
(address,
command, control) tied to VTT
Same as DDR3
•
ODT handles data signals
Less than 1A of burst current
Voltage Level
2.5-V Core and I/O 1.25-V VTT
1.8-V Core and I/O 0.9-V VTT
1.5-V Core and I/O 0.75-V VTT
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0.6-V VTT
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 VIN Capacitor
Add a ceramic capacitor, with a value between 1-μF and 4.7-μF, placed close to the VIN pin, to stabilize the bias
supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply.
8.2.1.2.2 VLDO Input Capacitor
Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of
source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or greater)
ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is
used at the VO pin. In general, use one-half of the COUT value for input.
8.2.1.2.3 Output Capacitor
For stable operation, the total capacitance of the VO output pin must be greater than 20 μF. Attach three, 10-μF
ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series
inductance (ESL). If the ESR is greater than 2 mΩ, insert an R-C filter between the output and the VOSNS input
to achieve loop stability. The R-C filter time constant must be almost the same as or slightly lower than the time
constant of the output capacitor and its ESR.
8.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications
Figure 22 shows the typical characteristics for a single memory cell.
VDDQ
VTT
Q1
25 W
RS
20 W
Ouput
Buffer
(Driver)
Receiver
Q2
VOUT
VIN
VSS
UDG-08023
Figure 22. DDR Physical Signal System Bi-Directional SSTL Signaling
In Figure 22, when Q1 is on and Q2 is off:
• The current flows from VDDQ via the termination resistor to VTT
• VTT sinks current
In Figure 22, when Q2 is on and Q1 is off:
•
•
The current flows from VTT via the termination resistor to GND
VTT sources current
Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the
tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR
JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).
VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both DC and AC conditions
The specification indicates that VTT must keep track of VTTREF for proper signal conditioning.
The TPS51200A-Q1 device ensures the regulator output voltage to be:
VTTREF –25 mV < VTT < VTTREF + 25 mV, for both DC and AC conditions and –2 A < IVTT < 2 A
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The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to
DDR, DDR2, DDR3 and low-power DDR3/DDR4 applications (see Table 1 for detailed information). To meet the
stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on the
MLCC capacitors, three 10-μF ceramic capacitors are sufficient to meet the above requirement.
The TPS51200A-Q1 device is designed as a Gm driven LDO. The voltage droop between the reference input
and the output regulator is determined by the transconductance and output current of the device. The typical Gm
is 250 S at 2 A and changes with respect to the load to conserve the quiescent current (that is, the Gm is very
low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage
loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see
Equation 1).
FUGBW =
Gm
2 ´ p ´ COUT
where
•
•
•
FUGBW is the unity gain bandwidth
Gm is transconductance
COUT is the output capacitance
(1)
This type of regulator has two limitations on the output bulk capacitor requirement. To maintain stability, the zero
location contributed by the ESR of the output capacitors must be greater than the –3-dB point of the current loop.
This constraint means that higher ESR capacitors must not be used in the design. In addition, the impedance
characteristics of the ceramic capacitor must be well understood to prevent the gain peaking effect around the
Gm –3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO trace.
Figure 23. Bode Plot for a Typical DDR3 Configuration
Figure 23 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200A-Q1 device, where:
•
•
•
•
•
•
•
VIN = 3.3 V
VVLDOIN = 1.5 V
VVO = 0.75 V
IIO = 2 A
3 × 10-μF capacitors included
ESR = 2.5 mΩ
ESL = 800 pH
The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the
gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
Figure 24 shows the load regulation and Figure 25 shows the transient response for a typical DDR3
configuration. When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement
shows no difference between the DC and AC conditions.
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8.2.1.3 Application Curves
790
TA
780
± 40°C
0°C
25°C
85°C
Output Voltage (mV)
770
760
750
740
730
720
710
700
±3
±2
±1
0
1
Output Current (A)
2
VVIN = 3.3 V
3
DDR3
Figure 24. Output Current vs Output voltage
Figure 25. Transient Waveform
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8.2.2 Design Example 1
This design example describes a 3.3-VIN, DDR2 configuration.
TPS512 00A-Q1
R1
10 k
VVDD Q = 1.8 V
1
R2
10 k
REFIN
VIN
10
3.3 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVDD Q = 1.8 V
C7
10 µF
C2
10 µF
VLDOIN
3
VO
4
PGND
5
VOS NS
PGO OD
9
PGO OD
GND
8
EN
7
SLP_S3
REFOUT
6
VTTRE F
C8
10 µF
VVTT = 0.9 V
C1
10 µF
2
C6
4.7 µF
C3
10 µF
C5
0.1 µF
UDG-08028
Figure 26. 3.3-VIN, DDR2 Configuration
8.2.2.1 Design Parameters
For this design example, use the parameters listed in Table 2.
Table 2. Design Example 1 List of Materials
REFERENCE
DESIGNATOR
R1, R2
DESCRIPTION
Resistor
R3
C1, C2, C3
PART NUMBER
MANUFACTURER
GRM21BR70J106KE76L
Murata
10 kΩ
100 kΩ
10 μF, 6.3 V
C4
C5
SPECIFICATION
1000 pF
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.3 Design Example 2
This design example describes a 3.3-VIN, DDR3 configuration.
TPS512 00A-Q1
VVDD Q = 1.5 V
1
R2
10 k
REFIN
VIN
10
3.3 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVDD Q = 1.5 V
C7
10 µF
C2
10 µF
VLDOIN
3
VO
4
PGND
5
VOS NS
PGO OD
9
GND
8
EN
7
REFOUT
6
PGO OD
C8
10 µF
VVTT = 0.75 V
C1
10 µF
2
C6
4.7 µF
C3
10 µF
SLP_S3
VTTRE F
C5
0.1 µF
UDG-08029
Figure 27. 3.3-VIN, DDR3 Configuration
8.2.3.1 Design Parameters
For this design example, use the parameters listed in Table 3.
Table 3. Design Example 2 List of Materials
REFERENCE
DESIGNATOR
R1, R2
R3
DESCRIPTION
Resistor
SPECIFICATION
GRM21BR70J106KE76L
Murata
100 kΩ
10 μF, 6.3 V
C4
1000 pF
Capacitor
MANUFACTURER
10 kΩ
C1, C2, C3
C5
PART NUMBER
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.4 Design Example 3
This design example describes a 2.5-VIN, DDR3 configuration.
TPS512 00A-Q1
R1
10 k
VVDD Q = 1.5 V
1
R2
10 k
REFIN
VIN
10
2.5 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVDD Q = 1.5 V
C7
10 µF
C2
10 µF
VLDOIN
3
VO
4
PGND
5
VOS NS
PGO OD
9
GND
8
EN
7
REFOUT
6
PGO OD
C8
10 µF
VVTT = 0.75 V
C1
10 µF
2
C6
4.7 µF
C3
10 µF
SLP_S3
VTTRE F
C5
0.1 µF
UDG-08030
Figure 28. 2.5-VIN, DDR3 Configuration
8.2.4.1 Design Parameters
For this design example, use the parameters listed in Table 4.
Table 4. Design Example 3 List of Materials
REFERENCE
DESIGNATOR
R1, R2
DESCRIPTION
Resistor
R3
C1, C2, C3
PART NUMBER
MANUFACTURER
GRM21BR70J106KE76L
Murata
10 kΩ
100 kΩ
10 μF, 6.3 V
C4
C5
SPECIFICATION
1000 pF
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.5 Design Example 4
This design example describes a 3.3-VIN, LP DDR3 or DDR4 configuration.
TPS512 00A-Q1
VVDD Q = 1.2 V
1
R2
10 k
C7
10 µF
3.3 VIN
R3
100 k
2
VLDOIN
3
VO
4
PGND
5
VOS NS
C6
4.7 µF
PGO OD
9
GND
8
EN
7
SLP_S3
REFOUT
6
VTTRE F
PGO OD
C8
10 µF
VVTT = 0.6 V
C2
10 µF
10
C4
100 0 pF
VVLD OIN = VVDD Q = 1.2 V
C1
10 µF
VIN
REFIN
C3
10 µF
C5
0.1 µF
UDG-08031
Figure 29. 3.3-VIN, LP DDR3 or DDR4 Configuration
8.2.5.1 Design Parameters
For this design example, use the parameters listed in Table 5.
Table 5. Design Example 4 List of Materials
REFERENCE
DESIGNATOR
R1, R2
R3
DESCRIPTION
Resistor
SPECIFICATION
GRM21BR70J106KE76L
Murata
100 kΩ
10 μF, 6.3 V
C4
1000 pF
Capacitor
MANUFACTURER
10 kΩ
C1, C2, C3
C5
PART NUMBER
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.6 Design Example 5
This design example describes a 3.3-VIN, DDR3 tracking configuration.
TPS512 00A-Q1
R1
10 k
VVDD Q = 1.5 V
1
R2
10 k
REFIN
VIN
10
3.3 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVDD Q = 1.5 V
C7
10 µF
C2
10 µF
VLDOIN
3
VO
4
PGND
5
VOS NS
PGO OD
9
GND
8
EN
7
REFOUT
6
PGO OD
C8
10 µF
VVTT = 0.75 V
C1
10 µF
2
C6
4.7 µF
C3
10 µF
VTTRE F
C5
0.1 µF
UDG-08032
Figure 30. 3.3-VIN, DDR3 Tracking Configuration
8.2.6.1 Design Parameters
For this design example, use the parameters listed in Table 6.
Table 6. Design Example 5 List of Materials
REFERENCE
DESIGNATOR
R1, R2
DESCRIPTION
Resistor
R3
SPECIFICATION
GRM21BR70J106KE76L
Murata
100 kΩ
10 μF, 6.3 V
C4
1000 pF
Capacitor
MANUFACTURER
10 kΩ
C1, C2, C3
C5
PART NUMBER
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.7 Design Example 6
This design example describes a 3.3-VIN, LDO configuration.
TPS512 00A-Q1
2.5 V
1
R2
10 k
VIN
REFIN
10
3.3 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVLD OREF = 2.5 V
C7
10 µF
C2
10 µF
VLDOIN
3
VO
4
PGND
5
VOS NS
PGO OD
9
PGO OD
GND
8
EN
7
ENABL E
REFOUT
6
REFOUT
C8
10 µF
VVLD O = 1.8 V
C1
10 µF
2
C6
4.7 µF
C3
10 µF
C5
0.1 µF
UDG-08033
Figure 31. 3.3-VIN, LDO Configuration
8.2.7.1 Design Parameters
For this design example, use the parameters listed in Table 7.
Table 7. Design Example 6 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
R1
R2
SPECIFICATION
MANUFACTURER
GRM21BR70J106KE76L
Murata
10 kΩ
Resistor
3.86 kΩ
R3
100 kΩ
C1, C2, C3
10 μF, 6.3 V
C4
1000 pF
C5
PART NUMBER
Capacitor
0.1 μF
C6
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
C7, C8
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
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8.2.8 Design Example 7
This design example describes a 3.3-VIN, DDR3 configuration with Low Pass Filter (LPF).
TPS512 00A-Q1
VVDD Q = 1.5 V
1
R2
10 k
REFIN
VIN
10
3.3 VIN
C4
100 0 pF
R3
100 k
VVLD OIN = VVDD Q = 1.5 V
C7
10 µF
2
VLDOIN
3
VO
4
PGND
5
VOS NS
C6
4.7 µF
PGO OD
9
GND
8
EN
7
SLP_S3
REFOUT
6
VTTRE F
PGO OD
C8
10 µF
VVTT = 0.75 V
R4(1)
C1
10 µF
C2
10 µF
C3
10 µF
C5
0.1 µF
C9(1)
UDG-08034
Figure 32. 3.3-VIN, DDR3 Configuration with LPF
8.2.8.1 Design Parameters
For this design example, use the parameters listed in Table 8.
Table 8. Design Example 7 List of Materials
REFERENCE
DESIGNATOR
DESCRIPTION
R1, R2
SPECIFICATION
PART NUMBER
MANUFACTURER
GRM21BR70J106KE76L
Murata
4.7 μF, 6.3 V
GRM21BR60J475KA11L
Murata
10 μF, 6.3 V
GRM21BR70J106KE76L
Murata
10 kΩ
R3
Resistor
100 kΩ
R4 (1)
C1, C2, C3
10 μF, 6.3 V
C4
1000 pF
C5
Capacitor
C6
C7, C8
0.1 μF
C9 (1)
(1)
24
The values of R4 and C9 must be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output
capacitors (ESR and ESL).
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply with a range between 2.375 V and 3.5 V. This
input supply must be well regulated. TI recommends adding at least one 1-µF to 4.7-µF ceramic capacitor at the
VIN pin.
10 Layout
10.1 Layout Guidelines
Consider the following points before starting the layout design.
• The input bypass capacitor for VLDOIN must be placed as close as possible to the pin with short and wide
connections.
• The output capacitor for VO must be placed close to the pin with short and wide connection to avoid
additional ESR or ESL trace inductance.
• VOSNS must be connected to the positive node of VO output capacitors as a separate trace from the high
current power line. This configuration is strongly recommended to avoid additional ESR, ESL, or both. If
sensing the voltage at the point of the load is required, TI recommends to attach the output capacitors at that
point. Also, it is recommended to minimize any additional ESR, ESL, or both of ground trace between the
GND pin and the output capacitors.
• Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitors is larger than 2 mΩ.
• REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of REFOUT. Avoid any noise-generating lines.
• The negative node of the VO output capacitors and the REFOUT capacitor must be tied together by avoiding
common impedance to the high current path of the VO source/sink current.
• The GND and PGND pins must be connected to the thermal land underneath the die pad with multiple vias
connecting to the internal system ground planes (for better result, use at least two internal ground planes).
Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.
Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.
• To effectively remove heat from the package, properly prepare the thermal land. Apply solder directly to the
thermal pad of the package. The wide traces of the component and the side copper connected to the thermal
land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal land to the
internal/solder side ground planes must also be used to help dissipation.
• See the TPS51200-EVM User's Guide (SLUU323) for detailed layout recommendations.
10.1.1 LDO Design Guidelines
The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage
transconductance to drive a certain load. For device, a minimum of 300 mV (VLDOINMIIN – VOMAX) is needed to
support a Gm driven sourcing current of 2 A based on a design of VIN = 3.3 V and COUT = 3 × 10 μF. Because
the TPS51200A-Q1 device is essentially a Gm driven LDO, the impedance characteristics are both a function of
the 1 / Gm and RDS(on) of the sourcing MOSFET (see Figure 33). The current inflection point of the design is
between 2 A and 3 A. When ISRC is less than the inflection point, the LDO is considered to be operating in the
Gm region; when ISRC is greater than the inflection point but less than the overcurrent limit point, the LDO is
operating in the RDS(on) region. The maximum sourcing RDS(on) is 0.144 Ω with VIN = 3 V and TJ = 125°C.
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Output Voltage, VVO (V)
Layout Guidelines (continued)
1/Gm
Inflection
Point
(between
2 A and 3 A)
1/RDS(on)
Overcurrent
Limit
Source Current, ISRC (A)
UDG-08026
Figure 33. Impedance Characteristics
10.2 Layout Example
REFIN
1
10
VIN
VLDOIN
2
9
PGOOD
VO
3
8
GND
PGND
4
7
EN
VOSNS
5
6
REFOUT
Figure 34. Layout Example
26
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10.3 Thermal Considerations
Because the TPS51200A-Q1 device is a linear regulator, the VO current flows in both source and sink directions,
thereby dissipating power from the device. When the device is sourcing current, the voltage difference between
VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.
PDISS _ SRC =
(VVLDOIN
- VVO ) x IO _ SRC
(2)
In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power
loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power
dissipation, PDISS_SNK can be calculated by Equation 3.
PDISS _ SNK = VVO ´ IO _ SNK
(3)
Because the device does not sink and source current at the same time and the IO current may vary rapidly with
time, the actual power dissipation must be the time average of the above dissipations over the thermal relaxation
duration of the system. Another source of power consumption is the current used for the internal current control
circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less during normal
operatiing conditions. This power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by Equation 4.
PPKG = (TJ(MAX) – TA(MAX)) / RθJA
PPKG =
TJ(max) ´ TA(max)
R qJA
where
•
•
•
TJ(MAX) is 125°C
TA(MAX) is the maximum ambient temperature in the system
RθJA is the thermal resistance from junction to ambient
(4)
The thermal performance of an LDO depends on the printed circuit board (PCB) layout. The TPS51200A-Q1
device is housed in a thermally-enhanced package that has an exposed die pad underneath the body. For
improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This
ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, RθJA, 55.7°C/W, is
achieved based on a land pattern of 3 mm × 1,9 mm with four vias (0,33-mm via diameter, the standard thermal
via size) without air flow (see Figure 35).
Land Pad
3 mm × 1.9 mm
Exposed Thermal
Die Pad,
2.48 mm × 1.74 mm
UDG-08018
Figure 35. Recommend Land Pad Pattern for TPS51200A-Q1
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Thermal Considerations (continued)
TT on top of package
TB on PCB surface
1 mm
Figure 36. Package Thermal Measurement
To further improve the thermal performance of this device, using a larger than recommended thermal land as
well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical
thermal resistance from junction to thermal pad, RθJP, is 12.1°C/W (based on the recommend land pad and four
standard thermal vias).
28
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
TPS51200-EVM User's Guide, SLUU323
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Aug-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS51200AQDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
512AQ
TPS51200AQDRCTQ1
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
512AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS51200AQDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS51200AQDRCTQ1
VSON
DRC
10
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS51200AQDRCRQ1
VSON
DRC
10
3000
338.0
355.0
50.0
TPS51200AQDRCTQ1
VSON
DRC
10
250
205.0
200.0
33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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