Texas Instruments | LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator | Datasheet | Texas Instruments LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator Datasheet

Texas Instruments LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator Datasheet
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LP8733-Q1
SNVSB64 – SEPTEMBER 2018
LP8733xx-Q1 Dual High-Current Buck Converter and Dual Linear Regulator
1 Features
2 Applications
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1
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AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage: 2.8 V to 5.5 V
Two High-Efficiency Step-Down DC/DC
Converters:
– Output Voltage: 0.7 V to 3.36 V
– Maximum Output Current 3 A per phase
– Auto Phase Adding/Shedding and Force MultiPhase Operations in Dual-Phase Configuration
– Remote Differential Feedback Voltage Sensing
in Dual-Phase Configuration
– Programmable Output-Voltage Slew Rate
From 0.5 mV/µs to 10 mV/µs
– 2-MHz Switching Frequency
– Spread-Spectrum Mode and Phase
Interleaving for EMI Reduction
Two Linear Regulators:
– Input Voltage: 2.5 V to 5.5 V
– Output Voltage: 0.8 V to 3.3 V
– Maximum Output Current 300 mA
Configurable General-Purpose Output Signals
(GPO, GPO2)
Interrupt Function With Programmable Masking
Programmable Power-Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
28-pin, 5-mm × 5-mm VQFN Package with
Wettable Flanks
Configurable
multi-phase
VIN_B0
SW_B0
VIN_B1
The LP8733xx-Q1 is designed to meet the power
management
requirements
in
automotive
applications. The device has two step-down DC/DC
converters which can be configured as single dualphase regulator or two single-phase regulators and
two linear regulators and general-purpose digitaloutput signals. The device is controlled by an I2Ccompatible serial interface and by an enable signal.
The automatic PWM/PFM (AUTO mode) operation
together with the automatic phase adding/shedding
maximizes gives high efficiency over a wide outputcurrent range. The LP8733xx-Q1 supports remote
voltage
sensing
(differential
in
dual-phase
configuration) to compensate IR drop between the
regulator output and the point-of-load (POL), thus
improving the accuracy of the output voltage. In
addition, the switching clock can be forced to PWM
mode and also synchronized to an external clock to
minimize the disturbances.
The LP8733xx-Q1 device supports programmable
start-up and shutdown delays and sequences
including GPO signals synchronized to the enable
signal. During start-up and voltage change, the
device controls the output slew rate to minimize
output voltage overshoot and the in-rush current.
Device Information
PART NUMBER
LP8733xx-Q1
90
FB_B1
SDA
SCL
nINT
VOUT_LDO0
VOUT_LDO0
Efficiency (%)
FB_B0
VANA
80
70
CLKIN (GPO2)
GPO
BODY SIZE (NOM)
5.00 mm × 5.00 mm
100
VIN_LDO1
EN
PACKAGE
VQFN (28)
DC/DC Efficiency vs Output Current (Dual-Phase)
1±2
Outputs
SW_B1
VIN_LDO0
3 Description
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
Automotive Head Unit and Cluster
Automotive Camera Module
Surround View System ECU
Radar System ECU
VOUT_LDO1
VOUT_LDO1
1PH, Vin=3.7V, Vout=1.0V
1PH, Vin=3.7V, Vout=2.5V
2PH, Vin=3.7V, Vout=1.0V
2PH, Vin=3.7V, Vout=2.5V
60
PGOOD
GNDs
50
0.025
0.1
1
Output Current (A)
6
D420
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP8733-Q1
SNVSB64 – SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.5 Programming........................................................... 39
7.6 Register Maps ......................................................... 42
1
1
1
2
3
5
8
8.1 Application Information............................................ 60
8.2 Typical Applications ................................................ 60
9 Power Supply Recommendations...................... 73
10 Layout................................................................... 73
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
I2C Serial Bus Timing Parameters .......................... 12
Typical Characteristics ............................................ 14
10.1 Layout Guidelines ................................................. 73
10.2 Layout Example .................................................... 75
11 Device and Documentation Support ................. 76
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description ................................................
Device Functional Modes........................................
Application and Implementation ........................ 60
16
17
17
38
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
76
76
76
76
76
76
12 Mechanical, Packaging, and Orderable
Information ........................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
September 2018
*
Initial release
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SNVSB64 – SEPTEMBER 2018
5 Pin Configuration and Functions
RHD Package
28-Pin VQFN With Thermal Pad
Top View
21
20
19
18
17
16
15
PGND_B0
PGND_B0
SGND
SDA
SCL
PGND_B1
PGND_B1
22
SW_B0
SW_B1
14
23
SW_B0
SW_B1
13
24
VIN_B0
VIN_B1
12
25
VIN_B0
VIN_B1
11
26
GPO
CLKIN
10
27
PGOOD
28
VIN_LDO0
THERMAL PAD
VOUT_LDO0
FB_B0
FB_B1
AGND
VANA
EN
VOUT_LDO1
1
2
3
4
5
6
7
nINT
9
VIN_LDO1
8
Pin Functions
PIN
NUMBER
NAME
TYPE (1)
DESCRIPTION
1
VOUT_LDO0
P/O
2
FB_B0
A
Output voltage feedback (positive) for Buck 0
3
FB_B1
A
Output voltage feedback (positive) for Buck 1 in two single-phase configuration / Output ground
feedback (negative) for Buck 0 in dual-phase configuration
4
AGND
G
Ground
5
VANA
P/I
Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
6
EN
D/I
Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin
floating.
7
VOUT_LDO1
P/O
LDO1 output. If LDO1 is not used, leave the pin floating.
8
VIN_LDO1
P/I
Power input for LDO1. If LDO1 is not used, connect the pin to VANA.
9
nINT
D/O
Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.
10
CLKIN
D/I/O
External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not
used, leave the pin floating.
11, 12
VIN_B1
P/I
Input for Buck 1. The separate power pins VIN_Bx are not connected together internally VIN_Bx pins must be connected together in the application and be locally bypassed.
13, 14
SW_B1
P/O
Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.
15, 16
PGND_B1
P/G
Power ground for Buck 1
17
SCL
D/I
Serial interface clock input for I2C access. Connect a pullup resistor. If the I2C interface is not
used, connect the pin to Ground.
18
SDA
D/I/O
19
SGND
G
(1)
LDO0 output. If LDO0 is not used, leave the pin floating.
Serial interface data input and output for I2C access. Connect a pullup resistor. If the I2C
interface is not used, connect the pin to Ground.
Ground
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
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Pin Functions (continued)
PIN
NUMBER
NAME
TYPE (1)
DESCRIPTION
20, 21
PGND_B0
P/G
Power ground for Buck 0
22, 23
SW_B0
P/O
Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.
24, 25
VIN_B0
P/I
Input for Buck 0. The separate power pins VIN_Bx are not connected together internally VIN_Bx pins must be connected together in the application and be locally bypassed.
26
GPO
D/O
General-purpose digital output. If the pin is not used, leave the pin floating.
27
PGOOD
D/O
Power-good indication signal. If the pin is not used, leave the pin floating.
28
VIN_LDO0
P/I
Power input for LDO0. If LDO0 is not used, connect the pin to VANA.
—
—
Connect to PCB ground plane using multiple vias for good thermal performance.
Thermal
Pad
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VIN_Bx, VANA
Voltage on power connections (must use the same
input supply)
UNIT
–0.3
6
V
VIN_LDOx
Voltage on power connections
–0.3
6
V
V
SW_Bx
Voltage on buck switch nodes
–0.3
(VIN_Bx + 0.3 V) with 6-V
maximum
FB_Bx
Voltage on buck voltage sense nodes
–0.3
(VANA + 0.3 V) with 6-V
maximum
V
VOUT_LDOx
Voltage on LDO output
-0.3
(VIN_LDOx + 0.3 V) with 6-V
maximum
V
SDA, SCL, nINT, EN
Voltage on logic pins (input or output pins)
–0.3
6
V
V
PGOOD, GPO, CLKIN
(GPO2)
Voltage on logic pins (input or output pins)
–0.3
(VANA + 0.3 V) with 6-V
maximum
TJ-MAX
Junction temperature
−40
150
Tstg
Storage temperature
–65
150
Maximum lead temperature (soldering, 10 seconds)
(1)
(2)
°C
260
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
Human-body model (HBM)
V(ESD)
Electrostatic discharge
Charged-device model (CDM)
UNIT
±2000
All pins
±500
Corner pins (1, 7, 8, 14,
15, 21, 22, 28)
±750
V
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_Bx, VANA
Voltage on power connections (must use the same input
supply)
2.8
5.5
V
VIN_LDOx
Voltage on LDO inputs
2.5
5.5
V
EN, nINT
Voltage on logic pins (input or output pins)
0
5.5
V
Voltage on logic pins (input pin)
0
VANA with 5.5-V
maximum
V
Voltage on logic pins (output pins)
0
VANA
V
Voltage on I2C interface, Standard (100 kHz), Fast (400
kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
0
1.95
V
Voltage on I2C interface, Standard (100 kHz), Fast (400
kHz), and Fast+ (1 MHz) Modes
0
VANA with 3.6-V
maximum
V
CLKIN
PGOOD, GPO, GPO2
SCL, SDA
TEMPERATURE
TJ
Junction temperature
−40
140
°C
TA
Ambient temperature
−40
125
°C
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6.4 Thermal Information
LP8733xx-Q1
THERMAL METRIC (1)
RHD (VQFN)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
36.7
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
26.6
°C/W
RθJB
Junction-to-board thermal resistance
8.9
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
8.8
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted. (1) (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
CIN_BUCK
Input filtering
capacitance for buck
regulators
Effective capacitance, connected from VIN_Bx
to PGND_Bx
1.9
10
COUT_BUCK
Output filtering
capacitance for buck
regulators
Effective capacitance per phase
10
22
CPOL_BUCK
Point-of-load (POL)
capacitance for buck
regulators
Optional POL capacitance
COUT-
Buck output capacitance,
Total output capacitance per phase
total (local and POL)
TOTAL_BUCK
µF
500
22
µF
µF
500
µF
CIN_LDO
Input filtering
capacitance for LDO
regulators
Effective capacitance, connected from
VIN_LDOx to AGND. CIN_LDO must be at least
two times larger than COUT_LDO
0.6
2.2
COUT_LDO
Output filtering
capacitance for LDO
regulators
Effective capacitance
0.4
1
2.7
µF
ESRC
Input and output
capacitor ESR
[1-10] MHz
2
10
mΩ
L
Inductor
Inductance of the inductor
DCRL
Inductor DCR
µF
0.47
–30%
30%
25
µH
mΩ
BUCK REGULATORS
V(VIN_Bx),
V(VANA)
VOUT_Bx
IOUT_Bx
(1)
(2)
(3)
6
Input voltage range
Output voltage
Output current
VIN_Bx and VANA pins must be connected to
the same supply line
2.8
Programmable voltage range
0.7
Step size, 0.7 V ≤ VOUT < 0.73 V
3.7
5.5
V
1
3.36
V
10
Step size, 0.73 V ≤ VOUT < 1.4 V
5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
20
mV
Output current, single-phase output
3 (3)
Output current, dual-phase output
6 (3)
A
All voltage values are with respect to network ground.
Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the
junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient
temperature.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2).
PARAMETER
TEST CONDITIONS
Input and Output voltage Minimum voltage between V(VIN_Bx) and
difference
VOUT to fulfill the electrical characteristics
MIN
TYP
MAX
0.8
V
Force PWM mode, VOUT < 1 V
–20
20
DC output voltage
accuracy, includes
voltage reference, DC
load and line regulations,
process and temperature
Force PWM mode, VOUT ≥ 1 V
–2%
2%
PFM mode, VOUT < 1 V, the average output
voltage level is increased by max. 20 mV
–20mV
40mV
PFM mode, VOUT ≥ 1 V, the average output
voltage level is increased by max. 20 mV
–2%
2% + 20
mV
Ripple voltage, singlephase output
PWM mode
10
PFM mode, IOUT = 10 mA
25
Ripple voltage, dualphase output
PWM mode
5
PFM mode, IOUT = 10 mA
4
DCLNR
DC line regulation
IOUT = 1 A
±0.05
DCLDR
DC load regulation in
PWM mode
VOUT_Bx = 1 V, IOUT from 0 to IOUT(max)
0.3%
VOUT_Bx_DC
TLDSR
mVp-p
mVp-p
%/V
±55
mV
Transient load step
response, dual-phase
output
IOUT = 0.1 A to 4 A, TR = TF = 400 ns, PWM
mode
±50
mV
±10
mV
ILIM
Forward current limit per
phase (peak for every
switching cycle)
V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
Programmable range
1.5
Step size
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A
NEG
mV
IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM
mode
Transient line response
ILIM
mV
Transient load step
response, single-phase
output
TLNSR
FWD
UNIT
Negative current limit per
phase
4
A
0.5
–5%
7.5%
20%
–20%
7.5%
20%
1.6
2.0
3.0
A
RDS(ON) HS FET
On-resistance, high-side
FET
Each phase, between VIN_Bx and SW_Bx
pins (I = 1 A)
50
110
mΩ
RDS(ON) LS FET
On-resistance, low-side
FET
Each phase, between SW_Bx and PGND_Bx
pins (I = 1 A)
45
90
mΩ
ƒSW
Switching frequency
PWM mode
2
2.2
MHz
Current balancing for
dual-phase output
Current mismatch between phases, IOUT > 1
mA
Start-up time (soft start)
From ENx to VOUT_Bx = 0.35 V (slew-rate
control begins)
Output voltage slewrate (4)
(4)
1.8
10%
120
SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK <
80 µF per phase
10
SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK <
130 µF per phase
7.5
SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK <
250 µF per phase
SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK
< 500 µF per phase
µs
3.8
–15%
15%
mV/µs
1.9
SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK
< 500 µF per phase
0.94
SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK
< 500 µF per phase
0.47
The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPFM-PWM
PFM-to-PWM - current
threshold (5)
550
mA
IPWM-PFM
PWM-to-PFM - current
threshold (5)
290
mA
IADD
Phase adding level
(dual-phase output)
From 1-phase to 2-phase
1000
mA
ISHED
Phase shedding level
(dual-phase output)
From 2-phase to 1-phase
650
mA
RDIS_Bx
Output pulldown
resistance
Regulator disabled
150
250
350
Overvoltage threshold (compared to DC
output voltage level, VVOUT_Bx_DC)
39
50
64
Undervoltage threshold (compared to DC
output voltage level, VVOUT_Bx_DC)
–53
–40
–29
Ω
V(VIN_Bx) and V(VANA) fixed 3.7 V
Output voltage
monitoring for PGOOD
pin and for power-good
Interrupt
Deglitch time during operation and after
voltage change
Gating time for PGOOD
signal after regulator
enable or voltage
change
mV
4
PGOOD_MODE = 0
15
800
µs
µs
LDO REGULATORS
VIN_LDOx
Input voltage range for
LDO power inputs
VOUT_LDOx
Output voltage
IOUT_LDOx
Output current
Dropout voltage
VIN_LDOx can be higher or lower than V(VANA)
2.5
Programmable voltage range
0.8
Step size
VOUT_LDO_DC
DCLNR
DC line regulation
IOUT = 1 mA
DCLDR
DC load regulation
IOUT = 1 mA to IOUT(max)
TLDSR
Transient load step
response
IOUT = 1 mA to 300 mA, TR = TF = 1 µs
TLNSR
Transient line response
PSRR
(5)
8
3.3
V
V
300
mA
200
mV
–20
20
mV
–2%
2%
0.1
%/V
0.8%
–50/+40
mV
V(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF =
10 µs, IOUT = IOUT(max)
±7
mV
Power supply ripple
rejection
ƒ = 10 kHz, IOUT = IOUT(max)
53
dB
Noise
10 Hz < F < 100 kHz, IOUT = IOUT(max)
LDO current limit
VOUT = 0 V
Start-up time
From enable to valid output voltage
82
400
Slew rate during start-up
RDIS_LDOx
5.5
0.1
V(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max),
Programmed output voltage is higher than
V(VIN_LDOx)
DC output voltage
VOUT < 1 V
accuracy, includes
voltage reference, DC
load and line regulations, VOUT ≥ 1 V
process, temperature
ISHORT(LDOx)
3.7
Output pulldown
resistance
Regulator disabled
150
500
µVrms
600
mA
300
µs
15
mV/µs
250
350
Ω
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and
the inductor current level.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2).
PARAMETER
TEST CONDITIONS
Overvoltage monitoring, voltage rising
(compared to DC output voltage level,
VOUT_LDO_DC)
Output voltage
monitoring for PGOOD
pin and for power-good
interrupt
Overvoltage monitoring, hysteresis
Undervoltage monitoring, voltage falling
(compared to DC output voltage level,
VOUT_LDO_DC)
Undervoltage monitoring, hysteresis
Deglitch time during operation and after
voltage change
Gating time for PGOOD
signal after regulator
enable or voltage
change
MIN
TYP
MAX
106%
108%
110%
3%
3.5%
4%
90%
92%
94%
3%
3.5%
4%
4
PGOOD_MODE = 0
UNIT
15
µs
800
µs
EXTERNAL CLOCK AND PLL
Nominal frequency
fEXT_CLK
External input clock
(6)
Nominal frequency step size
Required accuracy from nominal frequency
External clock detection
1
24
MHz
1
–30%
10%
Delay for missing clock detection
1.8
Delay and debounce for clock detection
20
µs
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
µs
PLL output clock jitter
Cycle to cycle
300
ps, p-p
PROTECTION FUNCTIONS
Thermal warning
Temperature rising, TDIE_WARN_LEVEL = 0
115
125
135
Temperature rising, TDIE_WARN_LEVEL = 1
127
137
147
Hysteresis
Thermal shutdown
VANAOVP
VANA overvoltage
Temperature rising
VANAUVLO
140
Hysteresis
150
160
20
Voltage rising
5.6
5.8
6.1
Voltage falling
5.45
5.73
5.96
Hysteresis
°C
20
40
°C
V
mV
Voltage rising
2.51
2.63
2.75
Voltage falling
2.5
2.6
2.7
Buck short-circuit
detection
Threshold
280
360
440
mV
LDO short-circuit
detection
Threshold
190
300
450
mV
VANA undervoltage
lockout
V
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement
range
Maximum code
Resolution
LSB
Measurement accuracy
IOUT > 1 A per phase
Measurement time
PFM mode (automatically changing to PWM
mode for the measurement)
10.22
20
A
mA
<10%
45
PWM mode
µs
4
CURRENT CONSUMPTION
(6)
The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2).
PARAMETER
TEST CONDITIONS
MIN
Standby current
consumption, regulators
disabled
TYP
MAX
UNIT
9
µA
58
µA
100
µA
Active current
consumption, one buck
regulator enabled in auto Dual-phase output: IOUT_Bx = 0 mA, not
mode, internal RC
switching
oscillator, PGOOD
monitoring enabled
72
µA
Active current
consumption during
PWM operation, one
buck regulator enabled
Single-phase output: IOUT_Bx = 0 mA
15
mA
Active current
consumption during
PWM operation, two
buck regulators enabled
Single-phase output: IOUT_Bx = 0 mA
30
mA
Active current
consumption during
PWM operation, buck
regulator enabled
Dual-phase output: IOUT_Bx = 0 mA
15
mA
LDO regulator enabled
Additional current consumption per LDO,
IOUT_LDOx = 0 mA
86
µA
PLL and clock detector
current consumption
fEXT_CLK = 1 MHz, Additional current
consumption when enabled
2
mA
Active current
consumption, one buck
regulator enabled in auto Single-phase output: IOUT_Bx = 0 mA, not
mode, internal RC
switching
oscillator, PGOOD
monitoring enabled
Active current
consumption, two buck
regulators enabled in
auto mode, internal RC
oscillator, PGOOD
monitoring enabled
Single-phase output: IOUT_Bx = 0 mA, not
switching
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VIL
Input low level
VIH
Input high level
1.2
VHYS
Hysteresis of Schmitt
Trigger inputs
10
EN/CLKIN pulldown
resistance
0.4
EN_PD/CLKIN_PD = 1
80
200
500
V
mV
kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL
Output low level
RP
External pullup resistor
for nINT
nINT: ISOURCE = 2 mA
0.4
V
SDA: ISOURCE = 20 mA
0.4
V
To VIO Supply
10
kΩ
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOL
Output low level
VOH
Output high level,
configured to push-pull
10
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ISOURCE = 2 mA
ISINK = 2 mA
VVANA –
0.4
0.4
V
VVANA
V
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx
and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1)(2).
PARAMETER
VPU
Supply voltage for
external pullup resistor,
configured to open-drain
RPU
External pullup resistor,
configured to open-drain
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVANA
V
10
kΩ
ALL DIGITAL INPUTS
ILEAK
Input current
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All logic inputs over pin voltage range
−1
1
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6.6 I2C Serial Bus Timing Parameters
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See
(1)
and Figure 1.
MIN
fSCL
Serial clock frequency
Standard mode
100
Fast mode
400
Fast mode+
3.4
High-speed mode, Cb = 400 pF
SCL low time
4.7
Fast mode
1.3
tHIGH
tSU;DAT
tHD;DAT
tSU;STA
SCL high time
Data setup time
Data hold time
Setup time for a start or
a repeated start
condition
0.16
High-speed mode, Cb = 400 pF
0.32
Fast mode+
0.26
High-speed mode, Cb = 100 pF
0.06
High-speed mode, Cb = 400 pF
0.12
Standard mode
250
Fast mode
100
Fast mode+
50
High-speed mode
10
Standard mode
10
3450
Fast mode
10
900
Fast mode+
10
High-speed mode, Cb = 100 pF
10
70
High-speed mode, Cb = 400 pF
10
150
Standard mode
4.7
Fast mode
0.6
Fast mode+
0.26
High-speed mode
0.16
High-speed mode
Standard mode
Bus free time between a
Fast mode
stop and start condition
Fast mode +
tBUF
Standard mode
tSU;STO
Setup time for a stop
condition
4
0.6
Hold time for a start or a Fast mode
repeated start condition Fast mode+
(1)
12
ns
ns
µs
4
µs
0.26
0.16
4.7
1.3
µs
0.5
4
Fast mode
0.6
Fast mode+
0.26
High-speed mode
0.16
Fast mode
Rise time of SDA signal
µs
0.6
Standard mode
trDA
MHz
µs
Fast mode
Standard mode
tHD;STA
0.5
High-speed mode, Cb = 100 pF
Standard mode
kHz
1.7
Standard mode
Fast mode+
UNIT
1
High-speed mode, Cb = 100 pF
tLOW
MAX
µs
1000
20
Fast mode+
300
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
20
160
ns
Cb refers to the capacitance of one bus line.
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I2C Serial Bus Timing Parameters (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See (1) and Figure 1.
MIN
MAX
Standard mode
tfDA
Fall time of SDA signal
300
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
30
160
Standard mode
trCL1
Rise time of SCL signal
Rise time of SCL signal
after a repeated start
condition and after an
acknowledge bit
20
300
Fast mode+
120
High-speed mode, Cb = 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
20
160
Standard mode
tfCL
Fall time of a SCL signal
ns
1000
Fast mode
trCL
UNIT
ns
ns
300
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 10 – 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
Cb
Capacitive load for each
bus line (SCL and SDA)
tSP
Pulse width of spike
Standard mode, fast mode, and fast mode+
suppressed (SCL and
SDA spikes that are less
then the indicated width High-speed mode
are suppressed)
400
ns
pF
50
10
ns
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
tfCL
trDA
tSP
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
S
tHD;DAT
START
tSU;DAT
RS
P
S
REPEATED
START
STOP
START
Figure 1. I2C Timing
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6.7 Typical Characteristics
15
70
14
68
13
66
12
64
Input Current (PA)
Input Current (PA)
Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDO = 1 V, TA = 25°C, L = 0.47 µH
(TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF / phase, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF.
11
10
9
8
58
56
54
6
52
3
3.5
4
4.5
Input Voltage (V)
5
50
2.5
5.5
87
22
84
20
81
18
Input Current (mA)
24
78
75
72
69
10
6
VOUT_Bx = 1 V
5.5
Figure 4. Active State Current Consumption vs Input
Voltage, Regulator Enabled in PFM Mode (dual-phase)
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4
2.5
3
D422
Load = 0 mA
D102
Load = 0 mA
12
8
5
5.5
14
63
4
4.5
Input Voltage (V)
5
16
66
3.5
4
4.5
Input Voltage (V)
Figure 3. Active State Current Consumption vs Input
Voltage, One Buck Regulator Enabled in PFM Mode (singlephase)
90
3
3.5
VOUT_Bx = 1 V
Figure 2. Standby Current Consumption vs Input Voltage
60
2.5
3
D101
Regulators disabled
Input Current (µA)
60
7
5
2.5
14
62
VOUT_Bx = 1 V
3.5
4
4.5
Input Voltage (V)
5
5.5
D103
Load = 0 mA
Figure 5. Active State Current Consumption vs Input
Voltage, One Buck Regulator Enabled in Forced PWM Mode
(single-phase)
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Typical Characteristics (continued)
24
100
22
98
20
96
18
94
Input Current (PA)
Input Current (mA)
Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDO = 1 V, TA = 25°C, L = 0.47 µH
(TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF / phase, CPOL_BUCK = 22 µF, and COUT_LDO = 1 µF.
16
14
12
10
92
90
88
86
8
84
6
82
4
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
80
2.5
3
D423
VOUT_LDOx = 1 V
'
VOUT_Bx = 1 V
Load = 0 mA
Figure 6. Active State Current Consumption vs Input
Voltage, Regulator Enabled in Forced PWM Mode (dualphase)
Copyright © 2018, Texas Instruments Incorporated
3.5
4
4.5
Input Voltage (V)
5
5.5
D104
Load = 0 mA
Figure 7. Active State Current Consumption vs Input
Voltage, One LDO Regulator Enabled
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7 Detailed Description
7.1 Overview
The LP8733xx-Q1 is a high-efficiency, high-performance flexible power supply device with two step-down DC/DC
converter cores (Buck0 and Buck1) and two low-dropout (LDO) linear regulators (LDO0 and LDO1) for
automotive applications. The cores can be configured for a two single-phase output and dual-phase single output
configuration. Table 1 lists the output characteristics of the regulators.
Table 1. Supply Specification
SUPPLY
OUTPUT
VOUT RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM OUTPUT CURRENT (mA)
Buck0 (single-phase)
0.7 to 3.36
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
3000
Buck1 (single-phase)
0.7 to 3.36
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
3000
Buck0/1 (dual-phase)
0.7 to 3.36
10 (0.7 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
6000
LDO0
0.8 to 3.3
100
300
LDO1
0.8 to 3.3
100
300
The LP8733xx-Q1 also supports switching clock synchronization to an external clock (CLKIN pin). The nominal
frequency of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.
Additional features include:
• Soft-start
• Input voltage protection:
– Undervoltage lockout
– Overvoltage protection
• Output voltage monitoring and protection:
– Overvoltage monitoring
– Undervoltage monitoring
– Overload protection
• Thermal warning
• Thermal shutdown
The LP8733xx-Q1 has one dedicated general purpose digital output (GPO) signal. CLKIN pin can be
programmed as a second GPO signal (GPO2) if external clock is not needed. The output type (open-drain or
push-pull) is programmable for the GPOs.
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7.2 Functional Block Diagram
VANA
nINT
Interrupts
Buck0
ILIM Det
Pwrgood Det
Enable/
Disable,
Delay
Control
Slew-Rate
Control
EN
GPO
Overload and
SC Det
Iload ADC
Buck1
ILIM Det
SDA
SCL
Pwrgood Det
I2C
Overload and
SC Det
Iload ADC
Registers
PGOOD
OTP
EPROM
LDO0
ILIM Det
Pwrgood Det
Digital
Logic
Thermal
Monitor
UVLO
Overload
and SC Det
LDO1
SW
Reset
ILIM Det
Ref &
Bias
Oscillator
Pwrgood Det
Overload
and SC Det
CLKIN (GPO2)
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 DC/DC Converters
7.3.1.1 Overview
The LP8733xx-Q1 includes two step-down DC/DC converter cores. The cores are designed for flexibility; most of
the functions are programmable, thus giving a possibility to optimize the regulator operation for each application.
The cores can be configured either for a dual-phase single output configuration or for a single-phase dual output
configuration. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply
voltage.
The LP8733xx-Q1 has the following features:
• DVS support with programmable slew rate
• Automatic mode control based on the loading (PFM or PWM mode)
• Forced PWM mode option
• Optional external clock input to minimize crosstalk
• Optional spread-spectrum technique to reduce EMI
• Phase control for optimized EMI
• Synchronous rectification
• Current mode loop with PI compensator
• Soft start
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Feature Description (continued)
•
•
•
•
•
•
Power Good flag with maskable interrupt
Power Good signal (PGOOD) with selectable sources
Average output current sensing (for PFM entry, phase shedding/adding in dual-phase configuration, and load
current measurement)
Current balancing between the phases of the converter in dual-phase configuration
Differential voltage sensing from point of the load in dual-phase configuration
Dynamic phase shedding/adding, each output being phase shifted in dual-phase configuration
The following parameters can be programmed via registers, the default values are set by OTP bits:
• Output voltage
• Forced PWM operation
• Forced dual-phase operation (forces also the PWM operation)
• Switch current limit
• Output voltage slew rate
• Enable and disable delays
There are two modes of operation for the buck converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 600 mA or higher. When operating in PWM mode in dual-phase configuration the
phases are automatically added/shedded based on the load current level. Lighter output current loads cause the
converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is
disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels.
A block diagram of a single core is shown in Figure 8.
FB
POS
CURRENT
LIMIT
RAMP
GENERATOR
VOUT
-
GATE
CONTROL
ERROR
AMP
+
VOLTAGE
SETTING
VDAC
SLEW RATE
CONTROL
PROGRAMMABLE
PARAMETERS
+
-
VIN
+ -
HS FET
CURRENT
SENSE
POWER
GOOD
CONTROL
BLOCK
LOOP
COMP
NEG
CURRENT
LIMIT
LS FET
CURRENT
SENSE
MASTER
INTERFACE
SLAVE
INTERFACE
SW
ZERO
CROSS
DETECT
IADC
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Detailed Block Diagram Showing One Core
7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
Under heavy load conditions, the dual-phase converter switches both channel 180° apart. As a result, the dualphase converter has an effective ripple frequency two times greater than the switching frequency of a single
phase. However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this
operational inefficiency, the LP8733xx-Q1 can change the number of active phases to optimize efficiency for the
variations of the load. This is called phase adding/shedding. The concept is shown in Figure 9.
The converter can be forced to dual-phase operation by the BUCK0_FPWM_MP bit in BUCK0_CTRL_1 register.
If the regulator operates in forced dual-phase mode the forced PWM operation is automatically used. If the dualphase operation is not forced, the number of phases are added and shedded automatically to follow the required
output current.
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Feature Description (continued)
EFFICIENCY
2-PHASE
OPERATION
1-PHASE
OPERATION
BEST EFFICIENCY OBTAINED WITH
N=1
N=2
LOAD CURRENT
Figure 9. Multiphase Buck Converter Efficiency vs Number of Phases. All Converters in PWM mode.
(UPDATE) (1)
Interleaving switching action of the converters and channels in a 2-phase configuration is shown in Figure 10.
(1)
Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
IL_TOT_2PH
IL0
IL1
0
90
180
270
360
450
540
630
720
180
270
360
PHASE, DEGREES
450
540
630
720
PWM0
PWM1
SWITCHING CYCLE 360º
0
90
Figure 10. PWM Timings and Inductor Current Waveforms in 2-phase Configuration. (UPDATE)
(2)
7.3.1.3 Transition Between PWM and PFM Modes
PWM mode operation with phase-adding/shedding optimizes efficiency at mid to full load at the expense of lightload efficiency. The LP8733xx-Q1 converter operates in PWM mode at load current of about 600 mA or higher.
At lighter load current levels the device automatically switches into PFM mode for reduced current consumption
when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a
high efficiency is achieved over a wide output-load current range.
7.3.1.4 Dual-Phase Switcher Configurations
The LP8733xx-Q1 device supports the following regulator configurations:
• Single dual-phase configuration, Buck0 is master (buck0 and buck1)
• Two single-phase configuration (buck0 and buck1)
In the dual-phase configuration the control of the dual-phase regulator settings is done using the control registers
of the master buck. The following slave registers are ignored:
• BUCK1_CTRL_1, except EN_RDIS1 bit
• BUCK1_CTRL_2, except ILIM1[2:0] bits
• BUCK1_VOUT
• BUCK1_DELAY
• interrupt bits related to the slave buck, except BUCK1_ILIM_INT
(2)
20
Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
7.3.1.5 Buck Converter Load Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current
measurement sequence. The regulator is automatically forced to PWM mode for the measurement period. The
measurement sequence is 50 µs long, maximum.
LP8733xx-Q1 can be configured to give out an interrupt (I_MEAS_INT bit in INT_TOP_1 register) after the load
current measurement sequence is finished. Load current measurement interrupt can be masked with
I_MEAS_MASK bit (TOP_MASK_1 register). The measurement result can be read from registers I_LOAD_1 and
I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2
bit BUCK_LOAD_CURRENT[8] the MSB bit. The measurement result BUCK_LOAD_CURRENT[8:0] LSB is 20
mA, and maximum code value of the measurement corresponds to 10.22 A. In dual-phase configuration the
measured current is the total value of the master and slave phases.
7.3.1.6 Spread-Spectrum Mode
Radiated Energy
Power Spectrum is
Spread and Lowered
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8733xx-Q1 has register selectable spread-spectrum mode which
minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency
varies around the center frequency, reducing the EMI emissions radiated by the converter and associated
passive components and PCB traces (see Figure 11). This feature is available only when internal RC oscillator is
used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in CONFIG
register, and it affects both buck cores.
Frequency
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8733xx-Q1 spreads that energy over a large bandwidth.
Figure 11. Spread-Spectrum Modulation
7.3.2 Sync Clock Functionality
The LP8733xx-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with
the external clock. The block diagram of the clocking and PLL module is shown in Figure 12. Depending on the
EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt
is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1
register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL
register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy
limits (–30%/+10%) of the selected frequency for valid clock detection.
The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is
expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1
and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.
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Feature Description (continued)
24MHz
RC
Oscillator
Internal
24MHz
clock
CLKIN
Detector
Divider
´(;7_CLK_
)5(4´
CLKIN
1MHz
24MHz
Clock Select
Logic
PLL
´(1_3//´
1MHz
Divider
24
Figure 12. Clock and PLL Module
Table 2. PLL Operation
DEVICE
OPERATION MODE
EN_PLL
PLL AND CLOCK
DETECTOR STATE
INTERRUPT FOR
EXTERNAL CLOCK
CLOCK
STANDBY
0
Disabled
No
Internal RC
ACTIVE
0
Disabled
No
Internal RC
Automatic change to external
clock when available
Automatic change to external
clock when available
STANDBY
1
Enabled
When external clock
appears or disappears
ACTIVE
1
Enabled
When external clock
appears or disappears
7.3.3 Low-Dropout Linear Regulators (LDOs)
The LP8733xx-Q1 device includes two identical linear regulators, LDO0 and LDO1, targeting analog loads with
low noise requirements. The LDO regulators deliver 0.8-V to 3.3-V regulated voltage rails from a 2.5-V to 5.5-V
input voltage. Both regulators have dedicated inputs which can be higher or lower than the device system voltage
V(VANA) to minimize the power dissipation.
7.3.4 Power-Up
The power-up sequence for the LP8733xx-Q1 is as follows:
• VANA (and VIN_Bx) reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset
(POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before
writing or reading data to the LP8733xx-Q1.
• Device enters standby mode.
• The host can change the default register setting by I2C if needed.
• The regulators can be enabled/disabled and the GPO signals can be controlled by EN pin and by I2C
interface.
Transitions between the operating modes are shown in Modes of Operation.
7.3.5 Regulator Control
7.3.5.1 Enabling and Disabling Regulators
The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable
and disable the buck regulators:
• Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 0 in BUCKx_CTRL_1
register)
• Using EN control pin (BUCKx_EN bit is 1 AND BUCKx_EN_PIN_CTRL bit is 1)
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Similarly there are two ways to enable and disable the LDO regulators:
• Using LDOx_EN bit in LDOx_CTRL register (LDOx_EN_PIN_CTRL bit is 0 in LDOx_CTRL register)
• Using EN control pin (LDOx_EN bit is 1 AND LDOx_EN_PIN_CTRL bit is 1)
If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up
is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_STARTUP_DELAY[3:0] bits
in LDOx_DELAY register and the delay from control signal falling edge to shutdown is set by
BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_SHUTDOWN_DELAY[3:0] bits in
LDOx_DELAY register. The delays are valid only for EN signal transitions and not for control with I2C writings to
BUCKx_EN and LDOx_EN bits.
The control of the regulator (with 0-ms delays) is shown in Table 3. Dual-phase regulator is controlled with
registers of the master phase.
Table 3. Regulator Control
BUCKx_EN /
LDOx_EN
BUCKx_EN_PIN_CTRL /
LDOx_EN_PIN_CTRL
EN PIN
BUCKx OUTPUT VOLTAGE /
LDOx OUTPUT VOLTAGE
Enable/disable control with
BUCKx_EN/LDOx_EN bit
0
Don't Care
Don't Care
Disabled
1
0
Don't Care
BUCKx_VSET[7:0] / LDOx_VSET[4:0]
Enable/disable control with
EN pin
1
1
Low
Disabled
1
1
High
BUCKx_VSET[7:0] / LDOx_VSET[4:0]
The buck regulator is enabled by the EN pin or by I2C writing as shown in Figure 13. The soft-start circuit limits
the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes
slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the
0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), the
regulator is disabled, and BUCKx_SC_INT interrupt in INT_BUCK register is set. When the output voltage
reaches the Power-Good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set. The
Power-Good interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in
BUCK_MASK register. The Power-Good interrupt flag can be also generated when the output voltage becomes
invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK
register. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage: 1
means valid and 0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in PGOOD_CTRL_1 register
sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and
overvoltage detection.
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Voltage decrease because of load
Voltage
BUCKx_VSET[7:0]
Powergood
Ramp
BUCKx_CTRL_2(BUCKx_SLEW_RATE[2:0])
0.6V
0.35V
Resistive pull-down
(if enabled)
Soft start
Time
Enable
BUCK_STAT(BUCKx_STAT)
0
BUCK_STAT(BUCKx_PG_STAT)
0
1
INT_BUCK(BUCKx_PG_INT)
0
1
1
0
0
0
1
1
0 1
0
0
1
0
nINT
Powergood
interrupts
Host clears
interrupts
BUCK_MASK(BUCKx_PGF_MASK) = 0
BUCK_MASK(BUCKx_PGR_MASK) = 0
Figure 13. Buck Regulator Enable and Disable
The LDO regulator is enabled by the EN pin or by I2C writing as shown in Figure 14. The soft-start circuit limits
the in-rush current during start-up. Output voltage increase rate is less than 100 mV/μsec during soft-start. If
there is a short circuit at the output, and the output voltage does not increase above the 0.3-V level in 1 ms or
the output voltage drops below 0.3-V level during operation (for minimum of 1 ms), the regulator is disabled, and
LDOx_SC_INT interrupt in INT_LDO register is set. When the output voltage reaches the Power-Good threshold
level the LDOx_PG_INT interrupt flag in INT_LDO register is set. The Power-Good interrupt flag when reaching
valid output voltage can be masked using LDOx_PGR_MASK bit in LDO_MASK register. The Power-Good
interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid
output voltage detection is set by LDOx_PGF_MASK bit in LDO_MASK register. A LDOx_PG_STAT bit in
LDO_STAT register shows always the validity of the output voltage; 1 means valid, and 0 means invalid output
voltage. A PGOOD_WINDOW_LDO bit in PGOOD_CTRL_1 register sets the detection method for the valid LDO
output voltage, either undervoltage detection or undervoltage and overvoltage detection.
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Voltage decrease because of load
Voltage
LDOx_VSET[4:0]
Powergood
Resistive pull-down
(if enabled)
Time
Enable
LDO_STAT(LDOx_STAT)
0
LDO_STAT(LDOx_PG_STAT)
0
1
INT_LDO(LDOx_PG_INT)
0
1
1
0
0
0
1
1
0 1
0
0
1
0
nINT
LDO_MASK(LDOx_PGF_MASK) = 0
LDO_MASK(LDOx_PGR_MASK) = 0
Powergood
interrupts
Host clears
interrupts
Figure 14. LDO Regulator Enable and Disable
The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in
CONFIG register.
7.3.5.2 Changing Output Voltage
The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The
voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is
used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in BUCK0_CTRL_1
register, the regulator operates in dual-phase mode. If the dual-phase operation is not forced, the number of
phases are added and shedded automatically to follow the required slew rate. When the programmed output
voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit in
BUCKx_CTRL_1 register and by BUCK0_FPWM_MP bit.
The voltage change and Power-Good interrupts are shown in Figure 15.
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Ramp for Buck
Voltage
BUCKx_CTRL2(SLEW_RATEx[2:0])
BUCKx_VSET /
LDOx_VSET
Powergood
Powergood
Time
BUCK_STAT(BUCKx_STAT) /
LDO_STAT(LDOx_STAT)
1
BUCK_STAT(BUCKx_PG_STAT) /
LDO_STAT(LDOx_PG_STAT)
1
0
INT_BUCK(BUCKx_PG_INT) /
INT_LDO(LDOx_PG_INT)
0
1
1
0
0
1
1
0
nINT
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
BUCK_MASK(BUCKx_PGF_MASK)=0
BUCK_MASK(BUCKx_PGR_MASK)=0
LDO_MASK(LDOx_PGF_MASK)=0
LDO_MASK(LDOx_PGR_MASK)=0
Figure 15. Regulator Output Voltage Change
During an LDO voltage change the internal reference for the Power-Good detection is also changed. For this
reason the Power Good may toggle during the LDO voltage change can indicate valid output even when the
output voltage is changing. This period takes less than 100 µs and after that time the Power Good gives correct
value.
7.3.6 Enable and Disable Sequences
The LP8733xx-Q1 device supports start-up and shutdown sequencing with programmable delays for different
regulator outputs using single EN control signal. The Buck regulator is selected for delayed control with:
• BUCKx_EN = 1 in BUCKx_CTRL_1 register
• BUCKx_EN_PIN_CTRL = 1 in BUCKx_CTRL_1 register
• BUCKx_VSET[7:0] bits in BUCKx_VOUT register defines the voltage when EN pin is high
• The delay from rising edge of EN pin to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits in
BUCKx_DELAY register and
• The delay from falling edge of EN pin to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits
in BUCKx_DELAY register.
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In the same way the LDO regulator is selected for delayed control with:
• LDOx_EN = 1 in LDOx_CTRL register
• LDOx_EN_PIN_CTRL = 1 in LDOx_CTRL register
• LDOx_VSET[4:0] bits in LDOx_VOUT register defines the voltage when EN pin is high
• The delay from rising edge of EN pin to the regulator enable is set by LDOx_STARTUP_DELAY[3:0] bits in
LDOx_DELAY register and
• The delay from falling edge of EN pin to the regulator disable is set by LDOx_SHUTDOWN_DELAY[3:0] bits
in LDOx_DELAY register.
The GPO (and GPO2) digital output signals can be also controlled as a part of start-up and shutdown
sequencing with the following settings:
• GPOx_EN = 1 in GPO_CTRL register
• GPOx_EN_PIN_CTRL = 1 in GPO_CTRL register
• The delay from rising edge of EN pin to the rising edge of GPO/GPO2 signal is set by
GPOx_STARTUP_DELAY[3:0] bits in GPOx_DELAY register and
• The delay from falling edge of EN pin to the falling edge of GPO/GPO2 signal is set by
GPOx_SHUTDOWN_DELAY[3:0] bits in GPOx_DELAY register.
An example of the start-up and shutdown sequences for the buck regulators are shown in Figure 16. The start-up
and shutdown delays for the Buck0 regulator are 1 ms and 4 ms; for the Buck1 regulator start-up and shutdown
delays are 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.
Typical sequence
EN
EN_BUCK0
1ms
EN_BUCK1
4ms
3ms
1ms
Sequence with short EN low and high periods
EN
Startup cntr
0
Shutdown cntr
0
0
1
0
0
EN_BUCK0
1
2
3
1
4
5
6
0
0
1
2 0
1ms
EN_BUCK1
1
2
3
4
5
4ms
3ms
1ms
Figure 16. Start-Up and Shutdown Sequencing
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7.3.7 Device Reset Scenarios
There are three reset methods implemented on the LP8733xx-Q1:
• Software reset with SW_RESET bit in RESET register
• Undervoltage lockout (UVLO) reset from VANA supply
An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event
disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the
default values and OTP bits are loaded (see Figure 22). I2C interface is not reset during software reset.
If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately,
GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA
supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the
registers and a startup is initiated according to the register settings.
7.3.8 Diagnosis and Protection Features
The LP8733xx-Q1 is capable of providing four levels of protection features:
• Information of valid regulator output voltage which sets interrupt or PGOOD signal;
• Warnings for diagnosis which sets interrupt;
• Protection events which are disabling the regulators; and
• Faults which are causing the device to shutdown.
The LP8733xx-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT
pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the
pending interrupts are cleared.
When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in
INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is
not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded
from OTP during reset sequence.
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Table 4. Summary of Interrupt Signals
EVENT
OUTCOME
INTERRUPT BIT
INTERRUPT MASK BIT
RECOVERY/INTERRUPT
CLEAR
STATUS BIT
Buck current limit triggered
No effect
BUCK_INT
BUCKx_ILIM_INT
BUCKx_ILIM_MASK
BUCKx_ILIM_STAT
Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current
limit is active
LDO current limit triggered
No effect
LDO_INT
LDOx_ILIM_INT
LDOx_ILIM_MASK
LDOx_ILIM_STAT
Write 1 to LDOx_ILIM_INT bit
Interrupt is not cleared if current
limit is active
Buck short circuit (VVOUT < 0.35
V at 1 ms after enable) or
overload (VVOUT decreasing
below 0.35 V during operation,
1-ms debounce)
Regulator disable
BUCK_INT
BUCKx_SC_INT
N/A
N/A
Write 1 to BUCKx_SC_INT bit
LDO short circuit (VVOUT < 0.3
V at 1 ms after enable) or
overload (VVOUT decreasing
below 0.3 V during operation,
1-ms debounce)
Regulator disable
LDO_INT
LDOx_SC_INT
N/A
N/A
Write 1 to LDOx_SC_INT bit
Thermal warning
No effect
TDIE_WARN_INT
TDIE_WARN_MASK
TDIE_WARN_STAT
Write 1 to TDIE_WARN_INT bit
Interrupt is not cleared if
temperature is above thermal
warning level
Thermal shutdown
All regulators disabled
immediately and GPO
and GPO2 are set to low
TDIE_SD_INT
N/A
TDIE_SD_STAT
Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if
temperature is above thermal
shutdown level
VANA overvoltage (VANAOVP)
All regulators disabled
immediately and GPO
and GPO2 are set to low
OVP_INT
N/A
OVP_STAT
Write 1 to OVP_INT bit
Interrupt is not cleared if VANA
voltage is above VANAOVP level
Buck power good, output
voltage becomes valid
No effect
BUCK_INT
BUCKx_PG_INT
BUCKx_PGR_MASK
BUCKx_PG_STAT
Write 1 to BUCKx_PG_INT bit
Buck power good, output
voltage becomes invalid
No effect
BUCK_INT
BUCKx_PG_INT
BUCKx_PGF_MASK
BUCKx_PG_STAT
Write 1 to BUCKx_PG_INT bit
LDO Power Good, output
voltage becomes valid
No effect
LDO_INT
LDOx_PG_INT
LDOx_PGR_MASK
LDOx_PG_STAT
Write 1 to LDOx_PG_INT bit
LDO power good, output
voltage becomes invalid
No effect
LDO_INT
LDOx_PG_INT
LDOx_PGF_MASK
LDOx_PG_STAT
Write 1 to LDOx_PG_INT bit
PGOOD pin changing from
active to inactive state (1)
No effect
PGOOD_INT
PGOOD_MASK
PGOOD_STAT
Write 1 to PGOOD_INT bit
External clock appears or
disappears
No effect to regulators
SYNC_CLK_INT (2)
SYNC_CLK_MASK
SYNC_CLK_STAT
Write 1 to SYNC_CLK_INT bit
Load current measurement
ready
No effect
I_MEAS_INT
I_MEAS_MASK
N/A
Write 1 to I_MEAS_INT bit
Supply voltage VANAUVLO
triggered (VANA falling)
Immediate shutdown,
registers reset to default
values
N/A
N/A
N/A
N/A
Supply voltage VANAUVLO
triggered (VANA rising)
Startup, registers reset to
default values and OTP
bits loaded
RESET_REG_INT
RESET_REG_MASK
N/A
Write 1 to RESET_REG_INT bit
Software requested reset
Immediate shutdown
followed by power up,
registers reset to default
values
RESET_REG_INT
RESET_REG_MASK
N/A
Write 1 to RESET_REG_INT bit
(1)
(2)
PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD
pin polarity, not Power Good and PGOOD_INT interrupt polarity.
Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.
7.3.8.1 Power-Good Information (PGOOD pin)
In addition to the interrupt-based indication of the current limit and the Power-Good level the LP8733xx-Q1
device supports monitoring with PGOOD signal:
• Regulator output voltage,
• Input supply overvoltage,
• Thermal warning and
• Thermal shutdown.
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Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This
selection is individual for both buck regulators (only master buck in dual-phase configuration) and both LDO
regulators and is set by EN_PGOOD_BUCKx bits in PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in
PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is automatically masked to prevent it
forcing PGOOD inactive. A thermal warning can be also selected for PGOOD indication with
EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring from all the output rails, thermal warning
(TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal shutdown interrupt (TDIE_SD_INT)
are combined, and PGOOD pin is active only if all the selected sources shows a valid status.
The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in
PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and
overvoltage are monitored.
The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD
bits in the PGOOD_CTRL_1 register.
PGOOD is only active or asserted when all enabled power resource output voltages are within specified
tolerance for each requested/programmed output voltage.
PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance
for each requested/programmed output voltage.
The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.
7.3.8.1.1 PGOOD Pin Gated mode
The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2
register.
For the gated mode of operation, PGOOD behaves as follows:
• PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.
• PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status
indication.
• During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an
800-µs gated time period. It typically remains active or asserted for normal conditions.
• During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to
inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.
• Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown
sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit
configuration provides a smart PORz function for processor that eliminates the need for additional
components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.
The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the
PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and
TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the
corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by
toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 17.
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V(VANA)
VANA_UVLO
State
Shut
down
Read
OTP
Standby
Active
PGOOD pin
Clear fault
EN pin
4ms
Buck internal enable
800us Timer
VOUT (Buck1)
Buck1 internal powergood
2ms
LDO0 internal enable
800us Timer
VOUT (LDO0)
LDO0 internal powergood
Figure 17. PGOOD Pin Operation in Gated Mode
7.3.8.1.2 PGOOD Pin Continuous Mode
The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in
PGOOD_CTRL_2 register.
For the continuous mode of operation, PGOOD behaves as follows:
• PGOOD is set to active or asserted state upon exiting OTP configuration.
• PGOOD is set to inactive or de-asserted as soon as regulator is enabled.
• PGOOD status begins indicating output voltage regulation status immediately and continuously.
• During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or deasserted while output voltages are outside of regulation ranges and active or asserted when inside of
regulation ranges.
The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing
1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are
cleared by clearing the interrupt bits.
When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.
When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the
invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows
all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 18
and an example of operation is shown in Figure 19.
The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs
are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is
selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.
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EN_PGOOD
_BUCK0
Buck0
Power Good
EN_PGOOD
_BUCK1
Buck1
Power Good
EN_PGOOD
_LDO0
Power Good
LDO0
PGOOD
Active high
EN_PGOOD
_LDO1
LDO1
Power Good
EN_PGOOD
_TWARN
TDIE_WARN_STAT
TDIE_SD_INT
OVP_INT
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Figure 18. PGOOD Block Diagram (Continuous Mode)
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V(VANA)
VANA_UVLO
State
Shut
down
Read
OTP
Standby
Active
PGOOD pin
EN pin
Buck1 internal enable
4ms
VOUT (Buck1)
Buck1 internal powergood
LDO0 internal enable
2ms
VOUT (LDO0)
LDO0 internal powergood
Figure 19. PGOOD Pin Operation in Continuous Mode
7.3.8.2 Warnings for Diagnosis (Interrupt)
7.3.8.2.1 Output Power Limit
The Buck regulators have programmable output peak current limits. The limits are individually programmed for
both regulators with BUCKx_ILIM[2:0] bits in BUCKx_CTRL_2 register. The current limit settings of master and
slave regulators used for the same output voltage rail must be identical. If the load current is increased so that
the current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation).
The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20
µs, the LP8733xx-Q1 device sets the BUCKx_ILIM_INT bit in INT_BUCK register and pulls the nINT pin low. The
host processor can read BUCKx_ILIM_STAT bits in BUCK_STAT register to see if the regulator is still in peak
current regulation mode and the interrupt is cleared by writing 1 to BUCKx_ILIM_INT bit. The current limit
interrupt can be masked by setting BUCKx_ILIM_MASK bit in BUCK_MASK register to 1. The Buck overload
situation is shown in Figure 20.
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New startup if
enable is valid
Regulator disabled
by digital
Voltage
VOUTx
350mV
Resistive
pull-down
1ms
Time
Current
ILIMx
Time
20Ps
INT_BUCK(BUCKx_ILIM_INT)
0
1
0
INT_BUCK(BUCKx_SC_INT)
0
1
0
BUCK_STAT(BUCKx_STAT)
1
0
1
nINT
Host clearing the interrupt by writing to flags
Figure 20. Buck Regulator Overload Situation
The LDO regulators include also current limit circuitry. If the load current is increased so that the current limit is
triggered, the regulator limits the output current to the threshold level. The voltage may decrease if the load
current is higher than the current limit. If the current regulation continues for 20 µs, the LP8733xx-Q1 device sets
the LDOx_ILIM_INT bit in INT_LDO register and pulls the nINT pin low. The host processor can read
LDOx_ILIM_STAT bits in LDO_STAT register to see if the regulator is still in current regulation mode and the
interrupt is cleared by writing 1 to LDOx_ILIM_INT bit. The current limit interrupt can be masked by setting
LDOx_ILIM_MASK bit in LDO_MASK register to 1. The LDO overload situation is shown in Figure 21.
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New startup if
enable is valid
Regulator disabled
by digital
Voltage
VOUTx
300 mV
Resistive
pull-down
1ms
Time
Current
ILIMx
Time
20Ps
INT_LDO(LDOx_ILIM_INT)
0
1
0
INT_LDO(LDOx_SC_INT)
0
1
0
LDO_STAT(LDOx_STAT)
1
0
1
nINT
Host clearing the interrupt by writing to flags
Figure 21. LDO Regulator Overload Situation
7.3.8.2.2 Thermal Warning
The LP8733xx-Q1 device includes a protection feature against overtemperature by setting an interrupt for host
processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit in CONFIG
register.
If the LP8733xx-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN_INT
bit in INT_TOP_1 register and pulls the nINT pin low. The status of the thermal warning can be read from
TDIE_WARN_STAT bit in TOP_STAT register, and the interrupt is cleared by writing 1 to TDIE_WARN_INT bit.
The thermal warning interrupt can be masked by setting TDIE_WARN_MASK bit in TOP_MASK_1 register to 1.
7.3.8.3 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, input overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and
the output pulldown resistor is enabled (if enabled with BUCKx_RDIS_EN bit in BUCKx_CTRL_1 register and
LDOx_RDIS_EN bit in LDOx_CTRL register). The turnoff time of the output voltage is defined by the output
capacitance, load current, and the resistance of the integrated pull-down resistor. The pulldown resistors are
active as long as VANA voltage is above approximately a 1.2-V level.
7.3.8.3.1
Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP8733xx-Q1 to protect itself and external components against short
circuit at the output or against overload during start-up. For buck and LDO regulators the fault thresholds are
about 350 mV (buck) and 300 mV (LDO), and the protection is triggered and the regulator is disabled if the
output voltage is below the threshold level 1 ms after the regulator is enabled.
In a similar way the overload situation is protected during normal operation. If the output voltage falls below 0.35
V and 0.3 V and remains below the threshold level for 1 ms the regulator is disabled.
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In buck regulator short-circuit and overload situations the BUCKx_SC_INT bit in INT_BUCK register and the
INT_BUCKx bit in INT_TOP_1 register are set to 1, the BUCKx_STAT bit in BUCK_STAT register is set to 0, and
the nINT signal is pulled low. In LDO regulator short-circuit and overload situations the LDOx_SC_INT bit in
INT_LDO register and the INT_LDOx bit in INT_TOP_1 register are set to 1, the LDOx_STAT bit in LDO_STAT
register is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the
BUCKx_SC_INT or to the LDOx_SC_INT bit. Upon clearing the interrupt the regulator makes a new start-up
attempt if the regulator is in an enabled state.
7.3.8.3.2 Overvoltage Protection
The LP8733xx-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes.
If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without
switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled
(BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register and LDOx_RDIS_EN = 1 in LDOx_CTRL register), GPOs are
set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and
BUCKx_STAT bit in BUCK_STAT register and LDOx_STAT bit in LDO_STAT register are set to 0. The host
processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection
level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in
TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection
level or the overvoltage interrupt is pending.
7.3.8.3.3 Thermal Shutdown
The LP8733xx-Q1 has an overtemperature protection function that operates to protect itself from short-term
misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are
disabled immediately (without switching ramp, no shutdown delays), the TDIE_SD_INT bit in INT_TOP_1 register
is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT is cleared by writing 1 to the
TDIE_SD_INT bit. If the temperature is above thermal shutdown level the interrupt is not cleared. The host can
read the status of the thermal shutdown from the TDIE_SD_STAT bit in TOP_STAT register. Regulators cannot
be enabled as long as the junction temperature is above thermal shutdown level or the thermal shutdown
interrupt is pending.
7.3.8.4 Fault (Power Down)
7.3.8.4.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck and LDO regulators are disabled
immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the
pulldown resistor, and the LP8733xx-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO
threshold level, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the
RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The
host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the
RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been
below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the
registers are reset to default values.
7.3.9 Operation of the GPO Signals
The LP8733xx-Q1 device supports up to 2 general purpose output signals, GPO and GPO2. The GPO2 signal is
multiplexed with CLKIN signal. The selection between CLKIN and GPO2 pin function is set with CLKIN_PIN_SEL
bit in CONFIG register.
The GPO pins are configured with the following bits:
• GPOx_OD bit in GPO_CTRL register defines the type of the output, either push-pull with V(VANA) level or open
drain
The logic level of the GPOx pin is set by EN_GPOx bit in GPO_CTRL register.
The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence
with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown
sequence control see Enable and Disable Sequences.
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7.3.10 Digital Signal Filtering
The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
Table 5. Digital Signal Filtering
EVENT
SIGNAL/SUPPLY
Enable/disable for BUCKx,
LDOx or GPOx
EN
RISING EDGE
FALLING EDGE
LENGTH
LENGTH
3 µs
(1)
3 µs (1)
VANA UVLO
VANA
3 µs (1) (VANA voltage rising)
Immediate (VANA voltage falling)
VANA overvoltage
VANA
1 µs (VANA voltage rising)
20 µs (VANA voltage falling)
TDIE_WARN_INT
20 µs
20 µs
TDIE_SD_INT
20 µs
20 µs
Thermal warning
Thermal shutdown
Current limit
VOUTx_ILIM
20 µs
20 µs
Overload
FB_B0, FB_B1,
VOUT_LDO0, VOUT_LDO1
1 ms
N/V
PGOOD pin and power-good
interrupt
PGOOD / FB_B0, FB_B1,
VOUT_LDO0, VOUT_LDO1
6 µs
6 µs
(1)
No glitch filtering, only synchronization.
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7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN: The V(VANA) voltage is below VANAUVLO threshold level. All switch, reference, control, and bias
circuitry of the LP8733xx-Q1 device are turned off.
READ OTP: The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the
reference and bias circuitry of the LP8733xx-Q1 are enabled. The OTP bits are loaded to registers.
STANDBY: The main supply voltage V(VANA) is above VANAUVLO level. The regulators are disabled, and the
reference, control and bias circuitry of the LP8733xx-Q1 are enabled. All registers can be read or
written by the host processor via the system serial interface. The regulators can be enabled if
needed.
ACTIVE:
The main supply voltage V(VANA) is above VANAUVLO level. At least one regulator is enabled. All
registers can be read or written by the host processor via the system serial interface.
The operating modes and transitions between the modes are shown in Figure 22.
SHUTDOWN
V(VANA) < VANAUVLO
FROM ANY STATE
EXCEPT SHUTDOWN
V(VANA) > VANAUVLO
READ
OTP
REG
RESET
STANDBY
2
I C RESET
REGULATOR
ENABLED
REGULATOR(S)
DISABLED
ACTIVE
Figure 22. Device Operation Modes
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected
to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed on the line and
remain HIGH even when the bus is idle. The LP8733xx-Q1 supports standard mode (100 kHz), fast mode (400
kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 23. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP8733xx-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while
SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C
master always generates the START and STOP conditions.
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 24. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 25 shows the
SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.
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Programming (continued)
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
trDA
tSP
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
START
RS
P
S
REPEATED
START
STOP
START
Figure 25. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8733xx-Q1
pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8733xx-Q1 generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
NOTE
If the V(VANA) voltage is below VANAUVLO threshold level during I2C communication the
LP8733xx-Q1 device does not drive SDA line. The ACK signal and data transfer to the
master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
START
MSB Chip Address LSB
ACK from slave
W ACK MSB Register Address LSB ACK
MSB
Data LSB
ACK STOP
W ACK
address 0x40 data
ACK STOP
SCL
SDA
START
id = 0x60
address = 0x40
ACK
Figure 26. Write Cycle (w = write; SDA = 0). Example Device Address = 0x60
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Programming (continued)
ACK from slave
START
MSB Chip Address LSB
W
id = 0x60
W
ACK from slave
MSB Register Address LSB
REPEATED START
ACK from slave Data from slave NACK from master
RS
MSB Chip Address LSB
R
RS
id = 0x60
R
MSB
Data
LSB
STOP
SCL
SDA
START
address = 0x3F
ACK
ACK
address 0x3F data
ACK
NACK
STOP
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 27. Read Cycle (r = read; SDA = 1). Example Device Address = 0x60
7.5.1.4 I2C-Compatible Chip Address
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data is written. The third byte contains the data for the selected register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
Here in an example with device address of 1100000Bin = 60Hex.
Figure 28. Device Address Example
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP8733xx-Q1, the internal address index counter is incremented by one and the next
register is written. Table 6 shows writing sequence to two consecutive registers. Note that auto-increment feature
does not work for read.
Table 6. Auto-Increment Example
MASTER
START
ACTION
DEVICE
ADDRES WRITE
S=X
LP8733x
x-Q1
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REGISTER
ADDRESS
ACK
DATA
ACK
DATA
ACK
STOP
ACK
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7.6 Register Maps
7.6.1 Register Descriptions
The LP8733xx-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers,
their addresses and their abbreviations are listed in Table 7. A more detailed description is given in the
DEV_REV to I_LOAD_1 sections.
NOTE
This register map describes the default values for bits that are not read from OTP
memory. The orderable code and the default register bit values are defined in part-number
specific Technical Reference Manuals.
Table 7. Summary of LP8733xx-Q1 Control Registers
42
Addr
Register
Read /
Write
0x00
DEV_REV
R
0x01
OTP_REV
R
0x02
BUCK0_
CTRL_1
R/W
0x03
BUCK0_
CTRL_2
R/W
0x04
BUCK1_
CTRL_1
R/W
0x05
BUCK1_
CTRL_2
R/W
0x06
BUCK0_
VOUT
R/W
BUCK0_VSET[7:0]
0x07
BUCK1_
VOUT
R/W
BUCK1_VSET[7:0]
0x08
LDO0_
CTRL
R/W
Reserved
LDO0_RDIS
_EN
LDO0_
EN_PIN_CT
RL
LDO0_EN
0x09
LDO1_
CTRL
R/W
Reserved
LDO1_RDIS
_EN
LDO1_
EN_PIN_CT
RL
LDO1_EN
0x0A
LDO0_
VOUT
R/W
Reserved
LDO0_VSET[4:0]
0x0B
LDO1_
VOUT
R/W
Reserved
LDO1_VSET[4:0]
0x0C
BUCK0_
DELAY
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
0x0D
BUCK1_
DELAY
R/W
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
0x0E
LDO0_
DELAY
R/W
LDO0_SHUTDOWN_DELAY[3:0]
LDO0_STARTUP_DELAY[3:0]
0x0F
LDO1_
DELAY
R/W
LDO1_SHUTDOWN_DELAY[3:0]
LDO1_STARTUP_DELAY[3:0]
0x10
GPO_
DELAY
R/W
GPO_SHUTDOWN_DELAY[3:0]
GPO_STARTUP_DELAY[3:0]
0x11
GPO2_
DELAY
R/W
GPO2_SHUTDOWN_DELAY[3:0]
GPO2_STARTUP_DELAY[3:0]
0x12
GPO_
CTRL
R/W
Reserved
GPO2_OD
GPO2_
EN_PIN_CT
RL
GPO2_EN
Reserved
GPO_OD
GPO_
EN_PIN_CT
RL
GPO_EN
0x13
CONFIG
R/W
Reserved
STARTUP_
DELAY_SE
L
SHUTDOW
N_DELAY_
SEL
CLKIN_PIN
_SEL
CLKIN_PD
EN_PD
TDIE
_WARN
_LEVEL
EN_
SPREAD
_SPEC
0x14
PLL_CTRL
R/W
Reserved
EN_PLL
Reserved
D7
D6
D5
D4
D3
DEVICE_ID[1:0]
D2
D1
D0
Reserved
OTP_ID[7:0]
BUCK0_FP
WM_MP
Reserved
Reserved
BUCK0_ILIM[2:0]
Reserved
BUCK0_
BUCK0_RDI
EN_PIN_CT
S_EN
RL
BUCK0_EN
BUCK0_SLEW_RATE[2:0]
BUCK1_FP
WM
Reserved
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BUCK0_FP
WM
BUCK1_ILIM[2:0]
BUCK1_
BUCK1_RDI
EN_PIN_CT
S_EN
RL
BUCK1_EN
BUCK1_SLEW_RATE[2:0]
EXT_CLK_FREQ[4:0]
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Register Maps (continued)
Table 7. Summary of LP8733xx-Q1 Control Registers (continued)
Addr
Register
Read /
Write
D7
D6
D5
0x15
PGOOD_CT
RL_1
R/W
PGOOD_P
OL
PGOOD_O
D
PGOOD_WI
NDOW_LD
O
PGOOD_WI
EN_PGOOD EN_PGOOD EN_PGOOD EN_PGOOD
NDOW_BU
_LDO1
_LDO0
_BUCK1
_BUCK0
CK
0x16
PGOOD_CT
RL_2
R/W
Reserved
EN_PGOOD
_TWARN
PG_FAULT
_GATES_P
GOOD
PGOOD_M
ODE
0x17
PG_FAULT
R
PG_FAULT
_LDO0
PG_FAULT
_BUCK1
PG_FAULT
_BUCK0
0x18
RESET
R/W
0x19
INT_TOP_1
R/W
0x1A
INT_TOP_2
R/W
0x1B
INT_BUCK
R/W
Reserved
BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
Reserved
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
0x1C
INT_LDO
R/W
Reserved
LDO1_
PG_INT
LDO1_
SC_INT
LDO1_
ILIM_INT
Reserved
LDO0_
PG_INT
LDO0_
SC_INT
LDO0_
ILIM_INT
0x1D
TOP_
STAT
R
PGOOD_ST
AT
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_
WARN_
STAT
OVP_
STAT
Reserved
0x1E
BUCK_STA
T
R
BUCK1_
STAT
BUCK1_
PG_STAT
Reserved
BUCK1_
ILIM_STAT
BUCK0_
STAT
BUCK0_
PG_STAT
Reserved
BUCK0_
ILIM_STAT
0x1F
LDO_STAT
R
LDO1_
STAT
LDO1_
PG_STAT
Reserved
LDO1_
ILIM_STAT
LDO0_
STAT
LDO0_
PG_STAT
Reserved
LDO0_
ILIM_STAT
0x20
TOP_
MASK_1
R/W
PGOOD_
INT_MASK
SYNC_CLK
_MASK
Reserved
TDIE_WAR
N_MASK
Reserved
I_MEAS_
MASK
0x21
TOP_
MASK_2
R/W
0x22
BUCK_MAS
K
R/W
BUCK1_PG
F_MASK
BUCK1_PG
R_MASK
Reserved
BUCK1_
ILIM_
MASK
BUCK0_PG
F_MASK
BUCK0_PG
R_MASK
Reserved
BUCK0_
ILIM_
MASK
0x23
LDO_MASK
R/W
LDO1_PGF
_MASK
LDO1_PGR
_MASK
Reserved
LDO1_
ILIM_
MASK
LDO0_PGF
_MASK
LDO0_PGR
_MASK
Reserved
LDO0_
ILIM_
MASK
0x24
SEL_I_
LOAD
R/W
Reserved
LOAD_CUR
RENT_
BUCK_SEL
ECT
0x25
I_LOAD_2
R
Reserved
BUCK_LOA
D_CURREN
T[8]
0x26
I_LOAD_1
R
D4
D3
D2
PG_FAULT
_LDO1
Reserved
D1
SW_
RESET
Reserved
PGOOD_
INT
INT_
LDO
INT_
BUCK
SYNC_
CLK_INT
TDIE_SD_I
NT
TDIE_
WARN_INT
OVP_INT
Reserved
RESET_
REG_MASK
Reserved
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I_MEAS_
INT
RESET_
REG_INT
Reserved
Reserved
D0
BUCK_LOAD_CURRENT[7:0]
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7.6.1.1 DEV_REV
Address: 0x00
D7
D6
D5
D4
D3
DEVICE_ID[1:0]
D2
D1
D0
D1
D0
Reserved
Bits
Field
Type
Default
7:6
DEVICE_ID[1:0]
R
X
5:0
Reserved
R
00 0010
Description
Device specific ID code.
7.6.1.2 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
OTP_ID[7:0]
Bits
Field
Type
Default
7:0
OTP_ID[7:0]
R
X
Description
Identification Code of the OTP EPROM Version.
7.6.1.3 BUCK0_CTRL_1
Address: 0x02
D7
D6
D5
D4
Reserved
D3
D2
BUCK0_FPWM BUCK0_FPWM BUCK0_RDIS_
_MP
EN
D1
D0
BUCK0_EN_PI
N_CTRL
BUCK0_EN
Bits
Field
Type
Default
7:5
Reserved
R/W
000
Description
4
BUCK0_FPWM
_MP
R/W
X
Forces the Buck0 regulator to operate always in multi-phase and forced PWM
operation mode:
0 - Automatic phase adding and shedding.
1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration.
3
BUCK0_FPWM
R/W
X
Buck0 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
2
BUCK0_RDIS_EN
R/W
1
Enable output discharge resistor (RDIS_Bx) when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
BUCK0_EN_PIN
_CTRL
R/W
X
Enable control for Buck0:
0 - only BUCK0_EN bit controls Buck0
1 - BUCK0_EN bit AND EN pin control Buck0.
0
BUCK0_EN
R/W
X
Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.
7.6.1.4 BUCK0_CTRL_2
Address: 0x03
D7
D6
Reserved
44
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D5
D4
BUCK0_ILIM[2:0]
D3
D2
D1
D0
BUCK0_SLEW_RATE[2:0]
Copyright © 2018, Texas Instruments Incorporated
LP8733-Q1
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SNVSB64 – SEPTEMBER 2018
Bits
Field
Type
Default
7:6
Reserved
R/W
00
Description
5:3
BUCK0_ILIM[2:0]
R/W
X
Sets the switch current limit of Buck0. Can be programmed at any time during
operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0
BUCK0_SLEW_RA
TE[2:0]
R/W
X
Sets the output voltage slew rate for Buck0 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs
7.6.1.5 BUCK1_CTRL_1
Address: 0x04
D7
D6
D5
D4
Reserved
D3
D2
BUCK1_FPWM BUCK1_RDIS_
EN
D1
D0
BUCK1_EN_PI
N_CTRL
BUCK1_EN
Bits
Field
Type
Default
7:4
Reserved
R/W
0000
Description
3
BUCK1_FPWM
R/W
X
Buck1 mode selection:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation.
2
BUCK1_RDIS_EN
R/W
1
Enable output discharge resistor (RDIS_Bx) when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
BUCK1_EN_PIN
_CTRL
R/W
X
Enable control for Buck1:
0 - only BUCK1_EN bit controls Buck1
1 - BUCK1_EN bit AND EN pin control Buck1.
0
BUCK1_EN
R/W
X
Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.
7.6.1.6 BUCK1_CTRL_2
Address: 0x05
D7
D6
D5
Reserved
Copyright © 2018, Texas Instruments Incorporated
D4
BUCK1_ILIM[2:0]
D3
D2
D1
D0
BUCK1_SLEW_RATE[2:0]
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Bits
Field
Type
Default
7:6
Reserved
R/W
00
Description
5:3
BUCK1_ILIM[2:0]
R/W
X
Sets the switch current limit of Buck1. Can be programmed at any time during
operation:
0x0 - 1.5 A
0x1 - 2.0 A
0x2 - 2.5 A
0x3 - 3.0 A
0x4 - 3.5 A
0x5 - 4.0 A
0x6 - Reserved
0x7 - Reserved
2:0
BUCK1_SLEW_RA
TE[2:0]
R/W
X
Sets the output voltage slew rate for Buck1 regulator (rising and falling edges):
0x0 - Reserved
0x1 - Reserved
0x2 - 10 mV/µs
0x3 - 7.5 mV/µs
0x4 - 3.8 mV/µs
0x5 - 1.9 mV/µs
0x6 - 0.94 mV/µs
0x7 - 0.47 mV/µs
7.6.1.7 BUCK0_VOUT
Address: 0x06
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK0_VSET[7:0]
R/W
X
Description
Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
7.6.1.8 BUCK1_VOUT
Address: 0x07
D7
D6
D5
D4
D3
D2
BUCK1_VSET[7:0]
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Bits
Field
Type
Default
7:0
BUCK1_VSET[7:0]
R/W
X
Description
Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00 ... 0x13
0.7 V - 0.73 V, 10 mV steps
0x14 - 0.7V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
7.6.1.9 LDO0_CTRL
Address: 0x08
D7
D6
D5
D4
D3
Reserved
Bits
D2
D1
D0
LDO0_RDIS_E
N
LDO0_EN_PIN
_CTRL
LDO0_EN
Field
Type
Default
Description
7:3
Reserved
R/W
0 0000
2
LDO0_RDIS_EN
R/W
1
Enable output discharge resistor (RDIS_LDOx) when LDO0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
LDO0_EN_PIN
_CTRL
R/W
X
Enable control for LDO0:
0 - only LDO0_EN bit controls LDO0
1 - LDO0_EN bit AND EN pin control LDO0.
0
LDO0_EN
R/W
X
Enable LDO0 regulator:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.
7.6.1.10 LDO1_CTRL
Address: 0x09
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
LDO1_RDIS_E
N
LDO1_EN_PIN
_CTRL
LDO1_EN
Bits
Field
Type
Default
7:3
Reserved
R/W
0 0000
2
LDO1_RDIS_EN
R/W
1
Enable output discharge resistor (RDIS_LDOx) when LDO1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
1
LDO1_EN_PIN
_CTRL
R/W
X
Enable control for LDO1:
0 - only LDO1_EN bit controls LDO1
1 - LDO1_EN bit AND EN pin control LDO1.
0
LDO1_EN
R/W
X
Enable LDO1 regulator:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.
Copyright © 2018, Texas Instruments Incorporated
Description
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7.6.1.11 LDO0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
D1
D0
D1
D0
LDO0_VSET[4:0]
Bits
Field
Type
Default
7:5
Reserved
R/W
000
4:0
LDO0_VSET[4:0]
R/W
X
Description
Sets the output voltage of LDO0 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F
7.6.1.12 LDO1_VOUT
Address: 0x0B
D7
D6
D5
D4
D3
Reserved
D2
LDO1_VSET[4:0]
Bits
Field
Type
Default
7:5
Reserved
R/W
000
4:0
LDO1_VSET[4:0]
R/W
X
Description
Sets the output voltage of LDO1 regulator
0.8 V - 3.3 V, 100 mV steps
0x00 - 0.8V
...
0x19 - 3.3 V
Reserved, DO NOT USE
0x1A ... 0x1F
7.6.1.13 BUCK0_DELAY
Address: 0x0C
D7
D6
D5
D4
D3
BUCK0_SHUTDOWN_DELAY[3:0]
D2
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of Buck0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of Buck0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.14 BUCK1_DELAY
Address: 0x0D
D7
D6
D5
BUCK1_SHUTDOWN_DELAY[3:0]
48
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D4
D3
D2
D1
D0
BUCK1_STARTUP_DELAY[3:0]
Copyright © 2018, Texas Instruments Incorporated
LP8733-Q1
www.ti.com
SNVSB64 – SEPTEMBER 2018
Bits
Field
Type
Default
7:4
BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of Buck1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
Description
3:0
BUCK1_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of Buck1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.15 LDO0_DELAY
Address: 0x0E
D7
D6
D5
D4
D3
LDO0_SHUTDOWN_DELAY[3:0]
D2
D1
D0
LDO0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
LDO0_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of LDO0 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
Description
3:0
LDO0_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of LDO0 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.16 LDO1_DELAY
Address: 0x0F
D7
D6
D5
D4
D3
LDO1_SHUTDOWN_DELAY[3:0]
D2
D1
D0
LDO1_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
LDO1_
SHUTDOWN_
DELAY[3:0]
R/W
X
Shutdown delay of LDO1 from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
Description
3:0
LDO1_
STARTUP_
DELAY[3:0]
R/W
X
Startup delay of LDO1 from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.17 GPO_DELAY
Address: 0x10
D7
D6
D5
D4
GPO_SHUTDOWN_DELAY[3:0]
Bits
Field
Type
Default
7:4
GPO_
SHUTDOWN_
DELAY[3:0]
R/W
X
Copyright © 2018, Texas Instruments Incorporated
D3
D2
D1
D0
GPO_STARTUP_DELAY[3:0]
Description
Delay for GPO falling edge from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
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Bits
Field
Type
Default
3:0
GPO_
STARTUP_
DELAY[3:0]
R/W
X
Description
Delay for GPO rising edge from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.18 GPO2_DELAY
Address: 0x11
D7
D6
D5
D4
D3
GPO2_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPO2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
GPO2_
SHUTDOWN_
DELAY[3:0]
R/W
X
Delay for GPO2 falling edge from falling edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if SHUTDOWN_DELAY_SEL=1 in CONFIG register)
Description
3:0
GPO2_
STARTUP_
DELAY[3:0]
R/W
X
Delay for GPO2 rising edge from rising edge of EN signal:
0x0 - 0 ms
0x1 - 0.5 ms (1 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
...
0xF - 7.5 ms (15 ms if STARTUP_DELAY_SEL=1 in CONFIG register)
7.6.1.19 GPO_CTRL
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPO2_OD
GPO2_EN_PIN
_CTRL
GPO2_EN
Reserved
GPO_OD
GPO_EN_PIN_
CTRL
GPO_EN
Bits
Field
Type
Default
7
Reserved
R
0
6
GP02_OD
R/W
X
GPO2 signal type when configured as General Purpose Output (CLKIN pin):
0 - Push-pull output (VANA level)
1 - Open-drain output
5
GPO2_EN_PIN_C
TRL
R/W
X
Control for GPO2:
0 - Only GPO2_EN bit controls GPO2
1 - GPO2_EN bit AND EN pin control GPO2.
4
GPO2_EN
R/W
X
Output level of GPO2 signal (when configured as General Purpose Output):
0 - Logic low level
1 - Logic high level
3
Reserved
R
0
2
GPO_OD
R/W
X
GPO signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
1
GPO_EN_PIN_CT
RL
R/W
X
Control for GPO:
0 - Only GPO_EN bit controls GPO
1 - GPO_EN bit AND EN pin control GPO.
0
GPO_EN
R/W
X
Output level of GPO signal:
0 - Logic low level
1 - Logic high level
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7.6.1.20 CONFIG
Address: 0x13
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
STARTUP_DE
LAY_SEL
SHUTDOWN_
DELAY_SEL
CLKIN_PIN_SE
L
CLKIN_PD
EN2_PD
TDIE_WARN_
LEVEL
EN_SPREAD
_SPEC
Bits
Field
Type
Default
Description
7
Reserved
R/W
0
6
STARTUP_DELAY
_SEL
R/W
X
Startup delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
5
SHUTDOWN_DEL
AY_SEL
R/W
X
Shutdown delay range from EN signals.
0 - 0 ms - 7.5 ms with 0.5 ms steps
1 - 0 ms - 15 ms with 1 ms steps
4
CLKIN_PIN_SEL
R/W
X
CLKIN pin function:
0 - GPO2
1 - CLKIN
3
CLKIN_PD
R/W
X
Selects the pull down resistor on the CLKIN input pin. (valid also when selected as
GPO2)
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
2
EN_PD
R/W
X
Selects the pull down resistor on the EN input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
1
TDIE_WARN_
LEVEL
R/W
X
Thermal warning threshold level.
0 - 125°C
1 - 137°C.
0
EN_SPREAD
_SPEC
R/W
X
Enable spread spectrum feature:
0 - Disabled
1 - Enabled
7.6.1.21 PLL_CTRL
Address: 0x14
D7
D6
D5
Reserved
EN_PLL
Reserved
D4
D3
D2
D1
D0
EXT_CLK_FREQ[4:0]
Bits
Field
Type
Default
7
Reserved
R/W
0
6
EN_PLL
R/W
X
Selection of external clock and PLL operation:
0 - Forced to internal RC oscillator. PLL disabled.
1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use
when available, interrupt generated if external clock appears or disappears.
5
Reserved
R/W
0
This bit must be set to '0'.
4:0
EXT_CLK_FREQ[4
:0]
R/W
X
Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See electrical specification for input clock frequency tolerance.
Copyright © 2018, Texas Instruments Incorporated
Description
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7.6.1.22 PGOOD_CTRL_1
Address: 0x15
D7
D6
PGOOD_POL
PGOOD_OD
D5
D4
D3
PGOOD_
PGOOD_
EN_PGOOD_L
WINDOW_LDO WINDOW_BUC
DO1
K
D2
EN_PGOOD_L
DO0
D1
D0
EN_PGOOD_B EN_PGOOD_B
UCK1
UCK0
Bits
Field
Type
Default
7
PGOOD_POL
R/W
X
PGOOD signal polarity.
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
Description
6
PGOOD_OD
R/W
X
PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
5
PGOOD_
WINDOW_LDO
R/W
X
LDO Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
4
PGOOD_
WINDOW_BUCK
R/W
X
Buck Output voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring.
3
EN_PGOOD_LDO
1
R/W
X
PGOOD signal source control from LDO1
0 - LDO1 is not monitored
1 - LDO1 Power-Good threshold voltage monitored
2
EN_PGOOD_LDO
0
R/W
X
PGOOD signal source control from LDO0
0 - LDO0 is not monitored
1 - LDO0 Power-Good threshold voltage monitored
1
EN_PGOOD_BUC
K1
R/W
X
PGOOD signal source control from Buck1
0 - Buck1 is not monitored
1 - Buck1 Power-Good threshold voltage monitored
0
EN_PGOOD_BUC
K0
R/W
X
PGOOD signal source control from Buck0
0 - Buck0 is not monitored
1 - Buck0 Power-Good threshold voltage monitored
7.6.1.23 PGOOD_CTRL_2
Address: 0x16
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
EN_PGOOD_T
WARN
PG_FAULT_G
ATES_PGOOD
PGOOD_MOD
E
Bits
Field
Type
Default
7:3
Reserved
R/W
0 0000
Description
2
EN_PGOOD_TWA
RN
R/W
X
Thermal warning control for PGOOD signal:
0 - Thermal warning not monitored
1 - PGOOD inactive if thermal warning flag is active.
1
PG_FAULT_GATE
S_PGOOD
R/W
X
Type of operation for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PG_FAULT register, inactive when at least one PG_FAULT_x
bit is inactive.
0
PGOOD_MODE
R/W
X
Operating mode for PGOOD signal:
0 - Gated mode
1 - Continuous mode
7.6.1.24 PG_FAULT
Address: 0x17
D7
D6
D5
Reserved
52
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D4
D3
D2
D1
D0
PG_FAULT_LD PG_FAULT_LD PG_FAULT_BU PG_FAULT_BU
O1
O0
CK1
CK0
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Bits
Field
Type
Default
7:4
Reserved
R/W
0000
Description
3
PG_FAULT_LDO1
R/W
0
Source for PGOOD inactive signal:
0 - LDO1 has not set PGOOD signal inactive.
1 - LDO1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when LDO1 output is valid.
2
PG_FAULT_LDO0
R/W
0
Source for PGOOD inactive signal:
0 - LDO0 has not set PGOOD signal inactive.
1 - LDO0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when LDO0 output is valid.
1
PG_FAULT_BUCK
1
R/W
0
Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when Buck1 output is valid.
0
PG_FAULT_BUCK
0
R/W
0
Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 is selected for PGOOD signal and it has set PGOOD signal inactive. This bit
can be cleared by writing '1' to this bit when Buck0 output is valid.
7.6.1.25 RESET
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
SW_RESET
R/W
0
D0
SW_RESET
Description
Software commanded reset. When written to 1, the registers will be reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
7.6.1.26 INT_TOP_1
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
PGOOD_INT
LDO_INT
BUCK_INT
SYNC_CLK_IN
T
TDIE_SD_INT
TDIE_WARN_I
NT
OVP_INT
I_MEAS_INT
Bits
Field
Type
Default
7
PGOOD_INT
R/W
0
Latched status bit indicating that the PGOOD pin has changed from active to inactive.
Write 1 to clear interrupt.
6
LDO_INT
R
0
Interrupt indicating that LDO1 and/or LDO0 have a pending interrupt. The reason for
the interrupt is indicated in INT_LDO register.
This bit is cleared automatically when INT_LDO register is cleared to 0x00.
5
BUCK_INT
R
0
Interrupt indicating that Buck1 and/or Buck0 have a pending interrupt. The reason for
the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared to 0x00.
4
SYNC_CLK_INT
R/W
0
Latched status bit indicating that the external clock has appeared or disappeared.
Write 1 to clear interrupt.
3
TDIE_SD_INT
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulators have been disabled if they were enabled and
GPO and GPO2 signals are driven low. The regulators cannot be enabled if this bit is
active. The actual status of the thermal shutdown is indicated by TDIE_SD_STAT bit in
TOP_STAT register.
Write 1 to clear interrupt.
2
TDIE_WARN_INT
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
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Bits
Field
Type
Default
Description
1
OVP_INT
R/W
0
Latched status bit indicating that the input voltage has exceeded the over-voltage
detection level. The regulators have been disabled if they were enabled and GPO and
GPO2 signals are driven low. The actual status of the over-voltage is indicated by
OVP_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
0
I_MEAS_INT
R/W
0
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
7.6.1.27 INT_TOP_2
Address: 0x1A
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
RESET_REG_INT
R/W
0
D0
RESET_REG_I
NT
Description
Latched status bit indicating that either VANA supply voltage has been below
undervoltage threshold level or the host has requested a reset using SW_RESET bit in
RESET register. The regulators have been disabled, and registers are reset to default
values and the normal startup procedure is done.
Write 1 to clear interrupt.
7.6.1.28 INT_BUCK
Address: 0x1B
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
BUCK1_PG_INT
R/W
0
Latched status bit indicating that Buck1 Power-Good event has been detected.
Write 1 to clear.
5
BUCK1_SC_INT
R/W
0
Latched status bit indicating that the Buck1 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
4
BUCK1_ILIM_INT
R/W
0
Latched status bit indicating that the Buck1 output current limit has been active.
Write 1 to clear.
3
Reserved
R/W
0
2
BUCK0_PG_INT
R/W
0
Latched status bit indicating that Buck0 Power-Good event has been detected.
Write 1 to clear.
1
BUCK0_SC_INT
R/W
0
Latched status bit indicating that the Buck0 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
0
BUCK0_ILIM_INT
R/W
0
Latched status bit indicating that the Buck0 output current limit has been active.
Write 1 to clear.
7.6.1.29 INT_LDO
Address: 0x1C
54
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LDO1_PG
_INT
LDO1_SC
_INT
LDO1_ILIM
_INT
Reserved
LDO0_PG
_INT
LDO0_SC
_INT
LDO0_ILIM
_INT
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Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
LDO1_PG_INT
R/W
0
Latched status bit indicating that LDO1 Power-Good event has been detected.
Write 1 to clear.
5
LDO1_SC_INT
R/W
0
Latched status bit indicating that the LDO1 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
4
LDO1_ILIM_INT
R/W
0
Latched status bit indicating that the LDO1 output current limit has been active.
Write 1 to clear.
3
Reserved
R/W
0
2
LDO0_PG_INT
R/W
0
Latched status bit indicating that LDO0 Power-Good event has been detected.
Write 1 to clear.
1
LDO0_SC_INT
R/W
0
Latched status bit indicating that the LDO0 output voltage has been over 1 ms below
short-circuit threshold level.
Write 1 to clear.
0
LDO0_ILIM_INT
R/W
0
Latched status bit indicating that the LDO0 output current limit has been active.
Write 1 to clear.
7.6.1.30 TOP_STAT
Address: 0x1D
D7
D6
PGOOD_STAT
D5
Reserved
D4
D3
D2
D1
D0
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Bits
Field
Type
Default
7
PGOOD_STAT
R
0
Description
6:5
Reserved
R
00
4
SYNC_CLK_STAT
R
0
Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid.
3
TDIE_SD_STAT
R
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level.
2
TDIE_WARN
_STAT
R
0
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level.
1
OVP_STAT
R
0
Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level.
0
Reserved
R
0
Status bit indicating the status of PGOOD pin:
0 - PGOOD pin is inactive
1 - PGOOD pin is active
7.6.1.31 BUCK_STAT
Address: 0x1E
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
7
BUCK1_STAT
R
0
Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled.
6
BUCK1_PG_STAT
R
0
Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output voltage is valid.
1 - Buck1 output voltage is invalid.
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Bits
Field
Type
Default
5
Reserved
R
0
Description
4
BUCK1_ILIM
_STAT
R
0
Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active.
3
BUCK0_STAT
R
0
Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled.
2
BUCK0_PG_STAT
R
0
Status bit indicating Buck0 output voltage validity (raw status)
0 - Buck0 output voltage is valid.
1 - Buck0 output voltage is invalid.
1
Reserved
R
0
0
BUCK0_ILIM
_STAT
R
0
Status bit indicating Buck0 current limit status (raw status)
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active.
7.6.1.32 LDO_STAT
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
LDO1_STAT
LDO1_PG
_STAT
Reserved
LDO1_ILIM
_STAT
LDO0_STAT
LDO0_PG
_STAT
Reserved
LDO0_ILIM
_STAT
Bits
Field
Type
Default
Description
7
LDO1_STAT
R
0
Status bit indicating the enable/disable status of LDO1:
0 - LDO1 regulator is disabled
1 - LDO1 regulator is enabled.
6
LDO1_PG_STAT
R
0
Status bit indicating LDO1 output voltage validity (raw status)
0 - LDO1 output voltage is valid.
1 - LDO1 output voltage is invalid.
5
Reserved
R
0
4
LDO1_ILIM
_STAT
R
0
Status bit indicating LDO1 current limit status (raw status)
0 - LDO1 output current is below current limit level
1 - LDO1 output current limit is active.
3
LDO0_STAT
R
0
Status bit indicating the enable/disable status of LDO0:
0 - LDO0 regulator is disabled
1 - LDO0 regulator is enabled.
2
LDO0_PG_STAT
R
0
Status bit indicating LDO0 output voltage validity (raw status)
0 - LDO0 output voltage is valid.
1 - LDO0 output voltage is invalid.
1
Reserved
R
0
0
LDO0_ILIM
_STAT
R
0
Status bit indicating LDO0 current limit status (raw status)
0 - LDO0 output current is below current limit level
1 - LDO0 output current limit is active.
7.6.1.33 TOP_MASK_1
Address: 0x20
D7
D6
PGOOD_INT_
MASK
D5
Reserved
Bits
Field
Type
Default
7
PGOOD_INT
_MASK
R/W
X
6:5
Reserved
R/W
00
56
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D4
D3
D2
D1
D0
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
Description
Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect PGOOD_STAT status bit in TOP_STAT register.
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Bits
Field
Type
Default
4
SYNC_CLK
_MASK
R/W
X
3
Reserved
R/W
0
2
TDIE_WARN
_MASK
R/W
X
1
Reserved
R/W
0
0
I_MEAS
_MASK
R/W
X
Description
Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register.
Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1
register).
0 - Interrupt generated
1 - Interrupt not generated.
7.6.1.34 TOP_MASK_2
Address: 0x21
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
RESET_REG
_MASK
R/W
X
D0
RESET_REG
_MASK
Description
Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):
0 - Interrupt generated
1 - Interrupt not generated.
This change of this bit by I2C writing has no effect because it will be read from OTP
memory during reset.
7.6.1.35 BUCK_MASK
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_PGF
_MASK
BUCK1_PGR
_MASK
Reserved
BUCK1_ILIM
_MASK
BUCK0_PGF
_MASK
BUCK0_PGR
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
Field
Type
Default
7
BUCK1_PGF_MAS
K
R/W
X
Masking of Power Good invalid detection for Buck1 power good interrupt
(BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
Description
6
BUCK1_PGR_MAS
K
R/W
X
Masking of Power Good valid detection for Buck1 Power Good interrupt
(BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register.
5
Reserved
R
0
4
BUCK1_ILIM
_MASK
R/W
X
Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register.
3
BUCK0_PGF_MAS
K
R/W
X
Masking of Power Good invalid detection for Buck0 power good interrupt
(BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
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Bits
Field
Type
Default
2
BUCK0_PGR_MAS
K
R/W
X
1
Reserved
R
0
0
BUCK0_ILIM
_MASK
R/W
X
Description
Masking of Power Good valid detection for Buck0 power good interrupt
(BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register.
Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register.
7.6.1.36 LDO_MASK
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
LDO1_PGF
_MASK
LDO1_PGR
_MASK
Reserved
LDO1_ILIM
_MASK
LDO0_PGF
_MASK
LDO0_PGR
_MASK
Reserved
LDO0_ILIM
_MASK
Bits
Field
Type
Default
7
LDO1_PGF_MASK
R/W
X
Masking of Power Good invalid detection for LDO1 power good interrupt
(LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
6
LDO1_PGR_MASK
R/W
X
Masking of Power Good valid detection for LDO1 power good interrupt
(LDO1_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_PG_STAT status bit in LDO_STAT register.
5
Reserved
R
0
4
LDO1_ILIM
_MASK
R/W
X
Masking for LDO1 current limit detection interrupt (LDO1_ILIM_INT in INT_LDO
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO1_ILIM_STAT status bit in LDO_STAT register.
3
LDO0_PGF_MASK
R/W
X
Masking of Power Good invalid detection for LDO0 power good interrupt
(LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
2
LDO0_PGR_MASK
R/W
X
Masking of Power Good valid detection for LDO0 power good interrupt
(LDO0_PG_INT in INT_LDO register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_PG_STAT status bit in LDO_STAT register.
1
Reserved
R
0
0
LDO0_ILIM
_MASK
R/W
X
Description
Masking for LDO0 current limit detection interrupt (LDO0_ILIM_INT in INT_LDO
register):
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect LDO0_ILIM_STAT status bit in LDO_STAT register.
7.6.1.37 SEL_I_LOAD
Address: 0x24
D7
D6
D5
D4
Reserved
58
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D3
D2
D1
D0
LOAD_CURRE
NT_BUCK
_SELECT
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Bits
Field
Type
Default
7:1
Reserved
R/W
000 0000
0
LOAD_CURRENT_
BUCK_SELECT
R/W
0
Description
Start the current measurement on the selected regulator:
0 - Buck0
1 - Buck1
The measurement is started when register is written.
If the selected buck is master, the measurement result is a sum current of master and
slave buck.
If the selected buck is slave, the measurement result is a current of the selected slave
buck.
7.6.1.38 I_LOAD_2
Address: 0x25
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R
000 0000
0
BUCK_LOAD_
CURRENT[8]
R
0
D0
BUCK_LOAD_
CURRENT[8]
Description
This register describes the MSB bit of the average load current on selected regulator
with a resolution of 20 mA per LSB and maximum 10.22-A current.
7.6.1.39 I_LOAD_1
Address: 0x26
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Bits
Field
Type
7:0
BUCK_LOAD_
CURRENT[7:0]
R
Default
Description
0000 0000 This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and maximum 10.22-A current.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP8733xx-Q1 is a power management unit including two step-down regulators, two linear regulators, and
two general-purpose digital output signals.
8.2 Typical Applications
L0
VOUT_B0
VIN
VIN_B0
CIN_BUCK0
CIN_BUCK1
SW_B0
VIN_B1
FB_B0
COUT_BUCK0
LOAD
CPOL_BUCK0
VIN_LDO0
CIN_LDO0
CIN_LDO1
L1
VIN_LDO1
VOUT_B1
SW_B1
VANA
CANA
FB_B1
SDA
COUT_BUCK1
LOAD
CPOL_BUCK1
SCL
nINT
EN
VOUT_LDO0
VOUT_LDO0
CLKIN (GPO2)
GPO
VOUT_LDO1
VOUT_LDO1
PGOOD
GNDs
COUT_LDO0
COUT_LDO1
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Two Single-phase Buck Outputs Configuration
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Typical Applications (continued)
L0
VOUT_B0
VIN
VIN_B0
CIN_BUCK0
CIN_BUCK1
SW_B0
VIN_B1
FB_B0
COUT_BUCK0
VIN_LDO0
CIN_LDO0
CIN_LDO1
L1
VIN_LDO1
LOAD
VANA
CANA
CPOL_BUCK
SW_B1
FB_B1
SDA
COUT_BUCK1
SCL
nINT
EN
VOUT_LDO0
VOUT_LDO0
CLKIN (GPO2)
GPO
VOUT_LDO1
VOUT_LDO1
PGOOD
GNDs
COUT_LDO0
COUT_LDO1
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Single Dual-phase Buck Output Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors L0 and L1 are shown in the Typical Applications. The inductance and DCR of the inductor affects
the control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8. Pay
attention to the saturation current and temperature rise current of the inductor. Check that the saturation current
is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms
output current. Minimum effective inductance to ensure good performance is 0.22 μH at maximum peak output
current over the operating temperature range. DC resistance of the inductor must be less than 0.05 Ω for good
efficiency at high-current condition. The inductor AC loss also affects conversion efficiency. Higher Q factor at
switching frequency usually gives better efficiency at light load to middle load. Shielded inductors are preferred
as they radiate less noise.
Table 8. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS L × W × H (mm)
RATED DC CURRENT
ISAT maximum (typical) /
ITEMP maximum (typical) (A)
DCR
typical / maximum (mΩ)
TOKO
DFE252012PDR47M
0.47 µH (20%)
2.5 × 2 × 1.2
5.2 (–) / 4 (–) (1)
— / 27
Tayo Yuden
MDMK2020TR47M
MV
0.47 µH (20%)
2 × 2 ×1.2
4.2 (4.8) / 2.3 (2.45)
40 / 46
(1)
Operating temperature range is up to 125°C including self temperature rise.
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8.2.1.2 Buck Input Capacitor Selection
The input capacitors CIN_BUCK0 and CIN_BUCK1 are shown in the Typical Applications. A ceramic input bypass
capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to
the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input
voltage filtering. Use X7R type of capacitors, not Y5V or F. Also the DC bias characteristics capacitors must be
considered. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at
maximum input voltage including tolerances, ambient temperature range and aging. This is assuming that there
are at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See
Table 9.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient
ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
Table 9. Recommended Buck Input Capacitor (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
2 × 1.25 × 1.25
10 V
8.2.1.3 Buck Output Capacitor Selection
The output capacitor COUT_BUCK0 and COUT_BUCK1 are shown in Typical Applications. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias
voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current
flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low
ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance is
10 μF per phase including the DC voltage rolloff, tolerances, aging, and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 10.
POL capacitors CPOL_BUCKx can be used to improve load transient performance and to decrease the ripple
voltage. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as
well as decreases the PFM switching frequency. However, output capacitance higher than 150 μF per phase is
not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output voltage
ramp, see Specifications for maximum output capacitance for different slew-rate settings. For large output
capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of
the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output
capacitor to target value might be longer. At shutdown the output voltage is discharged to 0.6 V level using
forced-PWM operation. This can increase the input voltage if the load current is small and the output capacitor is
large compared to input capacitor. Below 0.6 V level the output capacitor is discharged by the internal discharge
resistor and with large capacitor more time is required to settle VOUT down as a consequence of the increased
time constant.
Table 10. Recommended Buck Output Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE RATING
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
3.2 × 1.6 × 1.6
10 V
8.2.1.4 LDO Input Capacitor Selection
The input capacitors CIN_LDO0 and CIN_LDO1 are shown in the . A ceramic input capacitor of 2.2 μF, 6.3 V is
sufficient for most applications. Place the input capacitor as close as possible to the VIN_LDOx pin and AGND
pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of
capacitors, not Y5V or F. DC bias characteristics of capacitors must be considered, minimum effective input
capacitance to ensure good performance is 0.6 μF per LDO input at maximum input voltage including tolerances,
ambient temperature range and aging. See Table 11.
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Table 11. Recommended LDO Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE RATING
Murata
GCM188R70J225KE22
2.2 µF (10%)
0603
1.6 × 0.8 × 0.8
6.3 V
Murata
GCM21BR71C475KA73
4.7 µF (10%)
0805
2 × 1.25 × 1.25
16 V
8.2.1.5 LDO Output Capacitor Selection
The output capacitors COUT_LDO0 and COUT_LDO1 are shown in the Typical Applications. A ceramic output
capacitor of minimum 1.0 μF is required. Place the output capacitor as close to the VOUT_LDOx pin and AGND
pin of the device as possible. Use X7R type of capacitors, not Y5V or F. DC bias characteristics of capacitors
must be considered, minimum effective output capacitance to ensure good performance is 0.4 μF per LDO input
at maximum input voltage including tolerances, ambient temperature range and aging. See Table 12.
The output capacitance must be smaller than the input capacitance in order to ensure the stability of the LDO.
With a 1-μF output capacitor it is recommended to use at least 2.2-μF input capacitor; with a 2.2-μF output
capacitor at least 4.7-μF input capacitance.
The VANA input is used to supply analog and digital circuits in the device. See Table 13 for recommended
components from for VANA input supply filtering.
Table 12. Recommended LDO Output Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H (mm)
Murata
Murata
VOLTAGE RATING
GCM188R71C105KA64
1 µF (10%)
0603
1.6 × 0.8 × 0.8
16 V
GCM188R70J225KE22
2.2 µF (10%)
0603
1.6 × 0.8 × 0.8
6.3 V
Table 13. Recommended Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H (mm)
VOLTAGE RATING
Murata
GCM155R71C104KA55
100 nF (10%)
0402
1 × 0.5 × 0.5
16 V
Murata
GCM188R71C104KA37
100 nF (10%)
0603
1.6 × 0.8 × 0.8
16 V
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8.2.1.6 Current Limit vs. Maximum Output Current
The inductor current ripple can be calculated using Equation 1 and Equation 2:
VOUT
D
VIN(max) u K
'IL
(VIN(max)
(1)
VOUT ) u D
fSW u L
(2)
Example using Equation 1 and Equation 2:
VIN(max) = 5.5 V
VOUT = 1 V
η = 0.75
fSW = 1.8 MHz
L = 0.38 µH
then D = 0.242 and ΔIL = 1.59 A
Peak current is half of the current ripple. If ILIM_FWD_SET_OTP is 3 A, the minimum forward current limit would be
2.85 A when taking the –5% tolerance into account. In this case the difference between set peak current and
maximum load current = 0.795 A + 0.15 A = 0.945 A.
Inductor current =
Forward current
ILIM_FWD_MAX (+20%)
ILIM_FWD_TYP (+7.5%)
ILIM_FWD_SET_OTP (1.5...4 A, 0.5-A step)
ILIM_FWD_MIN (-5%)
Minimum 1A guard band
to take current ripple,
inductor inductance
variation into account
IL_AVG = IOUT
1 / fSW
IOUT_MAX < ILIM_FWD_SET_OTP ± 1 A
Figure 31. Current Limit vs Maximum Output Current
8.2.2 Detailed Design Procedure
The performance of the LP8733xx-Q1 device depends greatly on the care taken in designing the printed circuit
board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,
while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling
capacitors must be connected close to the device and between the power and ground pins to support high peak
currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output
traces as short as possible, because trace inductance, resistance, and capacitance can easily become the
performance limiting items. The separate buck regulator power pins VIN_Bx are not connected together
internally. Connect the VIN_Bx power connections together outside the package using power plane construction.
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8.2.3 Application Curves
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Measurements are done using typical application set up with connections shown in Typical Applications. Graphs
may not reflect the OTP default settings. Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V,
VOUT_Bx = 1 V, VOUT_LDOx = 1 V, TA = 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF /
phase, and CPOL_BUCK = 22 µF, COUT_LDO = 1 µF.
70
60
Vin=5V, AUTO
Vin=3.3V, AUTO
Vin=5V, FPWM
Vin=3.3V, FPWM
50
40
0.001
0.01
0.1
Output Current (A)
1
70
60
Vin=5V, AUTO
Vin=3.3V, AUTO
Vin=5V, FPWM
Vin=3.3V, FPWM
50
3
40
0.001
D003
0.01
VOUT = 1.8 V
90
90
80
80
Efficiency (%)
Efficiency (%)
100
Vout=1V
Vout=1.8V
Vout=2.5V
50
40
0.001
0.01
0.1
Output Current (A)
1
70
60
Vout=1V
Vout=1.8V
Vout=2.5V
D007
40
0.001
VIN = 3.3 V
Figure 34. Buck Efficiency in Forced PWM Mode (SinglePhase Output)
Copyright © 2018, Texas Instruments Incorporated
D005
50
3
6
Figure 33. Buck Efficiency in PFM/PWM and Forced PWM
Mode (Dual-Phase Output)
100
60
1
VOUT = 1.8 V
Figure 32. Buck Efficiency in PFM/PWM and Forced PWM
Mode (Single-Phase Output)
70
0.1
Output Current (A)
0.01
0.1
Output Current (A)
1
6
D009
VIN = 3.3 V
Figure 35. Buck Efficiency in Forced PWM Mode (DualPhase Output)
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100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
SNVSB64 – SEPTEMBER 2018
70
60
70
60
Vout=1V
Vout=1.8V
Vout=2.5V
50
40
0.001
0.01
0.1
Output Current (A)
1
Vout=1V
Vout=1.8V
Vout=2.5V
50
3
40
0.001
D011
0.01
VIN = 5 V
1.02
1.016
1.012
1.012
1.008
1.008
Output Voltage (V)
Output Voltage (V)
1.02
0.996
0.992
0.988
0.5
1
1.5
2
Output Current (A)
2.5
1.004
1
0.996
0.992
Vin=3.3V, FPWM
Vin=5.0V, FPWM
0.984
0.98
0
D013
0.988
Vin=3.3V, FPWM
Vin=5.0V, FPWM
0.984
6
Figure 37. Buck Efficiency in Forced PWM Mode (DualPhase Output)
1.016
1
1
VIN = 5 V
Figure 36. Buck Efficiency in Forced PWM Mode (SinglePhase Output)
1.004
0.1
Output Current (A)
3
0.98
D015
0
0.5
1
1.5
VOUT = 1 V
Figure 38. Buck Output Voltage vs Load Current in Forced
PWM Mode (Single-Phase Output)
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
D017
VOUT = 1 V
Figure 39. Buck Output Voltage vs Load Current in Forced
PWM Mode (Dual-Phase Output)
1.02
1.02
1.016
1.015
1.012
Output Voltage (V)
Output Voltage (V)
1.01
1.005
1
0.995
1.008
1.004
1
0.996
0.992
0.99
0.988
0.985
Vin=3.3V, AUTO
Vin=5.0V, AUTO
0.98
0.98
0
66
Vin=3.3V, AUTO
Vin=5.0V, AUTO
0.984
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
0
0.2
D019
0.4
0.6
Output Current (A)
0.8
1
D020
VOUT = 1 V
VOUT = 1 V
Figure 40. Buck Output Voltage vs Load Current in
PFM/PWM Mode (Single-Phase Output)
Figure 41. Buck Output Voltage vs Load Current in
PFM/PWM Mode (Dual-Phase Output)
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1.02
1.016
1.016
1.012
1.012
1.008
1.008
Output Voltage (V)
Output Voltage (V)
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1.004
1
0.996
0.992
1.004
1
0.996
0.992
0.988
0.988
0.984
0.984
0.98
2.5
3
3.5
VOUT = 1 V
4
4.5
Input Voltage (V)
5
0.98
2.5
5.5
3
3.5
D021
Load = 1 A
VOUT = 1 V
Figure 42. Buck Output Voltage vs Input Voltage in PWM
Mode (Single-Phase Output)
4
4.5
Input Voltage (V)
5
5.5
D022
Load = 1 A
Figure 43. Buck Output Voltage vs Input Voltage in PWM
Mode (Dual-Phase Output)
3
1.02
1.015
2
1.005
Phases
Output Voltage (V)
1.01
1
0.995
1
0.99
0.985
ADDING
SHEDDING
PFM
PWM
0.98
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
0.2
0.4
0.6
D023
Figure 44. Buck Output Voltage vs Temperature
2
D025
ILOAD = 0 A
VOUT = 1 V
VOUT = 1 V
Figure 46. Buck Start-Up With EN1, Forced PWM Mode
(Single-Phase Output)
Copyright © 2018, Texas Instruments Incorporated
1.8
Figure 45. Buck Phase Adding and Shedding vs Load
Current (Dual-Phase Output)
Slew-rate = 10 mV/µs
ILOAD = 0 A
1.6
VIN = 3.7 V
Load = 1 A (PWM) and 0.1 A (PFM)
Slew-rate = 10 mV/µs
0.8
1
1.2 1.4
Output Current (A)
Figure 47. Buck Start-Up With EN1, Forced PWM Mode
(Dual-Phase Output)
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Slew-rate = 10 mV/µs
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RLOAD = 1 Ω
VOUT = 1 V
Figure 48. Buck Start-Up with EN1, Forced PWM Mode
(Single-Phase Output)
Slew-rate = 10 mV/µs
RLOAD = 1 Ω
VOUT = 1 V
Figure 50. Buck Shutdown With EN1, Forced PWM Mode
(Single-Phase Output)
IOUT = 10 mA
Figure 52. Buck Output Voltage Ripple, PFM Mode (SinglePhase Output)
68
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Slew-rate = 10 mV/µs
RLOAD = 0.5 Ω
VOUT = 1 V
Figure 49. Buck Start-Up with EN1, Forced PWM Mode
(Dual-Phase Output)
Slew-rate = 10 mV/µs
RLOAD = 0.5 Ω
VOUT = 1 V
Figure 51. Buck Shutdown With EN1, Forced PWM Mode
(Dual-Phase Output)
IOUT = 10 mA
Figure 53. Buck Output Voltage Ripple, PFM Mode (DualPhase Output)
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IOUT = 200 mA
IOUT = 200 mA
Figure 54. Buck Output Voltage Ripple,
Forced PWM Mode (Single-Phase Output)
Figure 55. Buck Output Voltage Ripple,
Forced PWM Mode (Dual-Phase Output)
Figure 56. Buck Transient From PFM-to-PWM Mode
(Single-Phase Output)
Figure 57. Buck Transient From PFM-to-PWM Mode (DualPhase Output)
Figure 58. Buck Transient From PWM-to-PFM Mode
(Single-Phase Output)
Figure 59. Buck Transient From PWM-to-PFM Mode (DualPhase Output)
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Figure 60. Buck Transient From 1-Phase to 2-Phase
Operation (Dual-Phase Output)
IOUT = 0.1 A → 2 A
→ 0.1 A
TR = TF = 400 ns
Figure 62. Buck Transient Load Step Response, AUTO
Mode (Single-Phase Output)
IOUT = 0.1 A → 2 A
→ 0.1 A
TR = TF = 400 ns
Figure 64. Buck Transient Load Step Response, Forced
PWM Mode (Single-Phase Output)
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Figure 61. Buck Transient From 2-Phase to 1-Phase
Operation (Dual-Phase Output)
IOUT = 0.1 A → 4 A
→ 0.1 A
TR = TF = 400 ns
Figure 63. Buck Transient Load Step Response, AUTO
Mode (Dual-Phase Output)
IOUT = 0.1 A → 4 A
→ 0.1 A
TR = TF = 400 ns
Figure 65. Buck Transient Load Step Response, Forced
PWM Mode (Dual-Phase Output)
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VOUT(200mV/div)
VOUT(200mV/div)
Time (400 µs/div)
Figure 66. Buck VOUT Transition from 0.6 V to 1.4 V With
Different Slew Rate Settings
Figure 67. Buck VOUT Transition from 1.4 V to 0.6 V With
Different Slew Rate Settings
Figure 68. Buck Start-up With Short on Output (SinglePhase Output)
Figure 69. Buck Start-up With Short on Output (DualPhase Output)
1.02
1.02
1.015
1.015
1.01
1.01
Output Voltage (V)
Output Voltage (V)
Time (400 µs/div)
1.005
1
0.995
0.99
1.005
1
0.995
0.99
0.985
0.985
Vin=3.3V
Vin=5V
0.98
0
50
100
150
200
Output Current (mA)
250
300
VOUT = 1 V
Figure 70. LDO Output Voltage vs Load Current
Copyright © 2018, Texas Instruments Incorporated
0.98
2.5
3
D050
VOUT = 1 V
3.5
4
4.5
Input Voltage (V)
5
5.5
D051
Load = 200 mA
Figure 71. LDO Output Voltage vs Input Voltage
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1.02
1.015
Output Voltage (V)
1.01
1.005
1
0.995
0.99
0.985
0.98
-40
-20
0
20
VOUT = 1 V
40
60
80
Temperature (qC)
100
120
140
D052
Load = 200 mA
ILOAD = 0 A
Figure 73. LDO Start-Up
Figure 72. LDO Output Voltage vs Temperature
RLOAD = 3.3 Ω
VOUT = 1 V
ILOAD = 0 A
Figure 74. LDO Start-Up
IOUT = 0 A → 0.3 A → 0 A
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VOUT = 1 V
Figure 75. LDO Shutdown
TR = TF = 1 µs
Figure 76. LDO Transient Load Step Response
72
VOUT = 1 V
Figure 77. LDO VOUT Transition from 1.8 V to 1.2 V
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Figure 78. LDO VOUT Transition from 1.2 V to 1.8 V
SNVSB64 – SEPTEMBER 2018
Start-up
delay is 500
µs
Figure 79. LDO Start-Up With Short on Output
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. The VANA input
and VIN_Bx buck inputs must be connected together, and they must use the same input supply. This input
supply must be well regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the
input current transient does not cause too high a drop in the LP8733xx-Q1 supply voltage that can cause false
UVLO fault triggering. If the input supply is located more than a few inches from the LP8733xx-Q1 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. The VIN_LDOx LDO input supply
voltage range is 2.5 V to 5.5 V and can be higher or lower than VANA supply voltage.
10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP8733xx-Q1 make the choice of layout important. Good
power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and
generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP8733xx-Q1, as well as the trace between the negative node of the input capacitor and power PGND_Bx
pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source
for the switching converter. The inductance of the connection is the most important parameter of a local
decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper
device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to
top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the output capacitors of the LP8733xx-Q1 and the input capacitors of the
load direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
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Layout Guidelines (continued)
4. If remote voltage sensing can be used for the load, connect the LP8733xx-Q1 feedback pins FB_Bx to the
respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept
away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as
the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close
to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if
possible. If series resistors are used for load current measurement, place them after connection of the
voltage feedback.
5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers
which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
6. LDO performance (PSRR, noise and transient response) depend on the layout of the PCB. Best performance
is achieved by placing CIN and COUT as close to the LP8733xx-Q1 device as practical. The ground
connections for CIN and COUT must be back to the LP8733xx-Q1 AGND with as wide and as short of a
copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using
long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances
and resistance that results in inferior performance especially during transient conditions.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends
performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design
process by using a thermal modeling analysis software.
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10.2 Layout Example
VOUT0
VOUT1
COUT0
COUT1
GND
L1
AGND
L0
PGND_B1
PGND_B1
SCL
SDA
SGND
PGND_B0
VIN
PGND_B0
AGND
14
SW_B1
13
VIN_B1
12
VIN_B0
VIN_B1
11
26
GPO
CLKIN
10
27
PGOOD
nINT
9
SW_B0
24
VIN_B0
25
CIN2
15
SW_B1
23
VIN
GND
20 19 18 17 16
SW_B0
22
CIN0
21
29
AGND
VIN
GND
CIN3
VIN_LDO1 8
28 VIN_LDO0
VIN
VOUT_LDO0
FB_B0
FB_B1
AGND
VANA
EN
VOUT_LDO1
1
2
3
4
5
6
7
COUT2
VOUT2
CIN1
VIN
CANA
AGND
AGND
COUT3
AGND
VOUT3
Figure 80. LP8733xx-Q1 Board Layout
In dual-phase buck configuration short VOUT0 and VOUT1 together.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
76
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Copyright © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP873300RHDRQ1
ACTIVE
VQFN
RHD
28
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
LP8733
00-Q1
LP873300RHDTQ1
ACTIVE
VQFN
RHD
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
LP8733
00-Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP873300RHDRQ1
VQFN
RHD
28
3000
330.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
LP873300RHDTQ1
VQFN
RHD
28
250
180.0
12.4
5.25
5.25
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP873300RHDRQ1
VQFN
RHD
28
3000
370.0
355.0
55.0
LP873300RHDTQ1
VQFN
RHD
28
250
220.0
205.0
50.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHD0028W
VQFN - 1 mm max height
SCALE 2.500
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.1
4.9
0.1 MIN
(0.05)
SECTION A-A
A-A 25.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
3.4 0.1
(0.2) TYP
8
14
EXPOSED
THERMAL PAD
24X 0.5
7
15
A
A
4X
3
1
SYMM
21
28X
PIN 1 ID
(OPTIONAL)
28
22
SYMM
28X
0.65
0.45
0.3
0.2
0.1
0.05
C A B
4222120/B 02/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHD0028W
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.4)
SYMM
22
28
28X (0.75)
1
21
28X (0.25)
(1.45)
SYMM
(4.65)
(0.5) TYP
15
7
(R0.05) TYP
( 0.2) TYP
VIA
14
8
(1.45)
(4.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222120/B 02/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHD0028W
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.84) TYP
22
28
METAL
TYP
28X (0.75)
1
21
28X (0.25)
(0.84)
TYP
SYMM
(4.65)
24X (0.5)
15
7
(R0.05) TYP
8
14
4X ( 1.47)
(4.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222120/B 02/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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