Texas Instruments | TPS7B770x-Q1, Automotive, Single- and Dual-Channel Antenna LDO With Current Sense (Rev. C) | Datasheet | Texas Instruments TPS7B770x-Q1, Automotive, Single- and Dual-Channel Antenna LDO With Current Sense (Rev. C) Datasheet

Texas Instruments TPS7B770x-Q1, Automotive, Single- and Dual-Channel Antenna LDO With Current Sense (Rev. C) Datasheet
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TPS7B7701-Q1, TPS7B7702-Q1
SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
TPS7B770x-Q1, Automotive, Single- and Dual-Channel Antenna LDO With Current Sense
1 Features
3 Description
•
•
The TPS7B770x-Q1 family of devices feature a single
and dual, high-voltage low-dropout regulator (LDO)
with current sensing, designed to operate with a wide
input-voltage range from 4.5 V to 40 V (45-V load
dump protection). These devices provide power to the
low-noise amplifiers of the active antenna through a
coax cable with 300 mA per channel current. Each
channel also provides an adjustable output voltage
from 1.5 V to 20 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification 2
– Device CDM ESD Classification C4B
Single and Dual-Channel LDO With Current
Sense and Adjustable Current-Limit
4.5-V to 40-V Wide Input Voltage Range, 45-V
Load Dump
Power Switch Mode When Tying FB to GND
1.5-V to 20-V Adjustable Output Voltage
Up to 300-mA Output Current per Channel
Adjustable Current-Limit With External Resistor
High Accuracy Current-Sense to Detect Antenna
Open Condition at Low Current Without Further
Calibration
High Power-Supply Rejection Ratio: Typical 73 dB
at 100 Hz
Integrated Reverse-Polarity Protection, Down to
–40 V and No Need for External Diode
500-mV Max Dropout Voltage at 100-mA Load
Stable With Output Capacitor in 2.2-µF to 100-µF
Range (ESR 1 mΩ to 5 Ω)
Integrated Protection and Diagnostics
– Thermal Shutdown
– Undervoltage Lockout (UVLO)
– Short-Circuit Protection
– Reverse Battery Polarity Protection
– Reverse-Current Protection
– Output Short-to-Battery Protection
– Output Inductive Load Clamp
– Multiplexing Current Sense Between Channels
and Devices
– Ability to Distinguish All Faults With Current
Sense
16-Pin HTSSOP PowerPAD™ Package
These devices provide diagnostics through the
current sense and error pins. To monitor the load
current, a high-side current-sense circuitry provides a
proportional analog output to the sensed load current.
The accurate current sense allows detection of open,
normal, and short-circuit conditions without the need
for further calibration. Current sense can be
multiplexed between channels and devices to save
analog-to-digital converter (ADC) resources. Each
channel also implements adjustable current limit with
an external resistor.
An integrated reverse polarity diode eliminates the
need for an external diode. These devices feature
standard
thermal
shutdown,
short-to-battery
protection on the output, and reverse current
protection. Each channel has internal inductive clamp
protection on the output during inductive switch off.
These devices operate over a –40°C to +125°C
ambient temperature range.
Device Information(1)
PART NUMBER
•
•
•
Infotainment Active-Antenna Power Supplies
Surround-View Camera Power Supplies
High-Side Power Switch For Small-Current
Applications
CHANNEL
HTSSOP (16)
Single
TPS7B7702-Q1
HTSSOP (16)
Dual
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Diagram
Active
Antenna
IN
Battery
Input
10 F
OUT1/2
Filter Coil
Filter Coil
Cable
10 F
MCU I/O
MCU I/O
1 F
10 F
SENSE_EN
FB1/2
SENSE_SEL
SENSE1/2
2 Applications
PACKAGE
TPS7B7701-Q1
TPS7B770x-Q1
R(SENSE)
EN1/2
ILIM1/2
MCU I/O
R(LIM)
VCC
ERR
MCU I/O
1 F
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B7701-Q1, TPS7B7702-Q1
SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2015) to Revision C
Page
•
Changed NC pin description in Pin Functions table to clarify which pins are internally connected ...................................... 3
•
Added row to Recommended Operating Conditions for OUT1, OUT2, and OUT regarding switched-mode operation ....... 4
•
Changed Current-Limit Resistor Selection section for clarity ............................................................................................... 17
Changes from Revision A (May 2015) to Revision B
Page
•
Deleted the min and max limits of –4% and 4% from the current-limit threshold voltage parameter in the Electrical
Characteristics table ............................................................................................................................................................... 6
•
Added to the current-limit accuracy table note for the programmable current-limit accuracy parameter in the
Electrical Characteristics table ............................................................................................................................................... 6
•
Added graphs for the TPS7B7701-Q1 device in the Typical Characteristics section ........................................................... 7
•
Deleted the channel 2 PSRR graph in the Typical Characteristics section ........................................................................... 7
•
Added additional test conditions for the 9- to 16-V Line Transient and Power Up graphs in the Typical
Characteristics section .......................................................................................................................................................... 9
•
Added additional test conditions of the Power Up graphs in the Application Curves section ............................................. 18
Changes from Original (January 2015) to Revision A
•
2
Page
Released full version of data sheet ........................................................................................................................................ 1
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Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com
SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
Single-Channel TPS7B7701-Q1 PWP Package
16-Pin HTSSOP With PowerPAD
Top View
Dual-Channel TPS7B7702-Q1 PWP Package
16-Pin HTSSOP With PowerPAD
Top View
IN
1
16
OUT1
FB
EN1
2
15
FB1
14
NC
EN2
3
14
OUT2
13
NC
VCC
4
13
FB2
IN
1
16
OUT
EN
2
15
NC
3
VCC
4
PowerPAD (GND)
PowerPAD (GND)
SENSE1
5
12
GND
NC
SENSE2
6
11
LIM2
LIM
SENSE_SEL
7
10
LIM1
ERR
SENSE_EN
8
9
ERR
SENSE
5
12
GND
NC
6
11
NC
7
10
SENSE_EN
8
9
Not to scale
Not to scale
Pin Functions
PIN
SINGLECHANNEL
DUALCHANNEL
TYPE
EN
2
—
Input
Active-high enable input for the OUT pin with internal pulldown.
EN1
—
2
Input
Active-high enable input for the OUT1 pin with internal pulldown.
EN2
—
3
Input
Active-high enable input for the OUT2 pin with internal pulldown.
ERR
9
9
Output
FB
15
—
Input
Feedback input for setting OUT voltage. Connect FB to GND for current-limited switch operation.
FB1
—
15
Input
Feedback input for setting OUT1 voltage. Connect FB1 to GND for current-limited switch operation.
FB2
—
13
Input
Feedback input for setting OUT2 voltage. Connect FB2 to GND for current-limited switch operation.
GND
12
12
Ground
Ground reference
IN
1
1
Power
Input power-supply voltage
LIM
10
—
Output
Programmable current-limit pin. Connect a resistor to GND to set the current limitation level. This pin
does not need an external capacitor. To set to internal current limit, short this pin to GND.
LIM1
—
10
Output
Programmable current-limit pin for channel 1. Connect a resistor to GND to set the current limitation
level for channel 1. This pin does not need an external capacitor. To set to internal current limit, short
this pin to GND.
LIM2
—
11
Output
Programmable current-limit pin for channel 2. Connect a resistor to GND to set the current limitation
level for channel 2. This pin does not need an external capacitor. To set to internal current limit, short
this pin to GND.
3, 13, 14
—
—
Not connected. Connect the NC pins to ground or leave floating.
6, 7, 11
—
—
Internally connected. These pins must either be floated or connected to GND.
OUT
16
—
Power
Output voltage
OUT1
—
16
Power
Output voltage 1
OUT2
—
14
Power
Output voltage 2
SENSE
5
—
Output
Output of current sense for sensing. To set the SENSE output voltage level, connect a resistor
between this pin and GND. In addition, connect a 1-µF capacitor from this pin to GND for frequency
compensation of the current-sense loop. Short this pin to GND if not used.
SENSE1
—
5
Output
SENSE2
—
6
Output
SENSE_EN
8
8
Input
This pin is the enable and disable of the current-sense pin for multiplexing, active-low enable.
SENSE_SEL
—
7
Input
This pin selects the current sense between channel 1 and channel 2. See Table 2 for details.
VCC
4
4
Output
Internal 4.5-V regulator. Connect 1-μF ceramic capacitor between VCC and GND for frequency
compensation.
NAME
NC
DESCRIPTION
This pin is an open-drain fault indicator for general faults.
Output of current sense for sensing. SENSE1 current is proportional to the current flow through OUT1
and SENSE 2 current is proportional to OUT2 current when SENSE_SEL and SENSE_EN are low. To
set the SENSEx output voltage level, connect a resistor between this pin and GND. In addition,
connect a 1-µF capacitor from the SENSEx pin to GND for frequency compensation of the currentsense loop. Short the SENSEx pin to GND if not used.
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Unregulated input, IN
–40
45
V
EN, EN1, and EN2
–0.3
45
V
VCC (3) (4)
–0.3
6
V
OUT1 and OUT2
–0.3
45
V
–0.3
VCC + 0.3
V
–0.3
7
V
Operating junction temperature, TJ
–40
150
°C
Operating ambient temperature, TA
–40
125
°C
Storage Temperature, Tstg
–65
150
°C
Input voltage
Regulated output (2)
SENSE, SENSE1, and SENSE2
Low-voltage pins
(1)
(2)
(3)
(4)
(3) (4)
LIM, LIM1, LIM2, SENSE_EN , SENSE_SEL, ERR, FB, FB1, and
FB2 (3) (4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
There is an internal diode connects between the OUT and GND pins with 300-mA DC current capability for inductive clamp protection.
All voltage values are with respect to GND.
Absolute maximum voltage.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner pins (1, 8, 9, and 16)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI
MIN
MAX
4.5
40
V
0
40
V
0
5.3
V
Normal-mode operation
1.5
20
Switched-mode operation
1.5
35
2.2
100
Unregulated input
EN, EN1, and EN2
Low-voltage pins
OUT1, OUT2, and OUT
SENSE, SENSE1, SENSE2, SENSE_EN , SEN_SEL ,
ERR , FB, FB1, FB2, LIM, LIM1, LIM2, and VCC
UNIT
V
CO
Output capacitor stability range
CO(ESR)
Output capacitor ESR stability range
0.001
5
Ω
TJ
Junction temperature
–40
150
°C
TA
Ambient temperature
–40
125
°C
4
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µF
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1
TPS7B7701-Q1, TPS7B7702-Q1
www.ti.com
SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
6.4 Thermal Information
THERMAL METRIC
(1)
TPS7B7701-Q1
TPS7B7702-Q1
PWP
(HTSSOP)
PWP
(HTSSOP)
16 PINS
16 PINS
(2)
UNIT
RθJA
Junction-to-ambient thermal resistance
45.9
40.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.2
27.7
°C/W
RθJB
Junction-to-board thermal resistance
24.7
22.3
°C/W
ψJT
Junction-to-top characterization parameter
1.3
0.8
°C/W
ψJB
Junction-to-board characterization parameter
24.5
22
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.7
2.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The thermal data is based on JEDEC standard high K profile – JESD 51-7. The copper pad is soldered to the thermal land pattern. Also
correct attachment procedure must be incorporated
6.5 Electrical Characteristics
at VI = 14 V and TJ = –40ºC to +150ºC (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
VI
Input voltage
IQ
4.5
Quiescent current
I(shutdown)
Shutdown current
Inom
Operating current
40
TPS7B7701-Q1: VI = 4.5 to 40 V, V(EN) ≥ 2 V,
I(OUT) = 0.1 mA
0.6
1
TPS7B7702-Q1: VI = 4.5 to 40 V, V(EN1) and
V(EN2) ≥ 2 V, I(OUT1) and I(OUT2) = 0.1 mA
0.6
1
mA
TPS7B7701-Q1: EN = GND
5
TPS7B7702-Q1: EN1 = EN2 = GND
5
TPS7B7701-Q1: V(EN) ≥ 2 V, I(OUT) ≤ 300 mA,
GND current
Bandgap
Reference voltage for FB
V(UVLO)
Undervoltage lockout falling
Ramp IN down until the output turns off
Vhys
Hysteresis
µA
4.5
mA
TPS7B7702-Q1: V(EN1) and V(EN2) ≥ 2 V, I(OUT1)
and I(OUT2) ≤ 300 mA, GND current
V(BG)
V
6
–2%
1.233
2%
V
4
V
0.4
V
INPUT CONTROL PINS (EN, EN1, EN2, SENSE_EN, AND SENSE_SEL)
VIL
Logic input low level
For EN, EN1, EN2, SENSE_EN, and
SENSE_SEL
0
VIH
Logic input high level
For EN, EN1, EN2, SENSE_EN, and
SENSE_SEL
2
II(SENSE_EN)
SENSE_EN input current
V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V
10
µA
II(SENSE_SEL)
SENSE_SEL input current
V(SENSE_EN) = 5 V, V(ENx) ≥ 2 V
10
µA
II(EN)
Enable input current
V(ENx) ≤ 40 V
10
µA
0.7
V
V
REGULATED OUTPUT (OUT, OUT1, AND OUT2)
VO
Regulated output
40 V ≥ VI ≥ VO + 1.5 V and VI ≥ 4.5 V, IO = 1 to
300 mA (1)
ΔVO(ΔVI)
Line regulation
VI = VO + 1.5 V to 40 V and VI ≥ 6 V, IO = 10
mA, voltage variation on FB pin
10
mV
ΔVO(ΔIO)
Load regulation
IO = 1 mA to 200 mA, voltage variation on FB
pin
20
mV
V(DROPOUT)
Dropout voltage
Measured between IN and OUTx, IO = 100 mA
500
mV
IO
Output current
VO in regulation
300
mA
PSRR
Power supply ripple rejection (2)
IO = 100 mA, CO = 2.2 µF, ƒ = 100 Hz
73
VI = 4.5 V to 40 V, 5 mA ≤ IO ≤ 300 mA
198
–2%
2%
0
dB
CURRENT SENSE AND CURRENT-LIMIT
IO/ISENSE
(1)
(2)
OUTx to SENSEx current ratio (IO / ISENSEx)
External feedback resistor is not considered.
Design information; specified by design, not production tested.
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Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1
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Electrical Characteristics (continued)
at VI = 14 V and TJ = –40ºC to +150ºC (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
IO = 100 to 300 mA
OUTx to SENSEx current ratio accuracy
MAX
–5%
5%
IO = 10 to 50 mA
–10%
10%
IO = 5 to 10 mA
–20%
OUTx to LIMx current ratio (IO / ILIM)
VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA
I(LIMx)
Programmable current-limit accuracy (3)
VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA
IL(LIMx)
Internal current-limit
LIMx shorted to GND
Ilkg
SENSE, SENSE1, SENSE2, LIM, LIM1,
and LIM2 leakage current
ENx = GND, TA = 25°C
V(LIMx_th)
Current-limit threshold voltage
Voltage on the LIM, LIM1, and LIM2 pins when
output current is limited
V(SENSEx_stb)
Current-sense short-to-battery fault voltage
When short-to-battery or reverse current
conditions are detected
V(SENSEx_tsd)
Current-sense thermal shutdown fault
voltage
V(SENSEx_cl)
UNIT
3%
IO = 50 to 100 mA
IO/ILIM
I(SENSEx_H)
TYP
–3%
20%
198
–8%
8%
340
550
mA
2
µA
1.233
V
3.05
3.2
3.3
V
When thermal shutdown is detected
2.7
2.85
3
V
Current-sense current-limit fault voltage
When current-limit conditions are detected
2.4
2.55
2.65
V
Current-sense fault condition current
When short-to-battery, reverse current, thermal
shutdown, or current-limit conditions are
detected
3.3
mA
FAULT DETECTION
V(stb_th)
Short-to-battery threshold
V(OUTx) – VI, checked during turnon sequence
–500
–55
110
mV
I(REV)
Reverse current detection level
Power FET on (SW or LDO mode)
–100
–40
–1
mA
TSD
Thermal shutdown
Junction temperature
TSD(hys)
Thermal shutdown hysteresis
175
°C
15
°C
INTERFACE CIRCUITRY
VOL
Ilkg
ERR output low
I(SINK) = 5 mA
ERR open-drain leakage current
ERR high impedance, 5-V external voltage is
applied at ERR
(2)
0.4
V
1
µA
R(OUTx-off)
OUT pulldown resistor
ENx = GND
50
kΩ
IR(lkg)
Reverse leakage current
–40 V < VI < 0 V, reverse current to IN
0.6
mA
VCC
Internal voltage regulator
VI = 5.5 to 40 V, ICC = 0 mA
ICC(lim)
Internal voltage-regulator current-limit
(3)
4.25
4.5
15
4.75
70
V
mA
The current-limit accuracy is maintained when the current limit is set between 50 mA and 300 mA, and it includes the deviation of the
current-limit threshold voltage V(LIMx_th).
6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE AND CURRENT-LIMIT
td(SENSE_SEL_r)
Current-sense delay time from the rising edge
of SENSE_SEL (1)
V(ENx) ≥ 2 V, SENSE_EN = GND,
SENSE_SEL rise from 0 to 5 V
10
µs
td(SENSE_SEL_f)
Current-sense delay time from the falling edge
of SENSE_SEL (1)
V(ENx) ≥ 2 V, SENSE_EN = GND,
SENSE_SEL fall from 5 to 0 V
10
µs
td(SENSE_EN_r)
Current-sense delay time from rising edge of
SENSE_EN (1)
V(ENx) ≥ 2 V, SENSE_EN rise from 0 to
5V
10
µs
td(SENSE_EN_f)
Current-sense delay time from falling edge of
SENSE_EN (1)
V(ENx) ≥ 2 V, SENSE_EN fall from 5 to
0V
10
µs
FAULT DETECTION
t(PD_RC)
Reverse current (Short-to-BAT) shutdown
deglitch time
Delay to shut down the switch or LDO
after a drop over ron becomes negative,
I(OUTx) = –200 mA (typical), TA = 25°C
t(BLK_RC)
Reverse current blanking time
Blanking time for reverse-current
detection after power up, the rising
edge of the ENx pin, or the current
limiting event is over
(1)
6
5
16
20
µs
ms
Design information; specified by design; not production tested.
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SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
6.7 Typical Characteristics
at VI = 14 V (unless otherwise specified)
4.5
3
2.5
3.5
Quiescent Current (mA)
Quiescent Current (mA)
4
3
2.5
2
1.5
40qC
25qC
125qC
1
2
1.5
1
40qC
25qC
125qC
0.5
0.5
0
0
50
100
150
200
Output Current (mA)
250
300
0
Figure 1. Quiescent Current vs Output Current
(TPS7B7702-Q1)
100
150
200
Output Current (mA)
250
300
D012
Figure 2. Quiescent Current vs Output Current
(TPS7B7701-Q1)
3.5
0.8
3
0.75
Quiescent Current (mA)
Shutdown Current (PA)
50
D001
2.5
2
1.5
1
0.7
0.65
0.6
0.55
0.5
I(shutdown) (VI = 13.5 V)
I(shutdown) (VI = 40 V)
0
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0.5
-40
110 125
-25
-10
5
D002
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
D003
IO = 0.1 mA
Figure 3. Shutdown Current vs Ambient Temperature
(TPS7B7702-Q1)
Figure 4. Quiescent Current vs Ambient Temperature
(TPS7B7702-Q1)
0.6
1.28
1.27
1.26
1.25
0.5
FB Voltage (V)
Quiescent Current (mA)
0.55
0.45
0.4
1.24
1.23
1.22
1.21
1.2
0.35
1.19
0.3
-40
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
1.18
-40
-25
-10
D013
IO = 0.1 mA
5
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
D004
IO = 10 mA
Figure 5. Quiescent Current vs Ambient Temperature
(TPS7B7701-Q1)
Figure 6. FB Voltage vs Ambient Temperature
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Typical Characteristics (continued)
306
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
40qC
25qC
125qC
304
302
Current Limit (mA)
Dropout Voltage (V)
at VI = 14 V (unless otherwise specified)
300
298
296
294
292
0
30
60
90
120 150 180 210
Output Current (mA)
240
270
290
-40
300
-25
-10
D005
5
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
D006
ILIM = 300 mA
Figure 7. Dropout Voltage vs Output Current
Figure 8. Current Limit vs Ambient Temperature
0.52
40qC
25qC
125qC
0.516
100
Current Sense Ratio, 1/'i
Power Supply Rejection Ration (dB)
120
80
60
40
20
0.512
0.508
0.504
0.5
0.496
0.492
0.488
0.484
0
1E+1
0.48
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
CO = 10 µF
1E+6 5E+6
0
30
60
90
D007
120 150 180 210
Output Current (mA)
240
270
300
D009
IO = 10 mA
Figure 9. PSRR TPS7B770x-Q1
Figure 10. Current Sense Ratio vs Output Current,
TPS7B7702-Q1 Channel 1
0.52
40qC
25qC
125qC
Current Sense Ratio, 1/'i
0.516
0.512
10 V/div
IN
0.508
5 V/div
0.504
0.5
OUT1
0.496
200 mV/div AC
0.492
OUT1
0.488
0.484
100 mA/div
0.48
IO
0
30
60
90
120 150 180 210
Output Current (mA)
240
270
300
D010
Figure 11. Current Sense Ratio vs Output Current,
TPS7B7702-Q1 Channel 2
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VO = 8.5 V
CO = 10 µF
IO = 1 to 170 mA
Figure 12. 1-mA to 170-mA Load Transient
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Typical Characteristics (continued)
at VI = 14 V (unless otherwise specified)
10 V/div
5 V/div
IN
IN
5 V/div
20 mV/div AC
OUT2
OUT1
100 mV/div AC
OUT2
20 mV/div AC
OUT2
100 mA/div
IO
VO = 5 V
CO = 10 µF
IO = 1 to 100 mA
VO = 8.5 V
Figure 13. 1-mA to 100-mA Load Transient
IO = 50 mA
Figure 14. 9-V to 16-V Line Transient (1 V/µs)
5 V/div
IN
5 V/div
20 mV/div AC
IN
OUT1
5 V/div
OUT1
20 mV/div AC
5 V/div
OUT2
OUT2
VO = 5 V
IO = 50 mA
VO = 8.5 V
Figure 15. 9-V to 16-V Line Transient (1 V/µs)
IO = 100 mA
VI = 0 to 14 V
Figure 16. Power Up (1 V/µs)
100
Load Capacitance (PF)
80
5 V/div
IN
5 V/div
OUT1
60
Stable Region
40
20
5 V/div
OUT2
2.2
0.001
VO = 5 V
IO = 100 mA
Figure 17. Power Up (1 V/µs)
1
2
3
4
ESR of Output Capacitance (:)
5
VI = 0 to 14 V
Figure 18. Load Capacitance vs ESR of Output Capacitance
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7 Detailed Description
7.1 Overview
The TPS7B770x-Q1 family of devices feature a single- or dual-channel, high voltage LDO with a current-sense
function. These devices operate with a wide input-voltage range of 4.5 V to 40 V (45-V load dump protection).
These devices also offers protection of antenna lines against electrostatic discharge (ESD) and from short-toground, short-to-battery, and thermal overstress. Device output voltage is adjustable from 1.5 V to 20 V through
an external resistor divider. Alternatively, each channel can be configured as a switch.
These devices monitor the load. Accurate current sense allows for detection of open, normal, and short-circuit
conditions without the need of further calibration. The current sense can also be multiplexed between channels
and devices to save ADC resources. Each channel also provides an adjustable current limit with external
resistor.
7.2 Functional Block Diagram
Reverse polarity
OUT1
OUT2
IN
Reverse
current
monitor
Current
sense
EA
LIM
SENSE_EN
FB
Vref
1.233 V
Current
sense
FB1
FB2
SENSE_SEL
Logic control
EN1
EN2
SENSE1
SENSE2
ERR
Open and
short
protection
LIM1
LIM2
UVLO
VCC
Regulator
Reverse
current
protection
Temperature
sense
Internal
reference
GND
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7.3 Feature Description
7.3.1 Fault Detection and Protection
The device includes both analog current sense and digital fault pins for full diagnostics of different fault
conditions.
The current-sense voltage scale is selected based on the output-current range of interest. Figure 19 shows a
recommended setting that allows for full diagnostics of each fault. Before the device goes into current-limit mode,
the output current-sense voltage is linearly proportional to the actual load current. During a thermal-shutdown
(TSD) and short-to-battery (STB) condition, the current-sense voltage is set to the fault voltage level that is
specified in the Electrical Characteristics table.
3.3
Reverse Current and Short to Battery
3.2 V (Typical)
3.05
3.0
Thermal Shutdown
2.85 V (Typical)
Current Sense Voltage,
VSENSE (V)
2.7
2.65
Short Circuit and Current limit
(2.55 V Typical)
2.4
Linear Current Sense
Band Up to 2.4 V
Open load
Overcurrent
Normal
Short Circuit
Operating Range
Figure 19. Functionality of the Current-Sense Output
7.3.2 Short-Circuit and Overcurrent Protection
The current limit on each channel is programmed by selecting the external resistor. The voltage on LIMx pin is
compared with an internal voltage reference. When the threshold is exceeded, the current limit is triggered. The
output of the current limited channel continues to remain on and the current is limited.
Under current-limit status, the ERR pin asserts low and the SENSE voltage of the fault channel is internally
pulled up to a voltage rail between 2.4 V and 2.65 V as shown in Figure 19. At this moment, the output voltage is
not disabled. The microcontroller (MCU) should monitor the voltage at the SENSEx pin or ERR pin to disable the
faulted channel by pulling the ENx pin low. If a current-limit condition exists for a long period of time, thermal
shutdown can be triggered and shutdown the output.
7.3.3 Short-to-Battery and Reverse Current Detection
Shorting the OUT pin to the battery because of a fault in the system is possible. Each channel detects this failure
by comparing the voltage at the OUT and IN pins before the switch turns on. Each time the LDO switch is
enabled on the rising edge of the EN pin or during the exiting of the thermal shutdown, the short-to-battery
detection occurs. At this moment, if the device detects the short-to-battery fault, the LDO switch is latched off, the
ERR pin is asserted low, and the fault-channel SENSE voltage is pulled up internally to a voltage rail between
3.05 V and 3.3 V. The device operates normally when the short-to-battery is removed and the EN pin is toggled.
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Feature Description (continued)
During normal operation if a short-to-battery fault results in reverse current for more than 5 µs (typical), the LDO
switch is latched off and the ERR pin is asserted low. To remove the latched condition after a short-to-battery
(reverse current) fault, the condition must first be removed and then the EN pin must be toggled.
Series inductance and the output capacitor can produce ringing during power up or recovery from current limit,
resulting in an output voltage that temporarily exceeds the input voltage. The 16-ms (typical) reverse-current
blanking can help filter this ringing.
For the dual-channel antenna LDO application, if both channels are enabled and one channel is shorted to
ground after power up, the current drawn from the input capacitor can result in a temporary dip in the input
voltage, which can trigger the reverse-current detection fault. To avoid this false trigger event, care must be
taken when selecting the input capacitor; an increase of the input capacitor value is recommended.
7.3.4 Thermal Shutdown
The device incorporates a TSD circuit as a protection from overheating. For continuous normal operation, the
junction temperature should not exceed the TSD trip point. If the junction temperature exceeds the TSD trip
point, the output is turned off. When the junction temperature decreases by 15°C (typical) than the TSD trip point,
the output is turned on again. The SENSE voltage is internally pulled up to a voltage rail between 2.7 V and 3 V
during TSD status.
NOTE
The purpose of the design of the internal protection circuitry of the TPS7B770x-Q1 family
of devices is to protect against overload conditions and is not intended as a replacement
for proper heat-sinking. Continuously running the device into thermal shutdown degrades
device reliability.
7.3.5 Integrated Reverse-Polarity Protection
The device integrates a reverse-connected PMOS to block the reverse current during reverse polarity at the input
and output short-to-battery condition. A special ESD structure at the input is specified to withstand –40 V.
7.3.6 Integrated Inductive Clamp
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp to help dissipate the inductive energy stored in the cable. An internal diode
is connected between OUT and GND pins with a DC-current capability of 300 mA for inductive clamp protection.
7.3.7 Undervoltage Lockout
The device includes an undervoltage lockout (UVLO) threshold that is internally fixed. The undervoltage lockout
activates when the input voltage on the IN pin drops below V(UVLO). The UVLO makes sure that the regulator is
not latched into an unknown state during low input-supply voltage. If the input voltage has a negative transient
that drops below the UVLO threshold and then recovers, the regulator shuts down and powers up with a normal
power-up sequence when the input voltage is above the required levels.
Table 1. Fault Table
FAILURE MODE
Open load
Normal
Overcurrent
Short-circuit or current
limit
12
V(SENSE)
ERR
LDO SWITCH OUTPUT
LATCHED
IO u R(SENSE)
198
HIGH
Enabled
No
HIGH
Enabled
No
HIGH
Enabled
No
2.4 to 2.65 V
LOW
Enabled
No
Thermal shutdown
2.7 to 3 V
LOW
Disabled
No
Output short-to-battery
3.05 to 3.3 V
LOW
Disabled
Yes
Reverse current
3.05 to 3.3 V
LOW
Disabled
Yes
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7.3.8 Enable (EN, EN1, and EN2)
The TPS7B7702-Q1 device features two active-high enable inputs, EN1 and EN2. The EN1 pin controls output
voltage 1, OUT1, and the EN2 pin controls output voltage 2, OUT2. The devices consumes a maximum of
shutdown current 5-µA when the ENx pins are low. Both the EN1 and EN2 pins have a maximum internal
pulldown of 10 µA.
The TPS7B7701-Q1 device features one active-high enable input. The device consumes a maximum shutdown
current of 5 µA when the EN pin is low. The EN pin has a maximum internal pull down of 10 µA.
7.3.9 Internal Voltage Regulator (VCC)
The device features an internal regulator that regulates the input voltage to 4.5 V to power all internal circuitry.
Bypass a 1-µF ceramic capacitor from the VCC pin to the GND pin for frequency compensation. The VCC pin can
be used as a power supply for external circuitry with up to 15-mA current capability.
7.3.10 Current Sense Multiplexing
The two, independent current sense pins (one for each channel) provide flexibility in the system design. When
the ADC resource is limited, the device allows the multiplexing of the current sense pins by only using one
current sense pin and one ADC to monitor all the antenna outputs.
The SENSE_SEL pin (TPS7B7702-Q1 only) selects the channels to monitor the current. The SENSE_EN pin
enables and disables the SENSE pin, allowing multiplexing between chips. Therefore, only one ADC and one
resistor is needed for current-sense diagnostics of multiple outputs. When the SENSE1 pin is connected to an
ADC, the current flow through both channels can be sensed by changing the electrical level at the SENSE_SEL
pin.
Table 2 lists the selection logic for the current sense.
Table 2. SENSE_EN and SEN_SEL Logic Table
SENSE_EN
SEN_SEL
SENSE1 Status
LOW
LOW
CH1 current
SENSE2 Status
CH2 current
LOW
HIGH
CH2 current
HIGH impedance
HIGH
—
HIGH impedance
HIGH impedance
Figure 20 shows the application of four antenna channels sharing one ADC resource.
SENSE_EN
Current
Sense
Antenna AM/FM
SENSE_SEL
SENSE2
Antenna FM2
SENSE1
MCU
SENSE_EN
ADC
R(SENSE)
Current
Sense
Antenna DAB
SENSE_SEL
SENSE2
Antenna GPS
SENSE1
Figure 20. Current Multiplexing Application Block
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7.3.11 Adjustable Output Voltage (FB, FB1, and FB2)
Using an external resistor divider selects an output voltage between 1.5 V and 20 V. Use Table 2 to calculate the
output voltage (VO). The recommended value for both R1 and R2 is less than 100 kΩ.
V(FB) u (R1 R2)
VO
R2
where
•
V(FB) = 1.233 V
(1)
OUT
R1
TPS7B770x-Q1
FB
R2
Figure 21. TPS7B770x-Q1 Output Voltage Setting Connection
The TPS7B770x-Q1 family of devices can also be used as a current-limited switch by connecting the FB pin to
the GND pin.
7.4 Device Functional Modes
7.4.1 Operation With IN < 4.5 V
The maximum UVLO voltage is 4 V and the device operates at an input voltage above 4.5V. The device can also
operate at lower input voltage. No minimum UVLO voltage is specified. At an input voltage below the actual
UVLO voltage, the device does not operate.
7.4.2 Operation With EN Control
The threshold of EN rising edge is 2 V (maximum). With the EN pin held above that voltage and the input voltage
above 4.5 V, the device becomes active. The EN falling edge is 0.7 V (minimum). Holding the EN pin below that
voltage disables the device which therefore reduces the quiescent current of the device.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B770x-Q1 family of devices is a single- or dual-channel 300-mA LDO regulator with high, accurate
current sense and a programmable current-limit function. Use the PSPICE transient model to evaluate the base
function of the devices. Go to www.ti.com to download the PSPICE model and user's guide for the devices.
8.2 Typical Application
Figure 22 shows the typical application circuit for the TPS7B770x-Q1 family of devices. Different values of
external components can be used depending on the end application. An application can require a larger output
capacitor during fast load steps to prevent large drops on output voltage. TI recommends a low-ESR ceramic
capacitor with a dielectric of type X5R or X7R.
Active antenna
Reverse polarity
Battery
Input
Filter coil
OUT1
OUT2
IN
Filter coil
Cable
10 µF
10 µF
Reverse
current
monitor
Current
sense
EA
LIM
SENSE_EN
MCU I/O
FB
FB1
FB2
Vref
1.233 V
Current
sense
SENSE_SEL
MCU I/O
Logic control
EN1
EN2
MCU I/O
SENSE1
SENSE2
ERR
1 µF
R(SENSE)
LIM1
LIM2
UVLO
R(LIM)
VCC
MCU I/O
Open and
short
protection
Reverse
current
protection
Regulator
Temperature
sense
Internal
reference
1 µF
GND
Figure 22. TPS7B770x-Q1 Typical Application
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the design parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4.5 to 40 V
Output voltage
1.5 to 20 V
Output capacitor range
2.2 to 100 µF
Output Capacitor ESR range
0.001 to 5 Ω
SENSE resistor
See the Current Sense Resistor Selection section
Programmable current limit
50 to 300 mA
8.2.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process, determine the following:
Input voltage
Output voltage
Output current
Current limit
ADC voltage rating
8.2.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 10 µF. The voltage rating must be greater than the maximum
input voltage.
8.2.2.2 Output Capacitor
The device requires an output capacitor to stabilize the output voltage. The capacitor value should be between
2.2 µF and 100 µF. The ESR range should be between 1 mΩ and 5 Ω. TI recommends selecting a ceramic
capacitor with low ESR to improve the load transient response.
8.2.2.3 Current Sense Resistor Selection
The current-sense outputs, SENSEx (SENSE, SENSE1, and SENSE2), are proportional to the output current at
the OUT, OUT1, and OUT2 pins with a factor of 1/198. An output resistor, R(SENSE), must be connected between
the SENSEx pin and ground to generate a current sense voltage to be sampled by ADC. Use Equation 2 to
calculate the voltage at SENSEx pin (V(SENSEx)).
V(SENSEx) I(SENSEx) u R(SENSEx)
where
•
I(SENSEx)
I(OUTx)
198
(2)
For this example, select 1.5 kΩ as a value for R(SENSEx). Do not consider the resistor and current-sense accuracy.
For a load current of 198 mA, use Equation 3 to calculate the value of V(SENSEx).
198 mA
I(SENSEx)
1 mA o V(SENSEx) 1 mA u 1.5 k: 1.5 V
198
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(3)
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To avoid any overlap between normal operation and current-limit or short-to-ground phase, using Equation 4 to
select the value of the SENSE resistor is recommended.
198 u 2.4 V
R(SENSEx) d
IOmax
where
•
•
•
198 is the output current to current-sense ratio
2.4 V is the minimum possible voltage at the SENSEx pin under a short-circuit fault case
IOmax is the maximum possible output current under normal operation
(4)
To stabilize the current-sense loop, connecting a 1-µF ceramic capacitor at the SENSE, SENSE1, or SENSE2
pin is required. Table 4 lists the current sense accuracy across temperature.
Table 4. Current Sense Accuracy
OUTPUT CURRENT
CURRENT SENSE ACCURACY
5 mA to 10 mA
20%
10 mA to 50 mA
10%
50 mA to 100 mA
5%
100 mA to 300 mA
3%
8.2.2.4 Current-Limit Resistor Selection
The current at the LIMx pins (LIM, LIM1, and LIM2) is proportional to the load current at the OUTx (OUT, OUT1,
and OUT2) pins and is internally connected to a current-limit comparator referenced to 1.233 V. The current limit
is programmable through the external resistor connected at LIMx pin. Use Equation 5 to calculate the value of
the external resistor, R(LIMx). The programmable current limit accuracy is 8% maximum across all conditions. The
internal current limit of the device is set by shorting the LIM pin to ground. Because the current limit varies by
8%, Equation 6 shows how to calculate the minimum current limit value, and Equation 7 shows how to calculate
the maximum current limit value.
1.233 V
R(LIMx)
u 198
I(LIMx)
where
I(LIMx)(typ)
•
I(LIMx)(min)
I(LIMx)(max)
1.233 V
u 198
R(LIMx)
I(LIMx)(typ) u 0.92
I(LIMx)(typ) u 1.08
(5)
§ 1.233 V
·
u 198 ¸
0.92 ¨
¨ R(LIMx)
¸
©
¹
(6)
§ 1.233 V
·
u 198 ¸
1.08 ¨
¨ R(LIMx)
¸
©
¹
(7)
Select a maximum current-limit value of 200 mA and use Equation 8 to calculate the value of R(LIMx).
1.08 u 198 u 1.233 V
R(LIMx)
I(LIMx)(max)
(8)
Using Equation 8 yields a RLIMx value of 1.318 kΩ. The closest 1% resistor that can be selected is 1.33 kΩ. Now
using Equation 7 and plugging in 1.33 kΩ for RLIMx yields a maximum current of 198.2 mA. Keep in mind this
result does not include resistor tolerance in the calculation. To make sure that the current does not exceed the
set amount, resistor tolerance must also be included in the equation.
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8.2.3 Application Curves
5 V/div
5 V/div
IN
IN
5 V/div
5 V/div
OUT1
OUT1
5 V/div
5 V/div
OUT2
OUT2
VO = 8.5 V
IO = 100 mA
VI = 0 to 14 V
Figure 23. Power Up (1 V/µs)
VO = 5 V
IO = 100 mA
VI = 0 to 14 V
Figure 24. Power Up (1 V/µs)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply with a range between 4.5 V and 40 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the TPS7B770x-Q1
device, TI recommends adding an 10-µF electrolytic capacitor and a ceramic bypass capacitor at the input.
10 Layout
10.1 Layout Guidelines
For the layout of TPS7B770x-Q1 device, place the input and output capacitors close to the device as shown in
Figure 25. To enhance the thermal performance, TI recommends surrounding the device with some vias.
Minimize equivalent-series inductance (ESL) and ESR to maximize performance and provide stability. Place
every capacitor as close as possible to the device and on the same side of the PCB as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use long traces because they can negatively impact system performance and cause
instability.
If possible, and to maintain the maximum performance specified in this device data sheet, use the same layout
pattern used for the TPS7B770x-Q1 evaluation board, available online at www.ti.com/tool/TPS7B7702EVM.
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10.2 Layout Example
OUT1
VIN
OUT2
Thermal Pad
GND
(GND)
Figure 25. TPS7B770x-Q1 Layout Example
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TPS7B7701-Q1, TPS7B7702-Q1
SLVSCE8C – JANUARY 2015 – REVISED SEPTEMBER 2018
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TPS7B7702-Q1 Evaluation Module User's Guide
11.2 Related Links
Table 5 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS7B7701-Q1
Click here
Click here
Click here
Click here
Click here
TPS7B7702-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2015–2018, Texas Instruments Incorporated
Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7B7701QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B7701
TPS7B7702QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B7702
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS7B7701QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7B7701QPWPRQ1
HTSSOP
PWP
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
SEATING
PLANE
0.1 C
PIN 1 INDEX
AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
4.5
4.3
16X
(0.15) TYP
SEE DETAIL A
9
8
0.25
GAGE PLANE
3.55
2.68
0 -8
16
1
2.46
1.75
1.2 MAX
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
THERMAL
PAD
4223595/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 8
METAL COVERED
BY SOLDER MASK
(2.46)
16X (1.5)
16X (0.45)
SEE DETAILS
SYMM
1
16
(1.3) TYP
(R0.05) TYP
(0.65)
SYMM
(3.55)
(5)
NOTE 8
14X (0.65)
( 0.2) TYP
VIA
8
9
(1.35) TYP
SOLDER MASK
DEFINED PAD
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223595/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016J
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.46)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
16X (0.45)
METAL COVERED
BY SOLDER MASK
1
16
(R0.05) TYP
(3.55)
BASED ON
0.125 THICK
STENCIL
SYMM
14X (0.65)
9
8
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
2.75 X 3.97
2.46 X 3.55 (SHOWN)
2.25 X 3.24
2.08 X 3.00
4223595/A 03/2017
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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