Texas Instruments | LM5176-Q1 55-V Wide VIN Synchronous 4-Switch Buck-Boost Controller | Datasheet | Texas Instruments LM5176-Q1 55-V Wide VIN Synchronous 4-Switch Buck-Boost Controller Datasheet

Texas Instruments LM5176-Q1 55-V Wide VIN Synchronous 4-Switch Buck-Boost Controller Datasheet
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LM5176-Q1
SNVSB46 – SEPTEMBER 2018
LM5176-Q1 55-V Wide VIN Synchronous 4-Switch Buck-Boost Controller
1 Features
3 Description
•
The LM5176-Q1 is a synchronous four-switch buckboost DC/DC controller capable of regulating the
output voltage at, above, or below the input voltage.
The LM5176-Q1 operates over a wide input voltage
range of 4.2 V to 55 V (60 V absolute maximum) to
support a variety of applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Temperature Grade 1: -40°C to 125°C TA
Single Inductor Buck-Boost Controller for StepUp/Step-Down DC/DC Conversion
Wide VIN: 4.2 V (2.5 V with bias) to 55 V (60 V
Maximum)
Flexible VOUT: 0.8 V to 55 V
VOUT Short Protection
High Efficiency Buck-Boost Transition
Adjustable Switching Frequency
Optional Frequency Sync and Dithering
Integrated 2-A MOSFET Gate Drivers
Cycle-by-Cycle Current Limit and Optional Hiccup
Optional Input or Output Average Current Limiting
Programmable Input UVLO and Soft-Start
Power Good and Output Overvoltage Protection
Available in HTSSOP-28 Package
Create a Custom Design Using the LM5176-Q1
with the WEBENCH Power Designer
The LM5176-Q1 employs current-mode control both
in buck and boost modes of operation for superior
load and line regulation. The switching frequency is
programmed by an external resistor and can be
synchronized to an external clock signal.
The device also features a programmable soft-start
function and offers protection features including
cycle-by-cycle current limiting, input undervoltage
lockout (UVLO), output overvoltage protection (OVP),
and thermal shutdown. In addition, the LM5176-Q1
features optional average input or output current
limiting, optional spread spectrum to reduce peak
EMI, and optional hiccup mode protection in
sustained overload conditions.
Device Information(1)
PART NUMBER
LM5176QPWP
2 Applications
•
•
•
•
•
PACKAGE
HTSSOP-28
BODY SIZE (NOM)
9.7 mm x 4.4 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Automotive Start-Stop Systems
Backup Battery and Supercapacitor Charging
USB Power Delivery
Battery Powered Systems
LED Lighting
4 Simplified Schematic
VIN
Power Good
ISNS(+)
VIN
ISNS(-)
EN/UVLO
VISNS
VCC
Enable
VOUT
BOOT1
HDRV1
PGOOD
SW1
SS
LDRV1
SLOPE
CS
LM5176
RT/SYNC
CSG
LDRV2
COMP
SW2
AGND
BOOT2
PGND
VCC
BIAS
FB
MODE
VCC
DITH
HDRV2
VOSNS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5176-Q1
SNVSB46 – SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
6
6
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
Custom Design with WEBENCH Tools.................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
5 Revision History
2
DATE
REVISION
NOTES
September 2018
*
Initial Release
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6 Pin Configuration and Functions
HTSSOP-28
PWP Package
Top View
EN/UVLO
1
28
SW1
VIN
2
27
HDRV1
VISNS
3
26
BOOT1
MODE
4
25
LDRV1
DITH
5
24
BIAS
RT
6
23
VCC
SLOPE
7
22
PGND
SS
8
21
LDRV2
COMP
9
20
BOOT2
AGND
10
19
HDRV2
FB
11
18
SW2
VOSNS
12
17
PGOOD
ISNS(±)
13
16
CS
ISNS(+)
14
15
CSG
LM5176
HTSSOP-28
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Pin Functions
PIN
NAME
DESCRIPTION
HTSSOP
EN/UVLO
1
Enable pin. For EN/UVLO < 0.4 V, the LM5176-Q1 is in a low current shutdown mode. For EN/UVLO > 1.22 V,
the PWM function is enabled, provided VCC exceeds the VCC UV threshold.
VIN
2
The input supply pin to the IC. Connect VIN to a supply voltage between 4.2 V and 55 V.
VISNS
3
VIN sense input. Connect to power stage input rail.
MODE
4
DITH
5
A capacitor connected between the DITH pin and AGND is charged and discharged with a current source. As
the voltage on the DITH pin ramps up and down the oscillator frequency is modulated by 10% of the nominal
frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync
mode, the DITH pin voltage is ignored.
RT/SYNC
6
Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set
the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
SLOPE
7
A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable
current mode operation in both buck and boost mode.
SS
8
Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.
COMP
9
Output of the error amplifier. An external RC network connected between COMP and AGND compensates the
regulator feedback loop.
AGND
10
Analog ground of the IC.
FB
11
Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to
the FB pin.
VOSNS
12
VOUT sense input. Connect to the power stage output rail.
ISNS(–)
ISNS(+)
13
14
Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+)
and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage
across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active
and starts discharging the soft-start capacitor to regulate the drop across ISNS(+) and ISNS(-) to 50 mV. Short
ISNS(+) and ISNS(-) together to disable this feature.
CSG
15
The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of
the current sense resistor.
CS
16
The positive input to the PWM current sense amplifier.
PGOOD
17
Power Good open drain output. PGOOD is pulled low when FB is outside a -9%/+10% regulation window around
the 0.8-V VREF.
SW2
SW1
18
28
The boost and the buck side switching nodes respectively.
HDRV2
HDRV1
19
27
Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.
BOOT2
BOOT1
20
26
An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to
provide bias to the high-side MOSFET gate drivers.
LDRV2
LDRV1
21
25
Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.
PGND
22
Power ground of the IC. The high current ground connection to the low-side gate drivers.
VCC
23
Output of the VCC bias regulator. Connect capacitor to ground.
BIAS
24
Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce
power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin.
-
The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB
ground plane for improved power dissipation.
PowerPAD™
4
1.38 V < MODE < 2.22 V : CCM, Hiccup Enabled
(Set RMODE resistor to AGND = 93.1 kΩ)
2.6 V < MODE < VCC: CCM, Hiccup Disabled
(Set RMODE resistor to AGND = 200 kΩ or connect
to VCC)
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7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–)
–0.3
60
BIAS
–0.3
40
FB, SS, DITH, RT/SYNC, SLOPE, COMP
–0.3
3.6
–1
60
SW1, SW2
SW1, SW2 (20 ns transient)
–5.0
65
VCC, MODE, PGOOD
–0.3
8.5
LDRV1, LDRV2
–0.3
8.5
BOOT1, HDRV1 with respect to SW1
–0.3
8.5
BOOT2, HDRV2 with respect to SW2
–0.3
8.5
BOOT1, BOOT2
–0.3
68
ISNS(+) with respect to ISNS(-)
-0.3
0.3
CS, CSG
–0.3
0.3
Operating junction temperature
–40
150
Storage temperature, Tstg
-65
150
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
UNIT
(1)
±2000
HBM ESD Classification Level 2
Charged-device model (CDM), per AEC Q100-011
All pins
±500
CDM ESD Classification Level C4B
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
VIN
Input bias voltage
4.2
55
VISNS
Input power stage voltage with external bias (BIAS ≥ 5 V
or VIN ≥ 4.5 V)
2.5
55
BIAS
Bias supply voltage range (when VCC in regulation)
8
36
VOSNS
Output voltage range
0.8
55
EN/UVLO
Enable voltage range
0
55
ISNS(+), ISNS(-)
Average current sense common mode range
0
55
–40
150
°C
100
600
kHz
TJ
Operating temperature range
Fsw
Operating frequency range
(1)
(2)
(2)
V
Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions,
see Electrical Characteristics .
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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7.4 Thermal Information
LM5176-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
32.6
RθJC(top)
Junction-to-case (top) thermal resistance
21.4
RθJB
Junction-to-board thermal resistance
8.2
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
8.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated. (1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
2.6
10
µA
2
4
mA
SUPPLY VOLTAGE (VIN)
IQ
VIN shutdown current
VEN/UVLO = 0 V
VIN operating current
VEN/UVLO = 2 V, VFB = 0.9 V
VVCC(VIN)
Regulation voltage
VBIAS = 0 V, VCC open
6.95
7.35
7.88
VUV(VCC)
VCC Undervoltage lockout
VCC increasing
3.11
3.27
3.43
VCC
Undervoltage hysteresis
176
IVCC
VCC current limit
VVCC = 0 V
ROUT(VCC)
VCC regulator output impedance
IVCC = 30 mA, VIN = 4 V
BIAS switchover voltage
VIN = 24 V
VEN(STBY)
Standby threshold
EN/UVLO rising
IEN(STBY)
Standby source current
VEN/UVLO = 1.1 V
VEN(OP)
Operating threshold
ΔIHYS(OP)
V
mV
65
mA
8
16
Ω
7.25
8
8.75
V
0.55
0.82
0.97
V
1
2
3
µA
EN/UVLO rising
1.17
1.22
1.29
V
Operating hysteresis current
VEN/UVLO = 1.5 V
2.15
3.15
4.25
µA
ISS
Soft-start pull up current
VSS = 0 V
3.75
5
6.35
µA
VSS(CL)
SS clamp voltage
SS open
1.21
V
VFB - VSS
FB to SS offset
VSS = 0 V
-18
mV
BIAS
VBIAS(SW)
EN/UVLO
SS
EA (ERROR AMPLIFIER)
VREF
Feedback reference voltage
FB = COMP
0.788
0.800
0.812
gmEA
Error amplifier gm
ISINK/ISOURCE
COMP sink/source current
ROUT
Amplifier output resistance
BW
Unity gain bandwidth
IBIAS(FB)
Feedback pin input bias current
FB in regulation
fSW(1)
Switching Frequency 1
RT = 40 kΩ
175
200
225
fSW(2)
Switching Frequency 2
RT = 20 kΩ
350
390
430
1.31
VFB=VREF ± 300 mV
V
mS
280
µA
20
MΩ
2
MHz
25
nA
FREQUENCY
(1)
6
kHz
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
DITHER
IDITHER
Dither source/sink current
VDITHER
Dither high threshold
1.27
11
Dither low threshold
1.16
µA
V
SYNC
VSYNC
Sync input high threshold
2.1
Sync input low threshold
PWSYNC
1.2
Minimum sync input pulse width
50
V
ns
CURRENT LIMIT
VCS(BUCK)
Buck current limit threshold (Valley)
VIN = VVISNS = 24 V, VVOSNS = 12 V,
VSLOPE = 0 V
66
80
94
VCS(BOOST)
Boost current limit threshold (Peak)
VIN = VVISNS = 12 V, VVOSNS = 18 V,
VSLOPE = 0 V
100
120
140
IBIAS(CS/CSG)
CS/CSG pin bias current
VCS = VCSG = 0 V
IOFFSET(CS/CS
CSG pin bias current
VCS = VCSG = 0 V
mV
-80
19
µA
G)
CONSTANT CURRENT LOOP
VSNS
Average current loop regulation target
VISNS(-) = 24 V, sweep ISNS(+), VSS =
0.8 V
ISNS
ISNS(+)/ISNS(–) pin bias currents
VISNS(+) = VISNS(–) = VIN = 24 V
3
µA
Gm
gm of soft-start pull down amplifier
VISNS(+)–VISNS(–) = 55 mV, VSS = 0.5
V
1
mS
Buck adaptive slope current
VIN = VVISNS = 24 V, VVOSNS = 12 V,
VSLOPE = 0 V
24
30
35
Boost adaptive slope current
VIN = VVISNS = 12 V, VVOSNS = 18 V,
VSLOPE = 0 V
13
17
21
43
50
57
mV
SLOPE
ISLOPE
gmSLOPE
µA
Slope compensation amplifier gm
2
µS
MODE
IMODE
Source current out of MODE pin
17
20
23
µA
VCCM_HIC
CCM with hiccup threshold
1.18
1.28
1.38
V
VCCM
CCM no hiccup threshold
2.22
2.4
2.6
V
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PGOOD
VPGD
PGOOD trip threshold for falling FB
Measured with respect to VREF
–9
%
PGOOD trip threshold for rising FB
Measured with respect to VREF
10
%
2.5
%
Hysteresis
ILEAK(PGD)
PGOOD leakage current
ISINK(PGD)
PGOOD sink current
VPGOOD = 0.4 V
Output overvoltage threshold at FB pin
Measured with respect to VREF
2
4.2
100
nA
6.5
mA
OUTPUT OVP
VOVP
Hysteresis
10
%
2.5
%
NMOS DRIVERS
IHDRV1,2
ILDRV1,2
RHDRV1,2
VUV(BOOT1,2)
RLDRV1,2
Driver peak source current
VBOOT - VSW = 7 V
1.8
Driver peak sink current
VBOOT - VSW = 7 V
2.2
Driver peak source current
1.8
Driver peak sink current
2.2
A
Driver pull up resistance
VBOOT - VSW = 7 V
1.8
Driver pull down resistance
VBOOT - VSW = 7 V
1.1
BOOT1,2 to SW1,2 UVLO threshold
HDRV1,2 shut off
3.4
V
BOOT1,2 to SW1,2 UVLO hysteresis
HDRV1,2 start switching
150
mV
Driver pull up resistance
1.7
Driver pull down resistance
1.3
tDT1
Dead time HDRV1,2 off to LDRV1,2 on
45
tDT2
Dead time LDRV1,2 off to HDRV1,2 on
45
Ω
Ω
ns
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
TSD(HYS)
Thermal shutdown hysteresis
8
165
15
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7.6 Typical Characteristics
At TA = 25°C, unless otherwise stated.
100
99
96
EFFICIENCY (%)
EFFICIENCY (%)
98
97
96
95
92
88
84
94
VIN = 9V
VIN = 12V
VIN = 24V
80
93
5
10
15
20
VOUT=12 V
IOUT=5 A
25
30
VIN (V)
35
40
45
0
50
1
2
3
4
LOAD CURRENT (A)
D009
Fsw=300 kHz
L1=4.7 μH
VOUT =12 V
Figure 1. Efficiency vs VIN
5
6
D008
Fsw=300 kHz
L1=4.7 μH
Figure 2. Efficiency vs Load
600
8
6
400
VCC (V)
FREQUENCY (kHz)
500
300
4
200
2
100
0
10
0
20
30
40
50
60
RT (k:)
70
80
90
100
0
2
4
6
VIN (V)
D004
Figure 3. Oscillator Frequency
8
10
12
D002
Figure 4. VCC vs VIN
3.0
3.0
2.5
2.6
IIN (PA)
IIN (mA)
2.0
2.2
1.8
1.5
1.0
1.4
-40 qC
25 qC
125 qC
0.5
BIAS = 0V
BIAS = 12V
0.0
1.0
0
10
20
30
VIN (V)
40
50
60
0
D007
Figure 5. IIN Operating vs VIN
10
20
30
VIN (V)
40
50
60
D010
Figure 6. IIN Shutdown vs VIN
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise stated.
1.30
BUCK CURRENT LIMIT (mV)
110
VEN/UVLO (V)
1.26
1.22
1.18
1.14
1.10
-40
-20
0
20
40
60
80
TEMPERATURE (qC)
100
120
140
100
90
80
70
60
50
-40
-20
D013
Figure 7. ENABLE/UVLO Rising Threshold vs Temperature
0
20
40
60
80
TEMPERATURE (qC)
100
120
140
D014
Figure 8. Buck Current Limit vs Temperature
BOOST CURRENT LIMIT (mV)
150
140
SW1
130
SW2
120
110
IL1
100
90
-40
-20
0
20
40
60
80
TEMPERATURE (qC)
100
120
140
D015
VOUT=12 V
Figure 10. Forced CCM Operation (Boost)
Figure 9. Boost Current Limit vs Temperature
SW1
SW1
SW2
SW2
IL1
IL1
VOUT=12 V
VIN=11 V
VOUT=12 V
Figure 11. Forced CCM Operation (Buck-Boost)
10
VIN=6 V
VIN=12 V
Figure 12. Forced CCM Operation (Buck-Boost)
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise stated.
SW1
SW1
SW2
SW2
IL1
IL1
VOUT=12 V
VIN=13 V
VOUT=12 V
Figure 13. Forced CCM Operation (Buck-Boost)
VIN=24 V
Figure 14. Forced CCM Operation (Buck)
VOUT
500 mV/div
VOUT
500 mV/div
IOUT
2 A/div
IOUT
2 A/div
500 µs/div
500 µs/div
VIN=6 V
VOUT=12 V
Load 3A to 6A
VIN=12 V
Figure 15. Load Step (Boost)
Load 3A to 6A
Figure 16. Load Step (Buck-Boost)
VOUT
500 mV/div
VIN
10 V/div
IOUT
2 A/div
VOUT
1 V/div
500 µs/div
VIN=24 V
VOUT=12 V
VOUT=12 V
Load 3A to 6A
IL
5 A/div
VIN=8 V to 24 V
Figure 17. Load Step (Buck)
1 ms/div
VOUT=12 V
IOUT=3A
Figure 18. Line Transient
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise stated.
15
Overload
released
VOUT
5 V/div
VOUT (V)
12
9
6
3
IL
5 A/div
20 ms/div
VIN=24 V
VOUT=12 V
Hiccup Enabled
0
0
1
VIN=24 V
2
3
IOUT (A)
4
5
6
D021
RSNS=10 mΩ
Figure 19. Hiccup Mode Current Limit
Figure 20. Constant Current Constant Voltage (CCCV)
Operation
8 Detailed Description
8.1 Overview
The LM5176-Q1 is a wide input voltage four-switch buck-boost controller IC with integrated drivers for N-channel
MOSFETs. It operates in the buck mode when VIN is greater than VOUT and in the boost mode when VIN is less
than VOUT. When VIN is close to VOUT, the device operates in a proprietary transition buck or boost mode. The
control scheme provides smooth operation for any input/output combination within the specified operating range.
The buck or boost transition control scheme provides a low ripple output voltage when VIN equals VOUT without
compromising the efficiency.
The LM5176-Q1 integrates four N-Channel MOSFET drivers including two low-side drivers and two high-side
drivers, eliminating the need for external drivers or floating bias supplies. The internal VCC regulator supplies
internal bias rails as well as the MOSFET gate drivers. The VCC regulator is powered either from the input
voltage through the VIN pin or from the output or an external supply through the BIAS pin for improved efficiency.
The PWM control scheme is based on valley current mode control for buck operation and peak current mode
control for boost operation. The inductor current is sensed through a single sense resistor in series with the lowside MOSFETs. The sensed current is also monitored for cycle-by-cycle current limit. The behavior of the
LM5176-Q1 during an overload condition is dependent on the MODE pin programming (see MODE Pin
Configuration). If hiccup mode fault protection is selected, the controller turns off after a fixed number of
switching cycles in cycle-by-cycle current limit and restarts after another fixed number of clock cycles. The hiccup
mode reduces the heating in the power components in a sustained overload condition. If hiccup mode is disabled
through the MODE pin, the controller remains in a cycle-by-cycle current limit condition until the overload is
removed.
In addition to the cycle-by-cycle current limiting, the LM5176-Q1 also provides an optional average current
regulation loop that can be configured for either input or output current limiting. This is useful for battery charging
or other applications where a constant current behavior may be required.
The soft-start time of LM5176-Q1 is programmed by a capacitor connected to the SS pin to minimize the inrush
current and overshoot during startup.
The precision EN/UVLO pin supports programmable input undervoltage lockout (UVLO) with hysteresis. The
output overvoltage protection (OVP) feature turns off the high-side drivers when the voltage at the FB pin
exceeds the output overvoltage threshold (VOVP). The PGOOD output indicates when the FB voltage is inside the
PGOOD regulation window centered at VREF.
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8.2 Functional Block Diagram
BIAS
VIN
¨,HYS(OP)
+
-
EN/UVLO
VEN(OP)
VCC
OPERATING
EN & BIAS
LOGIC
IEN(STBY)
+
-
VEN(STBY)
THERMAL
SHUTDOWN
STANDBY
45 mV
1.2 V
PGOOD
+
1.1VREF
OV
VOVP
FB
+
+
ISS
-
SS
+
ISNS(+)
-
ISNS(-)
+
1 mA/V
0.91VREF
CONSTANT
CURRENT LOOP
3.3V
SS
FB
VREF
GM ERROR
AMPLIFIER
+
+
BOOT1
PWM
COMPARATOR
1.6V
HDRV1
+
-
-
SW1
VCC
LDRV1
COMP
CS AMPLIFIER
CS
CLK
BOOT2
+
ACS=5
CSG
BUCK-BOOST CONTROLLER
LOGIC
HDRV2
ILIMIT
COMPARATOR
-
SW2
+
-
VCC
LDRV2
VISNS
VILIM
SLOPE COMP
VOSNS
SLOPE
HICCUP CURRENT
LIMIT
RT/SYNC
OSC/SYNC
MODE
CLK
DITH
AGND
PGND
8.3 Feature Description
8.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
The LM5176-Q1 implements a fixed frequency current mode control of both the buck and boost switches. The
output voltage, scaled down by the feedback resistor divider, appears at the FB pin and is compared to the
internal reference (VREF) by an internal error amplifier. The error amplifier produces an error voltage by driving
the COMP pin. An adaptive slope compensation signal based on VIN, VOUT, and the capacitor at the SLOPE pin
is added to the current sense signal measured across the CS and CSG pins. The result is compared to the
COMP error voltage by the PWM comparator.
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Feature Description (continued)
The LM5176-Q1 regulates the output using valley current mode control in buck mode and peak current mode
control in boost mode. For valley current mode control, the high-side buck MOSFET controlled by HDRV1 is
turned on by the PWM comparator at the valley of the inductor ripple current and turned off by the oscillator clock
signal. Valley current mode control is advantageous for buck converters where the PWM controller must resolve
very short on-times. For peak current mode control in the boost mode, the low-side boost MOSFET controlled by
LDRV2 is turned on by the clock signal in each switching cycle and turned off by the PWM comparator at the
peak of the inductor ripple current.
The low-side gate drive LDRV1, complementary to the HDRV1 drive signal, controls the synchronous rectification
MOSFET of the buck stage. The high-side gate drive HDRV2, complementary to the low-side gate drive LDRV2,
controls the high-side synchronous rectifier of the boost stage. For operation with VIN close to VOUT, the LM5176Q1 uses a proprietary buck or boost transition scheme to achieve smooth, low ripple transition zone behavior.
Peak and valley current mode controllers require slope compensation for stable current loop operation at duty
cycle greater than 50% in peak current mode control and less than 50% in valley current mode control. The
LM5176-Q1 provides a SLOPE pin to program optimum slope for any VIN and VOUT combination using an
external capacitor.
8.3.2 VCC Regulator and Optional BIAS Input
The VCC regulator provides a regulated bias supply to the gate drivers. When EN/UVLO is above the standby
threshold (VEN(STBY)), the VCC regulator is turned on. For VIN less than the VCC regulation target, the VCC
voltage tracks VIN with a small voltage drop as shown in Figure 4. If the EN/UVLO input is above the operating
threshold (VEN(OP)) and VCC exceeds the VCC UV threshold (VUV(VCC)), the controller is enabled and switching
begins.
The VCC regulator draws power from VIN when there is no supply voltage connected to the BIAS pin. If the BIAS
pin is connected to an external voltage source that exceeds VCC by one diode drop, the VCC regulator draws
power from the BIAS input instead of VIN. Connecting the BIAS pin to VOUT in applications with VOUT greater than
8.5 V improves the efficiency of the regulator in the buck mode.
For low VIN operation, ensure that the VCC voltage is sufficient to fully enhance the MOSFETs. Use an external
bias supply if VIN dips below the voltage required to sustain the VCC voltage. For these conditions, use a series
blocking diode between the input supply and the VIN pin (Figure 21). This prevents VCC from back-feeding into
VIN through the body diode of the VCC regulator.
A ceramic capacitor of 16 V or higher voltage rating and a value between 1 µF and 4.7 µF is required to supply
the VCC regulator load transients. The VCC bypass capacitor should be connected between VCC and PGND
pins.
Series Blocking Diode
VIN
VIN
CVIN
LM5176
Optional
Bias Supply/ VOUT
BIAS
CBIAS
VCC
CVCC
Copyright © 2016, Texas Instruments Incorporated
Figure 21. VCC Regulator and Optional BIAS
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Feature Description (continued)
8.3.3 Enable/UVLO
The LM5176-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has
three distinct voltage ranges: shutdown, standby, and operating (see Shutdown, Standby, and Operating Modes).
When the EN/UVLO pin is below the standby threshold VEN(STBY), the converter is held in a low power shutdown
mode. When EN/UVLO voltage is greater than the standby threshold VEN(STBY) but less than the operating
threshold VEN(OP), the internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held low
and the PWM controller is disabled. A pull-up current IEN(STBY) is sourced out of the EN/UVLO pin in standby
mode to provide hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than
the operating threshold VEN(OP) and VCC is above the undervoltage threshold VUV(VCC), the controller starts
operation. A hysteresis current ΔIHYS(OP) is sourced out of the EN/UVLO pin when the EN/UVLO input exceeds
the operating threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly
changing input voltage.
The VIN UVLO threshold is
VIN(UV) is calculated using
EN/UVLO resistor divider:
§
VIN(UV) VEN(OP) u ¨ 1
©
typically set by a resistor divider from VIN to AGND (Figure 22). The turn-on threshold
Equation 1 where RUV2 is the upper resistor and RUV1 is the lower resistor in the
RUV2 ·
¸ RUV2 u IEN(STBY)
RUV1 ¹
(1)
The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the
EN/UVLO resistor divider and is given by:
'VHYS(UV) 'IHYS(OP) u RUV2
(2)
VIN
LM5176
RUV2
EN/UVLO
RUV1
Copyright © 2016, Texas Instruments Incorporated
Figure 22. UVLO Threshold Programming
8.3.4 Soft-Start
The LM5176-Q1 soft-start time is programmed using a soft-start capacitor from the SS pin to AGND. When the
converter is enabled, an internal current source (ISS) charges the soft-start capacitor. When the SS pin voltage is
below the feedback reference voltage VREF, the soft-start pin controls the regulated FB voltage. Once SS
exceeds VREF, the soft-start interval is complete and the error amplifier is referenced to VREF. The soft-start time
is given by Equation 3:
CSS u VREF
t ss
ISS
(3)
The soft-start capacitor is internally discharged when the converter is disabled because of EN/UVLO falling
below the operating threshold or VCC falling below the VCC UV threshold. The soft-start pin is also discharged
when the converter is in hiccup mode current limiting or in thermal shutdown. When average input or output
current limiting is active, the soft-start capacitor is discharged by the constant current loop transconductance
(gm) amplifier to limit either input or output current.
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Feature Description (continued)
8.3.5 Overcurrent Protection
The LM5176-Q1 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions.
In buck operation, the sensed valley voltage across the CSG and CS pins is limited to VCS(BUCK). The high-side
buck switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time.
In boost operation, the maximum peak voltage across CS and CSG is limited to VCS(BOOST). If the peak current in
the low-side boost switch causes the voltage across CS and CSG to exceed this threshold voltage, the boost
switch is turned off for the remainder of the clock cycle.
Applying the appropriate voltage to the MODE pin of the LM5176-Q1 enables hiccup mode fault protection (see
MODE Pin Configuration). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current
limiting for 128 consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is
automatically released after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is
not enabled through the MODE pin, the LM5176-Q1 will operate in cycle-by-cycle current limiting as long as the
overload condition persists.
8.3.6 Average Input/Output Current Limiting
The LM5176-Q1 provides optional average current limiting capability to limit either the input or the output current
of the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected
in series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the
ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50 mV
reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the
soft-start capacitor. When the soft-start capacitor discharges below the feedback reference voltage VREF, the
output voltage of the converter decreases to limit the input or output current. The average current limiting feature
can be used in applications requiring a regulated current from the input supply or into the load. The target
constant current is given by Equation 4:
50 mV
ICL(AVG)
RSNS
(4)
A filter network as shown in Figure 25 is often used across ISNS(+) and ISNS(-) pins to filter the ripple in the
average current sense signal.
The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together to AGND.
8.3.7 Operation Above 40-V Input
For application where input voltage is higher than 40 V, a 2 kΩ resistor in series with the VISNS pin is required
as shown in Figure 25.
8.3.8 CCM Operation
The LM5176-Q1 works in continuous conduction mode (CCM). In CCM operation the inductor current can flow in
either direction and the controller switches at a fixed frequency regardless of the load current. The CCM
operation is useful for noise-sensitive applications where a fixed switching eases filter design.
8.3.9 Frequency and Synchronization (RT/SYNC)
The LM5176-Q1 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from
the RT/SYNC pin to AGND. The RT resistor is related to the nominal switching frequency (Fsw) by the Equation 5:
§ 1 ·
¨
¸ 190 ns
F
R T © sw ¹
116 pF
(5)
Figure 3 in the Typical Characteristics shows the relationship between the programmed switching frequency (Fsw)
and the RT resistor.
The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The
external synchronization pulse is ac coupled using a capacitor to the RT/SYNC pin. The external synchronization
pulse frequency range is 75% to 125% of the resistor programmed frequency. A 50% duty cycle is acceptable for
external SYNC.
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Feature Description (continued)
LM5176
RT/SYNC
external SYNC
CSYNC
RT
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Using External SYNC
8.3.10 Frequency Dithering
The LM5176-Q1 provides an optional frequency dithering function that is enabled by connecting a capacitor from
DITH to AGND. Figure 24 illustrates the dithering circuit. A triangular waveform centered at 1.22 V is generated
across the CDITH capacitor. This triangular waveform modulates the oscillator frequency by 10% of the nominal
frequency set by the RT resistor. The CDITH capacitance value sets the rate of the low frequency modulation. A
lower CDITH capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the
dithering circuit to effectively reduce peak EMI, the modulation rate must be much less than the oscillator
frequency (Fsw). Equation 6 calculates the DITH pin capacitance required to set the modulation frequency, FMOD.
Connecting the DITH pin directly to AGND disables frequency dithering, and the internal oscillator operates at a
fixed frequency set by the RT resistor. Dither is disabled when external SYNC is used.
10 PA
CDITH
FMOD u 0.24 V
(6)
1.22 V + 5%
LM5176
1.22 V
1.22 V - 5 %
DITH
CDITH
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Dither Operation
8.3.11 Output Overvoltage Protection (OVP)
The LM5176-Q1 provides an output overvoltage protection (OVP) circuit that turns off the gate drives when the
feedback voltage is above the output overvoltage threshold VOVP. Switching resumes once the feedback voltage
falls below the OVP threshold. There is a small hysteresis to prevent chattering.
8.3.12 Power Good (PGOOD)
PGOOD is an open drain output that is pulled low when the voltage at the FB pin is outside -9% / +10% of the
nominal VREF. The PGOOD internal N-Channel MOSFET pull-down strength is typically 4.2 mA. This pin can be
connected to a voltage supply of up to 8 V through a pull-up resistor.
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Feature Description (continued)
8.3.13 Gm Error Amplifier
The LM5176-Q1 has a gm error amplifier for loop compensation. The gm amplifier output (COMP) range is 0.3 V
to 3 V. Connect an Rc1-Cc1 compensation network between COMP and ground for type II (PI) compensation (see
Figure 25). Another pole is usually added using Cc2 to suppress higher frequency noise and switching frequency
ripple.
The COMP output voltage (VCOMP) range limits the possible VIN and IOUT range for a given design. In buck mode,
the maximum VIN for which the converter can regulate the output at no load is when VCOMP reaches 0.3 V.
Equation 7 gives VCOMP as a function of VIN at no load in CCM buck mode:
2 PS ˜ VIN VOUT 6 PA
VOUT
˜ 1 DBUCK
˜ 1 DBUCK
VCOMP(BUCK) 1.6 V ACS ˜ RSENSE ˜
2 ˜ L1˜ Fsw
CSLOPE ˜ Fsw
(7)
Where DBUCK in the equation Equation 7 is the buck duty cycle given by:
VOUT
DBUCK
VIN
(8)
A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can
increase the maximum VIN range for buck operation.
For boost mode, the minimum VIN for which the converter can regulate the output at full load is when VCOMP
reaches 3 V. Equation 9 gives VCOMP as a function of VIN in boost mode:
§
· 2 PS ˜ VOUT VIN 5 PA
V
VIN
VCOMP(BOOST) 1.6 V ACS ˜ RSENSE ˜ ¨ IOUT ˜ OUT
˜ DBOOST ¸
˜ DBOOST
V
2
L1
F
CSLOPE ˜ Fsw
˜
˜
IN
sw
©
¹
(9)
Where DBOOST in the Equation 9 is the boost duty cycle given by:
VIN
DBOOST 1
VOUT
(10)
A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can extend
the minimum VIN range for boost operation.
8.3.14 Integrated Gate Drivers
The LM5176-Q1 provides four N-channel MOSFET gate drivers: two floating high-side gate drivers at the HDRV1
and HDRV2 pins, and two ground referenced low-side drivers at the LDRV1 and LDRV2 pins. Each driver is
capable of sourcing 1.8 A and sinking 2.2 A peak current. In buck operation, LDRV1 and HDRV1 are switched by
the PWM controller while HDRV2 remains continuously on. In boost operation, LDRV2 and HDRV2 are switched
while HDRV1 remains continuously on.
The low-side gate drivers are powered from VCC and the high-side gate drivers HDRV1 and HDRV2 are
powered from bootstrap capacitors CBOOT1 (between BOOT1 and SW1) and CBOOT2 (between BOOT2 and SW2)
respectively. The CBOOT1 and CBOOT2 capacitors are charged through external Schottky diodes connected to the
VCC pin as shown in Figure 25.
In most applications, ceramic capacitors of 16-V or higher voltage rating and values between 0.1 µF and 0.22 µF
are sufficient for CBOOT1 and CBOOT2.
8.3.15 Thermal Shutdown
The LM5176-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal junction
temperature exceeds 165°C (typical). The soft-start capacitor is discharged when thermal shutdown is triggered
and the gate drivers are disabled. The converter automatically restarts when the junction temperature drops by
the thermal shutdown hysteresis of 15°C below the thermal shutdown threshold.
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8.4 Device Functional Modes
Please refer to Enable/UVLO section for the description of EN/UVLO pin function. Shutdown, Standby, and
Operating Modes section lists the shutdown, standby, and operating modes for LM5176-Q1 as a function of
EN/UVLO and VCC voltages.
8.4.1 Shutdown, Standby, and Operating Modes
EN/UVLO
VCC
DEVICE MODE
EN/UVLO < VEN(STBY)
—
Shutdown: VCC off, No switching
VEN(STBY) < EN/UVLO < VEN(OP)
—
Standby: VCC on, No switching
EN/UVLO > VEN(OP)
VCC < VUV(VCC)
Standby: VCC on, No switching
EN/UVLO > VEN(OP)
VCC > VUV(VCC)
Operating: VCC on, Switching enabled
8.4.2 MODE Pin Configuration
The MODE pin is used to select hiccup mode current limit. The MODE selection is based on the voltages at the
MODE pin. The MODE voltage is decided by the programming resistor RMODE between MODE and AGND, and
the source current out of the MODE pin (IMODE). MODE is latched during startup.
MODE PIN CONNECTION
HICCUP FAULT PROTECTION
RMODE to AGND = 200 kΩ or connect
MODE to VCC
No Hiccup
RMODE to AGND = 93.1 kΩ
Hiccup Enabled
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM5176-Q1 is a four-switch buck-boost controller. A quick-start tool on the LM5176-Q1 product webpage
can be used to design a buck-boost converter using the LM5176-Q1. Alternatively, Webench®software can
create a complete buck-boost design using the LM5176-Q1 and generate bill of materials, estimate efficiency,
solution size, and cost of the complete solution. Typical Application describes a detailed step-by-step design
procedure for a typical application circuit.
9.2 Typical Application
A typical application example is a buck-boost converter operating from a wide input voltage range of 6 V to 50 V
and providing a stable 12 V output voltage with current capability of 6 A.
RSNS
0Ÿ
VIN
0.1 µF
CVIN
CIN
2 NŸ
RUV2
68 µF
10 Ÿ
249 NŸ
100 Ÿ
1 µF
COUT
10 µF
x5
CIN
4.7 µF
x5
100 Ÿ
RUV1
QH1
59.0 NŸ
EN/UVLO
VISNS
VIN
ISNS(-)
VOUT
COUT
180 µF
x2
QH2
ISNS(+)
HDRV1
VCC
10 NŸ
VCC
BOOT1
PGOOD
L1
4.7 µH
QL1
CBOOT1
QL2
0.1 µF
RMODE
SW1
MODE
93.1 NŸ
LDRV1
100 Ÿ
RT/SYNC
CS
CSYNC
1 nF RT
RSENSE
8 PŸ
47 pF
CSG
27.4 NŸ
LM5176
100 Ÿ
SS
CSS
0.1 µF
VOUT
LDRV2
BIAS
VCC
BOOT2
CBIAS
CBOOT2
0.1 µF
0.1 µF
SW2
AGND
HDRV2
PGND
VOSNS
VCC
COMP
DITH
CVCC
SLOPE
Cc1
33 nF
1 µF
Cc2
560 pF
Rc1
10 NŸ
FB
CSLOPE
220 pF
RRB2
RRB1
280 NŸ
20 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 25. LM5176-Q1 Four-Switch Buck Boost Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, the following are used as the input parameters.
DESIGN PARAMETER
EXAMPLE VALUE
Input Voltage Range
6 V to 50 V
Output
12 V
Load Current
6A
Switching Frequency
300 kHz
Mode
CCM, Hiccup
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the LM5176-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
9.2.2.2 Frequency
The switching frequency of LM5176-Q1 is set by an RT resistor connected from RT/SYNC pin to AGND. The RT
resistor required to set the desired frequency is calculated using Equation 5 or Figure 3 . A 1% standard resistor
of 27.4 kΩ is selected for Fsw = 300 kHz.
9.2.2.3 VOUT
The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally
the bottom resistor in the resistor divider is selected to be in the 1 kΩ to 100 kΩ range. Select
RFB1 20 k:
(11)
The top resistor in the feedback resistor divider is selected using Equation 12:
VOUT 0.8 V
u RFB1 280 k:
RFB2
0.8 V
(12)
9.2.2.4 Inductor Selection
The inductor selection is based on consideration of both buck and boost modes of operation. For the buck mode,
inductor selection is based on limiting the peak to peak current ripple ΔIL to ~40% of the maximum inductor
current at the maximum input voltage. The target inductance for the buck mode is:
(VIN(MAX) VOUT ) u VOUT
LBUCK
12.7 PH
0.4 u IOUT(MAX) u Fsw u VIN(MAX)
(13)
For the boost mode, the inductor selection is based on limiting the peak to peak current ripple ΔIL to ~30% of the
maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:
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LBOOST
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2
VIN(MIN)
u (VOUT
VIN(MIN) )
2
0.3 u IOUT(MAX) u Fsw u VOUT
2.8 PH
(14)
In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple
current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the
converter by moving the right half plane zero to lower frequencies. Therefore a judicious compromise should be
made based on the application requirements. For this design a 4.7-µH inductor is selected. With this inductor
selection, the inductor current ripple is 6.5 A, 4.3 A, and 2.1 A, at VIN of 50 V, 24 V, and 6 V respectively.
The maximum average inductor current occurs at the minimum input voltage and maximum load current:
VOUT u IOUT(MAX)
IL(MAX)
13.3 A
0.9 u VIN(MIN)
(15)
where a 90% efficiency is assumed. The peak inductor current occurs at minimum input voltage and is given by:
VIN(MIN) u (VOUT VIN(MIN) )
IL(PEAK) IL(MAX)
14.4 A
2 u L1u Fsw u VOUT
(16)
To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in
boost operation. The inductor peak current during overload depends on the current limit resistor RSENSE (refer to
the sub-section on selecting RSENSE). The peak inductor current in current limit when in boost mode is given by:
120 mV
IL(PEAK, ILIMIT, BOOST)
RSENSE
(17)
The peak inductor current in current limit when in buck mode happens at high input voltage and is given by:
IL(PEAK, ILIMIT, BUCK)
VIN(MAX)
80 mV
RSENSE
VOUT
L1u Fsw
§ V
·
u ¨ OUT ¸
¨ VIN(MAX) ¸
©
¹
(18)
The peak inductor current in current limit is 15 A and 16.5 A in boost mode and buck mode respectively. The
inductor should be selected to handle this current.
9.2.2.5 Output Capacitor
In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by Equation 19 where the minimum VIN corresponds to the maximum capacitor current.
ICOUT(RMS)
IOUT u
VOUT
VIN
1
(19)
In this example the maximum output ripple RMS current is ICOUT(RMS) = 6 A. A 5-mΩ output capacitor ESR
causes an output ripple voltage of 60 mV as given by:
I
u VOUT
'VRIPPLE(ESR) OUT
u ESR
VIN(MIN)
(20)
A 400 µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:
'VRIPPLE(COUT)
VIN(MIN) ·
§
IOUT u ¨ 1
¸
VOUT ¹
©
COUT u Fsw
(21)
Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current
capacity. The complete schematic in Figure 25 at the end of this section shows a good starting point for COUT for
typical applications.
9.2.2.6 Input Capacitor
In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given
by:
22
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ICIN(RMS)
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IOUT D u (1 D)
(22)
The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT/2 = 3 A. A combination of ceramic and
bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple.
The complete schematic in Figure 25 is a good starting point for CIN for typical applications.
9.2.2.7 Sense Resistor (RSENSE)
The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set
high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is
given by:
80 mV
RSENSE(BUCK)
13 m:
IOUT(MAX)
(23)
For the boost mode of operation, the current limit resistor is given by:
120 mV
RSENSE(BOOST)
8.3 m:
IL(PEAK)
(24)
The closest standard value of RSENSE = 8 mΩ is selected based on the boost mode operation.
The maximum power dissipation in RSENSE happens at VIN(MIN):
2
PRSENSE(MAX)
VIN(MIN) ·
§
§ 120mV ·
¸
¨
¸ ˜ RSENSE ˜ ¨ 1
VOUT ¹
© RSENSE ¹
©
0.9 W
(25)
Therefore, a sense resistor with 2 W power rating will be sufficient for this application.
For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG
sense lines. Please see Figure 25 for typical values. The filter resistance should not exceed 100 Ω.
9.2.2.8 Slope Compensation
For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected
based on Equation 26:
L1
4.7 PH
CSLOPE gmSLOPE u
2 PS u
235 pF
RSENSE u ACS
8 m: u 5
(26)
This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one
switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated
slope capacitor value in Equation 26). A smaller slope capacitor results in larger slope signal which is better for
noise immunity in the transition region (VIN~VOUT). A larger slope signal, however, restricts the achievable input
voltage range for a given output voltage, switching frequency, and inductor. For this design CSLOPE = 220 pF is
selected for better transition region behavior while still providing the required VIN range. This selection of slope
capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error
Amplifier section.
9.2.2.9 UVLO
The UVLO resistor divider must be designed for turn-on below 6V. Selecting a RUV2 = 249 kΩ gives a UVLO
hysteresis of 0.8 V based on Equation 2. The lower UVLO resistor is the selected using Equation 27:
RUV2 u VEN(OP)
RUV1
VIN UV IEN(STBY) u RUV2 VEN(OP)
(27)
A standard value of 59.0 kΩ is selected for RUV1.
When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs
with gate (Miller) plateau voltage lower than the minimum VIN.
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9.2.2.10 Soft-Start Capacitor
The soft-start time is programmed using the soft-start capacitor. The relationship between CSS and the soft-start
time is given by:
CSS u VREF
t ss
ISS
(28)
CSS = 0.1 µF gives a soft-start time of 16 ms.
9.2.2.11 Dither Capacitor
The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching
frequency. A larger CDITH results in lower modulation frequency. For proper operation the modulation frequency
(FMOD) must be much lower than the switching frequency. Use Equation 29 to select CDITH for the target
modulation frequency.
10 PA
CDITH
FMOD u 0.24 V
(29)
For the current design dithering is not being implemented. Therefore a 0 Ω resistor from the DITH pin to AGND
disables this feature.
9.2.2.12 MOSFETs QH1 and QL1
The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 50 V. In addition they
must withstand the transient spikes at SW1 during switching. Therefore QH1 and QL1 should be rated for 60 V
or higher. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the
converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.
The power loss in QH1 in the boost mode of operation is approximated by:
2
PCOND(QH1)
§
VOUT ·
¨ IOUT ˜
¸ ˜ RDSON(QH1)
VIN ¹
©
(30)
The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss
components given by Equation 31 and Equation 32 respectively:
PCOND(QH1)
PSW(QH1)
§ VOUT
¨
© VIN
·
2
¸ ˜ IOUT ˜ RDSON(QH1)
¹
1
˜ VIN ˜ IOUT ˜ tr
2
(31)
t f ˜ Fsw
(32)
The rise (tr) and the fall (tf) times are based on the MOSFET datasheet information or measured in the lab.
Typically a MOSFET with smaller RDSON (smaller conduction loss) will have longer rise and fall times (larger
switching loss).
The power loss in QL1 in the buck mode of operation is shown in Equation 33:
PCOND(QL1)
§
VOUT
¨1
VIN
©
·
2
¸ ˜ IOUT ˜ RDSON(QL1)
¹
(33)
9.2.2.13 MOSFETs QH2 and QL2
The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2
during switching. Therefore QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the
MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not
fully enhance during startup or overload conditions.
The power loss in QH2 in the buck mode of operation is approximated by:
PCOND(QH2)
IOUT 2 ˜ RDSON(QH2)
(34)
The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss
components given by Equation 35 and Equation 36 respectively:
24
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2
§
VOUT ·
VIN · §
¨1
¸ ˜ ¨ IOUT ˜
¸ ˜ RDSON(QL2)
VOUT ¹ ©
VIN ¹
©
PCOND(QL2)
§
·
V
1
˜ VOUT ˜ ¨ IOUT ˜ OUT ¸ ˜ tr
2
VIN ¹
©
PSW(QL2)
(35)
t f ˜ Fsw
(36)
The rise (tr) and the fall (tf) times can be based on the MOSFET datasheet information or measured in the lab.
Typically a MOSFET with smaller RDSON (lower conduction loss) has longer rise and fall times (larger switching
loss).
The power loss in QH2 in the boost mode of operation is shown in Equation 37:
2
PCOND(QH2)
·
V
VIN §
˜ ¨ IOUT ˜ OUT ¸ ˜ RDSON(QH2)
VOUT ©
VIN ¹
(37)
9.2.2.14 Frequency Compensation
This section presents the control loop compensation design procedure for the LM5176-Q1 buck-boost controller.
The LM5176-Q1 operates mainly in buck or boost modes, separated by a transition region, and therefore the
control loop design is done for both buck and boost operating modes. Then a final selection of compensation is
made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter
designed to go deep into both buck and boost operating regions, the boost compensation design is more
restrictive due to the presence of a right half plane zero (RHPZ) in the boost mode.
The boost power stage output pole location is given by:
·
1 §
2
¦p1(boost)
+]
¨
¸
2S © ROUT u COUT ¹
(38)
where ROUT = 2 Ω corresponds to the maximum load of 6 A.
The boost power stage ESR zero location is given by:
·
1 §
1
¦ z1
N+]
¨
¸
2S © RESR u COUT ¹
(39)
The boost power stage RHP zero location is given by:
¦RHP
1 § ROUT u (1 DMAX )2 ·
¨
¸
¸
2S ¨©
L1
¹
N+]
(40)
where DMAX is the maximum duty cycle at the minimum VIN.
The buck power stage output pole location is given by:
¦p1(buck)
·
1 §
1
¨
¸
2S © ROUT u COUT ¹
+]
(41)
The buck power stage ESR zero location is the same as the boost power stage ESR zero.
It is clear from Equation 40 that RHP zero is the main factor limiting the achievable bandwidth. For a robust
design the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the
RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:
¦bw
N+]
(42)
For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum
duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by
the RHP zero (fRHP/3) with 1/20 of the switching frequency and use the smaller of the two values as the
achievable bandwidth.
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The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this
locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase
loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost
loop:
¦ zc
+]
(43)
If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the
crossover, the compensation gain resistor Rc1 is calculated using the approximation:
S u ¦bw RFB1 RFB2 $ CS u 5SENSE u &OUT
u
u
Rc1
9.49 k:
gmEA
RFB1
1 DMAX
(44)
where DMAX is the maximum duty cycle at the minimum VIN in boost mode and ACS is the current sense amplifier
gain. The compensation capacitor Cc1 is then calculated from:
1
Cc1
27.9 nF
u S u ¦ zc u 5c1
(45)
The standard values of compensation components are selected to be Rc1 = 10 kΩ and Cc1 = 33 nF.
A high frequency pole (fpc2) is placed using a capacitor (Cc2) in parallel with Rc1 and Cc1. Set the frequency of this
pole at 7 to 10 times of fbw to provide attenuation of switching ripple and noise on COMP while avoiding
excessive phase loss at the crossover frequency. For a target fpc2 = 28 kHz, Cc2 is calculated using this equation:
1
Cc2
568 pF
u S u ¦pc2 u 5c1
(46)
Select a standard value of 560 pF for Cc2. These values provide a good starting point for the compensation
design. Each design should be tuned in the lab to achieve the desired balance between stability margin across
the operating range and transient response time.
9.2.3 Application Curves
99
100
98
EFFICIENCY (%)
EFFICIENCY (%)
96
92
88
84
VIN = 9V
VIN = 12V
VIN = 24V
1
2
3
4
LOAD CURRENT (A)
5
96
95
94
80
0
97
6
93
5
10
D008
Figure 26. Efficiency vs Load
26
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15
20
25
30
VIN (V)
35
40
45
50
D009
Figure 27. Efficiency vs Input Voltage
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VIN = 24 V
VIN
10 V/div
VIN = 12 V
VIN = 6 V
VOUT
1 V/div
200 mV/div
IL
5 A/div
5 µs/div
Figure 28. Output Voltage Ripple
1 ms/div
Figure 29. Line Transient Response (8 V - 24 V, IOUT = 2 A)
10 Power Supply Recommendations
The LM5176-Q1 is a power management device. The power supply for the device is any dc voltage source within
the specified input range. The supply should also be capable of supplying sufficient current based on the
maximum inductor current in boost mode operation. The input supply should be bypassed with additional
electrolytic capacitor at the input of the application board to avoid ringing due to parasitic impedance of the
connecting cables.
11 Layout
11.1 Layout Guidelines
The basic PCB board layout requires separation of sensitive signal and power paths. This checklist must be
followed to get good performance for a well designed board.
• Place the power components including the input filter capacitor CIN, the power MOSFETs QL1 and QH1, and
the sense resistor RSENSE close together to minimize the loop area for input switching current in buck
operation.
• Place the power components including the output filter capacitor COUT, the power MOSFETs QL2 and QH2,
and the sense resistor RSENSE close together to minimize the loop area for output switching current in boost
operation.
• Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the input
and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high
di/dt switching currents.
• Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.
• Layout the gate drive traces and return paths as directly as possible. Layout the forward and return traces
close together, either running side by side or on top of each other on adjacent layers to minimize the
inductance of the gate drive path.
• Use Kelvin connections to RSENSE for the current sense signals CS and CSG and run lines in parallel from the
RSENSE terminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 nodes or high-side gate
drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible.
• Place the CIN, COUT, and RSENSE ground pins as close as possible with thick ground trace and/or planes on
multiple layers.
• Place the VCC bypass capacitor close to the controller IC, between the VCC and PGND pins. A 1-µF ceramic
capacitor is typically used.
• Place the BIAS bypass capacitor close to the controller IC, between the BIAS and PGND pins. A 0.1-µF
ceramic capacitor is typically used.
• Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins.
• Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins.
• Bypass the VIN pin to AGND with a low ESR ceramic capacitor located close to the controller IC. A 0.1 µF
ceramic capacitor is typically used. When using external BIAS, use a diode between input rails and VIN pins to
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Layout Guidelines (continued)
•
•
•
prevent reverse conduction when VIN < VCC.
Connect the feedback resistor divider between the COUT positive terminal and AGND pin of the IC. Place the
components close to the FB pin.
Use care to separate the power and signal paths so that no power or switching current flows through the
AGND connections which can either corrupt the COMP, SLOPE, or SYNC signals, or cause dc offset in the
FB sense signal. The PGND and AGND traces can be connected near the PGND pin, near the VCC
capacitor PGND connection, or near the PGND connection of the CS, CSG pin current sense resistor.
When using the average current loop, divide the overall capacitor (CIN or COUT) between the two sides of the
sense resistor to ensure small cycle-by-cycle ripple. Place the average current loop filter capacitor close to
the IC between the ISNS(+) and ISNS(-) pins.
11.2 Layout Example
L1
SW1
SW2
VOUT
VIN
QL1
QL2
QH1
CIN
CIN
GND
QH2
RSENSE
RISNS
COUT
LM5176
COUT
GND
Figure 30. LM5176-Q1 Power Stage Layout
28
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12 Device and Documentation Support
12.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the LM5176-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
12.2 Documentation Support
12.2.1 Related Documentation
Please visit TI homepage for latest technical document including application notes, user guides, and reference
designs.
IC Package Thermal Metrics application report, Semiconductor and IC Package Thermal Metrics.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
Webench, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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29-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5176QPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
LM5176Q1
LM5176QPWPTQ1
ACTIVE
HTSSOP
PWP
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
LM5176Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Sep-2018
OTHER QUALIFIED VERSIONS OF LM5176-Q1 :
• Catalog: LM5176
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM5176QPWPRQ1
HTSSOP
PWP
28
2000
330.0
16.4
LM5176QPWPTQ1
HTSSOP
PWP
28
250
180.0
16.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.9
10.2
1.8
12.0
16.0
Q1
6.9
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5176QPWPRQ1
HTSSOP
PWP
28
2000
350.0
350.0
43.0
LM5176QPWPTQ1
HTSSOP
PWP
28
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
NOTE 3
8.45
14
15
B
0.30
0.19
0.1
C A B
28X
4.5
4.3
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14
15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
5.18
4.48
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
28
1
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
(5.18)
26X (0.65)
(0.6)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
( 0.2) TYP
VIA
15
14
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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EXAMPLE STENCIL DESIGN
PWP0028C
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28
28X (0.45)
(R0.05) TYP
26X (0.65)
(5.18)
BASED ON
0.125 THICK
STENCIL
SYMM
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.47 X 5.79
3.10 X 5.18 (SHOWN)
2.83 X 4.73
2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2019, Texas Instruments Incorporated
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