Texas Instruments | TLV741P 150-mA, Low-Dropout Regulator With Foldback Current Limit (Rev. A) | Datasheet | Texas Instruments TLV741P 150-mA, Low-Dropout Regulator With Foldback Current Limit (Rev. A) Datasheet

Texas Instruments TLV741P 150-mA, Low-Dropout Regulator With Foldback Current Limit (Rev. A) Datasheet
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TLV741P
SBVS309A – JULY 2017 – REVISED SEPTEMBER 2018
TLV741P 150-mA, Low-Dropout Regulator With Foldback Current Limit
1 Features
3 Description
•
•
•
•
The TLV741P low-dropout linear regulator (LDO) is a
low quiescent current device with excellent line and
load transient performance for power-sensitive
applications. This device provides a typical accuracy
of 1%.
1
•
•
•
•
•
•
Input Voltage Range: 1.4 V to 5.5 V
Stable Operation With 1-µF Ceramic Capacitors
Foldback Overcurrent Protection
Packages:
– 5-Pin SOT-23
– 4-Pin X2SON
Very Low Dropout: 230 mV at 150 mA
Accuracy: 1%
Low IQ: 50 µA
Available in Fixed-Output Voltages:
1 V to 3.3 V
High PSRR: 65 dB at 1 kHz
Active Output Discharge (P Version Only)
2 Applications
•
•
•
PDAs and Battery-Powered Portable Devices
MP3 Players and Other Hand-Held Products
WLAN and Other PC Add-On Cards
The TLV741P is designed to be stable with a small,
1-µF output capacitor.
The TLV741P provides inrush current control during
device power up and enabling. The TLV741P limits
the input current to the defined current limit to avoid
large currents from flowing from the input power
source. This functionality is especially important in
battery-operated devices.
The TLV741P is available in standard DBV (SOT-23)
and DQN (X2SON) packages. The TLV741P provides
an active pulldown circuit to quickly discharge output
loads.
Device Information(1)
DEVICE NAME
PACKAGE
TLV741P
BODY SIZE
SOT-23 (5)
2.90 mm × 1.60 mm
X2SON (4)
1.00 mm × 1.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Circuit
Dropout Voltage vs Output Current
350
TLV741P
CIN
EN
ON
OFF
OUT
GND
VOUT = 1.8 V
VOUT = 3.3 V
300
COUT
Dropout Voltage (mV)
IN
250
200
150
100
50
0
0
15
30
45
60
75
90 105
Output Current (mA)
120
135
150
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV741P
SBVS309A – JULY 2017 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
8.3 What to Do and What Not to Do ............................. 16
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Examples................................................... 17
10.3 Power Dissipation ................................................. 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (July 2017) to Revision A
•
2
Page
Added DQN (X2SON) package to data sheet ........................................................................................................................ 1
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SBVS309A – JULY 2017 – REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
DQN Package
4-Pin X2SON With Exposed Thermal Pad
Top View
5
OUT
4
NC
OUT
1
GND
2
Thermal Pad
4
IN
3
EN
Not to scale
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SOT-23
X2SON
EN
3
3
I
GND
2
2
—
IN
1
4
I
NC
4
—
—
No internal connection
OUT
5
1
O
Regulated output voltage pin. For best transient response, use a small 1-µF ceramic capacitor
from this pin to ground. See the Input and Output Capacitor Considerations section for more
details.
Thermal
pad
—
—
—
The thermal pad is electrically connected to the GND node. Connect the thermal pad to the
ground plane for improved thermal performance.
Enable pin. Driving EN over 0.9 V turns on the regulator.
Driving EN below 0.4 V puts the regulator into shutdown mode.
Ground pin
Input pin. Use a small capacitor from this pin to ground. See the Input and Output Capacitor
Considerations section for more details.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted). All voltages are with respect to GND. (1)
MIN
Voltage
Current
6
Enable, VEN
–0.3
VIN + 0.3
Output, VOUT
–0.3
3.6
(1)
V
Internally limited
Output short-circuit duration
Temperature
UNIT
–0.3
Maximum output, IOUT(max)
Total power dissipation
MAX
Input, VIN
Indefinite
Continuous, PD(tot)
See Thermal Information
Junction, TJ
–55
125
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
5.5
UNIT
VIN
Input voltage
1.4
VEN
Enable range
0
VIN
V
IOUT
Output current
0
150
mA
CIN
Input capacitor
0
COUT
Output capacitor
TJ
Operating junction temperature
1
V
µF
1
100
µF
–40
125
°C
6.4 Thermal Information
TLV741P
THERMAL METRIC (1)
DQN (X2SON)
DBV (SOT-23)
4 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
228.5
249
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
210.4
172.7
°C/W
RθJB
Junction-to-board thermal resistance
174.7
76.7
°C/W
ψJT
Junction-to-top characterization parameter
21.2
49.7
°C/W
ψJB
Junction-to-board characterization parameter
174.5
75.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
140.6
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report
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6.5 Electrical Characteristics
over operating temperature range TJ = –40°C to +125°C, VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
VOUT
TEST CONDITIONS
Output voltage
range
DC output accuracy
MAX
UNIT
3.3
VOUT ≥ 1.8 V
TJ = 25°C
–1%
1%
VOUT < 1.8 V
TJ = 25°C
–20
20
VOUT ≥ 1.2 V
–40°C ≤ TJ ≤ 125°C
–1.5%
1.5%
VOUT < 1.2 V
–40°C ≤ TJ ≤ 125°C
–50
50
mV
1
5
mV
mV
Line regulation
Maximum {VOUT(nom) + 0.5 V
VIN = 2 V} ≤ VIN ≤ 5.5 V
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 150 mA
VOUT = 0.98 × VOUT(nom),
TJ = –40°C to 85°C
Dropout voltage
VOUT = 0.98 × VOUT(nom)
TJ = –40°C to 125°C
IGND
TYP
1
ΔVOUT(ΔVIN)
VDO
MIN
10
30
1 V ≤ VOUT < 1.8 V
IOUT = 150 mA
600
900
VOUT = 1.1 V
IOUT = 100 mA
470
600
1.8 V ≤ VOUT < 2.1 V
IOUT = 30 mA
70
1.8 V ≤ VOUT < 2.1 V
IOUT = 150 mA
350
2.1 V ≤ VOUT < 2.5 V
IOUT = 30 mA
90
2.1 V ≤ VOUT < 2.5 V
IOUT = 150 mA
290
V
mV
575
481
2.5 V ≤ VOUT < 3 V
IOUT = 30 mA
50
2.5 V ≤ VOUT < 3 V
IOUT = 150 mA
246
3 V ≤ VOUT < 3.6 V
IOUT = 30 mA
46
3 V ≤ VOUT < 3.6 V
IOUT = 150 mA
230
420
1 V ≤ VOUT < 1.8 V
IOUT = 150 mA
600
1020
VOUT = 1.1 V
IOUT = 100 mA
470
720
1.8 V ≤ VOUT < 2.1 V
IOUT = 150 mA
350
695
2.1 V ≤ VOUT < 2.5 V
IOUT = 150 mA
290
601
2.5 V ≤ VOUT < 3 V
IOUT = 150 mA
246
565
3 V ≤ VOUT < 3.6 V
IOUT = 150 mA
230
540
445
mV
Ground pin current
IOUT = 0 mA
50
75
µA
ISHUTDOWN
Shutdown current
VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 5.5 V
TJ = 25°C
0.1
1
µA
PSRR
Power-supply
rejection ratio
VIN = 3.3 V
VOUT = 2.8 V
IOUT = 30 mA
Vn
Output noise voltage
BW = 100 Hz to 100 kHz
VIN = 2.3 V
VOUT = 1.8 V
IOUT = 10 mA
tSTR
Start-up time (1)
COUT = 1 μF
IOUT = 150 mA
(1)
f = 100 Hz
70
f = 10 kHz
55
f = 1 MHz
55
dB
73
µVRMS
100
µs
Start-up time is the time from EN assertion to (0.98 × VOUT(nom)).
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Electrical Characteristics (continued)
over operating temperature range TJ = –40°C to +125°C, VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VHI
Enable high
(enabled)
VLO
Enable low
(disabled)
IEN
EN pin current
EN = 5.5 V
0.01
µA
RPULLDOWN
Pulldown resistor
VIN = 4 V
120
Ω
ILIM
ISC
TSD
6
Output current limit
Short-circuit current
Thermal shutdown
0.9
VIN
V
0
0.4
V
VIN = 3.8 V
VOUT = 3.3 V
TJ = –40 to 85°C
180
VIN = 2.25 V
VOUT = 1.8 V
TJ = –40 to 85°C
180
VIN = 2 V
VOUT = 1.2 V
TJ = –40 to 85°C
180
VOUT = 0 V
mA
40
Shutdown, temperature increasing
158
Reset, temperature decreasing
140
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mA
°C
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6.6 Typical Characteristics
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
1.8
1.802
Output Voltage (V)
1.8
1.799
1.798
1.797
1.796
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.798
Output Voltage (V)
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.801
1.796
1.794
1.792
1.79
1.795
1.788
1.794
1.786
1.793
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
0
5.5
Figure 1. 1.8-V Line Regulation vs VIN and Temperature
40
60
80
100
Output Current (mA)
120
140
160
Figure 2. 1.8-V Load Regulation vs IOUT and Temperature
1.798
500
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.7975
400
Dropout Voltage (mV)
1.797
Output Voltage (V)
20
1.7965
1.796
1.7955
1.795
300
200
100
1.7945
1.794
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
Figure 3. 1.8-V Output Voltage Over Temperature
300
Ground Pin Current (PA)
Dropout Voltage (mV)
350
250
200
150
100
50
0
0
25
50
75
100
Output Current (mA)
125
150
Figure 5. 3.3-V Dropout Voltage vs IOUT and Temperature
50
75
100
Output Current (mA)
125
150
Figure 4. 1.8-V Dropout Voltage vs IOUT and Temperature
400
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
25
65
62.5
60
57.5
55
52.5
50
47.5
45
42.5
40
37.5
35
32.5
30
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
Figure 6. Ground Pin Current vs VIN and Temperature
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Typical Characteristics (continued)
80
500
75
300
200
70
Ground Pin Current (nA)
Ground Pin Current (PA)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
65
60
55
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
50
45
40
100
50
30
20
10
3
2
1
35
0
20
40
60
80
100
Output Current (mA)
120
140
2
160
Figure 7. Ground Pin Current vs IOUT and Temperature
90
80
60
PSRR (dB)
50
40
30
20
10
COUT = 1 µF, IOUT = 150 mA
COUT = 1 µF, IOUT = 30 mA
-10
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
1E+1
Figure 9. Power-Supply Rejection Ratio Over COUT
5
3
2
3
3.5
4
Input Voltage (V)
5
5.5
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
Figure 10. Power-Supply Rejection Ratio Over IOUT
COUT = 1 µF
6
0.024
5
0.016
4
0.008
3
0
2
-0.008
1
VIN (V)
0.5
0.3
0.2
0.1
0.05
0.03
0.02
1
-0.016
VIN = 4.5-5.5 V
VOUT = 3.3 V
0.01
0.005
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
0
-0.003
-0.0015
COUT = 1 µF
0
0.0015
Time (s)
0.003
0.0045
-0.024
0.006
D011
IOUT = 0 mA
Figure 11. Output Spectral Noise Density
8
4.5
VOUT (V)
PSRR (dB)
70
0
2.5
Figure 8. Shutdown Current vs VIN and Temperature
100
Voltage Noise (µV/√ Hz)
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
5
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Figure 12. Line Transient
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Typical Characteristics (continued)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
0.06
5
0.045
4
0.03
3
0.015
2
0
1
-0.015
6.4
0.06
VIN
VOUT 0.045
5.6
VIN = 4.5-5.5 V
VOUT = 3.3 V
-0.0015
0
0.0015
Time (s)
0.003
-0.03
0.006
0.0045
0.015
3.2
0
2.4
-0.015
1.6
-0.03
0.8
-0.045
0
-0.0014
-0.001
-0.0006
-0.0002
Time (s)
D012
IOUT = 150 mA
IOUT = 1 mA
Figure 14. Line Transient
Figure 13. Line Transient
0.24
0.52
0.045
IOUT = 0 mA - 20 mA
VOUT = 3.3 V
0.05
IOUT = 0 mA - 100 mA
VOUT = 3.3 V
0.47
0.14
0.015
0.09
0
0.04
IOUT (A)
0.03
VOUT (V)
0.19
IOUT (A)
-0.06
0.0006
0.0002
-0.015
0.04
0.42
0.03
0.37
0.02
0.32
0.01
0.27
0
0.22
-0.01
0.17
-0.02
0.12
-0.03
0.07
-0.04
0.02
-0.01
-0.5
-0.25
0
0.25
IOUT = 0 mA - 20 mA
0.5
0.75
Time (s)
1
-0.03
1.5
1.25
-0.05
-0.03
-0.5
-0.25
0
D014
D016
0.04
0.03
1.25
D015
0.37
0.02
0.32
0.01
0.27
0
0.22
-0.01
0.17
-0.02
0.12
-0.03
0.07
-0.04
0.02
-0.05
0
0.25
IOUT = 10 mA - 150 mA
0.5
0.75
Time (s)
1
1.25
-0.06
1.5
3
Output Voltage (V)
0.42
VOUT (V)
IOUT (A)
1
3.5
0.05
IOUT = 10 mA - 150 mA
VOUT = 3.3 V
-0.25
0.5
0.75
Time (s)
Figure 16. Load Transient
0.52
-0.03
-0.5
0.25
-0.06
1.5
VOUT = 3.3 V
Figure 15. Load Transient
0.47
VOUT (V)
0
-0.003
0.03
4
VIN (V)
VOUT (V)
VIN (V)
4.8
VOUT (V)
6
2.5
2
1.5
1
0.5
0
0
D016
100
150
200
Output Current (mA)
250
300
TLV74133P
VOUT = 3.3 V
Figure 17. Load Transient
50
Figure 18. 3.3-V Output Voltage vs Output Current
(Foldback Current Limit)
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Typical Characteristics (continued)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
2
4
VIN
VOUT
1.5
3
1.25
Voltage (V)
Output Voltage (V)
1.75
1
0.75
0.5
2
1
0.25
0
0
50
100
150
200
250
Output Current (mA)
300
350
TLV74118P
0
0
0.5
TLV74118P
Figure 19. 1.8-V Output Voltage vs Output Current
(Foldback Current Limit)
Channel 1
100 mV/div
Channel 2
1 V/div
Channel 3
1 V/div
EN
Channel 4
50 mA/div
EN
VOUT
Channel 4
100 mA/div
VIN = 2.3 V
VOUT = 1.8 V
COUT = 10 µF
IOUT = 90 mA
Figure 21. Start-Up With EN
IOUT
Time (50 ms/div)
Time (100 ms/div)
10
VIN
Channel 3
1 V/div
ILOAD
2
Figure 20. VIN Power-Up and Power-Down
Channel 2
2 V/div
VOUT
1.5
IOUT = 150 mA
Channel 1
2 V/div
VIN
1
Time (s)
CIN = 1 µF
TLV74118P
from design
VIN = 3 V
TPS74118P
VOUT = 1.8 V
No load
CIN = COUT = 1 µF
Figure 22. Shutdown Response With Enable
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7 Detailed Description
7.1 Overview
The TLV741P belongs to a new family of next-generation value low-dropout (LDO) regulators. The TLV741P
consumes low quiescent current and delivers excellent line and load transient performance. These
characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom makes the device
suitable for RF portable applications.
This regulator offers current limit and thermal protection. Device operating junction temperature is –40°C to
+125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120 :
Bandgap
Logic
TLV741P
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV741P uses a UVLO circuit that disables the output until the input voltage is greater than the rising UVLO
voltage. The circuit makes sure that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry, VIN(min). During UVLO disable, the output of
the TLV741P version is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
The TLV741P has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1.
t=
120 · RL
120 + RL
· COUT
(1)
7.3.3 Foldback Current Limit
The TLV741P has an internal foldback current limit that helps protect the regulator during fault conditions. The
current supplied by the device is gradually reduced while the output voltage decreases. When the output shorts,
the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in current limit,
and is calculated by Equation 2:
VOUT = ILIMIT ´ RLOAD
(2)
The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device
turns off. The internal thermal shutdown circuit turns on the device during cool down. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See Thermal Protection for more
details.
The TLV741P PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, TI
recommends externally limiting the rated output current to 5%.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, which protects the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions.
The TLV741P internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heat sinking. Continuously running the TLV741P into thermal shutdown degrades
device reliability.
12
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 lists conditions that result in different operating modes.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
—
VEN < VEN(low)
—
TJ > 158°C
Disabled mode
(any true condition disables the
device)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Considerations
The TLV741P uses an advanced internal control loop to obtain stable operation by using an input or output
capacitor. An output capacitance of 1 μF or larger generally provides good dynamic response. TI recommends
using X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and
equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. TI recommends using an input capacitor if the source impedance is more than
0.5 Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the
device is located several inches from the input power source.
8.1.2 Dropout Voltage
The TLV741P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
8.1.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
14
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8.2 Typical Application
Several versions of the TLV741P are suitable for powering the MSP430 microcontroller.
Figure 23 shows a diagram of the TLV741P powering an MSP430 microcontroller. Table 2 lists potential
applications of some voltage versions.
VI
OUT
IN
VO
(1.8 V to 3.6 V)
MSP430
1 µF
0.1 µF
EN
GND
Figure 23. TLV741P Powering a Microcontroller
Table 2. Typical MSP430 Applications
DEVICE
VOUT
(TYPICAL)
TLV741P18P
1.8 V
Allows for lowest power consumption with many MSP430s
TLV741P25P
2.5 V
2.2-V supply required by many MSP430s for flash programming and erasing
APPLICATION
8.2.1 Design Requirements
Table 3 lists the design requirements.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.2 V to 3 V (Lithium Ion battery)
Output voltage
1.8 V, ±1%
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
A small output capacitor allows for the minimal possible inrush current during start-up, and makes sure that the
180-mA maximum input current limit is not exceeded.
See Figure 29 to verify that the maximum junction temperature is not exceeded.
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8.2.3 Application Curves
4
100
90
Voltage ( mV / Hz )
80
PSRR (dB)
70
60
50
40
30
20
3
2
1
10
0
-10
1E+1
COUT = 1 µF, IOUT = 150 mA
COUT = 1 µF, IOUT = 30 mA
1E+2
0
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
10
100
1k
Frequency (Hz)
1E+7
VOUT = 1.8 V
Figure 24. Power-Supply Rejection Ratio vs Frequency
10k
100k
IOUT = 10 mA
Figure 25. Output Spectral Noise Density
4
VIN
VOUT
Voltage (V)
3
2
1
0
0
0.5
1
Time (s)
1.5
2
IOUT = 150 mA
Figure 26. VINPower Up and Power Down
8.3 What to Do and What Not to Do
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator for best transient
performance.
Place at least one 1-µF capacitor as close as possible to the IN pin for best transient performance.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not continuously operate the device in current limit or near thermal shutdown.
16
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9 Power Supply Recommendations
This device is designed to operate from an input voltage supply range from 1.4 V to 5.5 V. The input voltage
range must provide adequate headroom for the device to have a regulated output. This input supply must be
well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve
the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve AC performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin. High-ESR capacitors may
degrade PSRR performance.
10.2 Layout Examples
VOUT
OUT
TLV741P
IN
COUT(1)
VIN
CIN(1)
GND
EN
GND PLANE
Represents via used for
application-specific connections
(1)
Not required.
Figure 27. X2SON Layout Example
VOUT
VIN
IN
CIN
OUT
COUT
GND
EN
NC
GND PLANE
Represents via used for
application-specific connections
Figure 28. SOT-23 Layout Example
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10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heat sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 3:
PD = (VIN - VOUT ) ´ IOUT
(3)
Figure 29 shows the maximum ambient temperature versus the power dissipation of the TLV741P. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to make sure the TLV741P does not
operate above a junction temperature of 125°C.
Maximum Ambient Temperature (°C)
130
TLV741P DQN, High-K Layout
TLV741P DBV, High-K Layout
120
110
100
90
80
70
60
50
0
0.05
0.1
0.15
0.2
0.25
Power Dissipation (W)
0.3
0.35
Figure 29. Maximum Ambient Temperature vs Device Power Dissipation
Estimate junction temperature by using the ΨJT and ΨJB thermal metrics, shown inThermal Information. These
metrics are a more accurate representation of the heat transfer characteristics of the die and the package than
RθJA. The junction temperature can be estimated with Equation 4:
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 3,
TT is the temperature at the center-top of the device package,
TB is the PCB temperature measured 1 mm away from the device package on the PCB surface.
(4)
NOTE
Both TT and TB can be measured on actual application boards using a thermogun (an
infrared thermometer).
For more information about measuring TT and TB, see Using New Thermal Metrics , available for download at
www.ti.com.
18
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Universal Low-Dropout (LDO) Linear Voltage Regulator EVM User's Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV741105PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1NFT
TLV74110PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1C9T
TLV74110PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8T
TLV74111PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DHT
TLV74111PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8R
TLV74112PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DIT
TLV74112PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8Q
TLV74115PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DJT
TLV74115PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8P
TLV74118PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DKT
TLV74118PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8O
TLV74125PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DLT
TLV74125PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8N
TLV741285PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DMT
TLV741285PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8M
TLV74128PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DNT
TLV74128PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8L
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
11-Jun-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV74130PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1DOT
TLV74130PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8K
TLV74133PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1CAT
TLV74133PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
8J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
TLV741105PDBVR
SOT-23
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DBV
5
3000
178.0
9.0
3.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
TLV74110PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74110PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74111PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74111PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74112PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74112PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74115PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74115PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74118PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74118PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74125PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74125PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV741285PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV741285PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74128PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74128PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74130PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV74130PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
TLV74133PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
TLV74133PDQNR
X2SON
DQN
4
3000
180.0
8.4
1.16
1.16
0.53
2.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV741105PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74110PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74110PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74111PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74111PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74112PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74112PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74115PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74115PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74118PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74118PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74125PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74125PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV741285PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV741285PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74128PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74128PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74130PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74130PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
TLV74133PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV74133PDQNR
X2SON
DQN
4
3000
203.2
196.8
33.3
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
A
1.05
0.95
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
0.48+0.12
-0.1
(0.05) TYP
2
0.05
0.00
NOTE 6
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
1
PIN 1 ID
(OPTIONAL)
NOTE 4
4
4X 0.28
0.15
0.3
0.2
0.1
0.05
C A B
C
(0.11)
3X 0.30
0.15
4215302/E 12/2016
NOTES:
1.
2.
3.
4.
5.
6.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
Shape of exposed side leads may differ.
Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
(0.03)
4X (0.36)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7.
8.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DQN0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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