Texas Instruments | LMZ21701 1-A Nano Module With 17-V Maximum Input Voltage (Rev. E) | Datasheet | Texas Instruments LMZ21701 1-A Nano Module With 17-V Maximum Input Voltage (Rev. E) Datasheet

Texas Instruments LMZ21701 1-A Nano Module With 17-V Maximum Input Voltage (Rev. E) Datasheet
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LMZ21701
SNVS853E – AUGUST 2012 – REVISED AUGUST 2018
LMZ21701 1-A Nano Module With 17-V Maximum Input Voltage
1 Features
2 Applications
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1
Integrated Inductor
Miniature 3.5 mm × 3.5 mm × 1.75 mm Package
35-mm² Solution Size (Single Sided)
-40°C to 125°C Junction Temperature Range
Adjustable Output Voltage
Integrated Compensation
Adjustable Soft-Start Function
Starts into Prebiased Loads
Power Good and Enable Pins
Seamless Transition to Power-Save Mode
Up to 1000 mA Output Current
Input Voltage Range 3 V to 17 V
Output Voltage Range 0.9 V to 6 V
Efficiency up to 95 %
1.5-µA Shutdown Current
17-µA Quiescent Current
Create a Custom Design Using the LMZ21701
With WEBENCH® Power Designer
•
•
Point-of-Load Conversions from
3.3 V, 5 V, or 12 V Input Voltage
Space Constrained Applications
LDO Replacement
3 Description
The LMZ21701 nano module is an easy-to-use stepdown DC/DC solution capable of driving up to 1000mA load in space-constrained applications. Only an
input capacitor, an output capacitor, a soft-start
capacitor, and two resistors are required for basic
operation.
Device Information(1)
PART NUMBER
LMZ21701
PACKAGE
µSIP (8)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
space
Simplified Schematic
VIN
Efficiency for VIN = 12 V
VOUT
VIN
VOUT
EN
PG
100
90
80
LMZ21701
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
70
Efficiency (%)
CIN
60
50
40
30
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 5 V
20
10
0
0.0001
0.001
0.01
Output Current (A)
0.1
1
D023
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ21701
SNVS853E – AUGUST 2012 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
7.5
Overview ................................................................... 8
Functional Block Diagram ......................................... 9
Package Construction ............................................... 9
Feature Description................................................. 11
Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
8.3 Do's and Don'ts ...................................................... 26
9
Power Supply Recommendations...................... 26
9.1 Voltage Range ........................................................ 26
9.2 Current Capability ................................................... 26
9.3 Input Connection .................................................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
12.1 Tape and Reel Information ................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (#IMPLIED) to Revision E
Page
•
Added links for Webench and top navigator icon for TI reference design; deleted Simple Switcher branding .................... 1
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Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4
Changes from Revision C (October 2014) to Revision D
Page
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Changed from product Preview to Production Data .............................................................................................................. 1
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Changed to Final Limits ......................................................................................................................................................... 5
Changes from Revision B (August 2014) to Revision C
•
Added Device Information and Handling Rating tables, Feature Description, Application and Implementation Layout
Device and Documentation Support and Mechanical, Packaging, and Orderable Information, moved some curves to
Application Curves ................................................................................................................................................................. 1
Changes from Revision A (October 2013) to Revision B
•
2
Page
Updated datasheet to new TI standards ................................................................................................................................ 1
Changes from Original (August 2012) to Revision A
•
Page
Page
Changed Description .............................................................................................................................................................. 1
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5 Pin Configuration and Functions
Figure 1. LMZ21701 in the SIL0008E Package
SIL Package
8-Pin µSIP
Top View
TOP
SS
1
FB
2
PG
3
VOUT
4
PAD
(GND)
PAD
(GND)
8
VIN
7
EN
6
VOS
5
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SS
1
I
Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference
ramp time. It can be used for tracking and sequencing.
FB
2
I
Voltage feedback. Connect resistive voltage divider to this pin to set the output voltage.
PG
3
O
Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain
(requires pull-up resistor; goes low impedance when EN is low).
VOUT
4
O
Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter
capacitor between VOUT and PGND.
GND
5
I
Ground for the power MOSFETs and gate-drive circuitry.
VOS
6
I
Output voltage sense pin and connection for the control loop circuitry.
EN
7
I
Enable input (High = enabled, Low = disabled). Internal pull down resistor keeps logic level
low if pin is left floating.
VIN
8
I
Supply voltage for control circuitry and power stage.
PAD
Electrically connected to GND. Must be soldered to a ground copper plane to achieve
appropriate power dissipation and mechanical reliability.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VIN
−0.3
20
V
EN, SS
−0.3
VIN +0.3 V w/ 20 V
maximum
V
FB, PG, VOS
−0.3
7
V
10
mA
−40
125
°C
260
°C
150
°C
PG sink current
Junction temperature, TJ-MAX
Maximum lead temperature
−65
Storage temperature, Tstg
(1)
(2)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
Recommended load current
Junction temperature, TJ
(1)
MIN
MAX
3
17
UNIT
V
0.9
6
V
0
1000
mA
−40
125
°C
Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For
ensured specifications, see the Electrical Characteristics section.
6.4 Thermal Information
LMZ21701
THERMAL METRIC
(1)
SIL (µSIP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance (2)
42.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.8
°C/W
RθJB
Junction-to-board thermal resistance
9.4
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
9.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Junction-to-ambient thermal resistance (RθJA) is based on 4-layer board thermal measurements, performed under the conditions and
guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. RJθA varies with PCB copper area, power dissipation, and airflow.
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6.5 Electrical Characteristics (1)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12 V.
TYP (2)
MAX (1)
EN = high, IOUT = 0 mA, TJ = -40°C to
85°C
device not switching
17
25
μA
EN = high, IOUT = 0 mA, TJ = -40°C to
125°C
device not switching
17
28
μA
EN = low, TJ = -40°C to 85°C
1.5
4
μA
EN = low, TJ = -40°C to 125°C
1.5
5
μA
2.8
2.9
3
V
0.125
0.18
0.26
V
PARAMETER
TEST CONDITIONS
MIN (1)
UNIT
SYSTEM PARAMETERS
IQ
Operating quiescent current
ISD
Shutdown current
VINUVLO
Input under voltage lock out rising
threshold
VINUVLO-HYS
Input under voltage lock out
hysteresis
TSD
Thermal shutdown
TSD-HYST
Thermal shutdown hysteresis
Rising Threshold
160
°C
30
°C
CONTROL
VIH,
ENABLE
Enable logic HIGH voltage
0.9
VIL, ENABLE
Enable logic LOW voltage
ILKG
Input leakage current
EN = VIN or GND
VTH_PG
Power Good threshold voltage
Rising (% VOUT)
Falling (% VOUT)
V
0.3
V
0.01
1
μA
92%
95%
98%
87%
90%
93%
VOL_PG
Power Good output low voltage
IPG = -2 mA
0.07
0.3
V
ILKG_PG
Power Good leakage current
VPG = 1.8 V
1
400
nA
ISS
Softstart Pin source current
2.84
3.2
μA
2.5
POWER STAGE
RDS(ON)
High-Side MOSFET ON
Resistance
VIN ≥ 6 V
82
VIN = 3 V
120
Low-Side MOSFET ON
Resistance
VIN ≥ 6 V
40
VIN = 3 V
50
mΩ
mΩ
L
Integrated power inductor value
2.2
μH
DCR
Integrated power inductor DC
resistance
92
mΩ
ICL-HS
High-Side MOSFET Current Limit
TA = 25°C
ICL-LS
Low-Side MOSFET Current Limit
TA = 25°C
1.2
A
ICL-DC
Output (DC) current limit
VOUT = 5 V, TA = 85°C
1.3
A
(1)
(2)
1.4
1.8
2.2
A
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics(1) (continued)
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12 V.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
0.7869
0.803
0.8191
V
1
100
nA
UNIT
OUTPUT
VREF
Internal reference voltage
IFB
Feedback pin leakage current
VFB = 0.8 V
VOUT
Light load initial voltage accuracy
Power save mode, COUT = 22 µF, TA =
-40°C to 85°C, 1% FB Resistors
VOUT
Load regulation
VOUT = 3.3 V
PWM mode operation
0.05%
/A
VOUT
Line regulation
3 V ≤ VIN ≤ 17 V, VOUT= 3.3 V, IOUT =
1000 mA
PWM mode operation
0.02%
/V
-2.3%
2.8%
SYSTEM CHARACTERISTICS
η
6
Full Load Efficiency
VOUT = 3.3 V, IOUT = 1000 mA
93%
Light Load Efficiency
VOUT = 3.3 V, IOUT = 1 mA
72%
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6.6 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C
0.7
2-LAYER 70 µm (2 oz) Cu
4-LAYER 70 µm (2 oz) Cu
90
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.6
80
Power Dissipation (W)
Thermal Resistance J-A (°C/W)
100
70
60
50
40
0.5
0.4
0.3
0.2
0.1
30
20
0
0
5
10
Copper Area (cm2)
15
20
0
0.1
0.2
0.3
D012
VOUT = 1.2 V
Figure 2. Package Thermal Resistance vs. Board Copper
Area
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
005
TA = 85ºC
Figure 3. Power Dissipation
0.7
0.7
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.5
VIN = 3.3 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.6
Power Dissipation (W)
Power Dissipation (W)
0.6
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
0
0
0.1
0.2
0.3
VOUT = 1.8 V
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
0
0.1
0.2
TA = 85ºC
VOUT = 2.5 V
Figure 4. Power Dissipation
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
D007
TA = 85ºC
Figure 5. Power Dissipation
0.7
0.7
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.5
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.6
Power Dissipation (W)
0.6
Power Dissipation (W)
0.3
D006
0.4
0.3
0.2
0.5
0.4
0.3
0.2
0.1
0.1
0
0
0
0.1
0.2
VOUT = 3.3 V
0.3
0.4 0.5 0.6
Load Current (A)
0.7
0.8
TA = 85ºC
0.9
1
0
0.1
0.2
D008
VOUT = 5.0 V
Figure 6. Power Dissipation
0.3
0.4 0.5 0.6
Load Current (A)
0.7
0.8
0.9
1
D009
TA = 85ºC
Figure 7. Power Dissipation
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Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C
6
4
IOUT = 0.25 A
IOUT = 0.5 A
IOUT = 1 A
IOUT = 0.25 A
IOUT = 0.5 A
IOUT = 1 A
3.6
Output Voltage (V)
Output Voltage (V)
5.5
3.8
5
4.5
4
3.4
3.2
3
2.8
2.6
2.4
3.5
2.2
3
2
3
3.5
VOUT = 5.0 V
4
4.5
5
Input Voltage (V)
5.5
6
3
3.1
3.2
TA = 85ºC
3.4 3.5 3.6
Input Voltage (V)
VOUT = 3.3 V
Figure 8. Dropout
3.7
3.8
3.9
4
D010
TA = 85ºC
Figure 9. Dropout
80
100
Evaluation Board
EN 55022 Class B Limit
EN 55022 Class A Limit
70
Peak Emissions
Quasi Peak Limit
Average Limit
90
Conducted Emissions (dBµV)
Radiated Emissions (dBµV/m)
3.3
D011
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
0
200
VIN= 12 V
400
600
Frequency (MHz)
800
1000
0
0.1
1
VOUT = 3.3 V
IOUT = 1 A
10
Frequency (MHz)
D004
VIN= 12 V
Lf = 2.2 µH
Figure 10. Radiated EMI on EVM
VOUT = 3.3 V
Cf = 1.0 µF
100
D003
IOUT = 1 A
Figure 11. Conducted EMI on EVM
7 Detailed Description
7.1 Overview
The LMZ21701 Nano Module is an easy-to-use step-down DC/DC solution capable of driving up to 1000 mA load
in space-constrained applications. Only an input capacitor, an output capacitor, a softstart capacitor, and two
resistors are required for basic operation. The Nano Module comes in 8-pin DFN footprint package with an
integrated inductor. The LMZ21701 architecture is based on DCS-Control™ (Direct Control with Seamless
Transition into Power Save Mode). This architecture combines the fast transient response and stability of
hysteretic type converters along with the accurate DC output regulation of voltage mode and current mode
regulators.
The LMZ21701 architecture uses pulse width modulation (PWM) mode for medium and heavy load requirements
and Power Save Mode (PSM) at light loads for high efficiency. In PWM mode the switching frequency is
controlled over the input voltage range. The value depends on the output voltage setting and is typically reduced
at low output voltages to achieve higher efficiency. In PSM the switching frequency decreases linearly with the
load current. Since the architecture of the device supports both operation modes (PWM and PSM) in a single
circuit building block, the transition between the modes of operation is seamless with minimal effect on the output
voltage.
8
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7.2 Functional Block Diagram
HIGH SIDE
SWITCH
INDUCTOR
VIN
VOUT
2.2µH
LDO
BYPASS
5V LDO
UVLO
HIGH SIDE
CURRENT
LIMIT
HIGH SIDE DRIVER
WITH INTERNAL BOOTSTRAP
LOW SIDE
DRIVER
EN
400kŸ
CONTROL LOGIC
THERMAL
SHUTDOWN
SS
PG
LOW SIDE
SWITCH
LOW SIDE
CURRENT
LIMIT
ZERO
CURRENT
DETECT
SOFTSTART
CURRENT AND
TRACKING
VOS
DIRECT CONTROL
&
COMPENSATION
tON TIMER
6.6V
CLAMP
25pF
CFF
+
GND
FB
+
COMPARATOR
ERROR
AMPLIFIER
VREF
+
-
7.3 Package Construction
In order to achieve a small solution size the LMZ21701 Nano Module comes in an innovative MicroSiP™
package. The construction consists of a synchronous buck converter IC embedded inside an FR-4 laminate
substrate, with a power inductor mounted on top of the substrate material. See Figure 12 and Figure 13 below.
The bottom (landing pads) of the package resemble a typical 8-pin DFN package. See the Mechanical drawings
at the end of the datasheet for details on the recommended landing pattern and solder paste stencil information.
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Package Construction (continued)
Figure 12. LMZ21701 in the SIL0008E Package
INDUCTOR
FR-4 LAMINATE
SUBSTRATE
BOTTOM
COPPER PATTERN
EMBEDDED BUCK IC
Figure 13. LMZ21701 Package Construction Cross Section
(Illustration Only, Not to Scale)
10
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7.4 Feature Description
7.4.1 Input Undervoltage Lockout
The LMZ21701 features input undervoltage lockout (UVLO) circuit. It monitors the input voltage level and
prevents the device from switching the power MOSFETs if VIN is not high enough. The typical VIN UVLO rising
threshold is 2.9 V with 180 mV of hysteresis.
7.4.2 Enable Input (EN)
The enable pin (EN) is weakly pulled down internally through a 400-kΩ resistor to keep EN logic low when the
pin is floating. The pull-down resistor is not connected when EN is set high. Once the voltage on the enable pin
(EN) is set high the Nano Module will start operation. If EN is set low ( < 0.3 V ) the LMZ21701 will enter
shutdown mode. The typical shutdown quiescent current is 1.5 μA.
7.4.3 Soft Start and Tracking Function (SS)
When EN is set high for device operation the LMZ21701 start switching after 50-μs delay, and the output voltage
starts rising. The VOUT rising slope is controlled by the external capacitor CSS connected to the softstart (SS) pin.
The Nano Module has a 2.9 μA constant current source internally connected to the SS pin to program the
softstart time TSS:
TSS = CSS × 1.25 V / 2.9 μA
(1)
The soft-start capacitor voltage is reset to zero volts when EN is pulled low and when the thermal protection is
active.
If tracking function is desired, the SS pin can be used to track external voltage. If the applied external tracking
voltage is between 100 mV and 1.2 V, the FB voltage will follow SS according to the following relationship:
VFB = 0.64 x VSS
(2)
7.4.4 Power Good Function (PG)
The LMZ21701 features a power good function which can be used for sequencing of multiple rails. The PG pin is
an open-drain output and requires a pull-up resistor RPG to VOUT (or any other external voltage less than 7 V).
When the Nano Module is enabled and UVLO is satisfied, the power good function starts monitoring the output
voltage. The PG pin is kept at logic low if the output has not reached the proper regulation voltage. Refer to the
Electrical Characteristics table for the PG voltage thresholds. The PG pin can sink 2 mA of current which sets the
minimum limit of the RPG resistance value:
RPG-MIN= VPULL-UP / 2 mA
(3)
The PG pin goes low impedance if the device is disabled or the thermal protection is active.
7.4.5 Output Voltage Setting
The output voltage of the LMZ21701 is set by a resistive divider from VOUT to GND, connected to the feedback
(FB) pin. The output voltage can be set between 0.9 V and 6 V. The voltage at the FB pin is regulated to 0.8 V.
The recommended minimum divider current is 2 μA. This sets a maximum limit on the bottom feedback resistor
RFBB. Its value must not exceed 400 kΩ. The top feedback resistor RFBT can be calculated using the following
formula:
RFBT = RFBB x (VOUT/ 0.8 – 1)
(4)
7.4.6 Output Current Limit and Output Short Circuit Protection
The LMZ21701 has integrated protection against heavy loads and output short circuit events. Both, the high-side
FET and low-side FET have current monitoring circuitry. If the current limit threshold of the high-side FET is
reached , the high-side FET will be turned off and the low-side FET will be turned on to ramp down the inductor
current. Once the current through the low-side FET has decreased below a safe level, the high-side device will
be allowed to turn on again. The actual DC output current depends on the input voltage, output voltage, and
switching frequency. Refer to the Application Curves section for more information.
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Feature Description (continued)
7.4.7 Thermal Protection
The nano module monitors its junction temperature (Tj) and shuts itself off if the it gets too hot. The thermal
shutdown threshold for the junction is typically 160 °C. Both, high-side and low-side FETs are turned off until the
junction temperature has decreased under the hysteresis level, typically 30 °C below the shutdown temperature.
7.5 Device Functional Modes
7.5.1 PWM Mode Operation
The LMZ21701 operates in PWM mode when the output current is greater than half the inductor ripple current.
The frequency variation in PWM mode is controlled and depends on the VIN and VOUT settings. Refer to the
Application Curves section for switching frequency graphs for several typical output voltage settings. As the load
current is decreased and the valley of the inductor current ripple reaches 0 A the device enters PSM operation to
maintain high efficiency.
7.5.2 PSM Operation
Once the load current decreases and the valley of the inductor current reaches 0 A, the LMZ21701 transitions to
power save mode of operation. The device will remain in PSM as long as the inductor current is discontinuous.
The switching frequency will decrease linearly with the load current. If VIN decreases to about 15 % above VOUT
the device will not enter PSM and will maintain output regulation in PWM mode.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ21701 is a step down DC-to-DC converter. It is used to convert higher DC voltage to a regulated lower
DC voltage with maximum load current of 1 A. The following design procedure can be used to select components
for the LMZ21701. Alternatively, the WEBENCH® software can be used to select from a large database of
components, run electrical simulations, and optimize the design for specific performance. Please go to
webench.ti.com to access the WEBENCH® tool.
8.2 Typical Application
For a quick start, the following component values can be used as a design starting point for several typical output
voltage rails and 1 A of output load current.
VOUT
VIN
VIN
VOUT
EN
PG
RPG
LMZ21701
CIN
COUT
VOS
SS
RFBT
CSS
GND
FB
RFBB
COMPONENT VALUES FOR VOUT=1.2V
CIN
22µF
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
41.2k
1%
RFBB
82.5k
1%
RPG
10k
1%
• 25V
X7R or X5R
Figure 14. Typical Applications Circuit
Figure 15. External Component Values
( VOUT = 1.2 V )
COMPONENT VALUES FOR VOUT=1.8V
COMPONENT VALUES FOR VOUT=2.5V
CIN
X7R or X5R
CIN
22µF
• 10V
X7R or X5R
COUT
22µF
• 10V
X7R or X5R
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
1%
RFBT
357k
1%
118k
1%
RFBB
169k
1%
10k
1%
RPG
10k
1%
22µF
COUT
22µF
CSS
3300pF
RFBT
147k
RFBB
RPG
• 25V
• 25V
X7R or X5R
Figure 16. External Component Values
( VOUT = 1.8 V )
Figure 17. External Component Values
( VOUT = 2.5 V )
COMPONENT VALUES FOR VOUT=3.3V
COMPONENT VALUES FOR VOUT=5.0V
CIN
X7R or X5R
CIN
22µF
• 10V
X7R or X5R
COUT
22µF
• 10V
X7R or X5R
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
1%
RFBT
232k
1%
383k
1%
RFBB
44.2k
1%
10k
1%
RPG
10k
1%
22µF
COUT
22µF
CSS
3300pF
RFBT
1.21M
RFBB
RPG
• 25V
Figure 18. External Component Values
( VOUT = 3.3 V )
• 25V
X7R or X5R
Figure 19. External Component Values
( VOUT = 5.0 V )
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Typical Application (continued)
8.2.1 Design Requirements
The design procedure requires a few typical design parameters. See Table 1 below.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Input Voltage (VIN)
Range from 3.0 V to 17 V
Output Voltage (VOUT)
Range from 0.9 V to 6 V
Output Current (IOUT)
Up to 1000 mA
Softstart time (TSS)
Minimum of 0.5 ms recommended
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ21701 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Input Capacitor (CIN)
Low ESR multi-layer ceramic capacitors (MLCC) are recommended for the input capacitor of the LMZ21701.
Using a ≥ 10 µF ceramic input capacitor in ≥ 0805 (2012 metric) case size with 25-V rating typically provides
sufficient VIN bypass. Use of multiple capacitors can also be considered. Ceramic capacitors with X5R and X7R
temperature characteristics are recommended. These provide an optimal balance between small size, cost,
reliability, and performance for applications with limited space. The DC voltage bias characteristics of the
capacitors must be considered when selecting the DC voltage rating and case size of these components. The
effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals.
Selecting a part with larger capacitance, larger case size, or higher voltage rating can compensate for the
capacitance loss due to the DC voltage bias effect. For example, a 10-µF, X7R, 25-V rated capacitor used under
12-V DC bias may have approximately 8-µF effective capacitance in a 1210 (3225 metric) case size and about 6
µF in a 1206 (3216 metric) case size. As another example, a 10-µF, X7R, 16-V rated capacitor in a 1210 (3225
metric) case size used at 12-V DC bias may have approximately 5.5 µF effective capacitance. Check the
capacitor specifications published by the manufacturer.
8.2.2.3 Output Capacitor (COUT)
Similarly to the input capacitor, it is recommended to use low ESR multi-layer ceramic capacitors for COUT.
Ceramic capacitors with X5R and X7R temperature characteristics are recommended. Use 10 µF or larger value
and consider the DC voltage bias characteristics of the capacitor when choosing the case size and voltage
rating. For stability, the output capacitor should be in the 10 µF – 200 µF effective capacitance range.
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8.2.2.4 Soft-start Capacitor (CSS)
The softstart capacitor is chosen according to the desired softstart time. As described in the Softstart and
Tracking Function section the softstart time TSS = CSS x 1.25 V / 2.9 μA.
A minimum CSS value of 1000 pF is required for monotonic VOUT ramp up.
8.2.2.5 Power Good Resistor (RPG)
If the Power Good function is used, a pull up resistor RPG is necessary from the PG pin to an external pull-up
voltage.
The minimum RPG value is restricted by the pull down current capability of the internal pull down device.
RPG-MIN= VPULL-UP / 2 mA
(5)
The maximum RPG value is based on the maximum PG leakage current and the minimum “logic high” level
system requirements:
RPG-MAX= (VPULL-UP – VLOGIC-HIGH) / ILKG_PG
(6)
8.2.2.6 Feedback Resistors (RFBB and RFBT)
The feedback resistors RFBB and RFBT set the desired output voltage. Choose RFBB less than 400 kΩ and
calculate the value for RFBT using the following formula:
RFBT = RFBB x (VOUT/ 0.8 – 1)
(7)
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8.2.3 Application Curves
8.2.3.1 VOUT = 1.2 V
VOUT
VIN
VIN
VOUT
EN
PG
COMPONENT VALUES FOR VOUT=1.2V
RPG
LMZ21701
CIN
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
CIN
22µF
• 25V
X7R or X5R
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
41.2k
1%
RFBB
82.5k
1%
RPG
10k
1%
Figure 20. Typical Applications Circuit
Figure 21. External Component Values
(VOUT = 1.2 V)
100
0.6
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
90
0.5
Power Dissipation (W)
80
Efficiency (%)
70
60
50
40
30
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
20
10
0
0.0001
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.4
0.3
0.2
0.1
0.0
0.0
0.001
0.01
Load Current (A)
0.1
0.1
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
D013
1.0
C001
Figure 23. Power Dissipation VOUT = 1.2 V
Figure 22. Efficiency VOUT = 1.2 V
ILOAD 500mA/Div
PGOOD 1V/Div
ILOAD 500mA/Div
VOUT 500mV/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
Figure 24. Load Transient VOUT = 1.2 V
16
1ms/Div
20MHz BW
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Figure 25. Startup VOUT = 1.2 V
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COUT1 = 22 F 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22 F 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
50mV/Div
10mV/Div
1µs/Div
20MHz BW
Figure 26. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 1.2 V
500MHz BW
Figure 27. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 1.2 V
1.8
VOUT=1.2V
2.0
1.5
1.0
0.5
TYPICAL DC CURRENT LIMIT (A)
SWITCHING FREQUENCY (MHz)
2.5
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
C001
Figure 28. Typical Switching Frequency at 1000 mA Load
VOUT = 1.2 V
18
C001
Figure 29. Typical Current Limit VOUT = 1.2 V, TA = 85 °C
1.206
1.2
1.202
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.0
Output Current (A)
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
1.204
Output Voltage (V)
1µs/Div
1.2
1.198
1.196
1.194
0.8
0.6
0.4
VIN = 3.3 V
VIN = 5 V
VIN = 12 V
VIN = 17 V
0.2
1.192
0.0
1.19
0.0001
60
0.001
0.01
Load Current (A)
0.1
1
D014
Figure 30. Line and Load Regulation VOUT = 1.2 V
70
80
90
100
110
120
Ambient Temperature (ƒC)
130
C001
Figure 31. Thermal Derating for θJA = 47 ºC/W, VOUT = 1.2 V
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8.2.3.2 VOUT = 1.8 V
VOUT
VIN
VIN
VOUT
EN
PG
COMPONENT VALUES FOR VOUT=1.8V
RPG
LMZ21701
CIN
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
CIN
22µF
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
147k
1%
RFBB
118k
1%
RPG
10k
1%
Figure 32. Typical Applications Circuit
0.6
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
90
0.5
Power Dissipation (W)
80
Efficiency (%)
70
60
50
40
30
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
10
0
0.0001
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.4
0.3
0.2
0.1
0.0
0.0
0.001
0.01
Load Current (A)
0.1
X7R or X5R
Figure 33. External Component Values
(VOUT = 1.8 V)
100
20
• 25V
0.1
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
D015
1.0
C001
Figure 35. Power Dissipation VOUT = 1.8 V
Figure 34. Efficiency VOUT = 1.8 V
ILOAD 500mA/Div
PGOOD 1V/Div
ILOAD 500mA/Div
VOUT 1V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
Figure 36. Load Transient VOUT = 1.8 V
18
1ms/Div
20MHz BW
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Figure 37. Startup VOUT = 1.8 V
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COUT1 = 22 F 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22 F 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
Figure 38. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 1.8 V
500MHz BW
Figure 39. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 1.8 V
1.8
VOUT=1.8V
2.0
1.5
1.0
0.5
TYPICAL DC CURRENT LIMIT (A)
SWITCHING FREQUENCY (MHz)
2.5
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
C001
Figure 40. Typical Switching Frequency at 1000 mA Load
VOUT = 1.8 V
18
C001
Figure 41. Typical Current Limit VOUT = 1.8 V, TA = 85 °C
1.81
1.2
1.806
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.0
Output Current (A)
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
1.808
Output Voltage (V)
1µs/Div
1.804
1.802
1.8
1.798
1.796
0.8
0.6
0.4
VIN = 3.3 V
VIN = 5 V
VIN = 12 V
VIN = 17 V
0.2
1.794
1.792
0.0
1.79
0.0001
60
0.001
0.01
Load Current (A)
0.1
1
D016
Figure 42. Line and Load Regulation VOUT = 1.8 V
70
80
90
100
110
120
Ambient Temperature (ƒC)
130
C001
Figure 43. Thermal Derating for θJA= 47ºC/W VOUT = 1.8 V
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8.2.3.3 VOUT = 2.5 V
VOUT
VIN
VIN
VOUT
EN
PG
COMPONENT VALUES FOR VOUT=2.5V
RPG
LMZ21701
CIN
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
CIN
22µF
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
357k
1%
RFBB
169k
1%
RPG
10k
1%
Figure 44. Typical Applications Circuit
0.6
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
90
0.5
Power Dissipation (W)
80
Efficiency (%)
70
60
50
40
30
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
10
0
0.0001
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.4
0.3
0.2
0.1
0.0
0.0
0.001
0.01
Load Current (A)
X7R or X5R
Figure 45. External Component Values
(VOUT = 2.5 V)
100
20
• 25V
0.1
0.1
1
D017
Figure 46. Efficiency VOUT = 2.5 V
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
1.0
C001
Figure 47. Power Dissipation VOUT = 2.5 V
ILOAD 500mA/Div
PGOOD 2V/Div
ILOAD 500mA/Div
VOUT 1V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 48. Load Transient VOUT = 2.5 V
20
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Figure 49. Startup VOUT = 2.5 V
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COUT1 = 22 F 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22 F 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
Figure 50. 20MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 2.5 V
500MHz BW
Figure 51. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 2.5 V
1.8
VOUT=2.5V
2.0
1.5
1.0
0.5
TYPICAL DC CURRENT LIMIT (A)
SWITCHING FREQUENCY (MHz)
2.5
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
C001
Figure 52. Typical Switching Frequency at 1000 mA Load
VOUT = 2.5 V
18
C001
Figure 53. Typical Current Limit VOUT = 2.5 V, TA = 85 °C
2.5
1.2
2.496
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.0
Output Current (A)
VIN = 3 V
VIN = 3.3 V
VIN = 4.5 V
VIN = 5 V
2.498
Output Voltage (V)
1µs/Div
2.494
2.492
2.49
2.488
2.486
0.8
0.6
0.4
VIN = 5 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.2
2.484
2.482
0.0
2.48
0.0001
60
0.001
0.01
Load Current (A)
0.1
1
D018
Figure 54. Line and Load Regulation VOUT = 2.5 V
70
80
90
100
110
120
Ambient Temperature (ƒC)
130
C001
Figure 55. Thermal Derating for θJA = 47 ºC/W, VOUT = 2.5 V
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8.2.3.4 VOUT = 3.3 V
VOUT
VIN
VIN
VOUT
EN
PG
COMPONENT VALUES FOR VOUT=3.3V
RPG
LMZ21701
CIN
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
CIN
22µF
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
1.21M
1%
RFBB
383k
1%
RPG
10k
1%
Figure 56. Typical Applications Circuit
0.6
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
90
0.5
Power Dissipation (W)
80
Efficiency (%)
70
60
50
40
30
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
10
0
0.0001
0.4
0.3
0.2
0.1
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.0
0.0
0.001
0.01
Load Current (A)
0.1
X7R or X5R
Figure 57. External Component Values
(VOUT = 3.3 V)
100
20
• 25V
0.1
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
D019
1.0
C001
Figure 59. Power Dissipation VOUT = 3.3 V
Figure 58. Efficiency VOUT = 3.3 V
ILOAD 500mA/Div
VOUT 1V/Div
ILOAD 500mA/Div
PGOOD 2V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 60. Load Transient VOUT = 3.3 V
22
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Figure 61. Startup VOUT = 3.3 V
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COUT1 = 22 F 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22 F 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
Figure 62. 20 MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 3.3 V
500MHz BW
Figure 63. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 3.3 V
1.8
VOUT=3.3V
2.0
1.5
1.0
0.5
TYPICAL DC CURRENT LIMIT (A)
SWITCHING FREQUENCY (MHz)
2.5
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
C001
Figure 64. Typical Switching Frequency at 1000 mA Load
VOUT = 3.3 V
18
C001
Figure 65. Typical Current Limit VOUT = 3.3 V, TA = 85 °C
3.316
1.2
VIN = 4.5 V
VIN = 5 V
VIN = 9 V
3.314
VIN = 12 V
VIN = 15 V
VIN = 17 V
1.0
Output Current (A)
3.312
Output Voltage (V)
1µs/Div
3.31
3.308
3.306
3.304
0.8
0.6
0.4
VIN = 5 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.2
3.302
0.0
3.3
0.0001
60
0.001
0.01
Load Current (A)
0.1
1
D020
Figure 66. Line and Load Regulation VOUT = 3.3 V
70
80
90
100
110
120
Ambient Temperature (ƒC)
130
C001
Figure 67. Thermal Derating for θJA = 47 ºC/W, VOUT = 3.3 V
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8.2.3.5 VOUT = 5.0 V
VOUT
VIN
VIN
VOUT
EN
PG
COMPONENT VALUES FOR VOUT=5.0V
RPG
LMZ21701
CIN
SS
COUT
VOS
RFBT
CSS
GND
FB
RFBB
CIN
22µF
COUT
22µF
• 10V
X7R or X5R
CSS
3300pF
• 10V
X7R or X5R
RFBT
232k
1%
RFBB
44.2k
1%
RPG
10k
1%
Figure 68. Typical Applications Circuit
0.6
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
90
0.5
Power Dissipation (W)
80
Efficiency (%)
70
60
50
40
30
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
10
0
0.0001
0.4
0.3
0.2
0.1
0.0
0.0
0.001
0.01
Load Current (A)
0.1
X7R or X5R
Figure 69. External Component Values
(VOUT = 5.0 V)
100
20
• 25V
0.1
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
D021
1.0
C001
Figure 71. Power Dissipation VOUT = 5.0 V
Figure 70. Efficiency VOUT = 5.0 V
ILOAD 500mA/Div
VOUT 2V/Div
ILOAD 500mA/Div
PGOOD 5V/Div
VOUT 20mV/Div AC
ENABLE 500mV/Div
1ms/Div
20MHz BW
1ms/Div
20MHz BW
Figure 73. Startup VOUT = 5.0 V
Figure 72. Load Transient VOUT = 5.0 V
24
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COUT1 = 22 F 10V 0805 X5R
Taiyo Yuden MK212BJ226MG-T
VOUT RIPPLE
VOUT RIPPLE
COUT = 22 F 10V 0805 X5R
WITH 500MHz SCOPE BANDWIDTH
COUT2 = 3x1000pF 0805 NP0
Johanson Dielectrics 500R15N102JV4T
Taiyo Yuden MK212BJ226MG-T
10mV/Div
50mV/Div
1µs/Div
20MHz BW
Figure 74. 20MHz Oscilloscope Bandwidth
Output Voltage Ripple VOUT = 5.0 V
500MHz BW
Figure 75. 500 MHz Oscilloscope Bandwidth, 3x1000 pF
additional output capacitance
Output Voltage Ripple and HF Noise VOUT = 5.0 V
1.8
2.0
1.5
1.0
0.5
VOUT=5.0V
TYPICAL DC CURRENT LIMIT (A)
SWITCHING FREQUENCY (MHz)
2.5
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
18
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
C001
18
C001
Figure 76. Typical Switching Frequency at 1000 mA Load
VOUT = 5 V
Figure 77. Typical Current Limit VOUT = 5 V, TA = 85°C
5.05
1.2
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
5.04
5.035
1.0
Output Current (A)
5.045
Output Voltage (V)
1µs/Div
5.03
5.025
5.02
5.015
5.01
5.005
0.8
0.6
0.4
VIN = 9 V
VIN = 12 V
VIN = 15 V
VIN = 17 V
0.2
5
4.995
0.0
4.99
0.0001
60
0.001
0.01
Load Current (A)
0.1
1
D022
Figure 78. Line and Load Regulation VOUT = 5 V
70
80
90
100
110
120
Ambient Temperature (ƒC)
130
C001
Figure 79. Thermal Derating for θJA= 47 ºC/W, VOUT = 5 V
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8.3 Do's and Don'ts
● DO NOT exceed the Absolute Maximum Ratings.
● DO NOT exceed the Recommended Operating Conditions.
● DO NOT exceed the ESD Ratings.
● DO follow the Detailed Design Procedure.
● DO follow the PCB Layout Guidelines and Layout Example.
● DO follow the Power Supply Recommendations.
● DO visit the TI E2E Community Support Forum to have your questions answered and designs reviewed.
9 Power Supply Recommendations
9.1 Voltage Range
The voltage of the input supply must not exceed the Absolute Maximum Ratings and the Recommended
Operating Conditions of the LMZ21701.
9.2 Current Capability
The input supply must be able to supply the required input current to the LMZ21701 converter. The required
input current depends on the application's minimum required input voltage (VIN-MIN), the required output power
(VOUT × IOUT-MAX), and the converter efficiency (η).
IIN = VOUT x IOUT-MAX / (VIN-MIN x η)
For example, for a design with 10-V minimum input voltage, 5-V output, and 1-A maximum load, considering 90%
conversion efficiency, the required input current is 0.556 A.
9.3 Input Connection
Long input connection cables can cause issues with the normal operation of any buck converter.
9.3.1 Voltage Drops
Using long input wires to connect the supply to the input of any converter adds impedance in series with the
input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the
converter is loaded. If the input voltage is near the minimum operating voltage, this added voltage drop can
cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some
bulk (for example, electrolytic) capacitance at the input of the converter.
9.3.2 Stability
The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in
an under damped RLC network at the input of the Buck converter. This can cause oscillations on the input and
instability. If long wires are used, it is recommended to add some electrolytic capacitance in parallel with the
ceramic input capacitor. The electrolytic capacitor's ESR will improve the damping.
Use an electrolytic capacitor with CELECTROLYTIC≥ 4 × CCERAMIC and ESRELECTROLYTIC≈ √ (LCABLE / CCERAMIC)
For example, two cables (one for VIN and one for GND), each 1 meter (~3 ft) long with ~1-mm diameter (18
AWG), placed 1 cm (~0.4 in) apart will form a rectangular loop resulting in about 1.2 µH of inductance. The
inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 22 µF
ceramic input capacitor, the recommended parallel CELECTROLYTIC is ≥ 88 µF. Using a 100 µF capacitor will be
sufficient. The recommended ESRELECTROLYTIC≈ 0.23 Ω or larger, based on about 1.2 µH of inductance and 22
µF of ceramic input capacitance.
See application note SNVA489C for more details on input filter design.
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10 Layout
10.1 Layout Guidelines
The PCB layout is critical for the proper operation of any DC/DC switching converter. Although using modules
can simplify the PCB layout process, care should still be taken to minimize the inductance in the high di/dt loops
and to protect sensitive nodes. The following guidelines should be followed when designing a board layout with
the LMZ21701:
10.1.1 Minimize the High di/dt Loop Area
The input capacitor, the VIN terminal, and the GND terminal of the LMZ21701 form a high di/dt loop. Place the
input capacitor as close as possible to the VIN and GND terminals of the module IC. This minimizes the area of
the high di/dt loop and results in lower inductance in the switching current path. Lower inductance in the
switching current path translates to lower voltage spikes on the internal switch node and lower noise on the
output voltage. Make the copper traces between the input capacitor and the VIN and GND terminals wide and
short for better current handling and minimized parasitic inductance.
10.1.2 Protect the Sensitive Nodes in the Circuit
The feedback node is a sensitive circuit which can pick up noise. Make the feedback node as small as possible.
This can be achieved by placing the feedback divider as close as possible to the IC. Use thin traces to the
feedback pin in order to minimize the parasitic capacitance to other nodes. The feedback network carries very
small current and thick traces are not necessary. Another sensitive node to protect is the VOS pin. Use a thin
and short trace from the VOUT terminal of the output capacitor to the VOS pin. The VOS pin is right next to the
GND terminal. For very noisy systems, a small (0402 or 0201) 0.1 µF capacitor can be placed from VOS to GND
to filter high frequency noise on the VOS line.
10.1.3 Provide Thermal Path and Shielding
Using the available layers in the PCB can help provide additional shielding and improved thermal performance.
Large unbroken GND copper areas provide good thermal and return current paths. Flood unused PCB area with
GND copper. Use thermal vias to connect the GND copper between layers.
The required board area for proper thermal dissipation can be estimated using the power dissipation curves for
the desired output voltage and the package thermal resistance vs. board area curve. Refer to the power
dissipation graphs in the Typical Characteristics section. Using the power dissipation (PDISS) for the designed
input and output voltage and the max operating ambient temperature TA for the application, estimate the required
thermal resistance RθJA with the following expression.
RθJA - REQUIRED≤ (125ºC - TA) / PDISS
(8)
Then use Figure 80 to estimate the board copper area required to achieve the calculated thermal resistance.
Thermal Resistance J-A (°C/W)
100
2-LAYER 70 µm (2 oz) Cu
4-LAYER 70 µm (2 oz) Cu
90
80
70
60
50
40
30
20
0
5
10
Copper Area (cm2)
15
20
D012
Figure 80. Package Thermal Resistance vs. Board Copper Area
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Layout Guidelines (continued)
For example, for a design with 12-V input, 5-V output, and 1-A load the power dissipation according to Figure 7
is 0.53 W.
For 85°C ambient temperature, the RθJA-REQUIRED is ≤ (125°C – 85°C) / 0.53 W, or ≤ 75°C/W. Looking at
Figure 80 the minimum copper area required to achieve this thermal resistance with a 4-layer board and 70 µm
(2 oz) copper is approximately 3 cm².
10.2 Layout Example
The following example is for a 4-layer board. Layers 2 and 4 provide additional shielding and thermal path. If a 2layer board is used, apply the Layer 1 and Layer 3 copper patterns for the top and bottom layers, respectively.
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GND VIAS TO MINIMIZE INDUCTANCE IN
THE di/dt LOOP
GND
PLACE THE INPUT CAPACITOR AS CLOSE
AS POSSIBLE TO THE MODULE VIN AND
GND PINS
VIN
Layout Example (continued)
VIN EN VOS GND
GND
SS FB PG VOUT
LAYER 1
VOUT
PLACE THE FEEDBACK DIVIDER AS CLOSE
AS POSSIBLE TO THE MODULE TO KEEP
THE FB NODE SMALL
LAYER 2
UNBROKEN GND PLANE FOR THERMAL
PERFORMANCE AND SHIELDING
ENABLE CONNECTION
VOS CONNECTION t KEEP AWAY FROM
NOISE SOURCES
LAYER 3
CONNECTION TO THE SOFTSTART
CAPACITOR
POWER GOOD FLAG CONNECTION
UNBROKEN GND PLANE FOR THERMAL
PERFORMANCE AND SHIELDING
LAYER 4
Figure 81. Layout example
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Layout Example (continued)
10.2.1 High Density Layout Example for Space Constrained Applications
10.2.1.1 35 mm² Solution Size (Single Sided)
The following layout example uses 0805 case size components for the input and output capacitors and 0402
case size components for the rest of the passives.
LAYER 1
SS
VIN
FB
EN
LAYER 2
VIN
PG
VOS
VOUT
GND
GND
VOUT
GND
GND
LAYER 3
LAYER 4
VOS
VOUT
Figure 82. 35 mm² Solution Size (Single Sided)
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11 Device and Documentation Support
11.1 Device Support
Visit the TI E2E Community Support Forum to have your questions answered and designs reviewed.
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMZ21701 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Trademarks
DCS-Control, MicroSiP are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
32
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
LMZ21701SILR
uSiP
SIL
8
3000
330.0
12.4
3.75
3.75
2.2
8.0
12.0
Q2
LMZ21701SILT
uSiP
SIL
8
250
178.0
13.2
3.75
3.75
2.2
8.0
12.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ21701SILR
uSiP
SIL
8
3000
383.0
353.0
58.0
LMZ21701SILT
uSiP
SIL
8
250
223.0
194.0
35.0
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMZ21701SILR
ACTIVE
uSiP
SIL
8
3000
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 125
(TXN0703EC, TXN720
3EC)
EA
7485
1701
1701 7485 EA
LMZ21701SILT
ACTIVE
uSiP
SIL
8
250
Green (RoHS
& no Sb/Br)
NIAU
Level-3-260C-168 HR
-40 to 125
(TXN0703EC, TXN720
3EC)
EA
7485
1701
1701 7485 EA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMZ21701SILR
uSiP
SIL
8
3000
180.0
8.4
1.8
1.8
0.32
4.0
8.0
Q1
LMZ21701SILT
uSiP
SIL
8
250
180.0
8.4
1.8
1.8
0.32
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ21701SILR
uSiP
SIL
8
3000
182.0
182.0
20.0
LMZ21701SILT
uSiP
SIL
8
250
182.0
182.0
20.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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