Texas Instruments | TPS624xx-Q1 Automotive 2.25-MHz Fixed VOUT Dual Step-Down Converter (Rev. D) | Datasheet | Texas Instruments TPS624xx-Q1 Automotive 2.25-MHz Fixed VOUT Dual Step-Down Converter (Rev. D) Datasheet

Texas Instruments TPS624xx-Q1 Automotive 2.25-MHz Fixed VOUT Dual Step-Down Converter (Rev. D) Datasheet
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TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
TPS624xx-Q1 Automotive 2.25-MHz Fixed VOUT Dual Step-Down Converter
1 Features
3 Description
•
•
The TPS624xx-Q1 family of devices are synchronous
dual step-down DC-DC converters for Automotive
applications such as Advanced Driver Assistance
Systems (ADAS). They provide two independent
output voltage rails powered by a standard 3.3-V or
5-V voltage rail, with fixed output voltages optimized
for powering the CMOS imager or serializerdeserializer in ADAS camera modules.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Operating Junction Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
High Efficiency—Up to 95%
VIN Range From 2.5 V to 6 V
2.25-MHz Fixed-Frequency Operation
Output Current TPS62406-Q1 1000mA/400mA
Output Current TPS62407-Q1 400mA/600mA
Output Current TPS62422-Q1 1000mA/600mA
Output Current TPS62423-Q1 800mA/800mA
Output Current TPS62424-Q1 800mA/800mA
Fixed output voltages
EasyScale™ Optional One-Pin Serial Interface
Power-Save Mode at Light Load Currents
180° Out-of-Phase Operation
Output-Voltage Accuracy in PWM Mode ±1%
Typical 32-μA Quiescent Current for Both
Converters
100% Duty Cycle for Lowest Dropout
10 µF
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS62406-Q1
FB1
VSON (10)
3.00 mm × 3.00 mm
TPS62423-Q1
TPS62424-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
TPS62406-Q1 Efficiency vs Output Current, VOUT2
TPS62406-Q1
VIN
Device Information(1)
TPS62422-Q1
Automotive Point of Load Regulator
ADAS Camera Modules
Mirror Replacement (CMS)
Infotainment & Cluster
Simplified Schematic
VIN = 2.5 to 6 V
The TPS624xx-Q1 family of devices operates at 2.25MHz fixed switching frequency and enters the powersave mode operation at light load currents to maintain
high efficiency over the entire load-current range. For
low-noise applications, one can force the devices into
fixed-frequency PWM mode by pulling the
MODE/DATA pin high. The shutdown mode reduces
the current consumption to 1.2-μA, typical. The
devices allow the use of small inductors and
capacitors to achieve a small solution size.
TPS62407-Q1
2 Applications
•
•
•
•
The EasyScale™ serial interface allows outputvoltages modification during operation. The fixedoutput-voltage versions TPS624xx-Q1 support onepin-controlled simple dynamic voltage scaling for lowpower processors.
100
2.2 µH
SW1
DEF_1
VOUT1 = 1.125 V
1000 mA
90
80
10 µF
70
EN2
2.2 µH
SW2
MODE/
DATA
VOUT2 = 1.2 V
400 mA
10 µF
ADJ2
Efficiency (%)
EN1
60
50
40
30
20
VOUT2 = 1.2 V
MODE/DATA = low
GND
10
0
0.1
1
10
Output Current (mA)
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
100
400
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
8.5 Programming........................................................... 14
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
9.3 System Examples ................................................... 26
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
13.1 Package Option Addendum .................................. 30
13.2 Mechanical Data ................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2014) to Revision A
Page
•
Changed the IOUT1 and IOUT2 current for the TPS62406-Q1 device in the Device Comparison Table .................................. 3
•
Changed forward current limit PMOS and NMOS for the TPS62406-Q1 .............................................................................. 6
Changes from Revision A (October 2015) to Revision B
•
Page
Changed IOUT1 for the TPS62406-Q1 device to 1000 mA in the Electrical Characteristics table........................................... 6
Changes from Revision B (October 2016) to Revision C
Page
•
Revision C is the first public release of data sheet ............................................................................................................... 1
•
Changed data sheet title; changed device from TPS6240x-Q1 to TPS624xx-Q1 in all paragraphs; Revised text in
first paragraph of Description ................................................................................................................................................. 1
•
Added device numbers to Features list ................................................................................................................................. 1
•
Added TPS62422-Q1, TPS62423-Q1, and TPS62424-Q1 devices to the Design Requirements section ......................... 20
•
Added TPS62422-Q1 output voltage vs. output current characteristic ............................................................................... 23
•
Changed recommended layout example ............................................................................................................................. 28
Changes from Revision C (April 2018) to Revision D
•
2
Page
Changed TPS62422-Q1, TPS62423-Q1, and TPS62424-Q1 From: Product Preview To: Production.................................. 1
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SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
5 Device Comparison Table
PART NUMBER
DEFAULT OUTPUT VOLTAGE
VOUT1
TPS62406-Q1
Fixed default
DEF_1 = Low 1.125 V
VOUT2
Fixed default 1.2 V
VOUT1
TPS62407-Q1
DEF_1 = High 1.225 V
Fixed default
DEF_1 = Low 1.225 V
VOUT2
Fixed default 1.85 V
VOUT1
TPS62422-Q1
DEF_1 = High 1.8 V
Fixed default
DEF_1 = Low 1.15 V
VOUT2
Fixed default 1.2V
VOUT1
TPS62423-Q1
DEF_1 = High 1.5 V
Fixed default
DEF_1 = Low 1.2 V
VOUT2
Fixed default 1.8V
VOUT1
TPS62424-Q1
OUTPUT CURRENT
DEF_1 = High 1.125 V
DEF_1 = High 1.3 V
Fixed default
DEF_1 = Low 1.1 V
VOUT2
Fixed default 1.8V
IOUT1
1000 mA
IOUT2
400 mA
IOUT1
400 mA
IOUT2
600 mA
IOUT1
1000 mA
IOUT2
600 mA
IOUT1
800 mA
IOUT2
800 mA
IOUT1
800 mA
IOUT2
800 mA
6 Pin Configuration and Functions
DRC Package
10-Pin VSON With Thermal Pad
Top View
ADJ2
1
10
SW2
MODE/DATA
2
9
EN2
VIN
3
8
GND
FB1
4
7
EN1
DEF_1
5
6
SW1
Thermal Pad
Pin Functions
PIN
NAME
NO.
ADJ2
1
I/O
DESCRIPTION
I
Output voltage sense pin for the internal feedback divider. This pin must connect directly to the output. If
using the EasyScale interface-on converter 2, this pin must also connect directly to the output.
DEF_1
5
I
This pin defines the output voltage of converter 1 and is a digital input, that selects between two fixed
default output voltages. See Device Comparison Table for output voltage setting of the different device
options. For TPS62406-Q1 and TPS62407-Q1 the output voltage is same independent of DEF_1 pin
level. This pin must be terminated.
EN1
7
I
Enable input for converter 1, active-high. This pin must be terminated.
EN2
9
I
Enable input for converter 2, active-high. This pin must be terminated.
FB1
4
I
Output voltage sense pin for the internal feedback divider. This pin is connected to the output.
GND
8
—
GND for both converters; connect this pin to the thermal pad.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
This pin has two functions:
MODE/DATA
2
I/O
1. Operation-mode selection: With low level, enables power-save mode where the device operates in
PFM mode at light loads and automatically enters PWM mode at heavy loads. Pulling this PIN to
high forces the device to operate in PWM mode over the whole load range.
2. EasyScale interface function: One-wire serial interface to change the output voltage of both
converters. The pin has an open-drain output to provide an acknowledge condition if requested. The
current into the open-drain output stage may not exceed 500 μA. The EasyScale interface is active
if either EN1 or EN2 is high.
SW1
6
I/O
Switch pin of converter 1. Connect to inductor
SW2
10
I/O
Switch pin of converter 2. Connect to inductor
VIN
3
I
Thermal pad
—
Input pin, connect to supply or battery voltage, 2.5 V to 6 V. Connect the input capacitor CIN as close as
possible between VIN pin and GND pin.
Connect to GND
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Input voltage (2)
Voltage
(2)
Current
MIN
MAX
UNIT
VIN
–0.3
7
V
EN, MODE/DATA, DEF_1
–0.3
VIN + 0.3, ≤ 7
V
SW1, SW2
–0.3
7
V
ADJ2, FB1
–0.3
VIN + 0.3, ≤ 7
V
≤ 0.5
mA
150
°C
150
°C
MODE/DATA
Maximum operating junction temperature, TJmax
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 (1)
±2000
V
All pins
±500
Corner pins (1, 5, 6, and 10)
±750
Charged device model (CDM), per AEC
Q100-011
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Supply voltage
2.5
6
V
TJ
Operating junction temperature
–40
125
°C
4
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7.4 Thermal Information
TPS624xx-Q1
THERMAL METRIC (1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
42.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.9
°C/W
RθJB
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
18.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical values
are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
IQ
Operating quiescent current
ISD
Shutdown current
VUVLO
Undervoltage lockout threshold
2.5
6
One converter, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = 1 or EN2 = 1
19
35
Two converters, no load on the output. PFM mode
enabled (MODE/DATA = GND) device not switching,
EN1 = EN2 = 1
32
50
No load on the output, MODE/DATA = GND, for one
converter (1)
23
No load on the output, MODE/DATA = VIN, for one
converter (1)
3.6
EN1, EN2 = GND, VIN = 3.6 V
(2)
μA
mA
1.2
3
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V (3)
0.1
1.5
Falling
1.5
2.35
Rising
V
2.4
μA
V
ENABLE EN1, EN2
VIH
High-level input voltage range, EN1, EN2
1.2
VIN
VIL
Low-level input voltage range, EN1, EN2
0
0.4
V
IIN
Input bias current, EN1, EN2
1
μA
0.9
VIN
V
0
0.4
V
1
μA
V
EN1, EN2 = GND or VIN
0.05
V
DEF_1 INPUT
VDEF_1H
DEF_1 high-level digital input voltage range
VDEF_1L
DEF_1 low-level digital input voltage range
IIN
Input bias current DEF_1
DEF_1 = GND or VIN
0.01
MODE/DATA
VIH
High-level input voltage range, MODE/DATA
1.2
VIN
VIL
Low-level input voltage range, MODE/DATA
0
0.4
V
IIN
Input bias current, MODE/DATA
MODE/DATA = GND or VIN
1
μA
VOH
Acknowledge output voltage high
Open drain, through external pullup resistor
VIN
V
VOL
Acknowledge output voltage low
Open drain, sink current 500 μA
0.4
V
620
mΩ
1
μA
0.01
0
POWER SWITCH
rDS(on)
P-channel MOSFET on-resistance, converter
VIN = VGS = 3.6 V
1 and 2
ILK_PMOS
P-channel leakage current
(1)
(2)
(3)
280
VDS = 6 V
Device is switching with no load on the output, L1 = L2 = 3.3 μH, value includes losses of the coil.
These values are valid after enabling the device one time (EN1 or EN2 = high) and maintaining supply voltage VIN.
These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid
until enabling the device the first time (EN1 or EN2 = high). After the first enable, Note 3 becomes valid.
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Electrical Characteristics (continued)
VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical values
are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
N-channel MOSFET on-resistance converter
1 and 2
rDS(on)
ILK_SW1/SW2 Leakage current into SW1 or SW2 pin
Forward current limit
PMOS and NMOS
ILIMF
TSD
MIN
VIN = VGS = 3.6 V
Includes N-channel leakage current,
VIN = open, VSW = 6 V, EN = GND (4)
TYP
MAX
UNIT
200
450
mΩ
6
7.5
μA
TPS62406-Q1
VOUT1
2.5 V ≤ VIN ≤ 6 V
1.18
1.4
1.61
TPS62406-Q1
VOUT2
2.5 V ≤ VIN ≤ 6 V
0.68
0.8
0.92
TPS62407-Q1
VOUT1
2.5 V ≤ VIN ≤ 6 V
0.68
0.8
0.92
TPS62407-Q1
VOUT2
2.5 V ≤ VIN ≤ 6 V
0.75
1
1.15
TPS62422-Q1
VOUT1
2.5 V ≤ VIN ≤ 6 V
1.18
1.4
1.61
TPS62422-Q1
VOUT2
2.5 V ≤ VIN ≤ 6 V
0.75
1
1.15
TPS62423-Q1
VOUT1
2.5 V ≤ VIN ≤ 6 V
1
1.2
1.38
TPS62423-Q1
VOUT2
2.5 V ≤ VIN ≤ 6 V
1
1.2
1.38
TPS62424-Q1
VOUT1
2.5 V ≤ VIN ≤ 6 V
1
1.2
1.38
TPS62424-Q1
VOUT2
2.5 V ≤ VIN ≤ 6 V
1
1.2
1.38
A
Thermal shutdown
Increasing junction temperature
150
ºC
Thermal shutdown hysteresis
Decreasing junction temperature
20
ºC
600
mV
OUTPUT
Vref
Internal Reference voltage
Voltage positioning active,
MODE/DATA = GND,
device operating in PFM mode,
VIN = 2.5 V to 5 V (5) (6)
VOUTx(PFM)
DC output voltage accuracy
VOUTx(PWM)
DC output voltage load regulation
(4)
(5)
(6)
(7)
6
–1.5%
1%
2.5%
MODE/DATA = GND;
device operating in PWM mode,
VIN = 2.5 V to 6 V (6)
–1%
0%
1%
VIN = 2.5 V to 6 V, MODE/DATA = VIN,
Fixed PWM operation,
0 mA < IOUT1 < 400 mA ; 0 mA < IOUT2 < 600 mA (7)
–1%
0%
1%
PWM operation mode
0.5
%/A
An internal resistor of 1 MΩ connects pins SW1 and SW2 to GND.
Configuration L1 or L2 typ. 2.2 μH, COUTx typ 20 μF. See parameter measurement information, the output voltage ripple in PFM mode
depends on the effective capacitance of the output capacitor; larger output capacitors lead to tighter output voltage tolerance.
In power-save mode, the device typically enters PWM operation at IPSM = VIN / 32 Ω.
For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
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7.6 Timing Requirements
MIN
NOM
MAX
UNIT
INTERFACE TIMING
tStart
Start time
tH_LB
High-time low bit, logic 0 detection
Signal level on MODE/DATA pin is > 1.2 V
2
tL_LB
Low-time low bit, logic 0 detection
tL_HB
Low-time high bit, logic 1 detection
tH_HB
High-time high bit, logic 1 detection
Signal level on MODE/DATA pin is > 1.2 V
tEOS
End of stream
tACKN
Duration of acknowledge condition
(MODE/DATE line pulled low by the
device)
tvalACK
Acknowledge valid time
ttimeout
Time-out for entering power-save mode
μs
2
200
μs
Signal level on MODE/DATA pin < 0.4 V
2 x tH_LB
400
μs
Signal level on MODE/DATA pin < 0.4 V
2
200
μs
2 x tL_HB
400
μs
2
VIN 2.5 V to 6 V
400
MODE/DATA pin changes from high to low
μs
520
μs
2
μs
520
μs
7.7 Switching Characteristics
VIN = 3.6 V, EN1 = EN2 = VIN, MODE = GND, L1 = L2 = 2.2 μH, COUT1 = COUT2 = 20 μF, TJ = –40°C to 125°C, typical values
are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
2.25
2.7
MHz
OSCILLATOR
Oscillator frequency
3 V ≤ VIN ≤ 6 V (1)
tStart up
Start-up time
Activation time to start switching (2)
170
μs
tRamp
VOUTx ramp-up time
Time to ramp from 5% to 95% of
VOUTx
750
μs
fSW
OUTPUT
(1)
(2)
For VOUTx > 2 V, VIN min = VOUTx + 0.5 V
This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) with the other converter already
enabled (for example, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = 0) to active mode (EN1
and/or EN2 = 1), a typical value of typ 80 μs for ramp up of internal circuits must be added. After tStart, the converter starts switching and
ramps VOUTx.
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7.8 Typical Characteristics
2.6
30
2.4
28
Quiescent Current (PA)
Quiescent Current (PA)
26
2.2
2
1.8
1.6
1.4
24
22
20
18
16
40qC
25qC
85qC
125qC
1.2
1
2.5
40qC
25qC
85qC
125qC
14
12
10
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
2
2.5
3
3.5
4
4.5
Input Voltage (V)
D011
IOUT = 400 mA
MODE/DATA = high
EN1 = high
Figure 1. TPS62407-Q1 Switching Frequency
5
5.5
D012
EN2 = low
MODE/DATA = low
Figure 2. TPS26407-Q1 Quiescent Current, One Converter
On
0.55
50
–40°C
25°C
0.5
85°C
45
0.45
rDS(on) PMOS (W)
Quiescent Current (PA)
6
40
35
2.5
3
3.5
4
4.5
5
Input Voltage (V)
EN1 = EN2 = High
5.5
6
0.3
0.2
25
2
0.35
0.25
40qC
25qC
85qC
125qC
30
0.4
0.15
2.5
6.5
3
3.5
D001
4
4.5
5
5.5
6
Input Voltage (V)
MODE/DATA = low
Figure 3. TPS26407-Q1 Quiescent Current, Both Converters
On
Figure 4. rDS(on) PMOS vs VIN
0.3
–40°C
25°C
85°C
rDS(on) PMOS (Ω)
0.25
0.2
0.15
0.1
0.05
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
Figure 5. rDS(on) NMOS vs VIN
8
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8 Detailed Description
8.1 Overview
The TPS624xx-Q1 device includes two synchronous step-down converters. The converters operate with typically
2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. With the powersave mode enabled, the converters automatically enter power-save mode at light load currents and operate in
PFM (pulse frequency modulation).
During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with inputvoltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns
on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET turns off
and the N-channel MOSFET turns on. If the current in the N-channel MOSFET is above the N-MOS current limit
threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input rms current.
8.1.1 Converter 1
It is possible to change the output voltage of converter 1 with the EasyScale serial Interface. This makes the
device very flexible for output-voltage adjustment. In this case, the device uses an internal resistor network.
The output voltage can also be selected using the DEF_1 pin configuration as a digital input. For these voltage
version the DEF_1 pin select the same output voltage for DEF_1=high or DEF_1=low.
8.1.2 Converter 2
It is also possible to change the output voltage of converter 2 via the EasyScale interface.
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8.2 Functional Block Diagram
VIN
PMOS Current
Limit Comparator
Converter 1
VIN
FB_VOUT
Thermal
Shutdown
Softstart
VREF +1%
Skip Comp.
EN1
FB_VOUT
VREF- 1%
Ext. res. network
DEF1
Skip Comp. Low
VREF
Control
Stage
Error Amp.
Internal
FB
VOUT1 compensated
Int. Resistor
Network
PWM
Comp.
Cff 25pF
SW1
MODE
Register
RI 1
Sawtooth
Generator
DEF1_High
RI3
RI..N
FB1
Gate Driver
GND
DEF1_Low
Average
Current Detector
Skip Mode Entry
Note 1
NMOS Current
Limit Comparator
CLK 0°
Reference
Easy Scale
Interface
Mode/
DATA
ACK
MOSFET
Open drain
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180°
Converter 2
Int. Resistor
Network
Load Comparator
2.25MHz
Oscillator
VIN
FB_VOUT
VREF +1%
Skip Comp.
Register
FB_VOUT
DEF2
Note 2
Cff 25pF
VREF- 1%
Skip Comp. Low
VREF
Error Amp.
RI 1
Internal
compensated
RI..N
Control
Stage
Gate Driver
PWM
Comp.
SW2
MODE
FB_VOUT2
ADJ2
Thermal
Shutdown
Softstart
Sawtooth
Generator
CLK 180°
GND
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
EN2
Load Comparator
GND
10
(1)
In the fixed output-voltage version, the DEF_1 pin connects to an internal digital input and disconnects from the error
amplifier.
(2)
To set the output voltage of converter 2 through the EasyScale™ interface, the ADJ2 pin must directly connect to
VOUT2.
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8.3 Feature Description
8.3.1 Enable
The device has a separate EN pin for each converter to start up each converter independently. If EN1 or EN2 is
set to high, the corresponding converter starts up with soft start.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2
μA. In this mode, the P- and N-channel MOSFETs turn off and the entire internal control circuitry switches off.
For proper operation, terminate the EN1 and EN2 pins, do not leave them floating.
8.3.2 DEF_1 Pin Function
The DEF_1 pin, dedicated to converter 1, makes the output voltage selection very flexible to support dynamic
voltage management. Having this pin tied to a low level sets the output voltage according to the value in register
REG_DEF_1_Low. The default voltage is 1.125 V for TPS62406-Q1. Having the pin tied to a high level sets the
output voltage according to the value in register REG_DEF_1_High. The default value in this case is 1.125 V as
well. The level of the DEF_1 pin selects between the two registers, REG_DEF_1_Low and REG_DEF_1_High,
for the output-voltage setting. One can change the content of each register (and therefore output voltage)
individually through the EasyScale interface. This makes the device very flexible in terms of output voltage
setting; see Table 3
8.3.3 180° Out-of-Phase Operation
In PWM mode, the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This
prevents the high-side switches of both converters from turning on simultaneously, reducing the input current
ripple. This feature reduces the surge current drawn from the supply.
8.3.4 Short-Circuit Protection
Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it turns off and the NMOS switch turns on. The PMOS only turns on again
once the current in the NMOS decreases below the NMOS current limit.
8.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs turn off. The device continues its operation when the junction
temperature falls below the thermal-shutdown hysteresis.
8.3.6
EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
8.3.6.1 General
The EasyScale interface is a simple but very flexible one-pin interface to configure the output voltage of both DCDC converters. A master-slave structure is the basis of the interface, where the master is typically a
microcontroller or application processor. Figure 8 and Table 2 give an overview of the protocol. The protocol
consists of a device-specific address byte and a data byte. The device-specific address byte is fixed to 4E hex.
The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high
indicates the request-for-acknowledge condition. The acknowledge condition only applies after correct reception
of the protocol.
The advantage of the EasyScale interface compared to other one-pin interfaces is that its bit detection is to a
large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kb/s and
up to 160 kb/s. Furthermore, the interface shares the MODE/DATA pin and requires no additional pin.
8.3.6.2 Protocol
Transmission of all bits is MSB first and LSB last. Figure 9 shows the protocol without the acknowledge request
(bit RFA = 0), Figure 10 with the acknowledge request (bit RFA = 1).
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Feature Description (continued)
Prior to both bytes, device address byte and data byte, one must apply a start condition. For this, pull the
MODE/DATA pin high for at least tStart before the bit transmission starts with the falling edge. In case the
MODE/DATA line was already at a high level (forced PWM mode selection), the device requires no start
condition prior to the device address byte.
Close the transmission of each byte with an end-of-stream condition for at least tEOS.
8.4 Device Functional Modes
8.4.1 Power-Save Mode
Setting the MODE/DATA pin to low for both converters enables power-save mode. If the load current of a
converter decreases, this converter enters power-save-mode operation automatically. The transition of a
converter to power-save mode is independent from the operating condition of the other converter. During powersave mode, the converter operates with reduced switching frequency in PFM mode and with a minimum
quiescent current to maintain high efficiency. The converter positions the output voltage in PFM mode to typically
1% above nominal VOUTx. This voltage positioning feature minimizes voltage drops caused by a sudden load
step.
In order to optimize the converter efficiency at light load, the device monitors average inductor current. The
device changes from PWM mode to power-save mode if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold, which one can calculate using Equation 1 for each converter,
depends on VIN.
Equation 1: Average output current threshold to enter PFM mode
VINDCDC
I OUT_PFM_enter +
32 W
(1)
Equation 2: Average output current threshold to leave PFM mode
VINDCDC
I OUT_PFM_leave +
24 W
(2)
To keep the output-voltage ripple in power-save mode low, a single threshold comparator (skip comparator)
monitors the output voltage. As the output voltage falls below the skip-comparator threshold (skip comp) of 1%
above nominal VOUTx, the corresponding converter starts switching for a minimum time period of typically 1 μs
and provides current to the load and the output capacitor. Therefore, the output voltage increases and the device
maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment, all switching activity stops and the quiescent current reduces to minimum. The output capacitor supplies
the load until the output voltage has dropped below the threshold again. Hereupon, the device starts switching
again.
The converter leaves power-save mode and enters PWM mode if the output current exceeds the IOUT_PFM_leave
current or if the output voltage falls below a second comparator threshold, called the skip-comparator-low (Skip
Comp Low) threshold. This skip-comparator-low threshold is 2% below nominal VOUTx and enables a fast
transition from power-save mode to PWM mode during a load step.
Power-save mode typically reduces the quiescent current to 19 μA for one converter and 32 μA for both
converters active. This single-skip comparator threshold method in power-save mode results in a very low
output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.
Increasing output capacitor values minimizes the output ripple. One can disable the power-save mode by setting
the MODE/DATA pin to high. Both converters then operate in fixed PWM mode. Power-save mode enable or
disable applies to both converters.
8.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage under- and overshoots at load steps from light to heavy load and from heavy to
light load. Power-save-mode operation activates dynamic voltage positioning and provides more headroom for
both the voltage drop at a load step and the voltage increase when a load is switched off, which improves loadtransient behavior.
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Device Functional Modes (continued)
At light loads, in which the converter operates in PFM mode, the output voltage regulation is typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to 2% below the nominal value and enters PWM mode. During a
load transition from heavy load to light load, the device also minimizes voltage overshoot because of active
regulation turning on the N-channel switch.
Smooth
increased load
+1%
Fast load transient
PFM Mode
light load
PFM Mode
light load
VOUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
COMP_LOW threshold -2%
Figure 6. Dynamic Voltage Positioning
8.4.1.2 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during startup. Figure 7 shows
control of the output-voltage ramp-up during soft start.
EN
95%
5%
VOUT
t Startup
tRAMP
Figure 7. Soft Start
8.4.1.3 100% Duty-Cycle Low-Dropout Operation
The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the
100% duty-cycle mode. In this mode, the P-channel switch is constantly on. This is particularly useful in batterypowered applications to achieve longest operation time by taking full advantage of the whole battery-voltage
range. The minimum input voltage to maintain regulation depends on the load current and output voltage, which
one can calculate as:
Vin min + Vout max ) Iout max
ǒRDSonmax ) R LǓ
with
•
•
•
•
IOUTxmax = maximum output current plus inductor ripple current
rDS(on)max = maximum P-channel switch rDS(on)
RL = dc resistance of the inductor
VOUTxmax = nominal output voltage plus maximum output-voltage tolerance
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(3)
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Device Functional Modes (continued)
With decreasing load current, the device automatically switches into pulse-skipping operation, in which the power
stage operates intermittently based on load demand. Running cycles periodically minimizes the switching losses,
and the device runs with a minimum quiescent current, maintaining high efficiency.
8.4.1.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunction at low input voltages and from excessive
discharge of the battery, and disables the converters. The undervoltage lockout threshold is typically 1.5 V;
maximum of 2.35 V. In case the interface overwrites the default register values, the new values in the registers
REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall
below the undervoltage lockout threshold, independent of disabling of the converters.
8.4.2 Mode Selection
The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides mode selection) a one-pin interface
to receive serial data from a host to set the output voltage, as described in the EasyScale Interface section.
Connecting this pin to GND enables the automatic PWM and power-save-mode operation. The converters
operate in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads,
maintaining high efficiency over a wide load-current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light
load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the powersave mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
In the case of changing the operation mode from forced PWM mode (MODE/DATA = high) to power-save mode
(MODE/DATA = 0), enabling the power-save mode occurs after a delay time of ttimeout, which is 520 μs maximum.
Setting the MODE/DATA to 1 enables forced-PWM-mode operation immediately.
8.5 Programming
8.5.1 Addressable Registers
Three registers with a data content of 5 bits are addressable. With 5-bit data content, 32 different values for each
register are available. Table 1 shows the addressable registers to set the output voltage when the DEF_1 pin
works as a digital input. In this case, converter 1 has a related register for each DEF_1 pin condition, and one
register for converter 2. A high or low condition on pin DEF_1 selects either the content of register
REG_DEF_1_High or REG_DEF_1_Low, thus setting the output voltage of converter 1 according to the values in
Selectable Output Voltage Converter 1, With Pin DEF_1 as Digital Input. Use of a precise internal resistor divider
network to generate these output voltages makes external resistors unnecessary (less board space) and
provides higher output-voltage accuracy. Enabling at least one of the converters (EN1 or EN2 is high) activates
the interface. After the startup time tStart (170 μs), the interface is ready for data reception.
Table 1. Addressable Registers for Default Fixed-Output Voltage Options (PIN DEF_1 = Digital Input)
DEVICE
TPS624xx-Q1 ,
REGISTER
DESCRIPTION
A1
A0
D4
D3
D2
D1
D0
REG_DEF_1_High
Converter 1 output voltage setting for
DEF_1 = High condition. The content of the
register is active with the DEF_1 pin high.
High
0
1
Output voltage setting, see Table 3
REG_DEF_1_Low
Converter 1 output voltage setting for
DEF_1 = Low condition.
Low
0
0
Output voltage setting, see Table 3
REG_DEF_2
Converter 2 output voltage
Not
applicable
1
0
Output voltage setting, see Table 4
1
1
Do not use
14
DEF_1
PIN
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8.5.1.1 Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between the low time and high
time of the low or high bit (tL_xB and tH_xB). Bit detection can be simplified to:
High bit: tH_HB > tL_HB, but with tH_HB at least 2× tL_HB, see Figure 8.
Low bit: tL_LB > tH_LB, but with tL_LB at least 2× tH_LB, see Figure 8.
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Detection
of a 0 or 1 depends on the relation between tL_xB and tH_xB.
8.5.1.2 Acknowledge
The device only applies the acknowledge condition if all of the following occurs:
• A set RFA bit requests an acknowledge
• The transmitted device address matches with the device address of the device
• Correct reception of 16 bits occurred
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is 520 μs maximum. The acknowledge condition is valid after an internal delay time tvalACK. This
means the internal ACKN-MOSFET turns on after tvalACK, on detection of the last falling edge of the protocol. The
master controller keeps the line low during this time.
The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after
tvalACK and reading back a 0.
In case of an invalid device address, or not-correctly-received protocol, application of a no-acknowledge
condition does not occur; thus, the internal MOSFET does not turn on, and the external pullup resistor pulls the
MODE/DATA pin high after tvalACK. One can use the MODE/DATA pin again after the acknowledge condition
ends.
NOTE
The master device must have an open-drain output in order to request the acknowledge
condition.
In case of a push-pull output stage, TI recommends using a series resistor in the MODE/DATA line to limit the
current to 500 μA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET.
8.5.1.3 Mode Selection
Use of the MODE/DATA pin for two functions, interface and mode selection, necessitates a determination of
when to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device also stays in forced PWM mode during the entire protocol reception time.
With a falling edge on the MODE/DATA pin, the device starts bit decoding. If the MODE/DATA pin stays low for
at least ttimeout, the device gets an internal time-out and enables power-save-mode operation.
The device ignores a protocol sent within this time because the first interpretation of a falling edge for the mode
change is at the start of the first bit. In this case, TI recommends sending the protocol first, and then changing to
power-save mode at the end of the protocol.
DATA IN
Start
Start
Device Address
DA7 DA6 DA5 DA4
0
1
0
0
DA3 DA2 DA1
1
1
1
DATABYTE
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 8. EasyScale Protocol Overview
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Table 2. EasyScale Bit Description
BYTE
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
Device
address
byte
7
DA7
IN
0 MSB device address
6
DA6
IN
1
5
DA5
IN
0
4
DA4
IN
0
3
DA3
IN
1
2
DA2
IN
1
1
DA1
IN
1
4E hex
Data
byte
DESCRIPTION
0
DA0
IN
0 LSB device address
7 (MSB)
RFA
IN
Request for acknowledge; if high, the device applies an acknowledge condition.
6
A1
Address bit 1
5
A0
Address bit 0
4
D4
Data bit 4
3
D3
Data bit 3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
OUT
Acknowledge condition active 0, the device applies this condition only in the case of
a set RFA bit. Open-drain output, the host must pull the line high with a pullup
resistor.
One can only use this feature if the master has an open-drain output stage. In case
of a push-pull output stage, do not request an acknowledge condition.
tStart
DATA IN
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
0
TEOS
D0
1
TEOS
Figure 9. EasyScale Protocol Without Acknowledge
tStart
DATA IN
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
T EOS
RFA
1
D0
1
tvalACK
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
ACKN
tACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
Figure 10. EasyScale Protocol Including Acknowledge
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t Low
tHigh
t Low
t High
Low Bit
High Bit
(Logic 0)
(Logic 1)
Figure 11. EasyScale – Bit Coding
MODE/DATA
ttimeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 12. MODE/DATA PIN: Mode Selection
tStart Address Byte
tStart DATA Byte
MODE/DATA
TEOS
TEOS
t timeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 13. MODE/DATA Pin: Power-Save-Mode and Interface Communication
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Table 3. Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input
18
TPS624xx-Q1 OUTPUT
VOLTAGE [V]
REGISTER REG_DEF_1_LOW
TPS624xx-Q1
VOLTAGE [V]
REGISTER REG_DEF_1_HIGH
D4
D3
D2
D1
D0
0
0.8
0.9
0
0
0
0
0
1
0.825
0.925
0
0
0
0
1
2
0.85
0.95
0
0
0
1
0
3
0.875
0.975
0
0
0
1
1
4
0.9
1.0
0
0
1
0
0
5
0.925
1.025
0
0
1
0
1
6
0.95
1.050
0
0
1
1
0
7
0.975
1.075
0
0
1
1
1
8
1.0
1.1
0
1
0
0
0
9
1.025
1.125
0
1
0
0
1
10
1.050
1.150
0
1
0
1
0
11
1.075
1.175
0
1
0
1
1
12
1.1
1.2
0
1
1
0
0
13
1.125
1.225
0
1
1
0
1
14
1.150
1.25
0
1
1
1
0
15
1.175
1.275
0
1
1
1
1
16
1.2
1.3
1
0
0
0
0
17
1.225
1.325
1
0
0
0
1
18
1.25
1.350
1
0
0
1
0
19
1.275
1.375
1
0
0
1
1
20
1.3
1.4
1
0
1
0
0
21
1.325
1.425
1
0
1
0
1
22
1.350
1.450
1
0
1
1
0
23
1.375
1.475
1
0
1
1
1
24
1.4
1.5
1
1
0
0
0
25
1.425
1.525
1
1
0
0
1
26
1.450
1.55
1
1
0
1
0
27
1.475
1.575
1
1
0
1
1
28
1.5
1.6
1
1
1
0
0
29
1.525
1.7
1
1
1
0
1
30
1.55
1.8
1
1
1
1
0
31
1.575
1.9
1
1
1
1
1
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SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
Table 4. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT2)
OUTPUT VOLTAGE [V]
FOR REGISTER REG_DEF_2
D4
D3
D2
D1
D0
0
0.6
0
0
0
0
0
1
0.85
0
0
0
0
1
2
0.9
0
0
0
1
0
3
0.95
0
0
0
1
1
4
1
0
0
1
0
0
5
1.05
0
0
1
0
1
6
1.1
0
0
1
1
0
7
1.15
0
0
1
1
1
8
1.2
0
1
0
0
0
9
1.25
0
1
0
0
1
10
1.3
0
1
0
1
0
11
1.35
0
1
0
1
1
12
1.4
0
1
1
0
0
13
1.45
0
1
1
0
1
14
1.5
0
1
1
1
0
15
1.55
0
1
1
1
1
16
1.6
1
0
0
0
0
17
1.7
1
0
0
0
1
18
1.8
1
0
0
1
0
19
1.85
1
0
0
1
1
20
2
1
0
1
0
0
21
2.1
1
0
1
0
1
22
2.2
1
0
1
1
0
23
2.3
1
0
1
1
1
24
2.4
1
1
0
0
0
25
2.5
1
1
0
0
1
26
2.6
1
1
0
1
0
27
2.7
1
1
0
1
1
28
2.8
1
1
1
0
0
29
2.85
1
1
1
0
1
30
3
1
1
1
1
0
31
3.3
1
1
1
1
1
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9 Application and Implementation
NOTE
Information in the following application sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Application Information
The TPS624xx-Q1 family of devices are synchronous dual step-down DC-DC converters. The devices provide
two independent output voltage rails. The following information provides guidance on selecting external
components to complete the application design.
9.2 Typical Application
VIN = 2.5 to 6 V
TPS62406-Q1
VIN
10 µF
FB1
2.2 µH
SW1
DEF_1
VOUT1 = 1.125 V
1000 mA
10 µF
EN1
EN2
2.2 µH
SW2
MODE/
DATA
VOUT2 = 1.2 V
400 mA
10 µF
ADJ2
GND
Figure 14. Typical Application Schematic
9.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs. The following
design procedure is adequate for whole VIN, VOUTx and load current range of the TPS624xx-Q1 family of devices.
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Setting
9.2.2.1.1 Converter 1 Fixed Default Output-Voltage Setting
The DEF_1 pin selects output voltage VOUT1.
Pin DEF_1 = low:
• TPS62406-Q1, TPS62407-Q1 = 1.125 V
• TPS62422-Q1 = 1.15V
• TPS62423-Q1 = 1.2V
• TPS62424-Q1 = 1.1V
Pin DEF_1 = high:
• TPS62406-Q1 =
• TPS62407-Q1 =
• TPS62422-Q1 =
• TPS62423-Q1 =
• TPS62424-Q1 =
20
1.125 V
1.225 V
1.8V
1.5V
1.3V
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Typical Application (continued)
9.2.2.1.2 Converter 2 Fixed Default Output-Voltage Setting
ADJ2 pin must be directly connected with VOUT2:
• TPS62406-Q1, VOUT2 default = 1.2 V
• TPS62407-Q1, VOUT2 default = 1.85 V
• TPS62422-Q1, VOUT2 default = 1.2 V
• TPS62423-Q1, VOUT2 default = 1.8 V
• TPS62424-Q1, VOUT2 default = 1.8 V
9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
The converters operate with a minimum inductance of 1.75 μH and minimum capacitance of 6 μF. The device
operation is optimum with inductors of 2.2 μH to 4.7 μH and output capacitors of 10 μF to 22 μF.
9.2.2.2.1 Inductor Selection
Select the inductor based on its ratings for dc resistance and saturation current. The dc resistance of the inductor
directly influences the efficiency of the converter. Therefore, select an inductor with lowest dc resistance for
highest efficiency.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation-current rating of
the inductor should be higher than the maximum inductor current as calculated with Equation 5. TI makes this
recommendation because during heavy load transients the inductor current rises above the calculated value.
DI L + Vout
1 * Vout
Vin
ƒ
L
where
•
•
•
ΔIL = Peak-to-peak inductor ripple current
L = Inductor value
f = Switching frequency (2.25 MHz typical)
I Lmax + I outmax )
(4)
DI L
2
where
•
ILmax = Maximum inductor current
and the highest inductor current occurs at maximum VIN.
(5)
Open-core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Take into consideration that the core material from inductor to inductor differs, and this
difference has an impact on the efficiency.
See Table 5 and the typical application circuit examples for possible inductors.
Table 5. List of Inductors
DIMENSIONS [mm]
INDUCTOR TYPE
SUPPLIER
3.2 × 2.6 × 1
MIPW3226
FDK
3 × 3 × 0.9
LPS3010
Coilcraft
2.8 × 2.6 × 1
VLF3010
TDK
2.8 x 2.6 × 1.4
VLF3014
TDK
3 × 3 × 1.4
LPS3015
Coilcraft
3.9 × 3.9 × 1.7
LPS4018
Coilcraft
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9.2.2.2.2 Output-Capacitor Selection
The advanced fast-response voltage-mode control scheme of the converters allows the use of tiny ceramic
capacitors with a typical value of 10 μF to 22 μF, without having large output-voltage under- and overshoots
during heavy load transients. Ceramic capacitors with low ESR values result in lowest output-voltage ripple, and
TI therefore recommends them. The output capacitor requires either X7R or X5R dielectric. TI does not
recommend Y5V and Z5U dielectric capacitors because of their wide variation in capacitance.
If using ceramic output capacitors, the capacitor rms ripple-current rating always meets the application
requirements. The rms ripple current calculation is:
1 * Vout
1
Vin
I RMSCout + Vout
ƒ
L
2
Ǹ3
(6)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and
discharging the output capacitor:
DVout + Vout
1 * Vout
Vin
L
ƒ
ǒ8
1
Cout
ƒ
Ǔ
) ESR
where the highest output-voltage ripple occurs at the highest input voltage, VIN.
(7)
At light load currents, the converters operate in power-save mode and the output-voltage ripple depends on the
output-capacitor value. The internal comparator delay and the external capacitor set the output-voltage ripple.
Higher output capacitors like 22 μF values minimize the voltage ripple in PFM mode and tighten dc output
accuracy in PFM mode.
9.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, the device requires a low-ESR
input capacitor to prevent large voltage transients that can cause misbehavior of the device or interference with
other circuits in the system. An input capacitor of 10 μF is sufficient.
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves
60
50
40
30
40
20
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.1
1
10
Output Current (mA)
VOUT1 = 1.225 V
100
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1000
0
50
100
D004
MODE/DATA = low
Figure 15. TPS62407-Q1 Efficiency, VOUT1
22
50
30
20
0
0.01
60
VOUT1 = 1.225 V
150 200 250 300
Output Current (mA)
350
400
450
D009
MODE/DATA = high
Figure 16. TPS62407-Q1 Efficiency, VOUT1
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
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60
50
40
30
50
40
30
20
20
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.01
60
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.1
1
10
Output Current (mA)
VOUT2 = 1.85 V
100
1000
0
MODE/DATA = low
300
400
500
Output Current (mA)
600
700
D0010
MODE/DATA = high
Figure 18. TPS62407-Q1 Efficiency, VOUT2
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
200
VOUT2 = 1.85 V
Figure 17. TPS62407-Q1 Efficiency, VOUT2
60
50
40
30
60
50
40
30
20
20
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.1
1
10
Output Current (mA)
VOUT1 = 1.125 V
100
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.1
1000
1
10
Output Current (mA)
D003
MODE/DATA = low
VOUT1 = 1.125 V
Figure 19. TPS62406-Q1 Efficiency, VOUT1
100
1000
D007
MODE/DATA = high
Figure 20. TPS62406-Q1 Efficiency, VOUT2
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
D005
60
50
40
30
60
50
40
30
20
20
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
0
0.1
1
VOUT2 = 1.2 V
10
Output Current (mA)
100
VIN = 2.5 V
VIN = 3.5 V
VIN = 5 V
10
400
0
0.1
1
D006
MODE/DATA = low
Figure 21. TPS62406-Q1 Efficiency, VOUT2
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VOUT2 = 1.2 V
10
Output Current (mA)
100
400
D008
MODE/DATA = high
Figure 22. TPS62406-Q1 Efficiency, VOUT2
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1.836
1.171 Conditions:
VOUT1=1.15V, VOUT2=1.2V @ 1000mA
1.167 TA=85OC
1.163
Conditions:
1.828 VOUT1=1.8V, VOUT2=1.2V @ 600mA
TA=85OC
1.82
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
VIN=5.5V
VIN=6V
1.159
1.155
Output 1 Voltage [V]
Output 1 Voltage [V]
1.175
1.151
1.147
1.143
1.139
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
VIN=5.5V
VIN=6V
1.812
1.804
1.796
1.788
1.78
1.135
1.772
1.131
1.127
0.5
0.55
0.6
0.65 0.7 0.75 0.8 0.85
Output 1 Current [A]
VOUT1 = 1.15 V, VOUT2 = 1.2 V
0.9
0.95
1
MODE/DATA = high
Figure 23. TPS62422-Q1 VOUT1 vs. IOUT1
1.764
0.5
0.55
0.6
0.65 0.7 0.75 0.8 0.85
Output 1 Current [A]
VOUT1 = 1.8 V, VOUT2 = 1.2 V
0.9
0.95
1
MODE/DATA = high
Figure 24. TPS62422-Q1 VOUT1 vs. IOUT1
Output 2 Voltage [V]
1.224
1.22 Conditions:
VOUT2=1.2V, VOUT1=1.8V @ 1000mA
1.216 TA=85OC
1.212
VIN=2.7V
VIN=3.3V
VIN=3.9V
VIN=4.5V
VIN=5V
VIN=5.5V
VIN=6V
1.208
1.204
VO = 1.8 V 20 mV/div
1.2
1.196
Inductor current = 100 mA/div
1.192
1.188
1.184
1.18
1.176
0.3
0.35
0.4
0.45
0.5
Output 2 Current [A]
VOUT1 = 1.8 V, VOUT2 = 1.2 V
0.55
0.6
MODE/DATA = high
Figure 25. TPS62422-Q1 VOUT2 vs. IOUT2
Time base - 10 µs/div
Power save mode
MODE/DATA = low
IOUT = 10 mA
Figure 26. Light-Load Output-Voltage Ripple in PowerSave Mode
VO ripple 20 mV/div
VO = 1.8 V 20 mV/div
Inductor current 100 mA/div
Inductor current 200 mA/div
Time base - 400 ns/div
Forced PWM mode
MODE/DATA =
high
IOUT = 10 mA
Figure 27. Output-Voltage Ripple in Forced-PWM Mode
24
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Time base - 200 ns/div
PWM mode
VOUT = 1.8 V
IOUT = 400 mA
Figure 28. Output-Voltage Ripple in PWM Mode
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Forced PWM
Mode
VO = 1.575 V
50 mV/div
MODE/DATA 1 V/div
Enable Power Save Mode
Entering PFM Mode
Voltage positioning active
Voltage positioning in PFM
Mode reduces voltage drop
during load step
VO 20 mV/div
IO = 200 mA/div
PWM Mode operation
IO(1) = 360 mA
IO = 40 mA
Time base - 200 µs/div
VOUT = 1.8 V
Time base - 50 µs/div
IOUT = 20 mA
MODE/DATA = low
Figure 29. Forced PWM-to-PFM Mode Transition
VO = 1.575 V
50 mV/div
PWM Mode operation
IO = 200 mA/div
IO(1) = 360 mA
Figure 30. Load-Transient Response, PFM-to-PWM
VDD = 1 V/div
VO = 50 mV/div
IO = 40 mA
Time base - 400 µs/div
Time base - 50 µs/div
PWM mode
MODE/DATA = high
MODE/DATA = low
IOUT1 = 200 mA
VIN = 3.6 to 4.6 V
VOUT1 = 1.575 V
Figure 32. Line-Transient Response
Figure 31. Load-Transient Response, PWM Operation
EN1 and EN2 5 V/div
VO(1)
500 mV/div
SW1 1 V/div
I(coil) 500 mA/div
Time base - 200 µs/div
VIN = 3.8 V
IOUT1max = 400 mA
Figure 33. Startup Timing, One Converter
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9.3 System Examples
TPS62406-Q1
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
10 µF
SW1
VOUT1 = 1.125 V
1000 mA
22 µF
DEF_1
EN1
EN2
2.2 µH
SW2
MODE/
DATA
VOUT2 = 1.2 V
400 mA
22 µF
ADJ2
GND
Figure 34. TPS62406-Q1 Fixed 1.125-V and 1.2-V Outputs
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System Examples (continued)
TPS62407-Q1
VIN = 2.5 to 6 V
VIN
FB1
2.2 µH
10 µF
SW1
VOUT1 = 1.225 V
400 mA
10 µF
DEF_1
EN1
EN2
2.2 µH
SW2
MODE/
DATA
VOUT2 = 1.85 V
600 mA
10 µF
ADJ2
GND
Figure 35. TPS62407-Q1 Fixed 1.225-V and 1.85-V Outputs
VIN = 2.5 to 6 V
TPS62422-Q1
VIN
10 µF
FB1
2.2 µH
VOUT1 = 1.15 V
up to 1000 mA
SW1
DEF_1
22 µF
EN1
EN2
2.2 µH
VOUT2 = 1.2 V
up to 600 mA
SW2
MODE/
DATA
22 µF
ADJ2
GND
Figure 36. TPS62422-Q1 Fixed 1.15-V and 1.2-V Outputs
VOUT1 = 1.8V
up to 1000mA
22 µF
VOUT2 = 1.2V
up to 600mA
22 µF
Figure 37. TPS62422-Q1 Fixed 1.8-V and 1.2-V Outputs
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10 Power Supply Recommendations
This device has no special recommendation for the power supply. TI recommends to use the values listed in the
Recommended Operating Conditions table.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout.
It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for
the main current paths as indicated in bold in Figure 38.
Place the input capacitor as close as possible to the IC pins VIN and GND, the inductor and output capacitor
as close as possible to the pins SW1 and GND.
Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each
converter, use a common power GND node and a different node for the signal GND to minimize the effects of
ground noise.
Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common
path to the GND PIN, which returns the small signal components and the high current of the output
capacitors, as short as possible to avoid ground noise.
Connect the output voltage-sense lines (FB 1, DEF_1, ADJ2) right to the output capacitor and route them
away from noisy components and traces (for example, the SW1 and SW2 lines).
If operating the EasyScale interface with high transmission rates, route the MODE/DATA trace away from the
ADJ2 line to avoid capacitive coupling into the ADJ2 pin.
A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
COUT
VOUT1
CIN
VIN
CIN
COUT
VOUT2
11.2 Layout Example
GND
Figure 38. Layout Diagram
28
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 6. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62406-Q1
Click here
Click here
Click here
Click here
Click here
TPS62407-Q1
Click here
Click here
Click here
Click here
Click here
TPS62422-Q1
Click here
Click here
Click here
Click here
Click here
TPS62423-Q1
Click here
Click here
Click here
Click here
Click here
TPS62424-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
EasyScale, the EasyScale, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
29
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
www.ti.com
13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Op Temp (°C)
Device Marking (4) (5)
TPS62406QDRCRQ1
PREVIEW
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
2406Q
TPS62407QDRCRQ1
PREVIEW
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
SHU
TPS62422QDRCRQ1
PREVIEW
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
TPS62423QDRCRQ1
PREVIEW
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
TPS62424QDRCRQ1
PREVIEW
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
30
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
www.ti.com
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS62406QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
W2
TPS62407QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
W2
TPS62422QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
W2
TPS62423QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
W2
TPS62424QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
W2
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
31
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
www.ti.com
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
32
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62406QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62407QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62422QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62423QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62424QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
www.ti.com
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
13.2 Mechanical Data
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
33
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
www.ti.com
13.2.1 Thermal Pad Mechanical Data
34
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
TPS62406-Q1, TPS62407-Q1, TPS62422-Q1, TPS62423-Q1, TPS62424-Q1
www.ti.com
SLVSCH9D – DECEMBER 2014 – REVISED AUGUST 2018
13.2.2 Land Pattern Data
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS62406-Q1 TPS62407-Q1 TPS62422-Q1 TPS62423-Q1 TPS62424-Q1
35
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS62406QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
2406Q
TPS62407QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
SHU
TPS62422QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
2422Q
TPS62423QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
2423Q
TPS62424QDRCRQ1
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-3-260C-168 HR
-40 to 125
2424Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS62406QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62407QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62422QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62423QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62424QDRCRQ1
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62406QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62407QDRCRQ1
VSON
DRC
10
3000
367.0
367.0
35.0
TPS62422QDRCRQ1
VSON
DRC
10
3000
338.0
355.0
50.0
TPS62423QDRCRQ1
VSON
DRC
10
3000
338.0
355.0
50.0
TPS62424QDRCRQ1
VSON
DRC
10
3000
338.0
355.0
50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
1.65 0.1
2X (0.5)
EXPOSED
THERMAL PAD
(0.2) TYP
4X (0.25)
5
2X
2
6
11
SYMM
2.4 0.1
10
1
8X 0.5
PIN 1 ID
(OPTIONAL)
10X
SYMM
0.5
10X
0.3
0.30
0.18
0.1
0.05
C A B
C
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
SYMM
(3.4)
(0.95)
8X (0.5)
6
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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