Texas Instruments | TPS650002-Q1 2.25-MHz Step-Down Converter With Dual LDOs | Datasheet | Texas Instruments TPS650002-Q1 2.25-MHz Step-Down Converter With Dual LDOs Datasheet

Texas Instruments TPS650002-Q1 2.25-MHz Step-Down Converter With Dual LDOs Datasheet
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TPS650002-Q1
SLVSEW4 – APRIL 2019
TPS650002-Q1 2.25-MHz Step-Down Converter With Dual LDOs
1 Features
3 Description
•
•
The TPS650002-Q1 device is a single-chip powermanagement IC (PMIC) for automotive applications.
This device combines a single step-down converter
with two low-dropout regulators. The step-down
converter enters a low-power mode at light load for
maximum efficiency across the widest possible range
of load currents. For low-noise applications, the
device can be forced into fixed-frequency PWM using
the MODE pin. The step-down converter allows the
use of a small inductor and capacitors to achieve a
small solution size. A power-good status output can
be used for sequencing. The LDOs can supply 300
mA, and can operate with an input voltage range from
1.6 V to 6 V, thus allowing them to be supplied from
the step-down converter. The step-down converter
and the LDOs have separate voltage inputs and
enables, thus allowing for design and sequencing
flexibility.
1
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 2: –40°C to +105°C,
TA
Step-down converters:
– VIN range from 2.3 V to 6 V
– 2.25-MHz Fixed-frequency operation
– 600-mA Output current
LDOs:
– VIN Range From 1.6 V to 6 V
– Up to 300-mA output current
– Separate power inputs and enables
3-mm × 3-mm 16-Pin WQFN
2 Applications
•
•
•
•
Automotive
Automotive
Automotive
Automotive
The TPS650002-Q1 device is available in a 16-pin
leadless package (3-mm × 3-mm WQFN).
camera module
infotainment
cluster
sensor fusion
Device Information(1)
PART NUMBER
TPS650002-Q1
PACKAGE
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
TI Device
2.2 µH
EN_DCDC
VIN
VINDCDC
MODE
A
10 …F
VDCDC
1.8 V
SW
FB_DCDC
10 …F
P
P
470 k
VIN
EN_LDO1
VINLDO1
2.2 …F
VIN
PG
VLDO1
2.8 V
VLDO1
FB_LDO1
10 …F
P
P
VIN
EN_LDO2
VINLDO2
2.2 …F
VLDO2
1.2 V
VLDO2
FB_LDO2
10 …F
P
AGND
A
P
PGND
P
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS650002-Q1
SLVSEW4 – APRIL 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Examples................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2019
*
Initial release.
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5 Pin Configuration and Functions
EN_LDO1
1
EN_LDO2
2
VINLDO2
VLDO2
FB_LDO2
VINLDO1
RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
16
15
14
13
12
VLDO1
11
FB_LDO1
Exposed Thermal Pad
AGND
PGND
4
9
FB_DCDC
SW
5
6
7
8
EN_DCDC
10
MODE
3
VINDCDC
PG
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
10
—
EN_DCDC
8
I
Enable DC-DC converter
EN_LDO1
1
I
Enable LDO1
EN_LDO2
2
I
Enable LDO2
FB_DCDC
9
I
Voltage to DC-DC error amplifier
FB_LDO1
11
I
Voltage to LDO1 error amplifier
FB_LDO2
14
I
Voltage to LDO2 error amplifier
MODE
7
I
Selects forced-PWM or PWM-to-PFM automatic-transition mode
PG
3
O
Open-drain active-low power-good output
PGND
4
—
Power ground – connected to the thermal pad
SW
5
O
Switch pin – connect inductor here
VINDCDC
6
I
Input voltage to DC-DC converter and all other control blocks
VINLDO1
13
I
Input voltage to LDO1
VINLDO2
16
I
Input voltage to LDO2
VLDO1
12
O
LDO1 output voltage
VLDO2
15
O
LDO2 output voltage
—
Exposed thermal pad
EP
Analog ground – Star back to PGND as close to the IC as possible
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
On all pins except AGND, PGND, EN_DCDC, FB_LDO1, FB_LDO2,
pins with respect to AGND
–0.3
7
On EN_DCDC with respect to AGND
–0.3
VIN + 0.3, ≤ 7
FB_LDO1, FB_LDO2
-0.3
3.6
Output voltage
On VLDO1, VLDO2,
–0.3
3.6
V
Output voltage
/PG
-0.3
7
V
Output voltage
SW
-0.6
7
V
Output voltage
SW for 20ns transients
Input voltage
Current
-2
V
10
V
VINDCDC, SW, PGND,
1800
mA
VINLDO1, VINLDO2, VLDO1, VLDO1, AGND
800
mA
1
mA
105
°C
150
°C
150
°C
At all other pins
Operating free-air temperature, TA
–40
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
UNIT
±2000
Corner pins (1, 4, 5, 8, 9, 12, 13,
and 16)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VINDCDC
2.3
6.0
V
VINLDO1,
VINLDO2
1.6
VINDCDC
V
MODE
0
VINDCDC
V
EN_DCDC
,
EN_LDO1,
EN_LDO2
0
VINDCDC
V
3.3
μH
L1
CI
CO
IO
TA
4
SW pin inductor
1.5
Input capacitor at VINDCDC
10
μF
Input capacitor at VINLDO1, VINLDO2
2.2
μF
Output capacitor for VDCDC
10
Output capacitor for LDO1, LDO2
2.2
2.2
22
μF
DC-DC converter output current
600
mA
LDO1 output current
300
mA
LDO2 output current
300
mA
105
°C
Operating ambient temperature
–40
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6.4 Thermal Information
TPS650002-Q1s
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
46.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.1
°C/W
RθJB
Junction-to-board thermal resistance
19.2
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
19.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
Input voltage for VINDCDC of DCDC converter
VIN
Input voltage for LDO1 (VINLDO1)
See
(1)
Input voltage for LDO2 (VINLDO2)
See
(1)
Internal undervoltage (UVLO)
lockout threshold
VCC falling
2.3
6
V
1.6
6
V
1.6
6
V
1.82
V
1.72
Internal undervoltage (UVLO)
lockout hysteresis
1.77
160
mV
SUPPLY CURRENT
IQ
Operating quiescent current
ISD
Shutdown Current
MODE low, EN_DCDC high,
EN_LDO1, EN_LDO2 low,
IOUT = 0 mA and no switching
23
MODE low, EN_DCDC low,
EN_LDO1, EN_LDO2 high, IOUT = 0 mA
IOUT = 0 mA and no switching
50
EN_DCDC high, MODE high,
EN_LDO1, EN_LDO2 low, IOUT = 0 mA
4
32
μA
EN_DCDC low EN_LDO1 and EN_LDO2 low
0.16
57
mA
2.2
μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
VIH
High-level input voltage
VIL
Low-level input voltage
1.2
VOL
Low-level output voltage
PG pins only, IO = –100 μA
Ilkg
Input leakage current
MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to
GND or VINDCDC,
V
0.4
V
0.4
V
0.01
0.1
μA
2.25
2.41
MHz
OSCILLATOR
fSW
Oscillator frequency
2.01
STEP-DOWN CONVERTER POWER SWITCH
rDS(on)
High-side MOSFET ON-resistance
VINDCDC = VGS = 3.6 V
240
480
mΩ
Low-side MOSFET ON-resistance
VINDCDC = VGS = 3.6 V
185
380
mΩ
IO
DC output current
ILIMF
Forward current limit, PMOS and
NMOS
(1)
2.3 V ≤ VINDCDC ≤ 2.5 V
300
2.5 V ≤ VINDCDC ≤ 6 V
600
2.3 V ≤ VINDCDC ≤ 6 V
800
1000
1400
mA
mA
The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the
DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.
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Electrical Characteristics (continued)
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STEP-DOWN CONVERTER POWER SWITCH (continued)
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
30
°C
1.825
V
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC
VDCDC
RDIS
Fixed output voltage, VDCDC
Output-voltage DC accuracy (PWM MODE = high,
mode) (2)
2.3 ≤ VINDCDC ≤ 6 V
-1.5%
+1.5%
Output-voltage DC accuracy (PFM
mode)
MODE low
+1% voltage positioning active
1%
Load regulation (PWM mode)
MODE high
0.5
%/A
Internal discharge resistance at
SW
EN_DCDC low
450
Ω
LOW-DROPOUT REGULATORS
VI
Input voltage for LDOx (VINLDOx)
VLDO1
Fixed output voltage, LDO1
(VLDO1) (3)
2.8
V
VLDO2
Fixed output voltage, LDO2
(VLDO2) (3)
1.2
V
IO
Continuous-pass FET current
ISC
Short-circuit current limit
VDO
Dropout voltage
(4)
1.6
6
300
2.3 V ≤ VINLDOx
340
825
VINLDOx < 2.3 V
210
825
mV
VINLDOx < 2.3 V, IOUT = 175 mA
370
mV
3.5%
IO = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V,
VLDOx = 1.2 V
–3.5%
3.5%
Load regulation
IO = 1 mA to 300 mA, VINLDOx = 3.6 V
VLDOx = 1.2 V
–1.5%
1.5%
Line regulation
VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at
IO = 1 mA
–0.5%
0.5%
PSRR
Power-supply rejection ratio
fNOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
VOUT = 1.3 V, IOUT = 10 mA
RDIS
Internal discharge resistance at
VLDOx
TSD
6
mA
370
–3.5%
(2)
(3)
(4)
mA
VINLDOx ≥ 2.3 V, IOUT = 250 mA
IO = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V,
VLDOx = 1.2 V
Output voltage accuracy
V
40
dB
EN_LDOx low
450
Ω
Thermal shutdown
Increasing temperature
150
°C
Thermal shutdown hysteresis
Decreasing temperature
30
°C
For VINDCDC = VDCDC + 1 V
Maximum output voltage VLDOx = 3.6 V.
VDO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STEP-DOWN CONVERTER OUTPUT VOLTAGE
tStart
Start-up time
EN_DCDC to start of switching
(10%)
250
µs
tRamp
VDCDC ramp-up time
VDCDC ramp from 10% to 90%
250
µs
VLDOx ramp from 10% to 90%
200
µs
LOW-DROPOUT REGULATORS
tRAMP
VLDOx ramp time
6.7 Typical Characteristics
100
90
100
VOUT = 1.2V
o
TA = 25 C
90
VOUT = 1.2V
o
TA = 25 C
4.2V
80
80
3.6V
3.3V
70
6V
2.8V
Efficiency - %
Efficiency - %
70
5.5V
60
5V
2.3V
50
4.5V
4.2V
40
3.3V
60
6V
2.8V
50
5.5V
2.3V
40
3.6V
30
30
20
20
10
10
0
0.00001
0.0001
0.001
0.01
0.1
1
4.5V
0
0.00001
IO - Output Current - A
0.0001
0.001
0.01
0.1
1
IO - Output Current - A
Figure 2. Efficiency (DC-DC 600-mA PWM Mode)
vs Output Current
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load Current = 60mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
Ch4: Load Current
DCDC
20mAdiv
Ch2: SW
2V/div
Ch2: SW
2V/div
Ch1: VDCDC
10mV/div
Ch1: VDCDC
10mV/div
Figure 1. Efficiency (DC-DC 600-mA PFM Mode)
vs Output Current
Ch3: Load Current
DCDC
20mAdiv
5V
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load DCDC = 400mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
t - Time - 2ms/div
t - Time - 200ns/div
Figure 3. Output Voltage Ripple (DC-DC PFM Mode)
Figure 4. Output Voltage Ripple (DC-DC PWM Mode)
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Ch1: VINLDOx
1V/div
VINDCDC = 3.6 V
o
o
TA = 25 C
VLDOx = 1.2 V
TA = 25 C
VDCDC = 1.2 V
Ch3: VLDOx
500mV/div
Ch3: SW
20V/div
VINDCDC = 3.6 V
VINLDOx = 2.3V
Ch1: EN_LDOx
500mV/div
Ch2: VDCDC Ch1: EN_DCDC
500mV/div
2V/div
Typical Characteristics (continued)
Load DCDC = 100mA
EN_DCDC = 0V to 3.6V
EN_LDO1 = low
EN_LDO2 = low
Load LDOx = 100mA
EN_LDOx = 0V to 2.3V
EN_DCDC = low
t - Time - 100µs/div
t - Time - 100µs/div
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
VINDCDC = 3.6 V to 4.2V to 3.6V
o
TA = 25 C
Ch2: VDCDC
20mV/div
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
t - Time - 100ms/div
Figure 8. Line Transient Response (DC-DC PWM Mode)
Ch1: VDCDC
50mV/div
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
o
TA = 25 C
Ch2: DCDC Load Current
200mA/div
Ch1: VINLDOx
500mV/div
t - Time - 100ms/div
Figure 7. Line Transient Response (DC-DC PFM Mode)
Ch2: VLDOx
20mV/div
8
Figure 6. Start-Up Timing (LDOx)
Ch1: VINDCDC
500mV/div
VINDCDC = 3.6 V to 4.2V to 3.6V
TA = 25oC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
Figure 5. Start-Up Timing (DC-DC)
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = GND
t - Time - 100ms/div
t - Time - 100ms/div
Figure 9. Line Transient Response (LDOx)
Figure 10. Load Transient Response (DC-DC PFM Mode)
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Ch1: LDOx Load Current
50mA/div
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
Ch2: VLDOx
20mV/div
Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
Typical Characteristics (continued)
VINDCDC = 3.6V
VINLDOx = 3.6V
o
TA = 25 C
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
t - Time - 200ms/div
Figure 12. Load Transient Response (LDOx)
Ch1: Mode
2V/div
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
Ch2: VDCDC
20mV/div
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
Ch3: SW
2V/div
Ch3: SW
2V/div
Ch2: VDCDC
20mV/div
Ch1: Mode
2V/div
t - Time - 100ms/div
Figure 11. Load Transient Response (DC-DC PWM Mode)
t - Time - 4ms/div
t - Time - 4ms/div
Figure 13. PFM to PWM Transition (DC-DC)
Figure 14. PWM to PFM Transition (DC-DC)
100
VIN = 2.3V
VLDOx = 1.3V
CI = 2.2mF
CO = 10mF
90
Rejection Ratio - dB
80
70
60
50
IO = 10mA
40
30
20
10
0
10
100
1k
10k
100k
1M
10M
f - Frequency - MHz
Figure 15. Power-Supply Rejection Ratio (LDOx) vs Frequency
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7 Detailed Description
7.1 Overview
The TPS650002-Q1 device has one step-down converter, and two low dropout regulators. The device has an
input voltage range of 2.3 V to 6 V. This device is intended for (but not limited to) powering automotive camera
modules.
To maximize efficiency, there are two modes of operation based on load conditions: PWM or PFM. By pulling the
MODE pin high, forced PWM can be achieved. Pulling this pin low results in an automatic adjustment between
PFM and PWM modes.
The two general-purpose low-dropout regulators each have their own separate enables and voltage inputs. The
inputs can be tied to the output of the step-down converter or to a separate voltage source.
The switching frequency of the step-down converter is handled by the oscillator, with a typical frequency of
2.25 MHz.
The TPS650002-Q1 device also provides a power good signal to monitor the condition of the DC-DC and both
LDOs. The DC-DC and LDOs are only monitored if their enable signal is high. If all enabled resources are in
regulation, the pin is pulled low. If one or more of the enabled resources are out of regulation, the pin is placed in
Hi-Z.
7.2 Functional Block Diagram
Oscillator
VINDCDC
SW
Buck Converter
600 mA
EN_DCDC
FB_DCDC
PG
MODE
VLDO1
VINLDO1
EN_LDO1
LDO1
300 mA
FB_LDO1
PGND
VINLDO2
EN_LDO2
VLDO2
LDO2
300 mA
FB_LDO2
AGND
Band-Gap Reference
7.3 Feature Description
7.3.1 Step-Down Converter
The step-down converter is intended to allow maximum flexibility in the end equipment. Figure 16 shows the
necessary connections.
10
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Feature Description (continued)
VIN_DCDC
SW
EN_DCDC
CO
DIS CHG
Switch Control
MODE
ZLOAD
P
FB_DCDC
+
JA DIO DE
P
P
±
Oscillator
VREF(DC DC)
AGND
A
PGND
P
Figure 16. DC-DC Converter Block Diagram
Externally adjustable output voltages and additional current-limit options are also possible. Contact TI for further
information.
The step-down converter has two modes of operation to maximize efficiency at different load conditions. At
moderate to heavy load currents, the device operates in a fixed-frequency pulse-width modulation (PWM) mode
that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM
mode over the entire load range.
At light load currents, the device operates in a pulsed frequency-modulation (PFM) mode to improve efficiency.
The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating
discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from the PWM mode
value. This voltage positioning is intended to minimize both the voltage undershoot of a load step from light to
heavy loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load
removal. shows the voltage positioning behavior for a light-to-heavy load step.
Output voltage
VOUT(nom) + 1%
Light load
PFM Mode
VOUT(nom)
moderate to heavy load
PWM Mode
Time
Figure 17. PFM Voltage Positioning
Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to
maximize efficiency.
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Feature Description (continued)
The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC
goes low or when the UVLO condition is met.
7.3.2 Soft Start
The step-down converter has an internal soft-start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp-up is controlled as shown in Figure 18.
EN
90%
10%
VOUT
tRAMP
tStart
Figure 18. Soft Start
7.3.3 Linear Regulators
The two linear dropout regulators (LDOs) in the TPS650002-Q1 are designed to provide flexibility in system
design. Each LDO has a separate voltage input and enable signal. The input can be tied to the output of the
step-down converter or the output of another voltage source. Each LDO output discharges to ground
automatically when EN_LDOx goes low.
The LDOs are general-purpose devices that can handle inputs from 6 V down to 1.6 V. Figure 19 shows the
necessary connections for LDO1. The same architecture applies to LDO2.
VLDO1
VINLDO1
+
EN_LDO1
FB_LDO1
DIS CHG
DIO DE
CO(LD O1)
ZLOAD
±
JA
VREF(LD01)
P
AGND
A
PGND
P
Figure 19. LDO Block Diagram
7.3.4 Power Good
The open-drain PG output is used to indicate the condition of the step-down converter and each LDO. This is a
combined output, with the outputs being compared when the appropriate enable signal is high. The pin is pulled
low when all enabled outputs are greater than 95%of the target voltage, and it is pulled into Hi-Z when an
enabled output is less than 90% of its intended value or when all the enable signals are pulled low.
12
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Feature Description (continued)
EN_DCDC
EN_LDO1
EN_LDO2
VDCDC
VDCDC
VDCDC
Target
PG
+
A
VLDO1
VLDO1
Target
VLDO2
VLDO2
Target
+
-
+
-
Figure 20. Power-Good Functionality
7.4 Device Functional Modes
The step-down converter has two modes of operation to maximize efficiency:
1. PFM
– For light loads
– For automatic transition between this mode and PWM mode when MODE pin is pulled low over all load
ranges
2. PWM
– For moderate to heavy loads
– For a small output ripple
– For maintaining the specified switching frequency variation by pulling the MODE pin high which places
the device in a forced PWM mode over the entire load range.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS650002-Q1 can be used in an automotive-camera sensor module to generate the AVDD, DVDD, and
IOVDD voltage rails. For noise immunity, one of the LDOs should be used to generate the AVDD voltage rail. To
minimize power dissipation, the DC-DC converter should be used to power the DVDD rail because the DVDD rail
normally has a lower operating voltage and higher current consumption.
8.2 Typical Application
Regulators with fixed voltage outputs do not require external feedback resistors. Feedback pins must externally
connect to the output capacitors.
TI Device
2.2 µH
EN_DCDC
VIN
VINDCDC
MODE
A
10 …F
VDCDC
1.8 V
SW
FB_DCDC
10 …F
P
P
470 k
VIN
EN_LDO1
VINLDO1
2.2 …F
VIN
PG
VLDO1
2.8 V
VLDO1
FB_LDO1
10 …F
P
P
VIN
EN_LDO2
VINLDO2
2.2 …F
VLDO2
1.2 V
VLDO2
FB_LDO2
10 …F
P
AGND
P
PGND
A
P
Figure 21. Typical Fixed Voltage Application Schematic
8.2.1 Design Requirements
For this example, the fixed voltage TPS650002-Q1 device operates with the parameters listed in Table 1.
Table 1. Design Parameters
14
RESOURCES
VOLTAGE
SW
1.8 V
VLDO1
2.8 V
VLDO2
1.2 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
8.2.2.1.1 Inductor Selection
The typical value for the converter inductor is 2.2-μH output inductor. Larger or smaller inductor values in the
range of 1.5 μH to 3.3 μH can optimize the performance of the device for specific operation conditions. The
selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance
influences the efficiency of the converter directly. An inductor with lowest DC resistance must be selected for
highest efficiency. For more information on inductor selection, refer to the Choosing Inductors and Capacitors for
DC/DC Converters application report.
Equation 1 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 2. TI
recommends this because during heavy load transient, the inductor current rises above the calculated value.
V
1 - OUT
VIN
DIL = VOUT x
Lxf
where
•
•
•
f = Switching Frequency (2.25-MHz typical)
L = Inductor Value
ΔIL = Peak-to-peak Inductor Ripple Current
ILmax = IOUTmax
(1)
DI
+ L
2
where
•
ILmax = Maximum Inductor Current
(2)
The highest inductor current occurs at maximum VIN.
Open-core inductors have a soft saturation characteristic and can usually handle higher inductor currents versus
a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consider that the core material from inductor to inductor differs and impacts the
efficiency especially at high-switching frequencies.
The step down converter has internal loop compensation. TI designed the internal loop compensation to work
with a certain output filter corner frequency calculated as in Equation 3:
1
fC =
with L = 2.2mH, COUT = 10mF
2p L x COUT
(3)
The selection of external L-C filter must be consistent with Equation 3. The product of L × COUT must be constant
while selecting smaller inductor or increasing output capacitor value.
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8.2.2.1.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converter allows the use of small ceramic
capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy
load transients. TI recommends ceramic capacitors with low ESR values because they result in lowest output
voltage ripple. See for the TI-recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as in Equation 4:
V
1 - OUT
VIN
1
IRMSCout = VOUT x
x
Lxf
2x 3
(4)
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor as calculated in Equation 5:
V
1 - OUT
æ
ö
VIN
1
DVOUT = VOUT x
x ççç
+ ESR÷÷÷
Lx f
èç 8 x COUT x f
ø÷
(5)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents, the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
8.2.2.2 Input Capacitor Selection
Due to the DC-DC converter having a pulsating input current, a low-ESR input capacitor is required for best input
voltage filtering, and minimizing the interference with other circuits caused by high-input voltage spikes . Place
the input capacitor as close as possible to the VINDCDC pin with the clean GND connection. Do the same for
the output capacitor and the inductor. The converters require a ceramic input capacitor, a 10 μF is
recommended . The input capacitor can increase without any limit for better input voltage filtering.
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
16
VINDCDC = 3.6 V to 4.2V to 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
VINDCDC = 3.6 V to 4.2V to 3.6V
TA = 25oC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
8.2.3 Application Curves
t - Time - 100ms/div
t - Time - 100ms/div
Figure 22. Line Transient Response (DC-DC PFM Mode)
Figure 23. Line Transient Response (DC-DC PWM Mode)
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Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
o
TA = 25 C
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = GND
t - Time - 100ms/div
Figure 25. Load Transient Response (DC-DC PFM Mode)
Ch1: LDOx Load Current
50mA/div
t - Time - 100ms/div
Figure 24. Line Transient Response (LDOx)
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
Ch2: VLDOx
20mV/div
Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
Ch2: VLDOx
20mV/div
Ch1: VINLDOx
500mV/div
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VINDCDC = 3.6V
VINLDOx = 3.6V
o
TA = 25 C
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
t - Time - 100ms/div
t - Time - 200ms/div
Figure 26. Load Transient Response (DC-DC PWM Mode)
Figure 27. Load Transient Response (LDOx)
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 1.6 V to 6 V. This input supply can be
from a DC supply, or other externally regulated supply. If the input supply is located more than a few inches from
the TPS650002-Q1, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
An electrolytic capacitor with a value of 10 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
The VINDCDC and VINLDOx pins must be bypassed to ground with a low-ESR ceramic bypass capacitor. TI
recommends the typical bypass capacitance is 10 μF and 2.2 μF with a X5R dielectric.
The optimum placement is closest to the VINDCDCx and VINLDOx pins of the device. Minimize the loop area
formed by the bypass capacitor connection, the VINDCDC and VINLDO pins, and the thermal pad of the
device.
The thermal pad must be tied to the PCB ground plane with multiple vias.
The traces of the VLDOx and VDCDCx pins (feedback pins) must be routed away from any potential noise
source to avoid coupling.
VODC output capacitance must be placed immediately at the VODC pin. Excessive distance between the
capacitance and DCDCx pin may cause poor converter performance.
AGND star back to PGND as close to the device as possible.
DGND connect to the thermal pad
10.2 Layout Examples
Thermal pad
Vias to GND
plane
Figure 28. Layout Recommendation
Bypass capacitors to GND for VIN pins
Vias to
GND
Figure 29. Bypass Capacitor and Via Placement Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Choosing Inductors and Capacitors for DC/DC Converters application report
• Texas Instruments, Using the TPS65000EVM 2.25 MHz Step-Down Converter with Dual LDO user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS650002TRTERQ1
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
SJO2
TPS650002TRTETQ1
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
SJO2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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