Texas Instruments | BUF20800-Q1 18-Channel Programmable Gamma Voltage Generator With Two Programmable VCOM Channels (Rev. C) | Datasheet | Texas Instruments BUF20800-Q1 18-Channel Programmable Gamma Voltage Generator With Two Programmable VCOM Channels (Rev. C) Datasheet

Texas Instruments BUF20800-Q1 18-Channel Programmable Gamma Voltage Generator With Two Programmable VCOM Channels (Rev. C) Datasheet
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BUF20800-Q1
SBOS571C – AUGUST 2011 – REVISED AUGUST 2018
BUF20800-Q1 18-Channel Programmable Gamma Voltage Generator
With Two Programmable VCOM Channels
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4
Low Supply Current: 900 μA/ch
Analog Supply Voltage: 7 V to 18 V
Digital Supply Voltage: 2 V to 5.5 V
18-Channel Gamma Correction
2-Channel Programmable VCOM: 50 mA IOUT
10-Bit Resolution
Rail-to-Rail Output
I2C Interface
– 3.4 MHz High-Speed Mode
Demo Board and Software Available
(1)
Device Information
PART NUMBER
PACKAGE
BUF20800-Q1
HTSSOP (38)
BODY SIZE (NOM)
9.80 mm × 9.60 mm
Related Products
FEATURES
PRODUCT
12-Channel Programmable Buffer, 10-Bit
BUF12800
Programmable VCOM
BUF01900
11-, 6-, 4-Channel Gamma Correction Buffer, 18V
Supply
BUFxx704
High-Speed VCOM, 1 and 2 Channels
SN10501
Complete LCD DC/DC Solution
TPS65100
Simplified Block Diagram
Analog
(7V to 18 V)
Digital
(2.0 V to 5.5 V)
REFH
BUF20800-Q1
2 Applications
•
•
•
REFH OUT
Replaces Resistor-Based Gamma Solutions
TFT-LCD Reference Drivers
Dynamic Gamma Control
VCO M OUT1
VCO M OUT2
3 Description
All channels are programmable using an I2C interface
that supports high-speed data transfers up to 3.4
MHz.
This programmability replaces the traditional, time
consuming process of changing resistor values to
optimize the various gamma voltages and allows
designers to determine the correct gamma voltages
for a panel very quickly. Required changes are easily
implemented without hardware changes.
The BUF20800-Q1 uses TI’s latest, small-geometry
analog CMOS process, which makes it a very
competitive choice for full production, not just
evaluation.
1
OUT 2
18 Output Channels plus
Two VCOM Channels
OUT 17
OUT 18
REFL OUT
SDA
Control
Control IF
F
I
SCL
LD
AO
REFL
Copyright © 2016, Texas Instruments Incorporated
For lower channel count, please contact your local
sales or marketing representative.
The BUF20800-Q1 is available in an HTSSOP-38
package withPowerPAD™. It is specified from −40°C
to +105°C.
OUT 1
DAC R
Registers
egisters
DAC
DAC Registers
The BUF20800-Q1 is a programmable voltage
reference generator designed for gamma correction
in TFT-LCD panels. It provides 18 programmable
outputs for gamma correction and two channels for
VCOM adjustment, each with 10-bit resolution.
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BUF20800-Q1
SBOS571C – AUGUST 2011 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
5
5
5
6
8
Absolute Maximum Ratings ....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ....................................... 10
Feature Description................................................. 10
Device Functional Modes........................................ 13
7.5 Programming........................................................... 15
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application ................................................. 21
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2018) to Revision C
Page
•
Changed OUT1-9 high output swing MIN number from "17.7" to "17.6"................................................................................ 6
•
Added OUT1-9 high output swing for TA = +25°C" ................................................................................................................ 6
Changes from Revision A (November 2017) to Revision B
Page
•
Added INL spec over temperature.......................................................................................................................................... 6
•
Added R1 and R2 callouts and corrected capacitor '10mF' value to '10µF' in Typical Application Configuration ............... 22
Changes from Original (August 2011) to Revision A
Page
•
Reformat to new TI standard: Added Device Information table, Pin Configuration and Functions section,
Specifications section, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Changed to "Code 978" from "Code 1023" ............................................................................................................................ 6
•
Changed to "Code 32" from "Code 00" .................................................................................................................................. 6
•
Added MAX value for "OUT 10-18 output swing : low " parameter........................................................................................ 6
2
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5 Pin Configuration and Functions
DCP Package
38-Pin HTSSOP
TOP VIEW
VCOM OUT2
1
38
VCOM OUT1
REFH
2
37
REFL
NC(1)
3
36
NC (1)
NC(1)
4
35
NC (1)
OUT 1
5
34
REFL OUT
OUT 2
6
33
OUT 18
OUT 3
7
32
OUT 17
OUT 4
8
31
OUT 16
30
OUT 15
29
OUT 14
28
GNDA(2)
PowerPAD
LeadFrame
Die Pad
Exposed on
Underside
OUT 5
9
OUT 6
10
(2)
11
VS
12
27
VS
OUT 7
13
26
OUT 13
OUT 8
14
25
OUT 12
OUT 9
15
24
OUT 11
REFH OUT
16
23
OUT 10
VSD
17
22
GNDD(2)
SCL
18
21
LD
SDA
19
20
AO
GNDA
(1)
NC denotes no connection
(2)
GNDD and GNDA are internally connected and must be at the same voltage potential.
Pin Functions
PIN
NAME
A0
GNDA
NO.
20
28
11
GNDD
22
LD
21
I/O
I
DESCRIPTION
Two-wire serial interface address select pin
—
Analog ground. Must be connected to digital ground GNDD.
—
Digital ground. Must be connected to analog ground GNDA.
Output latch pin
3
NC
4
35
—
No connection. Leave this pin floating.
36
OUT1
5
O
DAC output 1
OUT2
6
O
DAC output 2
OUT3
7
O
DAC output 3
OUT4
8
O
DAC output 4
OUT5
9
O
DAC output 5
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
OUT6
10
O
DAC output 6
OUT7
13
O
DAC output 7
OUT8
14
O
DAC output 8
OUT9
15
O
DAC output 9
OUT10
23
O
DAC output 10
OUT11
24
O
DAC output 11
OUT12
25
O
DAC output 12
OUT13
26
O
DAC output 13
OUT14
29
O
DAC output 14
OUT15
30
O
DAC output 15
OUT16
31
O
DAC output 16
OUT17
32
O
DAC output 17
OUT18
33
O
DAC output 18
REFH
2
I
Reference voltage REFH input
REFH OUT
16
O
Reference voltage REFH output
REFL
37
I
Reference voltage REFL input
REFL OUT
34
O
Reference voltage REFL output
SCL
18
I
Serial clock input; open drain.
SDA
19
I/O
Serial data I/O; open drain.
VCOMOUT1
38
O
VCOM channel 1
1
O
VCOM channel 2
I
Analog supply
I
Digital supply
VCOMOUT2
12
VS
27
VSD
17
6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
.
MINIMUM
MAXIMUM
UNIT
VS
Supply voltage
19
V
VSD
Supply voltage
6
V
Signal input terminals, SCL, SDA, AO, LD
Output Short-Circuit
Voltage
–0.5
Current
6
±10
(2)
V
mA
Continuous
TA
Operating temperature
–40
+105
°C
Tstg
Storage temperature
–65
+150
°C
TJ
Junction temperature
125
°C
Latch-up per JESD78B
(1)
(2)
4
Class 1
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Short-circuit to ground, one channel at a time.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS
Analog supply
7
18
V
VSD
Digital supply
2
5.5
V
REFH
Reference high
4
VS – 0.2
V
REFL
Reference low
GND + 0.2
VS – 4
V
TA
Operating ambient temperature
–40
105
°C
TJ
Operating junction temperature
125
°C
6.4 Thermal Information
BUF20800-Q1
THERMAL METRIC
(1)
DCP Package
(HTSSOP Family)
UNIT
38 PINS
RθJA
Junction-to-ambient thermal resistance
28.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.4
°C/W
RθJB
Junction-to-board thermal resistance
7.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
7.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
At TA = 25°C, VS = 18 V, VSD = 5 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
BUF20800-Q1
PARAMETER
CONDITIONS
MIN
TYP
Sourcing 10 mA, VREFH = 17.8 V, Code 1023,
TA = –40°C to +105°C
17.6
Sourcing 10 mA, VREFH = 17.8 V, Code 1023,
TA = +25°C
17.7
17.8
Sourcing 10 mA, VREFH = 17.8 V, Code 978,
TA = –40°C to +105°C
16.8
17.2
MAX
UNIT
ANALOG GAMMA BUFFER CHANNELS
OUT 1−9 output swing: high
OUT 10−18 output swing: high
OUT 1−9 output swing: low
Sinking 10 mA, VREFL = 0.2 V, Code 32,
TA = –40°C to +105°C
0.6
1.0
OUT 10−18 output swing: low
Sinking 10 mA, VREFL = 0.2 V, Code 00,
TA = –40°C to +105°C
0.2
0.4
VCOM buffer output swing: high
Sourcing 50 mA, VREFH =17.8 V,
TA = –40°C to +105°C
VCOM buffer output swing: low
Sinking 50 mA, VREFL = 0.2 V,
TA = –40°C to +105°C
Output current (1)
IO
V
13
40
No Load, VREFH = 17 V, VREFL = 1 V
Integral nonlinearity
DNL
Differential nonlinearity
No Load, VREFH = 17 V, VREFL = 1 V, TA = –40°C to 105°C
No Load, VREFH = 17 V, VREFL = 1 V
0.3
Load regulation, All References
40 mA, All Channels
V
mA
1.5
1
Bits
Bits
0.12
%
5
μs
No Load, VREFH = 17 V, VREFL = 1 V
±20
No Load, VREFH = 17 V, VREFL = 1 V,
TA = –40°C to +105°C
±25
mV
100
MΩ
Input resistance at VREFH and VREFL
REG
2.0
2.5
Program to out delay
Output accuracy
V
45
0.3
Gain error
RINH
15.5
1
All Channels, Code 512, Sinking/Sourcing
INL
tD
V
±50
mV
VOUT = VS/2,
IOUT = 5 mA to –5 mA Step
0.5
1.5
mV/mA
VOUT = VS/2,
ISINKING = 40 mA, ISOURCING = 40 mA
0.5
1.5
mV/mA
ANALOG POWER SUPPLY
VS
Operating range
7
No Load
IS
Total analog supply current
18
Outputs at Reset Values, No Load, Two-Wire Bus Inactive,
TA = –40°C to +105°C
18
V
28
mA
28
mA
DIGITAL
VIH
Logic 1 input voltage
VIL
Logic 0 input voltage
VOL
Logic 0 output voltage
0.7 ×
VSD
0.3 ×
VSD
ISINK = 3 mA
Input leakage
fCLK
(1)
6
Clock frequency
V
V
0.15
0.4
V
±0.01
±10
μA
Standard/Fast Mode, TA = –40°C to +105°C
400
kHz
High-Speed Mode, TA = –40°C to +105°C
3.4
MHz
See typical characteristic graph Output Voltage vs Output Current
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Electrical Characteristics (continued)
At TA = 25°C, VS = 18 V, VSD = 5 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
BUF20800-Q1
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL POWER SUPPLY
VSD
ISD
Operating range
Digital supply current (2)
2.0
Outputs at Reset Values, No Load, Two-Wire Bus Inactive
25
Outputs at Reset Values, No Load, Two-Wire Bus Inactive,
TA = –40°C to +105°C
100
5.5
V
50
μA
μA
TEMPERATURE RANGE
Operating temperature range
Junction Temperature < +125°C
Storage temperature range
–40
+105
°C
–65
+150
°C
θJA
Thermal resistance, HTSSOP-38:
Junction-to-Ambient
30
°C/W
θJC
Thermal resistance, HTSSOP-38:
Junction-to-Case
15
°C/W
(2)
See typical characteristic graph Digital Supply Current vs Temperature
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6.6 Typical Characteristics
At TA = 25°C, VS = 18 V, VSD = 5 V, VREFH = 17 V, VREFL = 1 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless
otherwise noted.
16
30
VS = 5V
VS = 18V
14
25
VS = 10V
Digital IQ (mA)
Analog I Q (mA)
12
10
8
6
20
VS = 3. 3 V
15
10
4
5
2
0
−40
0
−40
−20
10
20
40
60
80
100
−20
10
Temperature (°C)
20
40
60
80
100
Temperature (°C)
Figure 2. Digital Supply Current vs Temperature
Figure 1. Analog Supply Current vs Temperature
18
17
Output Voltage (V )
Output Voltage (5V/div)
REFH =17V
REFL =1V
Code 3FF →000
Code 000 →3FF
16
OUT1018 (sourcing), Code =3FFh
VREFL = 0.2 V, VREFH = 17 V
OUT19, V
RLOAD Connected to GND
15
COM
12 (sourcing)
Code =3FFh
VREFL= 1 V, VREFH = 17..8 V
OUT19, V
3
COM
RLOAD Connected to GND
12 (sinking)
OUT1018 (sin king) , Code =000 h
Code =000h
VREF L = 1V, VREF H = 17..8 V
2
VREFL = 0.2 V, VREFH = 17V
RLOAD Connected to 18V
RLOAD Connected to 18V
1
0
Time (1ms/div)
0
10
20
Figure 3. Full−scale Output Swing
30
40
50
60
70
Output Current (mA)
80
90
100
0.6
0.4
0.4
0.2
DNL Error (LSB)
INL Error (LSB)
Figure 4. Output Voltage vs Output Current
0.6
0
−0.2
−0.4
0
−0.2
−0.4
−0.6
−0.6
0
8
0.2
200
400
600
800
1000
0
200
400
600
800
1000
Input Code
Input Code
Figure 5. Integral Nonlinearity Error vs Input Code
Figure 6. Differential Nonlinearity Error vs Input Code
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7 Detailed Description
7.1 Overview
The BUF20800-Q1 programmable voltage reference allows fast, easy adjustment of 18 programmable reference
outputs and two channels for VCOM adjustment, each with 10-bit resolution. It offers very simple, time-efficient
adjustment of the gamma reference and VCOM voltages. The BUF20800-Q1 is programmed through a highspeed, standard, two-wire interface. The BUF20800-Q1 features a double-register structure for each DAC
channel to simplify the implementation of dynamic gamma control. This structure allows pre-loading of register
data and rapid updating of all channels simultaneously.
Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative
supply rail. Buffers 10−18 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the
negative supply rail.
The BUF20800-Q1 can be powered using an analog supply voltage from 7V to 18V, and a digital supply from 2V
to 5.5V. The digital supply must be applied prior to or simultaneously with the analog supply to avoid excessive
current and power consumption; damage to the device may occur if it is left connected only to the analog supply
for extended periods of time. Figure 7 shows the power supply timing requirements.
VSD
Digital Supply:
GND D
VS
Analog Supply:
GND
t1
t1: 0s minimum delay between Digital Supply and Analog Supply.
Figure 7. Power Supply Timing Requirements
Figure 14 shows the BUF20800-Q1 in a typical configuration. In this configuration, the BUF20800-Q1 device
address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data are
received in the corresponding register (LD = 0).
For maximum dynamic range, set VREFH = VS − 0.2 V and VREFL = GND + 0.2 V.
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7.2 Functional Block Diagram
Analog
(7V to 18 V)
Digital
(2.0 V to 5.5 V)
REFH
BUF20800-Q1
REFH OUT
VCO M OUT1
VCO M OUT2
DAC Registers
DAC R
Registers
egisters
DAC
OUT 1
OUT 2
18 Output Channels plus
Two VCOM Channels
OUT 17
OUT 18
REFL OUT
SDA
Control
Control IF
F
I
SCL
LD
AO
REFL
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 General-call Reset and Power-up
The BUF20800-Q1 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a
data byte of 06h (0000 0110). The BUF20800-Q1 acknowledges both bytes. Upon receiving a General Call
Reset, the BUF20800-Q1 performs a full internal reset, as though it had been powered off and then on. It always
acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call
data bytes other than 06h (0000 0110).
10
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Feature Description (continued)
The BUF20800-Q1 automatically performs a reset upon power up. As part of the reset, all outputs are set to
(VREFH − VREFL)/2. Other reset values are available as a custom modification—contact your TI representative for
details.
The BUF20800-Q1 resets all outputs to (VREFH − VREFL)/2 after sending the device address, if a valid DAC
address is sent with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed in this
most significant byte (MSB) and the following least significant byte (LSB) will be reset.
7.3.2 Output Voltage
Buffer output values are determined by the reference voltages (VREFH and VREFL) and the decimal value of the
binary input code used to program that buffer. The value is calculated using Equation 1:
VOUT =[
VREFH - VREFL
´ Decimal Value of Code]+ VREFL
1024
(1)
The valid voltage ranges for the reference voltages are:
4V ≤ VREFH – VS ≤ 0.2 V and 0.2 V ≤ VREFL ≤ VS – 4 V
(2)
The BUF20800-Q1 outputs are capable of a full-scale voltage output change in typically 5 μs—no intermediate
steps are required.
7.3.3 Output Latch
Updating the DAC register is not the same as updating the DAC output voltage, because the BUF20800-Q1
features a double-buffered register structure. There are three methods for latching transferred data from the
storage registers into the DACs to update the DAC output voltages.
Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which will update each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer
and until LD = LOW, which will then simultaneously update the output voltages of all DACs to the new register
values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update.
Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a 1
in bit 15 of any DAC register. The update will occur after receiving the 16-bit data for the currently-written
register.
The General Call Reset and the power-up reset will update the DAC regardless of the state of the latch pin.
7.3.4 Programmable VCOM
The VCOM channels of the BUF20800-Q1 can swing to 2V from the positive supply rail while sourcing 50 mA and
to 1 V above the negative rail while sinking 50 mA (see Figure 4, typical characteristic Output Voltage vs Output
Current). To store the gamma and the VCOM values, an external EEPROM is required. During power-up of the
LCD panel, the timing controller can then read the EEPROM and load the values into the BUF20800-Q1 to
generate the desired VCOM voltages, as illustrated in Figure 10 and Figure 8. The VCOM channels can be
programmed independently from the gamma channels.
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Feature Description (continued)
BUF20800-Q1
VCOM OUT1
VCOM
VCOM OUT2
Register
OUT1
OUT2
Gamma
References
OUT17
OUT18
SDA
Control Interface
SCL
Copyright © 2016, Texas Instruments Incorporated
Figure 8. BUF20800-Q1 Used for Programmable VCOM
7.3.5 REFH and REFL Input range
Best performance and output swing range of the BUF20800-Q1 are achieved by applying REFH and REFL
voltages that are slightly below the power-supply voltages. Most specifications have been tested at REFH = Vs −
200mV and REFL = GND + 200mV. The REFH internal buffer is designed to swing very closely to Vs and the
REFL internal buffer to GND. However, there is a finite limit on how close they can swing before saturating. To
avoid saturation of the internal REFH and REFL buffers, the REFH voltage should not be greater than Vs
−100mV and REFL voltage should not be lower than GND + 100mV. Figure 9 shows the swing capability of the
REFH and REFL buffers.
The other consideration when trying to maximize the output swing capability of the gamma buffers is the
limitation in the swing range of output buffers (OUT1−18, VCOM1, and VCOM2), which depends on the load current.
A typical load in the LCD application is 5−10mA. For example, if OUT1 is sourcing 10mA, the swing is typically
limited to about Vs − 200mV. The same applies to OUT18, which typically limits at GND + 200mV when sinking
10mA. An increase in output swing can only be achieved for much lighter loads. For example, a 3mA load
typically allows the swing to be increased to approximately Vs − 100mV and GND + 100mV.
Connecting REFH directly to Vs and REFL directly to GND does not damage the BUF20800-Q1. As discussed
above however, the output stages of the REFH and REFL buffers will saturate. This condition is not desirable
and can result in a small error in the measured output voltages of OUT1−18, VCOM1, and VCOM2. As described
above, this method of connecting REFH and REL does not help to maximize the output swing capability.
12
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Feature Description (continued)
18
Output Voltage (V)
17
16
REFH OUT (sourcing), Code =3FFh
VREFL = 1 V, VREFH = 17.8 V
15
RLOAD Connected to GND
3
REFL OUT (sinking), Code =000h
VREFL = 0.2 V, VREFH = 17V
R LOAD Connected to 18V
2
1
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
Figure 9. Reference Buffer Output Voltage vs Output Current
7.4 Device Functional Modes
7.4.1 Replacement of Traditional Gamma Buffer
Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma
voltages. During development, the optimization of these gamma voltages can be time-consuming. Programming
these gamma voltages with the BUF20800-Q1 can significantly reduce the time required for gamma voltage
optimization. The final gamma values can be written into an external EEPROM to replace a traditional gamma
buffer solution. During power-up of the LCD panel, the timing controller reads the EEPROM and loads the values
into the BUF20800-Q1 to generate the desired gamma voltages. Figure 10a shows the traditional resistor string;
Figure 10b shows the more efficient alternative method using the BUF20800-Q1.
BUF20800-Q1 uses the most advanced high-voltage CMOS process available today, which allows it to be
competitive with traditional gamma buffers.
This technique offers significant advantages:
• It shortens development time significantly.
• It allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set
of gamma values.
• It allows simple adjustment of gamma curves during production to accommodate changes in the panel
manufacturing process or end-customer requirements.
• It decreases cost and space.
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Device Functional Modes (continued)
a) Traditional
b)BUF20800-Q1 Solution
BUFxx704
BUF20800-Q1
VCOM OUT1
VCOM
VCOM OUT2
Timing
Controller
OUT1
PC
Register
SDA
SCL
OUT2
Gamma
References
EEPROM
OUT17
OUT18
SDA
Control Interface
SCL
LCD Panel Electronics
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Replacement of the Traditional Gamma Buffer
7.4.2 Dynamic Gamma Control
Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The
brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The
gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 11 shows
a block diagram using the BUF20800-Q1 for dynamic gamma control and VCOM output.
The BUF20800-Q1 is ideally suited for rapidly changing the gamma curves because of its unique topology:
• double register input structure to the DAC;
• fast serial interface;
• simultaneous updating of all DACs by software. See the Read/Write Operations to write to all registers and
the Output Latch sections.
The double register input structure saves programming time by allowing updated DAC values to be pre-loaded
into the first register bank. Storage of this data can occur while a picture is still being displayed. Because the
data are only stored into the first register bank, the DAC output values remain unchanged—the display is
unaffected. During the vertical sync period, the DAC outputs (and therefore, the gamma voltages) can be quickly
updated either by using an additional control line connected to the LD pin, or through software—writing a ‘1’ in bit
15 of any DAC register. For the details on the operation of the double register input structure, see the Output
Latch section.
Example: Update all 18 gamma registers simultaneously via software.
Step 1: Check if LD pin is placed in HIGH state.
Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’.
14
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Device Functional Modes (continued)
Step 3: Write any DAC register a second time with identical data. Make sure that bit 15 is ‘1’. All DAC
channels will be updated simultaneously after receiving the last bit of data. (Note: this step may be
eliminated by setting bit 15 of DAC 18 to ‘1’ in the previous step.)
Histogram
Gamma
Adjustment
Algorithm
Digital
Picture
Data
Black
White
SDA
SCL
BUF20800-Q1
Gamma References
1 through 18
Timing Controller/mController
Source Driver
Source Driver
VCOM
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Dynamic Gamma Control
7.5 Programming
7.5.1 Two-wire Bus Overview
The BUF20800-Q1 communicates through an industry standard, two-wire interface to receive data in slave
mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus
lines are driven to a logic low level only. The device that initiates the communication is called a master, and the
devices controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the START and STOP conditions.
To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a
HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last
bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed
responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and eight bits of data are sent followed by an Acknowledge Bit. During data
transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted
as a START or STOP condition.
Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW
to HIGH while SCL is HIGH.
The BUF20800-Q1 can act only as a slave device; therefore, it never drives SCL. SCL is only an input for the
BUF20800-Q1. Table 1 and Table 2 summarize the address and command codes, respectively, for the
BUF20800-Q1.
7.5.2 Data Rates
The two-wire bus operates in one of three speed modes:
• Standard: allows a clock frequency of up to 100kHz;
• Fast: allows a clock frequency of up to 400kHz; and
• High-speed mode (also called Hs mode): allows a clock frequency of up to 3.4MHz.
The BUF20800-Q1 is fully compatible with all three modes. No special action is required to use the device in
Standard or Fast modes, but High-speed mode must be activated. To activate High-speed mode, send a special
address byte of 00001xxx, with SCL = 400kHz, following the START condition; xxx are bits unique to the Hscapable master, which can be any value. This byte is called the Hs master code. (Note that this is different from
normal address bytes—the low bit does not indicate read/write status.) The BUF20800-Q1 will respond to the
High-speed command regardless of the value of these last three bits. The BUF20800-Q1 will not acknowledge
this byte; the communication protocol prohibits acknowledgment of the Hs master code. On receiving a master
code, the BUF20800-Q1 will switch on its Hs mode filters, and communicate at up to 3.4MHz. Additional highspeed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a
STOP. The BUF20800-Q1 will switch out of Hs mode with the next STOP condition.
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Programming (continued)
7.5.3 Read/Write Operations
The BUF20800-Q1 is able to read from a single DAC, or multiple DACs, or write to the register of a single DAC,
or multiple DACs in a single communication transaction. DAC addresses begin with 0000 0000, which
corresponds to DAC_1, through 0001 0011, which corresponds to VCOM OUT2.
Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH will perform a
read transaction.
7.5.3.1 Writing
To
1.
2.
3.
write to a single DAC register
1. Send a START condition on the bus.
Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
Send a DAC address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be acknowledged. Table 3 shows the DAC addresses.
4. Send two bytes of data for the specified DAC register. Begin by sending the most significant byte first (bits
D15−D8, of which only bits D9 and D8 are used, and bits D15−D14 must not be 01), followed by the least
significant byte (bits D7−D0). The register is updated after receiving the second byte.
5. Send a STOP condition on the bus
The BUF20800-Q1 will acknowledge each data byte. If the master terminates communication early by sending a
STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not
the same as updating the DAC output voltage. See the Output Latch section.
The process of updating multiple DAC registers begins the same as when updating a single register. However,
instead of sending a STOP condition after writing the addressed register, the master continues to send data for
the next register. The BUF20800-Q1 automatically and sequentially steps through subsequent registers as
additional data is sent. The process continues until all desired registers have been updated or a STOP condition
is sent.
To
1.
2.
3.
write to multiple DAC registers:
1. Send a START condition on the bus.
Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC
will be the first in the sequence of DACs to be updated. The BUF20800-Q1 will begin with this DAC and step
through subsequent DACs in sequential order.
4. Send the bytes of data; begin by sending the most significant byte (bits D15−D8, of which only bits D9 and
D8 have meaning), followed by the least significant byte (bits D7−D0). The first two bytes are for the DAC
addressed in step 3 above. Its register is automatically updated after receiving the second byte. The next two
bytes are for the following DAC. That DAC register is updated after receiving the fourth byte. This process
continues until the registers of all following DACs have been updated.
5. Send a STOP condition on the bus.
The BUF20800-Q1 will acknowledge each byte. To terminate communication, send a STOP or START condition
on the bus. Only DAC registers that have received both bytes of data will be updated.
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Programming (continued)
7.5.3.2 Reading
Reading a DAC register will return the data stored in the DAC. This data can differ from the data stored in the
DAC register. See the Output Latch section.
To
1.
2.
3.
4.
5.
6.
7.
8.
read the DAC value:
Send a START condition on the bus.
Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be acknowledged.
Send a START or STOP/START condition on the bus.
Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte
(bits D15−D8; only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
Acknowledge after receiving the first byte.
Do not acknowledge the second byte to end the read transaction.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not
sending the acknowledge.
To
1.
2.
3.
4.
5.
6.
7.
8.
Read Multiple DACs:
Send a START condition on the bus.
Send the device address and read/write bit = LOW. The BUF20800-Q1 will acknowledge this byte.
Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC
will be the first in the sequence of DACs to be read. The BUF20800-Q1 will begin with this DAC and step
through subsequent DACs in sequential order.
Send a START or STOP/START condition on the bus.
Send correct device address and read/write bit = HIGH. The BUF20800-Q1 will acknowledge this byte.
Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte
(bits D15−D8, only bits D9 and D8 have meaning); the next byte is the least significant byte (bits D7−D0).
Acknowledge after receiving each byte of data except for the last byte. The acknowledge bit of the last byte
should be HIGH to end the read operation.
When all desired DACs have been read, send a STOP or repeated START condition on the bus.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not
sending the acknowledge.
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Figure 12. Timing Diagram for Write DAC Register
18
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Figure 13. Timing Diagram for Read DAC Register
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7.5.4 Register Maps
7.5.4.1 Addressing the BUF20800-Q1
The address of the BUF20800-Q1 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the
device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on
address 75h (1110101).
Other valid addresses are possible through a simple mask change. Contact your TI representative for
information.
Table 1. Quick-Reference Table of BUF20800-Q1
Addresses
DEVICE/COMPONENT
BUF20800-Q1 Address:
ADDRESS
A0 pin is LOW
(device acknowledges on address 74h)
1110100
A0 pin is HIGH
(device acknowledges on address 75h)
1110101
Table 2. Quick-Reference Table of Command Codes
COMMAND
CODE
General Call Reset
Address byte of 00h followed by a data byte of
06h.
High-Speed Mode
00001xxx, with SCL ≤ 400kHz; where xxx are
bits unique to the Hs-capable master. This byte
is called the Hs master code.
7.5.5 Registers
Table 3. DAC Addresses
20
DAC
ADDRESS
DAC_1
0000 0000
DAC_2
0000 0001
DAC_3
0000 0010
DAC_4
0000 0011
DAC_5
0000 0100
DAC_6
0000 0101
DAC_7
0000 0110
DAC_8
0000 0111
DAC_9
0000 1000
DAC_10
0000 1001
DAC_11
0000 1010
DAC_12
0000 1011
DAC_13
0000 1100
DAC_14
0000 1101
DAC_15
0000 1110
DAC_16
0000 1111
DAC_17
0001 0000
DAC_18
0001 0001
VCOM OUT1
0001 0010
VCOM OUT2
0001 0011
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The BUF20800-Q1 device was designed to provide 18 programmable outputs for gamma correction for the
source driver IC and two VCOM channels for the common plane in LCD display applications.
8.2 Typical Application
Figure 14 shows a typical application circuit for the BUF20800-Q1 device.
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Typical Application (continued)
(1)
VCOM1
VS
R1
1
BUF20800-Q1
VCOM OUT2
VCOM OUT1
38
2
REFH (3)
REFL(3)
37
3
NC
NC
36
4
NC
NC
35
5
OUT1
REFL OUT
34
6
OUT2
OUT18
33
7
OUT3
OUT17
32
8
OUT4
OUT16
31
9
OUT5
OUT15
30
10 OUT6
OUT14
29
GNDA(2)
28
VS
27
13 OUT7
OUT13
26
14 OUT8
OUT12
25
R2
(1)
(1)
(1)
(1)
(1)
11 GNDA(2)
VS
100nF
10µF
(1)
Source
Driver
(1)
(1)
3.3V
1µF
VCOM2
R2
VS
R1
(1)
Source
Driver
(1)
100nF
12 VS
(1)
(1)
(1)
Source
Driver
(1)
(1)
100nF
10µF
VS
(1)
(1)
Source
Driver
(1)
15 OUT9
OUT11
24
16 REFH OUT
OUT10
23
17 VSD
GNDD(2)
22
18 SCL
LD
21
19 SDA
AO
20
(1)
Timing
Controller
(1) RC combination optional.
(2) GNDA and GNDD must be connected together.
(3) Connecting a capacitor to this node is not recommended.
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Typical Application Configuration
22
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Typical Application (continued)
8.2.1 Design Requirements
Table 4 shows the design parameters for this design.
Table 4. Design Requirements
PARAMETER
SYMBOL
VALUE
Analog Input Supply Voltage
VS
18 V
Digital Input Supply Voltage
VSD
5V
REFH Input Voltage
VREFH
17.8 V
REFL Input Voltage
VREFL
0.2 V
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. Connect a 10-µF capacitor in
parallel to a 100-nF capacitor to all the analog input supply pins as shown in Figure 14. Connecting a 1-µF
capacitor in parallel to a 100-nF capacitor is as well recommended at the digital input supply pin.
8.2.2.2 REFH and REFL Voltage Settings
The resistors R1 and R2 in Figure 14 shall be selected such as the ratio R2/(R1+R2) is close to 17/18. Use for
instance R1 = 1 kΩ and R2 = 75 kΩ.
8.2.3 Application Curves
Figure 15. Power-Up Response
Figure 16. Output Response to a General-Call Reset
8.2.4 Configuration for 20 Gamma Channels
The VCOM outputs can be used as additional gamma references in order to achieve two additional gamma
channels (20 total). The VCOM outputs will behave the same as the OUT1−9 outputs when sourcing or sinking
smaller currents (see Figure 4). The VCOM outputs are better able to swing to the positive rail than to the
negative rail. Therefore, it is better to use the VCOM outputs for higher reference voltages, as shown in
Figure 17.
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15V
2V5.5V
14.8V
Dig ital
Analog
REFH
BUF20800-Q1
REFH OUT
14.8V
V CO M OUT1
V CO M OUT2
GMA 1
GMA 2
GMA 3
OUT2
DAC Registers
DAC Registers
OUT1
Source
Driver
GMA 4
18 Gamma Channels
OUT17
GMA 19
OUT18
GMA 20
REFL OUT
0.2V
SDA
SCL
Control F
I
A0
LD
REFL
15V
0.2V
Copyright © 2016, Texas Instruments Incorporated
Figure 17. 20 Gamma Channel Solution − Two VCOM Channels Used as Additional Gamma Channels
8.2.5 Configuration for 22 Gamma Channels
In addition to the VCOM outputs, the REFH and REFL OUT outputs can also be used as fixed gamma references.
The output voltage will be set by the REFH and REFL input voltages, respectively. Therefore, REFH OUT should
be used for the highest voltage gamma reference, and REFL OUT for the lowest voltage gamma reference. A
22-channel solution can be created by using all 18 outputs, the two VCOM outputs, and both REFH/L OUT outputs
for gamma references—see Figure 15. However, the REFH and REFL OUT buffers were designed to only drive
light loads on the order of 5−10mA. Driving capacitive loads is not recommended with these buffers. In addition,
the REFH and REFL buffers must not be allowed to saturate from sourcing/sinking too much current from REFH
OUT or REFL OUT. Saturation of the REFH and REFL buffers results in errors in the voltages of OUT1−18 and
VCOM OUT1−2. The BUF01900 can be used to provide a programmable VCOM output.
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18V
Reference buffer
and V COM OUT
outputs can be used
for extra gamma channels.
17.8V
2V5.5V
Digital EFH Analo g
(REFH OUT
wil l be a
fixed voltage.)
R
BUF20800-Q1
Source
Driver
REFH OUT
17V
GMA 1
V COM OUT 1
GMA 2
V COM OUT 2
GMA 3
GMA 4
OUT 2
DAC Registers
DAC Registers
OUT 1
GMA 5
2 VCOM Channels plus
18 Output Channels
OUT 17
GMA 20
OUT18
GMA 21
REFL OUT
0.2V
SDA
GMA 22
Control F
I
SCL
Panel
LD 0
A
REFL
Output of referenc e
buffer can be use d
for an extra fixed
gamma channel
18V
0.2V
V COM
18V
2V5. 5V
Digital
Analog IAS
B
BUF01900 (1)
Progra m Command
Voltage Regulato r
4 x OT P
ROM
Switch
Control
10Bit
DAC
V COM
Buffer
V COM OUT
SDA
SCL
Con tro l IF
A0
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Figure 18. 22-Channel Gamma Solution
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8.2.6 The BUF20800-Q1 in Industrial Applications
The wide supply range, high output current, and very low cost make the BUF20800-Q1 attractive for a range of
medium accuracy industrial applications such as programmable power supplies, multi-channel data-acquisition
systems, data loggers, sensor excitation and linearization, power-supply generation, and other uses. Each DAC
channel features 1LSB DNL and INL.
Many systems require different levels of biasing and power supply for various components as well as sensor
excitation, control-loop set-points, voltage outputs, current outputs, and other functions. The BUF20800-Q1, with
its 20 total programmable DAC channels, provides great flexibility to the entire system by allowing the designer to
change all these parameters via software.
Figure 19 provides various ideas on how the BUF20800-Q1 can be used in applications. A micro-controller with
two-wire serial interface controls the various DACs of the BUF20800-Q1. The BUF20800-Q1 can be used for:
• sensor excitation
• programmable bias/reference voltages
• variable power-supplies
• high-current voltage output
• 4-20mA output
• set-point generators for control loops
NOTE: The output voltages of the BUF20800-Q1 DACs will be set to (VREFH − VREFL)/2 at power-up or reset.
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+18V
+5V
BU F 2 0 8 0 0 - Q 1
0.3V to17V
Voltage
Output
High Current
Voltage Output
+5V
2V to 16V, 100mA
Sensor Excitation/Linearization
Control Loop
Set Point
420 mA
+5V
Bias Voltage
Generator
420 mA
Generator
+2.5V Bias
LED Driver
Offset
Adjustment
INA
Ref
+4V
+4.3V
Comparator
Threshold
Supply Voltage
Generator
Ref
Reference
for MDAC
+7.5V
SDA SCL
MDAC
mC
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Figure 19. Industrial Applications for the BUF20800-Q1
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27
BUF20800-Q1
SBOS571C – AUGUST 2011 – REVISED AUGUST 2018
www.ti.com
8.2.7 Total TI Panel Solution
In addition to the BUF20800-Q1 programmable voltage reference, TI offers a complete set of ICs for the LCD
panel market, including gamma correction buffers, various power-supply solutions, and audio power solutions.
See Figure 20 for the total IC solution from TI.
VCOM
Gamma Correction
BUF20800-Q1
2.7V5V
TPS651xx
LCD
Supply
15V
26V
−14V
3.3V
TPA3005D2
TPA3008D2
Audio
Speaker
Driver
n
n
Logic and
Timing
Controller
Gate Driver
Source Driver
High Resolution
TFTLCS Panel
Copyright © 2016, Texas Instruments Incorporated
Figure 20. TI LCD Solution
9 Power Supply Recommendations
The device is designed to operate with an analog supply voltage from 7 V to 18 V, and a digital supply from 2 V
to 5.5 V. The digital supply must be applied before the analog supply to avoid excessive current and power
consumption, or possibly even damage to the device if left connected only to the analog supply for extended
periods
of
time.
The analog and digital supplies must be well regulated and the input capacitances shown in the application
circuit in Figure 14 are recommended for typical applications.
10 Layout
10.1 Layout Guidelines
10.1.1 General PowerPAD Design Considerations
The BUF20800-Q1 is available in a thermally-enhanced PowerPAD package. This package is constructed using
a downset leadframe upon which the die is mounted, see Figure 21(a) and Figure 21(b). This arrangement
results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 21(c).
This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by
providing a good thermal path away from the thermal pad.
28
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SBOS571C – AUGUST 2011 – REVISED AUGUST 2018
Layout Guidelines (continued)
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 21. Views of Thermally-Enhanced DCP Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This provides the necessary thermal and mechanical connection between the
lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for
the HTSSOP-38 DCP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package
(SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them
small, so that solder wicking through the holes is not a problem during reflow. An example thermal land
pattern mechanical drawing is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the BUF20800-Q1 IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
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Layout Guidelines (continued)
5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the BUF20800-Q1 PowerPAD package should make their connection to the internal plane with a
complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its twelve
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the BUF20800-Q1 IC is simply placed in position and run through the
solder reflow operation as any standard surface mount component. This preparation results in a properly
installed part.
For a given θJA (listed in the Electrical Characteristics table), the maximum power dissipation is shown in
Figure 22, and is calculated by Equation 3:
TMAX - TA
PD =
qJA
(
)
where
•
•
•
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature
(+125°C)
TA = free-ambient air temperature (°C)
(3)
Maximum Power Dissipation (W)
6
5
4
3
2
1
0
−40
−20
10
20
40
60
80
100
TA, Free Air Temperature (°C)
Figure 22. Maximum Power Dissipation
vs Free-Air Temperature
(with PowerPAD soldered down)
30
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SBOS571C – AUGUST 2011 – REVISED AUGUST 2018
10.2 Layout Example
VS
1
38
2
37
3
36
4
35
5
34
6
33
7
PowerPAD
32
8
LeadFrame
31
9
10
Die Pad
Exposed on
11
VS
30
29
28
Underside
12
27
13
26
VS
25
14
15
VS
Vias
24
16
23
VSD 17
22
18
21
19
20
Figure 23. PCB Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally-Enhanced Package, SLMA002
• Driving Capacitive Loads with Gamma Buffers, SBOA134
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: BUF20800-Q1
33
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
BUF20800ATDCPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
DCP
38
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
BUF20800Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF BUF20800-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2018
• Catalog: BUF20800
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BUF20800ATDCPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
DCP
38
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BUF20800ATDCPRQ1
HTSSOP
DCP
38
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.22 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/A
www.ti.com
PACKAGE OUTLINE
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9.8
9.6
NOTE 3
9
19
20
38X
4.5
4.3
B
0.27
0.17
0.08
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0 -8
0.15
0.05
0.75
0.50
DETAIL A
A 20
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
38X (1.5)
38X (0.3)
SYMM
SEE DETAILS
1
38
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(0.6) TYP
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
( 0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
SYMM
(4.7)
BASED ON
0.125 THICK
STENCIL
39
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.15
0.175
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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