Texas Instruments | TPS650861 Programmable Multirail PMU for Multicore Processors, FPGAs, and Systems | Datasheet | Texas Instruments TPS650861 Programmable Multirail PMU for Multicore Processors, FPGAs, and Systems Datasheet

Texas Instruments TPS650861 Programmable Multirail PMU for Multicore Processors, FPGAs, and Systems Datasheet
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TPS650861
SWCS142 – JULY 2018
TPS650861 Programmable Multirail PMU for Multicore Processors, FPGAs, and Systems
1 Device Overview
1.1
Features
1
• Two Banks of One-Time Programmable Memory
for Programming Default Voltages and Sequence
• Wide VIN Range From 5.6 V to 21 V
• Three Variable-Output Voltage Synchronous
Step-Down Controllers With D-CAP2™ Topology
– Scalable Output Current Using External FETs
With Selectable Current Limit
– I2C DVS Control From 0.41 V to 1.67 V in
10-mV Steps or 1 V to 3.575 V in 25-mV Steps
or Fixed 5 V Output
• Three Variable-Output Voltage Synchronous StepDown Converters With DCS-Control Topology
– VIN Range From 3 V to 5.5 V
– Up to 3 A of Output Current
– I2C DVS Control From 0.425 V to 3.575 V in 25mV Steps
• Three LDO Regulators With Adjustable Output
Voltage
– LDOA1: I2C-Selectable Voltage From 1.35 V to
3.3 V for up to 200 mA of Output Current
– LDOA2 and LDOA3: I2C-Selectable Voltage
From 0.7 V to 1.5 V for up to 600 mA of Output
1.2
•
•
•
•
•
•
Applications
Programmable Logic Controller
Machine Vision Camera
Video Surveillance
1.3
•
•
Current Each
VTT LDO for DDR Memory Termination
Three Load Switches With Slew Rate Control
– Up to 300 mA of Output Current With Voltage
Drop Less Than 1.5% of Nominal Input Voltage
– RDSON < 96 mΩ at Input Voltage of 1.8 V
5-V Fixed-Output Voltage LDO (LDO5)
– Power Supply for Gate Drivers of SMPS and for
LDOA1
– Automatic Switch to External 5-V Buck for
Higher Efficiency
Built-in Flexibility and Configurability by OTP
Programming
– Six GPI Pins Configurable to Enable (CTL1 to
CTL6) or Sleep Mode Entry (CTL3 and CTL6) of
Any Selected Rails
– Four GPO Pins Configurable to Power Good of
Any Selected Rails
– Open-Drain Interrupt Output Pin
I2C Interface Supports Standard Mode (100 kHz),
Fast Mode (400 kHz), and Fast Mode Plus (1
MHz)
•
•
•
Test and Measurement
Embedded PCs
Motion Control
Description
The TPS650861 device family is a single-chip power-management IC (PMIC) designed to be programmed
for optimal output voltages and sequencing. The TPS650861 has three controllers to provide flexible
power capable of up to 30A with large external FETs for high power designs but which can scale down in
both size and cost for smaller designs. Combined with three 3 A converters, three general purpose LDOs,
a termination LDO for DDR, and three load switches, the TPS650861 can provide system power for a
wide variety of applications. The D-CAP2™ and DCS-Control high-frequency voltage regulators use small
passives to achieve a small solution size. The D-CAP2 and DCS-Control topologies have excellent
transient response performance, ideal for processor core and system memory rails that have fast load
switching. The device has two banks of one-time programmable (OTP) memory. For large volume
opportunities, please contact a local TI sales representative to determine if use of TI's manufacturing for a
custom OTP is available. Third party distributors may also support programming of the TPS650861.
Device Information (1)
PART NUMBER
TPS650861
(1)
PACKAGE
VQFN (64)
BODY SIZE (NOM)
8.00 mm × 8.00 mm
For more information, see the Mechanical, Packaging, and Orderable Information section.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS650861
SWCS142 – JULY 2018
1.4
www.ti.com
PMIC Functional Block Diagram
LDO5V
LDOA1
1.35 ± 3.3 V
200 mA
CTL1
CTL2
VIN
DRV5V_1_6
DRV5V_2_A1
LDOA1
LDO1
BOOT1
DRVH1
VSET
EN
CTL3/SLPENB1
Control
Inputs
CTL4
EN
SW1
BUCK1
1 3.575 V
0.41 ± 1.67 V
(DVS)
VSET
V1
DRVL1
FBVOUT1
PGNDSNS1
CTL5
ILIM1
CTL6/SLPENB2
VPULL
VIN
BOOT2
DRVH2
CLK
SoC
&
System
I2C CTL
DATA
SW2
VSET
VPULL
EN
Control
Outputs
IRQB
Internal
Interrupt
Events
GPO3
GPO4
V2
DRVL2
FBVOUT2
PGNDSNS2
FBGND2
INTERRUPT_CTL
GPO1
GPO2
BUCK2
1 3.575 V
0.41 ± 1.67 V
(DVS)
ILIM2
3.3V ± 5V
PVIN3
BUCK3
VSET 0.425 3.575 V
LX3
0.41 ± 1.67 V
EN
FB3
(DVS)
<PGND_BUCK3>
3A
TEST CTL
OTP
REGISTERS
V3
3.3V ± 5V
PVIN4
BUCK4
VSET 0.425 3.575 V
LX4
0.41 ± 1.67 V
EN
FB4
(DVS)
3A
<PGND_BUCK4>
LDO5P0
LDO5P0
Digital Core
3.3V ± 5V
V5ANA
V4
3.3V ± 5V
PVIN5
BUCK5
VSET 0.425 3.575 V
LX5
0.41 ± 1.67 V
EN
FB5
(DVS)
3A
<PGND_BUCK5>
±
4.7V
+
STDBY
LDO5V
V5
VIN
REFSYS
VSYS
5.6V±21V
LDO3P3
BOOT6
Thermal
Monitoring
LDO3P3
DRVH6
LDO3P3
Thermal Shutdown
VREF
VSET
EN
Bandgap
SW6
BUCK6
1 3.575 V
0.41 ± 1.67 V
(DVS)
VDDQ
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
AGND
PVIN_VTT
VTT
VTT
VTTFB
EN
VTT_LDO
VDDQ/2
LOAD SWB2
VG3
VING2
SWB2
PVINSWB1_B2
VG2
SWB1
VG1
VING1
LOAD SWB1
SWA1
PVINSWA1
LOAD SWA1
LDOA3
LDO3
EN
EN
LDOA3
0.7 1.5 V
600 mA
PVINLDOA2_A3
VINLDO
LDO2
LDOA2
LDOA2
0.7 1.5 V
600 mA
EN
VSET
EN
VSET
EN
Copyright © 2017, Texas Instruments Incorporated
2
Device Overview
Copyright © 2018, Texas Instruments Incorporated
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TPS650861
www.ti.com
SWCS142 – JULY 2018
Table of Contents
1
Device Overview ......................................... 1
4
Detailed Description ................................... 19
Features .............................................. 1
5.1
Overview
1.2
Applications ........................................... 1
5.2
Functional Block Diagram ........................... 20
1.3
Description ............................................ 1
...................... 21
.......................... 22
5.5
LDOs and Load Switches ........................... 30
5.6
Power Goods (PGOOD or PG) and GPOs ......... 30
5.7
One-Time Programmable Memory .................. 32
5.8
Power Sequencing and VR Control ................. 33
5.9
Device Functional Modes ........................... 38
5.10 I2C Interface ......................................... 38
5.11 I2C Address: 0x5E Register Maps .................. 42
5.12 I2C Address: 0x38 Register Maps ................... 83
Applications, Implementation, and Layout ...... 123
6.1
Application Information ............................ 123
6.2
Typical Application ................................. 123
6.3
Power Supply Coupling and Bulk Capacitors...... 134
6.4
Do's and Don'ts ................................... 134
Device and Documentation Support .............. 135
7.1
Device Support .................................... 135
7.2
Documentation Support ............................ 135
7.3
Receiving Notification of Documentation Updates. 135
7.4
Community Resources............................. 135
7.5
Trademarks ........................................ 135
7.6
Electrostatic Discharge Caution ................... 136
7.7
Glossary............................................ 136
.....................
Revision History .........................................
Pin Configuration and Functions .....................
3.1
Pin Functions .........................................
Specifications ............................................
4.1
Absolute Maximum Ratings ..........................
4.2
ESD Ratings ..........................................
4.3
Recommended Operating Conditions ................
4.4
Thermal Information ..................................
1.4
2
3
5
1.1
4.5
4.6
4.7
4.8
PMIC Functional Block Diagram
2
3
4
4
7
7
7
8
8
Electrical Characteristics: Total Current
Consumption.......................................... 8
Electrical Characteristics: Reference and Monitoring
System ................................................ 9
Electrical Characteristics: Buck Controllers ......... 10
Electrical Characteristics: Synchronous Buck
Converters ........................................... 11
....................
4.9
Electrical Characteristics: LDOs
4.10
Electrical Characteristics: Load Switches ........... 14
4.11
Digital Signals: I2C Interface ........................ 15
4.12
Digital Input Signals (CTLx) ......................... 15
4.13
Digital Output Signals (IRQB, GPOx) ............... 15
4.14
Timing Requirements
4.15
4.16
...............................
Switching Characteristics ...........................
Typical Characteristics ..............................
6
7
12
15
16
17
8
............................................
5.3
Programming the TPS650861
5.4
SMPS Voltage Regulators
19
Mechanical, Packaging, and Orderable
Information ............................................. 136
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
COMMENT
July 2018
*
Initial release
Pin Configuration and Functions
Copyright © 2018, Texas Instruments Incorporated
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Product Folder Links: TPS650861
3
TPS650861
SWCS142 – JULY 2018
www.ti.com
3 Pin Configuration and Functions
ILIM2
CTL5
CTL4
CTL3/SLPENB1
CTL2
DATA
CLK
V5ANA
LDO5P0
VSYS
LDO3P3
VREF
AGND
LDOA2
PVINLDOA2_A3
LDOA3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Figure 3-1 shows the 64-pin RSK Plastic Quad Flatpack No-Lead package.
FBGND2
1
48
VTTFB
FBVOUT2
2
47
VTT
DRVH2
3
46
PVINVTT
SW2
4
45
ILIM6
BOOT2
5
44
FBVOUT6
PGNDSNS2
6
43
DRVH6
DRVL2
7
42
SW6
DRV5V_2_A1
8
41
BOOT6
LDOA1
9
40
PGNDSNS6
Thermal
Pad
30
31
32
SWA1
PVINSWA1
DRVH1
ILIM1
33
29
16
FBVOUT1
GPO1
28
SW1
GPO4
34
27
15
GPO3
IRQB
26
BOOT1
GPO2
35
25
14
LX4
CTL6/SLPENB2
24
PGNDSNS1
PVIN4
36
23
13
FB4
CTL1
22
DRVL1
FB5
37
21
12
PVIN5
FB3
20
DRV5V_1_6
LX5
38
19
11
SWB2
PVIN3
18
DRVL6
PVINSWB1_B2
39
17
10
SWB1
LX3
Not to scale
NOTE: The thermal pad must be connected to the system power ground plane.
Figure 3-1. 64-Pin RSK VQFN With Exposed Thermal Pad (Top View)
3.1
Pin Functions
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
SMPS REGULATORS
1
4
FBGND2
I
Remote negative feedback sense for BUCK2 controller. Connect to negative terminal of output capacitor. Connect to
ground when not in use.
Pin Configuration and Functions
Copyright © 2018, Texas Instruments Incorporated
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SWCS142 – JULY 2018
Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
2
FBVOUT2
I
Remote positive feedback sense for BUCK2 controller. Connect to positive terminal of output capacitor. Connect to
ground when not in use.
3
DRVH2
O
High-side gate driver output for BUCK2 controller. Leave floating when not in use.
4
SW2
I
Switch node connection for BUCK2 controller. Connect to ground when not in use.
5
BOOT2
I
Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin. Leave floating
when not in use.
6
PGNDSNS2
I
Power GND connection for BUCK2. Connect to ground terminal of external low-side FET. Connect to ground when not
in use.
7
DRVL2
O
Low-side gate driver output for BUCK2 controller. Leave floating when not in use.
8
DRV5V_2_A1
I
5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on
board to LDO5P0 pin typically. Bypass not required if BUCK2 and LDOA1 are not in use.
10
LX3
O
Switch node connection for BUCK3 converter. Connect to ground when not in use.
11
PVIN3
I
Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if
BUCK3 is not in use.
12
FB3
I
Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor. Connect to ground
when not in use.
20
LX5
O
Switch node connection for BUCK5 converter. Leave floating when not in use.
21
PVIN5
I
Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if
BUCK5 is not in use.
22
FB5
I
Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor. Connect to ground
when not in use.
23
FB4
I
Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor. Connect to ground
when not in use.
24
PVIN4
I
Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor. Bypass not required if
BUCK4 is not in use.
25
LX4
O
Switch node connection for BUCK4 converter. Leave floating when not in use.
29
FBVOUT1
I
Remote feedback sense for BUCK1 controller. Connect to positive terminal of output capacitor. Connect to ground
when not in use.
30
ILIM1
I
Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side
FET. Connect to ground when BUCK1 not in use.
33
DRVH1
O
High-side gate driver output for BUCK1 controller. Leave floating when not in use.
34
SW1
I
Switch node connection for BUCK1 controller. Connect to ground when not in use.
35
BOOT1
I
Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin. Leave floating
when not in use.
36
PGNDSNS1
I
Power GND connection for BUCK1. Connect to ground terminal of external low-side FET. Connect to ground when not
in use.
37
DRVL1
O
Low-side gate driver output for BUCK1 controller. Leave floating when not in use.
38
DRV5V_1_6
I
5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on
board to LDO5P0 pin typically. Bypass not required if BUCK1 and BUCK6 are not in use.
39
DRVL6
O
Low-side gate driver output for BUCK6 controller. Leave floating when not in use.
40
PGNDSNS6
I
Power GND connection for BUCK6. Connect to ground terminal of external low-side FET. Connect to ground when not
in use.
41
BOOT6
I
Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin. Leave floating
when not in use.
42
SW6
I
Switch node connection for BUCK6 controller. Connect to ground when not in use.
43
DRVH6
O
High-side gate driver output for BUCK6 controller. Leave floating when not in use.
44
FBVOUT6
I
Remote feedback sense for BUCK6 controller and reference voltage for VTT LDO regulation. Connect to positive
terminal of output capacitor. Connect to ground when not in use.
45
ILIM6
I
Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side
FET. Connect to ground when BUCK6 not in use.
64
ILIM2
I
Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side
FET. Connect to ground when BUCK2 not in use.
LDO AND LOAD SWITCHES
9
LDOA1
O
LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
17
SWB1
O
Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
18
PVINSWB1_B2
I
Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient
performance. Connect to ground when not in use.
Pin Configuration and Functions
Copyright © 2018, Texas Instruments Incorporated
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
19
SWB2
O
Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
31
SWA1
O
Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
32
PVINSWA1
I
Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient
performance. Connect to ground when not in use.
46
PVINVTT
I
Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Bypass not required if VTT
LDO is not in use.
47
VTT
O
Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating when not in
use.
48
VTTFB
I
Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Connect to ground when not in
use.
49
LDOA3
O
Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
50
PVINLDOA2_A3
I
Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Connect to ground
when not in use.
51
LDOA2
O
Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
54
LDO3P3
O
Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
56
LDO5P0
O
Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF
(typical) ceramic capacitor.
57
V5ANA
I
Bias used by converters (BUCK3, BUCK4, and BUCK5) for regulation. Must be same supply as PVINx. Also has an
internal load switch that connects this pin to LDO5P0 pin if 5-V is used. Bypass this pin with an optional ceramic
capacitor to improve transient performance.
13
CTL1
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin.
14
CTL6/SLPENB2
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out
of (H) sleep state where their output voltages may be different from those in normal state.
15
IRQB
O
Open-drain output interrupt pin. Refer to Section 5.11.4, IRQ: PMIC Interrupt Register, for definitions. For programming,
this pin must be supplied with a stable 7-V supply to burn the OTP memory. Recommend bypassing to ground with a 1µF (typical) ceramic capacitor. Do not back-drive any pull-up on this output if programming. (1)
16
GPO1
O
General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the
configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled
by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
26
GPO2
O
General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the
configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled
by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
27
GPO3
O
General purpose output that can be configured to either open-drain or push-pull arrangement. Regardless of the
configuration, the pin can be programmed either to reflect Power Good status of VRs of any choice or to be controlled
by an I2C register bit by the user, which then can be used as an enable signal to an external VR.
28
GPO4
O
Open-drain output that can be configured to reflect Power Good status of VRs of any choice or to be controlled by an
I2C register bit by the user, which then can be used as an enable signal to an external VR.
INTERFACE
58
CLK
I
I2C clock
59
DATA
I/O
I2C data
60
CTL2
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin.
61
CTL3/SLPENB1
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin. Alternatively, when configured to active-low sleep enable, a group of VRs chosen can be entered into (L) or out
of (H) sleep state where their output voltages may be different from those in normal state.
62
CTL4
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin. For programming, this pin must be supplied with a stable 7-V supply to enter the programming state. Because
of this requirement, CTL4 is generally not used to enable or disable regulators for the TPS650861 to avoid enabling
rails during programming or damaging devices connected to CTL4. No bypass capacitor is needed for this pin. (1)
63
CTL5
I
Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or disabled at deassertion of
this pin.
52
AGND
—
Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
53
VREF
O
Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet
ground.
55
VSYS
I
System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (typical) ceramic
capacitor.
REFERENCE
(1)
6
Ambient temperature must remain below 50 °C during programming, total time must be less than one minute.
Pin Configuration and Functions
Copyright © 2018, Texas Instruments Incorporated
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Product Folder Links: TPS650861
TPS650861
www.ti.com
SWCS142 – JULY 2018
Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
THERMAL PAD
Thermal pad
(PGND)
—
—
Connect to PCB ground plane using multiple vias for good thermal and electrical performance.
4 Specifications
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input voltage from battery, VSYS
–0.3
28
V
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6
–0.3
7
V
V5ANA
–0.3
6
V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
–0.3
0.3
V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
–0.3
34
V
SW1, SW2, SW6
–5 (2)
28
V
ANALOG
(3)
LX3, LX4, LX5
–2
8
V
Differential voltage, BOOTx to SWx
–0.3
5.5
V
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6,
PVINVTT, VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1
–0.3
3.6
V
PVINLDOA2_A3, LDOA2, LDOA3
–0.3
3.3
V
DATA, CLK, GPO1-GPO3
–0.3
3.6
V
CTL1-CTL6, GPO4, IRQB (normal use)
–0.3
7
V
CTL4, IRQB (programming) (4)
-0.3
8.4
V
Storage temperature, Tstg
–40
150
°C
DIGITAL IO
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transient for less than 5 ns
Transient for less than 20 ns
Ambient temperature must remain below 50 °C during programming, total time must be less than one minute.
4.2
ESD Ratings
VALUE
VESD
(1)
(2)
Electrostatic discharge
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±1000
Charged Device Model (CDM), per JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Specifications
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Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VSYS
5.6
13
21
V
VREF
–0.3
1.3
V
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1
–0.3
5.5
V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
–0.3
0.3
V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
–0.3
26.5
v
DRVL1, DRVL2, DRVL6
–0.3
5.5
V
ANALOG
SW1, SW2, SW6
–1
21
V
LX3, LX4, LX5
–1
5.5
V
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5
–0.3
3.6
V
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1
–0.3
PVINVTT
–0.3
BUCK6
3.3
V
FBVOUT6
V
V
VTT, VTTFB
–0.3
0.5 ×
FBVOUT6
PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2
–0.3
3.6
V
PVINLDOA2_A3
–0.3
1.8
V
LDOA2, LDOA3
–0.3
1.5
V
3.3
V
7.3
V
DIGITAL IO
DATA, CLK, CTL1–CTL6, GPO1–GPO4, IRQB (normal use)
–0.3
CTL4, IRQB (during programming) (1)
6.7
7
Operating ambient temperature, TA
–40
27
85
°C
Operating junction temperature, TJ
–40
27
125
°C
CHIP
(1)
Ambient temperature must remain below 50 °C during programming, total time must be less than one minute.
4.4
Thermal Information
TPS650861
THERMAL METRIC
(1)
RSK (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
25.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
11.3
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.4
°C/W
Junction-to-case (bottom) thermal resistance
0.7
°C/W
RθJC(bot)
(1)
4.5
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.
Electrical Characteristics: Total Current Consumption
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
ISD
8
PMIC shutdown current that includes IQ for
references, LDO5, LDO3P3, and digital core
TEST CONDITIONS
VSYS = 13 V, all functional output rails
are disabled
Specifications
MIN
TYP
65
MAX
UNIT
µA
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SWCS142 – JULY 2018
Electrical Characteristics: Reference and Monitoring System
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
VREF
Band-gap reference voltage
1.25
Accuracy
–0.5%
CVREF
Band-gap output capacitor
VSYS_UVLO_5V
VSYS UVLO threshold for LDO5
VSYS falling
VSYS_UVLO_5V_HYS
VSYS UVLO threshold hysteresis for
LDO5
VSYS rising above
VSYS_UVLO_5V
VSYS_UVLO_3V
VSYS UVLO threshold for LDO3P3
VSYS falling
VSYS_UVLO_3V_HYS
VSYS UVLO threshold hysteresis for
LDO3P3
VSYS rising above
VSYS_UVLO_3V
TCRIT
Critical threshold of die temperature
TJ rising
TCRIT_HYS
Hysteresis of TCRIT
TJ falling
THOT
Hot threshold of die temperature
TJ rising
THOT_HYS
Hysteresis of THOT
TJ falling
V
0.5%
0.047
0.1
0.22
µF
5.24
5.4
5.56
V
200
3.45
3.6
mV
3.75
150
130
145
mV
160
10
110
115
V
°C
°C
120
10
°C
°C
LDO5
VIN
Input voltage at VSYS pin
VOUT
DC output voltage
IOUT
DC output current
IOCP
Overcurrent protection
Measured with output shorted to
ground
VTH_PG
Power Good assertion threshold in
percentage of target VOUT
VOUT rising
VTH_PG_HYS
Power Good deassertion hysteresis
VOUT rising or falling
IQ
Quiescent current
VIN = 13 V, IOUT = 0 A
COUT
External output capacitance
IOUT = 10 mA
5.6
13
21
4.9
5
5.1
V
100
180
mA
200
V
mA
94%
4%
20
2.7
4.7
µA
10
µF
1
Ω
V5ANA-to-LDO5P0 LOAD SWITCH
RDSON
On resistance
VIN = 5 V, measured from
V5ANA pin to LDO5P0 pin at
IOUT = 200 mA
VTH_PG
Power Good threshold for external 5V supply
VV5ANA rising
4.7
V
VTH_HYS_PG
Power Good threshold hysteresis for
external 5-V supply
VV5ANA falling
100
mV
ILKG
Leakage current
Switch disabled,
VV5ANA = 5 V, VLDO5 = 0 V
10
µA
21
V
LDO3P3
VIN
VOUT
IOUT
Input voltage at VSYS pin
5.6
DC output voltage
IOUT = 10 mA
Accuracy
VIN = 13 V,
IOUT = 10 mA
13
3.3
–3%
V
3%
DC output current
40
IOCP
Overcurrent protection
Measured with output shorted to
ground
VTH_PG
Power Good assertion threshold in
percentage of target VOUT
VOUT rising
92%
VTH_PG_HYS
Power Good deassertion hysteresis
VOUT falling
3%
IQ
Quiescent current
VIN = 13 V,
IOUT = 0 A
20
COUT
External output capacitance
70
2.2
mA
4.7
µA
10
Specifications
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µF
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Electrical Characteristics: Buck Controllers
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.6
13
21
V
BUCK1, BUCK2, BUCK6
Power input voltage for
external HSD FET
VIN
DC output voltage VID
range and options
VOUT
DC output voltage
accuracy
VID step size = 10 mV, BUCKx_VID[6:0]
progresses from 0000001 to 1111111
0.41
1.67
V
VID step size = 25 mV, BUCKx_VID[6:0]
progresses from 0000001 to 1111111
1 (1)
3.575
V
VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,
IOUT = 100 mA to 7 A
–2%
2%
–30
40
mV
416
mV
65
nA
Total output voltage
accuracy (DC + ripple) in IOUT = 10 mA, VOUT ≤ 1 V
DCM
VFB_EXT_BUCK1
Feedback regulation
voltage
Applies only to the Buck1 Controller if
programmed for external feedback voltage
adjustability
IFB_LKG_BUCK1
Feedback pin leakage
current
Applies only to the Buck1 Controller if
programmed for external feedback voltage
adjustability
SR(VOUT)
Output DVS slew rate
ILIM_LSD
Low-side output valley
current limit accuracy
(programmed by external
resistor RLIM)
ILIMREF
Source current out of
ILIM1 pin
T = 25°C
45
VLIM
Voltage at ILIM1 pin
VLIM = RLIM × ILIMREF
ΔVOUT/ΔVIN
Line regulation
VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3 V,
IOUT = 7 A
ΔVOUT/ΔIOUT
Load regulation
VIN = 13 V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5,
3.3 V, IOUT = 0 A to 7 A,
referenced to VOUT at IOUT = IOUT_MAX
VTH_PG
Power Good deassertion
threshold in percentage
of target VOUT
RDSON_DRVH
Driver DRVH resistance
RDSON_DRVL
Driver DRVL resistance
Output auto-discharge
resistance
RDIS
CBOOT
Bootstrap capacitance
RON_BOOT
Bootstrap switch ON
resistance
(1)
10
384
400
VID step size = 10 mV
2.5
3.125
VID step size = 25 mV
3.125
4
–15%
mV/µs
15%
50
55
µA
0.2
2.25
V
–0.5%
0.5%
0%
1%
VOUT rising
105.5%
108%
110.5%
VOUT falling
89.5%
92%
94.5%
Source, IDRVH = –50 mA
3
Ω
Sink, IDRVH = 50 mA
2
Ω
Source, IDRVL = –50 mA
3
Ω
Sink, IDRVL = 50 mA
0.4
Ω
BUCKx_DISCHG[1:0] = 01
100
Ω
BUCKx_DISCHG[1:0] = 10
200
Ω
BUCKx_DISCHG[1:0] = 11
500
Ω
100
nF
20
Ω
BUCKx_VID[6:0] = 0000001 – 0011000
Specifications
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4.8
SWCS142 – JULY 2018
Electrical Characteristics: Synchronous Buck Converters
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK3, BUCK4, BUCK5
VIN
Power input voltage
DC output voltage VID range
and options
VOUT
DC output voltage accuracy
SR(VOUT)
Output DVS slew rate
IOUT
Continuous DC output current
IIND_LIM
HSD FET current limit
3.0
5.5
V
0.425
3.575
V
VIN = 5.0 V, VOUT = 1, 1.2, 1.35, 1.5,
1.8, 2.5, 3.3 V,
IOUT = 1.5 A
–2%
2%
VIN = 3.3 V, VOUT = 1, 1.2, 1.35, 1.5,
1.8 V,
IOUT = 1.5 A
–2%
2%
VIN = 5.0 V, VOUT = 1, 1.2, 1.35, 1.5,
1.8 V, 2.5, 3.3 V,
IOUT = 100 mA
–2.5%
2.5%
VIN = 3.3 V, VOUT = 1, 1.2, 1.35, 1.5,
1.8 V,
IOUT = 100 mA
–2.5%
2.5%
VID step size = 25 mV,
BUCKx_VID[6:0] progresses from
0000001 to 1111111
3.125
ΔVOUT/ΔVIN
Line regulation
VOUT = 1, 1.2, 1.35, 1.5, 1.8,
2.5, 3.3 V, IOUT = 1.5 A
ΔVOUT/ΔIOUT
Load regulation
VIN = 5 V, VOUT = 1, 1.2, 1.35, 1.5,
1.8, 2.5, 3.3 V,
IOUT = 0 A to 3 A, referenced to
VOUT at IOUT = 1.5 A
VTH_PG
Power Good deassertion
threshold in percentage of
target VOUT
VTH_HYS_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
COUT
Output filtering capacitance
RDIS
Output auto-discharge
resistance
4
A
A
4.3
7
–0.5%
0.5%
–0.2%
2%
VOUT rising
108%
VOUT falling
92%
VOUT rising or falling
mV/µs
3
3%
400
BUCKx_DISCHG[1:0] = 01
100
BUCKx_DISCHG[1:0] = 10
200
BUCKx_DISCHG[1:0] = 11
500
Ω
Specifications
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11
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Electrical Characteristics: LDOs
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5
5
UNIT
LDOA1
VIN
Input voltage
VOUT
5.5
V
DC output voltage
Set by LDOA1_VID[3:0]
1.35
3.3
V
Accuracy
IOUT = 0 to 200 mA
–2%
2%
V
200
mA
–0.5%
0.5%
–2%
2%
IOUT
DC output current
ΔVOUT/ΔVIN
Line regulation
IOUT = 40 mA
ΔVOUT/ΔIOUT
Load regulation
IOUT = 10 mA to 200 mA
IOCP
Overcurrent protection
VIN = 5 V, Measured with output
shorted to ground
VTH_PG
Power Good deassertion
threshold in percentage of
target VOUT
tSTARTUP
Start-up time
Measured from EN = H to reach 95%
of final value,
COUT = 4.7 µF
IQ
Quiescent current
IOUT = 0 A
mA
VOUT rising
108%
VOUT falling
92%
External output capacitance
COUT
500
500
23
2.7
4.7
ESR
Output auto-discharge
resistance
RDIS
µs
µA
10
µF
100
mΩ
LDOA1_DISCHG[1:0] = 01
100
Ω
LDOA1_DISCHG[1:0] = 10
190
Ω
LDOA1_DISCHG[1:0] = 11
450
Ω
LDOA2 and LDOA3
VIN
VOUT + VDROP (1)
Power input voltage
VOUT
IOUT
LDOA2 DC output voltage
Set by LDOA2_VID[3:0]
0.7
LDOA3 DC output voltage
Set by LDOA3_VID[3:0]
0.7
DC output voltage accuracy
IOUT = 0 to 600 mA
1.8
See
–2%
1.98
V
1.5
V
1.5
V
3%
DC output current
600
mA
350
mV
VDROP
Dropout voltage
VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA
ΔVOUT/ΔVIN
Line regulation
IOUT = 300 mA
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
IOUT = 10 mA to 600 mA
–2%
2%
IOCP
Overcurrent protection
Measured with output shorted to
ground
0.65
VTH_PG
Power Good assertion
threshold in percentage of
target VOUT
tSTARTUP
Start-up time
Measured from EN = H to reach 95%
of final value, COUT = 4.7 µF
IQ
Quiescent current
IOUT = 0 A
20
µA
f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF
48
dB
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF – 4.7 µF
30
dB
PSRR
COUT
RDIS
(1)
12
Power supply rejection ratio
1.25
VOUT rising
108%
VOUT falling
92%
External output capacitance
500
2.2
4.7
ESR
Output auto-discharge
resistance
A
LDOA[2,3]_DISCHG[1:0] = 01
80
LDOA[2,3]_DISCHG[1:0] = 10
180
LDOA[2,3]_DISCHG[1:0] = 11
475
µs
10
µF
100
mΩ
Ω
The minimum value must be equal to or greater than 1.62 V.
Specifications
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SWCS142 – JULY 2018
Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2
3.3
UNIT
VTT LDO
VIN
Power input voltage
DC output voltage
VOUT
DC output voltage accuracy
DC Output Current (Rms
Value Over Operation)
IOUT
ΔVOUT/ΔIOUT
ΔVOUT_TR
IOCP
VIN = 1.2 V, Measured at VTTFB pin
Load transient regulation
Overcurrent protection
V
Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.35 V
–10
10
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.35 V
–25
25
1.1 V ≤ VIN ≤ 1.5 V
source(+) and sink(–): IOCP = 0.95 A,
Pulsed Current (Duty Cycle
1.1 V ≤ VIN ≤ 1.5 V
Limited to Remain Below DC
source(+) and sink(–): IOCP = 1.8 A,
Rms Specification)
1.1 V ≤ VIN ≤ 1.5 V
Load regulation
VIN / 2
V
mV
–500
0
500
–500
500
–1800
1800
Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.5 V
–10
10
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.5 V
–20
20
Relative to VIN / 2, IOUT ≤ 1200 mA,
1.1 V ≤ VIN ≤ 1.5 V
–30
30
Relative to VIN / 2, IOUT ≤ 1800 mA,
1.1 V ≤ VIN ≤ 1.5 V
–40
40
DC + AC at sense point, 1.1 V ≤ VIN
≤ 1.5 V,
(IOUT = 0 to 350 mA and 350 mA to
0) AND
(0 to –350 mA and –350 mA to 0)
with 1 µs of rise and fall time
COUT = 40 µF
–5%
5%
Measured with output shorted to
ground: OTPs with VTT ILIM = 0.95 A
0.95
Measured with output shorted to
ground: OTPs with VTT ILIM = 1.8 A
1.8
mA
mA
mV
A
VTH_PG
Power Good deassertion
threshold in percentage of
target VOUT
VOUT rising
110%
VOUT falling
95%
VTH_HYS_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
IQ
Total ground current
VIN = 1.2 V, IOUT = 0 A
ILKG
OFF leakage current
VIN = 1.2 V, disabled
CIN
External input capacitance
10
µF
COUT
External output capacitance
35
µF
RDIS
Output auto-discharge
resistance
5%
VTT_DISCHG = 0
1000
VTT_DISCHG = 1
60
240
µA
1
µA
kΩ
80
100
Specifications
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4.10 Electrical Characteristics: Load Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWA1
VIN
Input voltage range
IOUT
DC output current
RDSON
0.5
ON resistance
60
93
VIN = 3.3 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
100
165
108%
VOUT falling
92%
VTH_HYS_PG
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
IINRUSH
Inrush current upon turnon
VIN = 3.3 V, COUT = 0.1 µF
ILKG
Leakage current
COUT
External output capacitance
RDIS
mΩ
VOUT rising
Power Good deassertion threshold in
percentage of target VOUT
Quiescent current
V
mA
VIN = 1.8 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
VTH_PG
IQ
3.3
300
2%
10
VIN = 3.3 V, IOUT = 0 A
10.5
VIN = 1.8 V, IOUT = 0 A
9
µA
Switch disabled, VIN = 1.8 V
7
370
Switch disabled, VIN = 3.3 V
10
900
0.1
Output auto-discharge resistance
SWA1_DISCHG[1:0] = 01
100
SWA1_DISCHG[1:0] = 10
200
SWA1_DISCHG[1:0] = 11
500
mA
nA
µF
Ω
SWB1, SWB2, SWB1_2
VIN
Input voltage range
IOUT
DC current per output
RDSON
0.5
ON resistance per output
68
92
mΩ
VIN = 3.3 V, measured from PVINSWB1_B2
pin to SWBx pin at IOUT = IOUT(MAX), per
output switch
75
125
mΩ
10
mA
VOUT rising
108%
VOUT falling
92%
Power Good deassertion threshold in
percentage of target VOUT
VTH_HYS_PG
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
IINRUSH
Inrush current upon turning on
VIN = 3.3 V, COUT = 0.1 µF
Quiescent current
ILKG
Leakage current
COUT
External output capacitance
RDIS
14
Output auto-discharge resistance
V
mA
VIN = 1.8 V, measured from PVINSWB1_B2
pin to SWBx pin at IOUT = IOUT(MAX), per
output switch
VTH_PG
IQ
3.3
400
2%
VIN = 3.3 V, IOUT = 0 A
10.5
VIN = 1.8 V, IOUT = 0 A
9
µA
Switch disabled, VIN = 1.8 V
7
460
Switch disabled, VIN = 3.3 V
10
1150
0.1
SWBx_DISCHG[1:0] = 01
100
SWBx_DISCHG[1:0] = 10
200
SWBx_DISCHG[1:0] = 11
500
Specifications
nA
µF
Ω
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SWCS142 – JULY 2018
4.11 Digital Signals: I2C Interface
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
VOL
Low-level output voltage
VIH
High-level input voltage
VIL
Low-level input voltage
ILKG
Leakage current
RPULL-UP
Pullup resistance
TEST CONDITIONS
MIN
TYP
MAX
VPULL_UP = 1.8 V
V
1.2
VPULL_UP = 1.8 V
V
0.01
0.4
V
0.3
µA
Standard mode
8.5
Fast mode
2.5
Fast mode plus
COUT
UNIT
0.4
kΩ
1
Total load capacitance per pin
50
pF
4.12 Digital Input Signals (CTLx)
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.85
V
0.4
V
4.13 Digital Output Signals (IRQB, GPOx)
Over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
Low-level output voltage
IOL < 2 mA
ILKG
Leakage current
VPULL_UP = 1.8 V
MIN
TYP
MAX
UNIT
0.4
V
0.35
µA
4.14 Timing Requirements
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
MIN
NOM
MAX
UNIT
100
kHz
I2C INTERFACE
Clock frequency (standard mode)
fCLK
tr
tf
Clock frequency (fast mode)
400
kHz
Clock frequency (fast mode plus)
1000
kHz
Rise time (standard mode)
1000
ns
Rise time (fast mode)
300
ns
Rise time (fast mode plus)
120
ns
Fall time (standard mode)
300
ns
Fall time (fast mode)
300
ns
Fall time (fast mode plus)
120
ns
Specifications
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4.15 Switching Characteristics
over operating free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
550
850
µs
BUCK CONTROLLERS
tPG
Total turnon time
TON,MIN
Minimum on-time of
DRVH
TDEAD
Driver dead-time
fSW
Switching frequency
Measured from enable going high to when output reaches
90% of target value.
50
ns
DRVH off to DRVL on
15
ns
DRVL off to DRVH on
30
ns
Continuous-conduction mode,
VIN = 13 V, VOUT ≥ 1 V
1000
kHz
BUCK CONVERTERS
tPG
Total turnon time
Measured from enable going high to when output reaches
90% of target value.
fSW
Switching frequency
Continuous-conduction mode
Start-up time
Measured from enable going high to when output reaches
95% of final value,
VOUT = 1.2 V, COUT = 4.7 µF
Start-up time
Measured from enable going high to PG assertion,
VOUT = 0.675 V, COUT = 40 µF
250
See Figure 4-10
1000
µs
MHz
LDOAx
tSTARTUP
180
µs
22
µs
Measured from enable going high to reach 95% of final
value,
VIN = 3.3 V, COUT = 0.1 µF
0.85
ms
Measured from enable going high to reach 95% of final
value,
VIN = 1.8 V, COUT = 0.1 µF
0.63
ms
Measured from enable going high to reach 95% of final
value,
VIN = 3.3 V, COUT = 0.1 µF
1.1
ms
Measured from enable going high to reach 95% of final
value,
VIN = 1.8 V, COUT = 0.1 µF
0.82
ms
VTT LDO
tSTARTUP
SWA1
tTURN-ON
Turnon time
SWB1_2
tTURN-ON
16
Turnon time
Specifications
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4.16 Typical Characteristics
Measurements are taken at 25°C.
FET = CSD87588N
BUCK2_MODE = 0b
L = PIMB061H-R22ms
COUT = 2 × 150 µF + 1 × 22 µF
BUCK3_MODE = 0b
Figure 4-1. Example BUCK2 Controller Start-Up
Figure 4-2. Example BUCK3 Converter Start-Up
100%
95%
90%
80%
Efficiency
Efficiency (%)
85%
75%
70%
65%
Vout = 1 V
Vout = 1.8 V
Vout = 2.5 V
Vout = 3.3 V
60%
55%
50%
0.1
0.2
0.3 0.40.5 0.7 1
Iout (A)
FET = CSD87381P
BUCK1_MODE = 0b
2
3
L = PIFE32251B-R47ms
COUT = 4 × 22 µF
4 5 6 7
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
45%
40%
35%
30%
25%
20%
0.1
VOUT = 1 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0.2
D011
L = PIMB061H-R47ms
Figure 4-3. Example BUCK1 Efficiency at VIN = 13 V In Auto Mode
0.3 0.40.5 0.7 1
Load (A)
FET = CSD87381P
BUCK1_MODE = 1b
2
3
4 5 6 7
tps6
L = PIMB061H-R47ms
Figure 4-4. Example BUCK1 Efficiency at VIN = 13 V in Forced
PWM Mode
100%
100%
95%
90%
90%
80%
80%
Efficiency
Efficiency (%)
85%
75%
70%
70%
60%
65%
60%
55%
50%
0.1
0.2
0.3 0.40.5 0.7 1
Iout (A)
FET = CSD87381P
BUCK1_MODE = 0b
2
Vout = 1 V
Vout = 1.8 V
Vout = 2.5 V
Vout = 3.3 V
50%
3
40%
0.1
4 5 6 7
D012
L = PIMB061H-R47ms
VOUT = 1 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0.2
0.3 0.4 0.5 0.7
1
Output Current (A)
2
3
tps6
L = PIFE32251B-R47ms
Figure 4-6. Example BUCK3 Efficiency at VIN = 5 V
Figure 4-5. Example BUCK1 Efficiency at VIN = 18 V In Auto Mode
Specifications
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Typical Characteristics (continued)
Measurements are taken at 25°C.
710
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 2.8 V
2.7
40qC
25qC
85qC
700
Output Voltage (mV)
Measured Output Voltage (V)
2.9
2.5
2.3
2.1
1.9
1.7
690
680
670
660
650
640
630
-2
1.5
0
1
2
Load Current (A)
3
4
-1.5
-1
-0.5
0
0.5
Load Current (A)
D014
L = PIFE32251B-R47ms
D015
3.5
VIN = 5 V
VIN = 12 V
VIN = 18 V
2.1
3
Switching Frequency (MHz)
2.3
Frequency (MHz)
2
Figure 4-8. VTT LDO Regulation
2.5
1.9
1.7
1.5
1.3
1.1
0.9
2.5
2
1.5
1
0.5
0.7
0.8
1.2
1.6
2
2.4
2.8
Output Voltage Setting (V)
FET = CSD87381P
BUCK1_MODE = 1b
3.2
3.6
VIN = 5 V
VIN = 3.3 V
0
0.4
0.8
tps6
1.2
1.6
2
2.4
2.8
Output Voltage Setting (V)
3.2
3.6
D017
L = PIFE32251B-R47ms
L = PIMB061H-R47ms
Figure 4-9. Controller Switching Frequency (Forced PWM Mode)
18
1.5
FBVOUT6 = PVINVTT = 1.35 V
Figure 4-7. Converter Load Current Limitations with VIN = 3.3 V
0.5
0.4
1
Figure 4-10. Converter Switching Frequency
Specifications
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5 Detailed Description
5.1
Overview
The TPS650861 power-management integrated circuit (PMIC) provides a highly flexible, programmable,
and configurable power solution that can power a wide array of processors along with DDR3/DDR4
memory and other peripherals. Integrated in the PMIC are three step-down controllers (BUCK1, BUCK2,
and BUCK6), three step-down converters (BUCK3, BUCK4, and BUCK5), a sink or source LDO (VTT
LDO), three low-voltage VIN LDOs (LDOA1–LDOA3), and three load switches (SWA1, SWB1, and SWB2).
With on-chip one-time programmable (OTP) memory, configuration of each rail for default output value,
power-up sequence, fault handling, and Power Good mapping into a GPO pin are all conveniently flexible.
The TPS650861 has two OTP memory banks which are designed to be programmed to fit different
designs. (See Section 5.7) All VRs have a built-in discharge resistor, and the value can be changed using
the DISCHCNT1–DISCHCNT3 and LDOA1_SWB2_CTRL registers. When enabling a VR, the PMIC
automatically disconnects the discharge resistor for that rail without any I2C command. lists the key
characteristics of the voltage rails.
Table 5-1. Summary of Voltage Regulators
RAIL
TYPE
INPUT VOLTAGE (V)
OUTPUT VOLTAGE RANGE (V)
MIN
MAX
MIN
TYP
MAX
CURRENT (mA)
BUCK1
Step-down controller
4.5
21
0.41
OTP-programmable
3.575
scalable
BUCK2
Step-down controller
4.5
21
0.41
OTP-programmable
3.575
scalable
BUCK3
Step-down converter
3
5.5
0.41
OTP-programmable
3.575
3000
BUCK4
Step-down Converter
3
5.5
0.41
OTP-programmable
3.575
3000
BUCK5
Step-down converter
3
5.5
0.41
OTP-programmable
3.575
3000
BUCK6
Step-down controller
4.5
21
0.41
OTP-programmable
3.575
scalable
LDOA1
LDO
4.5
5.5
1.35
OTP-programmable
3.3
200 (1)
LDOA2
LDO
1.62
1.98
0.7
OTP-programmable
1.5
600
LDOA3
LDO
1.62
1.98
0.7
OTP-programmable
1.5
600
SWA1
Load switch
0.5
3.3
SWB1/SWB2
Load switch
0.5
3.3
400
1.8
OTPprogrammable
VTT
(1)
Sink and source LDO
1.1
300
FBVOUT6 / 2
When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max IOUT of LDO5.
Detailed Description
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Functional Block Diagram
LDO5V
LDOA1
1.35 ± 3.3 V
200 mA
CTL1
CTL2
VIN
DRV5V_1_6
DRV5V_2_A1
LDOA1
LDO1
BOOT1
DRVH1
VSET
EN
CTL3/SLPENB1
Control
Inputs
CTL4
EN
SW1
BUCK1
1 3.575 V
0.41 ± 1.67 V
(DVS)
VSET
V1
DRVL1
FBVOUT1
PGNDSNS1
CTL5
ILIM1
CTL6/SLPENB2
VPULL
VIN
BOOT2
DRVH2
CLK
SoC
&
System
I2C CTL
DATA
SW2
VSET
VPULL
EN
Control
Outputs
IRQB
Internal
Interrupt
Events
GPO3
GPO4
V2
DRVL2
FBVOUT2
PGNDSNS2
FBGND2
INTERRUPT_CTL
GPO1
GPO2
BUCK2
1 3.575 V
0.41 ± 1.67 V
(DVS)
ILIM2
3.3V ± 5V
PVIN3
BUCK3
VSET 0.425 3.575 V
LX3
0.41 ± 1.67 V
EN
FB3
(DVS)
<PGND_BUCK3>
3A
TEST CTL
OTP
REGISTERS
V3
3.3V ± 5V
PVIN4
BUCK4
VSET 0.425 3.575 V
LX4
0.41 ± 1.67 V
EN
FB4
(DVS)
3A
<PGND_BUCK4>
LDO5P0
LDO5P0
Digital Core
3.3V ± 5V
V5ANA
V4
3.3V ± 5V
PVIN5
BUCK5
VSET 0.425 3.575 V
LX5
0.41 ± 1.67 V
EN
FB5
(DVS)
3A
<PGND_BUCK5>
±
4.7V
+
STDBY
LDO5V
V5
VIN
REFSYS
VSYS
5.6V±21V
LDO3P3
BOOT6
Thermal
Monitoring
LDO3P3
DRVH6
LDO3P3
Thermal Shutdown
VREF
VSET
EN
Bandgap
SW6
BUCK6
1 3.575 V
0.41 ± 1.67 V
(DVS)
VDDQ
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
AGND
PVIN_VTT
VTT
VTT
VTTFB
EN
VTT_LDO
VDDQ/2
LOAD SWB2
VING2
VG3
SWB2
PVINSWB1_B2
VG2
SWB1
VG1
VING1
LOAD SWB1
SWA1
PVINSWA1
LOAD SWA1
LDOA3
LDO3
EN
EN
LDOA3
0.7 1.5 V
600 mA
PVINLDOA2_A3
VINLDO
LDO2
LDOA2
LDOA2
0.7 1.5 V
600 mA
EN
VSET
EN
VSET
EN
Copyright © 2017, Texas Instruments Incorporated
Figure 5-1. PMIC Functional Block Diagram
20
Detailed Description
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PMIC
Example SoC
PLATFORM
VIN
BUCK1
EXT FET
VCORE
VIN
BUCK2
5V Supply
EXT FET
VGPU
BUCK3 3A
VCCIO
BUCK4 3A
VCPU1
BUCK5 3A
Note: An LDO or
Buck Can Supply
the VPP Rail if
Needed for DDR.
VCPU2
VIN
BUCK6
EXT FET
VTT LDO ±0.5A
LDO5V or
5V Supply
VDDQ, VDD1&2
VDDQ, VDD1&2
VREF, VTT
VREF, VTT
DDR
DDR
LDOA1 0.2A
VSUPP1
LDOA2 0.6A
VSUPP2
LDOA3 0.6A
VSUPP3
Input up to 3.3V
SWA1 0.3A
VSUPP4
Input up to 3.3V
SWB1 0.3A
VSUPP5
SWB2 0.3A
VSUPP6
1.8V
VIN
VSYS
LDO5V
LDO5
5V Supply
PG_5V
LDO3P3
IRQB
GPO1 ± GPO4
CTL1 ± CTL6
SDA
SCL
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Figure 5-2. Power Map Example
5.3
Programming the TPS650861
Detailed information regarding the programming of the non-volatile one-time programmable (OTP)
memory is available in the TPS65086100 OTP Memory Programming Guide.
Detailed Description
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SMPS Voltage Regulators
The buck controllers integrate gate drivers for external power stages with programmable current limit (set
by an external resistor at ILIMx pin), which allows for optimal selection of external passive components
based on the desired system load. The buck converters include integrated power stage and require a
minimum number of pins for power input, inductor, and output voltage feedback input. Combined with
high-frequency switching, all these features allow use of inductors in small form factor, thus reducing totalsystem cost and size.
The controllers, BUCK1, BUCK2, and BUCK6, have selectable auto- and forced-pulse width modulation
(PWM) mode through the BUCKx_MODE bit in the BUCKxCTRL register. In auto mode, the VR
automatically switches between PWM and pulsed frequency modulation (PFM) (discontinuous conduction
mode) depending on the output load to maximize efficiency. In Force PWM mode, the VR remains in
PWM (constant conduction mode) in order to keep the regulator switching even at low load to prevent
switching noise in the audible range. The converters, BUCK3, BUCK4, and BUCK5, only support Forced
PWM mode.
All controllers and converters can be used with the default VOUT or can have their voltage dynamically
changed at any time. This means that the rails can be default programmed for any available VOUT by OTP
programming locally or at the factory, so the device starts up with the default voltage, or during operation
the rail can be configured by I2C to another operating VOUT while the rail is enable or disabled. There are
two step sizes or ranges available for VOUT selection for controllers: 10-mV and 25-mV steps. The stepsize range must be selected prior to use and must be programmed in the OTP locally or at the factory. It is
not subject to change during operation.
For the 10-mV step-size range VOUT options, see Table 5-2. For the 25-mV step-size range VOUT options,
see Table 5-3.
22
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Table 5-2. 10-mV Step-Size VOUT Range
VID BITS
VOUT
VID BITS
VOUT
VID BITS
VOUT
0000000
0
0101011
0.83
1010110
1.26
0000001
0.41
0101100
0.84
1010111
1.27
0000010
0.42
0101101
0.85
1011000
1.28
0000011
0.43
0101110
0.86
1011001
1.29
0000100
0.44
0101111
0.87
1011010
1.30
0000101
0.45
0110000
0.88
1011011
1.31
0000110
0.46
0110001
0.89
1011100
1.32
0000111
0.47
0110010
0.90
1011101
1.33
0001000
0.48
0110011
0.91
1011110
1.34
0001001
0.49
0110100
0.92
1011111
1.35
0001010
0.50
0110101
0.93
1100000
1.36
0001011
0.51
0110110
0.94
1100001
1.37
0001100
0.52
0110111
0.95
1100010
1.38
0001101
0.53
0111000
0.96
1100011
1.39
0001110
0.54
0111001
0.97
1100100
1.40
0001111
0.55
0111010
0.98
1100101
1.41
0010000
0.56
0111011
0.99
1100110
1.42
0010001
0.57
0111100
1.00
1100111
1.43
0010010
0.58
0111101
1.01
1101000
1.44
0010011
0.59
0111110
1.02
1101001
1.45
0010100
0.60
0111111
1.03
1101010
1.46
0010101
0.61
1000000
1.04
1101011
1.47
0010110
0.62
1000001
1.05
1101100
1.48
0010111
0.63
1000010
1.06
1101101
1.49
0011000
0.64
1000011
1.07
1101110
1.50
0011001
0.65
1000100
1.08
1101111
1.51
0011010
0.66
1000101
1.09
1110000
1.52
0011011
0.67
1000110
1.10
1110001
1.53
0011100
0.68
1000111
1.11
1110010
1.54
0011101
0.69
1001000
1.12
1110011
1.55
0011110
0.70
1001001
1.13
1110100
1.56
0011111
0.71
1001010
1.14
1110101
1.57
0100000
0.72
1001011
1.15
1110110
1.58
0100001
0.73
1001100
1.16
1110111
1.59
0100010
0.74
1001101
1.17
1111000
1.60
0100011
0.75
1001110
1.18
1111001
1.61
0100100
0.76
1001111
1.19
1111010
1.62
0100101
0.77
1010000
1.20
1111011
1.63
0100110
0.78
1010001
1.21
1111100
1.64
0100111
0.79
1010010
1.22
1111101
1.65
0101000
0.80
1010011
1.23
1111110
1.66
0101001
0.81
1010100
1.24
1111111
1.67
0101010
0.82
1010101
1.25
Detailed Description
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Table 5-3. 25-mV Step-Size VOUT Range
VID BITS
24
VOUT
(Converters)
VOUT
(Controllers)
VID BITS
VOUT
VID BITS
VOUT
0000000
0
0
0101011
1.475
1010110
2.550
0000001
0.425
1.000
0101100
1.500
1010111
2.575
0000010
0.450
1.000
0101101
1.525
1011000
2.600
0000011
0.475
1.000
0101110
1.550
1011001
2.625
0000100
0.500
1.000
0101111
1.575
1011010
2.650
0000101
0.525
1.000
0110000
1.600
1011011
2.675
0000110
0.550
1.000
0110001
1.625
1011100
2.700
0000111
0.575
1.000
0110010
1.650
1011101
2.725
0001000
0.600
1.000
0110011
1.675
1011110
2.750
0001001
0.625
1.000
0110100
1.700
1011111
2.775
0001010
0.650
1.000
0110101
1.725
1100000
2.800
0001011
0.675
1.000
0110110
1.750
1100001
2.825
0001100
0.700
1.000
0110111
1.775
1100010
2.850
0001101
0.725
1.000
0111000
1.800
1100011
2.875
0001110
0.750
1.000
0111001
1.825
1100100
2.900
0001111
0.775
1.000
0111010
1.850
1100101
2.925
0010000
0.800
1.000
0111011
1.875
1100110
2.950
0010001
0.825
1.000
0111100
1.900
1100111
2.975
0010010
0.850
1.000
0111101
1.925
1101000
3.000
0010011
0.875
1.000
0111110
1.950
1101001
3.025
0010100
0.900
1.000
0111111
1.975
1101010
3.050
0010101
0.925
1.000
1000000
2.000
1101011
3.075
0010110
0.950
1.000
1000001
2.025
1101100
3.100
0010111
0.975
1.000
1000010
2.050
1101101
3.125
0011000
1.000
1.000
1000011
2.075
1101110
3.150
0011001
1.025
1.025
1000100
2.100
1101111
3.175
0011010
1.050
1.050
1000101
2.125
1110000
3.200
0011011
1.075
1.075
1000110
2.150
1110001
3.225
0011100
1.100
1.100
1000111
2.175
1110010
3.250
0011101
1.125
1.125
1001000
2.200
1110011
3.275
0011110
1.150
1.150
1001001
2.225
1110100
3.300
0011111
1.175
1.175
1001010
2.250
1110101
3.325
0100000
1.200
1.200
1001011
2.275
1110110
3.350
0100001
1.225
1.225
1001100
2.300
1110111
3.375
0100010
1.250
1.250
1001101
2.325
1111000
3.400
0100011
1.275
1.275
1001110
2.350
1111001
3.425
0100100
1.300
1.300
1001111
2.375
1111010
3.450
0100101
1.325
1.325
1010000
2.400
1111011
3.475
0100110
1.350
1.350
1010001
2.425
1111100
3.500
0100111
1.375
1.375
1010010
2.450
1111101
3.525
0101000
1.400
1.400
1010011
2.475
1111110
3.550
0101001
1.425
1.425
1010100
2.500
1111111
3.575
0101010
1.450
1.450
1010101
2.525
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SWCS142 – JULY 2018
Controller Overview
The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two
external N-MOSFETs. They are D-CAP2 controller scheme that optimizes transient responses at high load
currents for such applications as CORE and DDR supplies. The output voltage is compared with internal
reference voltage after divider resistors. The PWM comparator determines the timing to turn on the highside MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage.
Because the device does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency
by feed-forwarding the input and output voltage into the on-time one-shot timer.
The D-CAP2 control scheme has an injected ripple from the SW node that is added to the reference
voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP™
mode control. Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used
with the controllers.
VDD
VREF ± VTH_PG
+
UV
PGOOD
±
PGOOD
FAULT
+
DCHG
VREF + VTH_PG
+
VFB
OV
±
EN
Control Logic
+
±
+
+
Ramp Generator
PWM
REF
BOOTx
SS Ramp Comp
HS
VSYS
SWx
50 µA
ILIM
DRVHx
XCON
±
OC
+
±
DRV5V_x_x
+
LS
±
NOC
+
GND
One-Shot
DRVLx
PGNDSNSx
+
ZC
±
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2017, Texas Instruments Incorporated
Figure 5-3. Controller Block Diagram
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5.4.2
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Converter Overview
The PMIC synchronous step-down DCDC converters include a unique hysteretic PWM controller scheme
which enables a high switching frequency converter, excellent transient and AC load regulation as well as
operation with cost-competitive external components. The device operates on a quasi-fixed frequency and
allows filtering of the switch noise by external filter components. The PMIC device offers fixed output
voltage options featuring smallest solution size by using only three external components per converter.
A significant advantage of PMIC compared to other hysteretic PWM controller topologies is its excellent
AC load transient regulation capability. When the output voltage falls below the threshold of the error
comparator, a switch pulse is initiated, and the high-side switch is turned on. The high-side switch remains
turned on until a minimum ON-time of tONmin expires and the output voltage trips the threshold of the error
comparator or the inductor current reaches the high-side switch current limit. When the high-side switch
turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the high-side
switch turns on again. In PWM mode operation, negative inductor current is allowed to enable continuous
conduction mode even at no load condition.
PVINx
Bandgap
Current
Limit Comparator
VREF
0.40 V
High-Side
Limit
MODE or EN
MODE
Softstart
VIN
FB
EN
Minimum ON Time
Gate Driver
Anti
Shoot-Through
Control
Logic
Minimum OFF Time
VREF
LXx
+
FBx
±
Integrated
Feedback
Network
Error
Comparator
Low-Side
Limit
Zero (Negative)
Current Limit Comparator
PGND/Thermal Pad
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2017, Texas Instruments Incorporated
Figure 5-4. Converter Block Diagram
5.4.3
DVS
BUCK1–BUCK6 support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs
can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID) defined in
Section 4.7 and Section 4.8. DVS slew rate is minimum 2.5 mV/µs. In order to meet the minimum slew
rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV or at 6-µs interval per 25-mV
steps. When DVS is active, the VR is forced into PWM mode, unless BUCKx_DECAY = 1, to ensure the
output keeps track of VID code with minimal delay. Additionally, PGOOD is masked when DVS is in
progress. Figure 5-5 shows an example of slew down and up from one VID to another (step size of
10 mV).
26
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VID
Number of Steps × 3 µs
VOUT
Figure 5-5. DVS Timing Diagram I (BUCKx_DECAY = 0)
As shown in Figure 5-6, if a BUCKx_VID[6:0] is set to 7b000 0000, its output voltage will slew down to the
minimum VID value first, and then will drift down to 0 V as the SMPS stops switching. Subsequently, if a
BUCKx_VID[6:0] is set to a value (neither 7b000 0000 nor 7b000 0001) when its output voltage is less
than 0.5 V, the VR will ramp up to 0.5 V first with soft-start kicking in, then will slew up to target voltage in
the slew rate aforementioned. It must be noted that a fixed 200 µs of soft-start time is reserved for VOUT to
reach 0.5 V.
VID
VOUT
Number of
Steps × 3 µs
Load and Time
Dependent
200 µs
Figure 5-6. DVS Timing Diagram II (BUCKx_DECAY = 0)
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Decay
In addition to DVS, BUCK1–BUCK6 can decay down to a lower voltage when BUCKx_DECAY bit in
BUCKxCTRL register is set to 1. Decay mode is only used in a downward direction of VID. The VR does
not control slew rate. As both high-side and low-side FETs stop switching, the output voltage ramps down
naturally, dictated by current drawn from the load and output filtering capacitance. When the VR is in the
middle of decay down its PGOOD is masked until VOUT falls below the over-voltage (OV) threshold of the
set VID value. Figure 5-7 shows two cases that differ from each other as to whether VOUT has reached the
target voltage corresponding to a new VID when the VR is commanded to slew back up to a higher
voltage. In case that VOUT has not decayed down below VID as denoted case 2, the VR will wait for VID to
catch up, and then VOUT will start ramping up to keep up with the VID ramp.
VID
VOUT
case 2
case 1
Figure 5-7. Decay Down to a Lower VOUT and Slew Up
VID
VOUT
case 2
200 us
case 1
Figure 5-8. Decay Down to 0 V and Slew Up
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Current Limit
The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the
current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for
a desired resistor value, depending on specific application conditions. ILIMREF is the current source out of
the ILIMx pin that is typically 50 µA, and RDSON is the maximum channel resistance of the low-side FET.
The scaling factor is 1.3 to take into account all errors and temperature variations of RDSON, ILIMREF, and
RILIM. Finally, 8 is another scaling factor associated with ILIMREF.
Iripple(min) ·
§
RDSON u 8 u 1.3 u ¨ ILIM
¸
2
©
¹
RILIM
ILIMREF
where
•
•
ILIM is the target current limit. An appropriate margin must be allowed when determining ILIM from
maximum output DC load current.
Iripple(min) is the minimum peak-to-peak inductor ripple current for a given VOUT.
Iripple(min)
VOUT (VIN(MIN)
(1)
VOUT )
Lmax u VIN(MIN) u fsw(max)
where
•
•
•
Lmax is maximum inductance
fsw(max) is maximum switching frequency
VIN(MIN) minimum input voltage to the external power stage
(2)
The buck converter limit inductor peak current cycle-by-cycle to IIND_LIM is specified in Section 4.8.
The current limit circuit also protects against reverse current going back into the low side FET from the
load. When operating in Force PWM mode, the inductor current is expected to go negative so it is
important to ensure that the RILIM value is sufficient to account for this. If operating in PFM, this can be
neglected. The equation for Force PWM minimum RILIM value is:
§ Iripple(max) ·
RDSON u 8 u 1.3 u ¨
¸
2
©
¹
RILIM t
ILIMREF
where
•
Iripple(max) is the maximum peak-to-peak inductor ripple current for a given VOUT.
Iripple(max)
VOUT (VIN(MAX)
(3)
VOUT )
Lmin u VIN(MAX) u fsw(min)
where
•
•
•
Lmin is minimum inductance
fsw(min) is minimum switching frequency
VIN(MAX) maximum input voltage to the external power stage
(4)
If RILIM is too low for the chosen inductor and voltage conditions, then the ripple current at no load will
trigger the negative current limit, forcing the low side FET to turn off. This will eventually result in the
output voltage increasing above target regulation point due to irregular duty cycle created by current limit
being triggered.
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5.5
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LDOs and Load Switches
5.5.1
VTT LDO
Typically powered from the BUCK6 output, the VTT LDO tracks FBVOUT6 and regulates it's output to
FBVOUT6 / 2. The LDO current limit is OTP dependent, and it is designed specifically to power DDR
memory. The LDO core is a transconductance amplifier with large gain, and it drives a current output
stage that either sources or sinks current depending on the deviation of the VTTFB pin voltage from the
target regulation voltage.
5.5.2
LDOA1–LDOA3
The TPS650861 device integrates three general purpose LDOs. LDOA1 is powered from a 5-V supply
through the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail (stay on even in
case of emergency shutdown) as long as a valid power supply is available at VSYS. See Table 5-4 for
LDOA1 output voltage options. LDOA2 and LDOA3 share a power input pin (PVINLDOA2_A3). The output
regulation voltages are set by writing to LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See Table 5-5
for LDOA2 and LDOA3 output voltage options. LDOA1 is controlled by the LDOA1_SWB2_CTRL register.
Table 5-4. LDOA1 Output Voltage Options
VID BITS
VOUT
VID BITS
VOUT
VID BITS
VOUT
VID BITS
VOUT
0000
1.35
0100
1.8
1000
2.3
1100
2.85
0001
1.5
0101
1.9
1001
2.4
1101
3.0
0010
1.6
0110
2.0
1010
2.5
1110
3.3
0011
1.7
0111
2.1
1011
2.6
1111
Not Used
Table 5-5. LDOA2 and LDOA3 Output Voltage Options
VID BITS
VOUT
VID BITS
VOUT
VID BITS
VOUT
VID BITS
VOUT
0000
0.70
0100
0.90
1000
1.10
1100
1.30
0001
0.75
0101
0.95
1001
1.15
1101
1.35
0010
0.80
0110
1.00
1010
1.20
1110
1.40
0011
0.85
0111
1.05
1011
1.25
1111
1.50
5.5.3
Load Switches
The PMIC features three general-purpose load switches. SWA1 has its own power input pin (PVINSWA1),
while SWB1 and SWB2 share one power input pin (PVINSWB1_B2). All switches have built-in slew rate
control during start-up to limit the inrush current.
5.6
Power Goods (PGOOD or PG) and GPOs
The device provides information on status of VRs through four GPO pins along with Power Good Status
registers defined in Section 5.11.50 and Section 5.11.51. Power Good information of any individual VR
and load switch can be assigned to be part of the PGOOD tree as defined from Section 5.11.40 to
Section 5.11.47. PGOOD assertion delays are programmable from 0 ms to 15 ms for GPO1, 5 ms to 100
ms for GPO3, and 0 ms to 100 ms for GPO2 and GPO4, respectively, as are defined in Section 5.11.21
and Section 5.11.34.
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BUCK1_PG
BUCK1_MSK (bit)
BUCK2_PG
BUCK2_MSK (bit)
BUCK3_PG
BUCK3_MSK (bit)
BUCK4_PG
BUCK4_MSK (bit)
BUCK5_PG
BUCK5_MSK (bit)
BUCK6_PG
BUCK6_MSK (bit)
SWA1_PG
SWA1_MSK (bit)
LDOA2_PG
LDOA2_MSK (bit)
Selectable
Rising
Edge
Delay
LDOA3_PG
LDOA3_MSK (bit)
GPO_PG
SWB1_PG
SWB1_MSK (bit)
SWB2_LDOA1_PG
SWB2_LDOA1_MSK (bit)
VTT_PG
VTT_MSK (bit)
CTL1
CTL1_MSK (bit)
CTL2
CTL2_MSK (bit)
CTL3/SLPENB1
CTL3_MSK (bit)
CTL4
CTL4_MSK (bit)
CTL5
CTL5_MSK (bit)
CTL6/SLPENB2
CTL6_MSK (bit)
Figure 5-9. Power Good Tree
Alternatively, the GPOs can be used as general purpose outputs controlled by the user through I2C. Refer
to the Section 5.11.37 for details on controlling the GPOs in I2C control mode.
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5.7
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One-Time Programmable Memory
The PMIC has two banks of non-volatile one-time programmable (OTP) memory which stores the default
settings for the device. The OTP memory is mapped to corresponding volatile registers which are cleared
when VSYS goes below UVLO. When VSYS goes above UVLO, the contents of the OTP memory is
loaded into the corresponding volatile registers which are then used to control the PMIC. The OTP is also
reloaded in case of any emergency shutdown condition. When programming the PMIC, the values in the
volatile registers which have OTP memory equivalents are burned into the OTP.
Some registers do not have OTP equivalent memory. For example, the IRQ register, which indicates
which interrupts have been triggered, does not need OTP memory equivalent because its values are
always determined after power up. Similarly, the IRQ_MASK register does not have OTP backing because
in order to be useful, the processor needs to communicate with the PMIC to set the masks correctly.
There is no need to have a default value other than 1b for these bits. OTP programmable bits are
indicated with an 'X' in the register map. Some registers are accessed using I2C address 0x5E, which can
be changed if necessary using the I2C_SLAVE_ADDR register (see Section 5.12.39). Other registers,
which can only be accessed while in programming mode, are accessed using I2C address 0x38, which
cannot be changed.
The OTP memory settings are set to 1b with a 7 V supply, in a process called "burning". Lower voltages
may result in values not being stored or the bit flipping (from 1b to 0b) after some time has passed. To
avoid this occurring, the IRQB pin should be probed with an oscilloscope during the prototyping phase of
development to ensure it does not drop below 6.7 V during OTP memory burn in. Any bit can be burned
from a 0b to a 1b, but once a bit is a 1b, it cannot go back to being a 0b. As a result, it is possible to burn
an OTP program and then make minor changes and re-burn the OTP as long as all of the changes are 0b
to 1b. For example, if the original OTP program had BUCK3_VID = 1 V (0011000b) then it can be
changed to BUCK3_VID = 1.15 V (0011110b) without issue since it is just bits 1 and 2 being changed
from 0b to 1b. However, if the new desired BUCK3_VID = 0.9 V (0010100b), then the second bank of
OTP would need to be used since bit 3 cannot change from 1b to 0b. The switch from OTP Bank 0 to
OTP Bank 1 is permanent as the pointer bit is also OTP.
Detailed information regarding the programming of the non-volatile one-time programmable (OTP)
memory is available in the TPS65086100 OTP Memory Programming Guide.
All OTP programmed settings should be validated during prototyping phase to ensure desired functionality
because parts cannot be returned in case of incorrect programming. Any issues should be reported to
http://e2e.ti.com/support/power_management/pmu/.
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5.8
SWCS142 – JULY 2018
Power Sequencing and VR Control
The device has three different ways of sequencing the rails during power up and power down:
• Rail enabled by CTLx pin
• Rail enabled by Power Good (PG) of previously enabled rail
• Rail enabled by I2C software command
A delay can be added from any CTLx pin or PG to the enable of the subjected enabled rail. This creates a
very flexible device capable of many sequence options. If a rail cannot be sequenced automatically, any
rail can be enabled or disabled through an I2C command.
5.8.1
CTLx Sequencing
The device has six control-input pins (CTL1–CTL6) to control six SMPS regulators, three LDO regulators,
and three load switches. This allows the user to define up to six distinctive groups, to which each VR can
be assigned for highly flexible power sequencing. Of the six CTLx pins, CTL3 and CTL6 can be configured
alternatively to active-low sleep enable pins. For instance, if a system level SLEEP state is defined such
that BUCK1 output regulation voltage is lower than in the normal mode, then BUCK1 SLEEP state can be
assigned to CTL3 or CTL6. By being pulled low, either CTL3 or CTL6 can be used to put BUCK1 into
SLEEP state, and BUCK1 will regulate its output at a voltage defined by BUCK1_SLP_VID[6:0] in
Section 5.11.23. For a demonstration of this feature, Figure 5-10 shows how BUCK1 is enabled from the
CTL1 pin.
5.8.2
PG Sequencing
Any rail can be sequenced by the Power Good of a prior rail. This can be combined with the CTLx method
to allow for further sequence control and create more distinctive groups of enables than the six from CTLx.
This also allows some of the CTLx pins to be freed up for other purposes such as logic input gates. For a
demonstration of this feature, Figure 5-10 shows how the BUCK5 is enabled from the BUCK4 PG.
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VSYS
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5.6 V
LDO5/LDO3P3
LDOA1/GPO1
I2C Available
CTL1
BUCK1
2 ms
BUCK2
4 ms
BUCK6
CTL2
BUCK3
BUCK4
BUCK5
GPO4
PG of all
BUCKs
CTL4
LDOA2
16 ms
LDOA3
GPO3
PG of BUCKs and LDOs
CTL5
SWA1
2 ms
SWB1
8 ms
SWB2
CTL6
VTT
Figure 5-10. Generic Power-Up Sequence Example
5.8.3
Enable Delay
A delay can be added to the enable of any rail after the desired CTLx and PGs are met. This allows for
the option to create additional timing groups from either CTLx pins or internal PGs. For a demonstration of
this feature, Figure 5-10 shows how BUCK2 and BUCK6 are enabled after BUCK1 is enabled from CTL1
pin.
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SWCS142 – JULY 2018
Power-Up Sequence
When a valid power supply is detected at the VSYS pin as VSYS crosses above VSYS_UVLO_5V +
VSYS_UVLO+5V_HYS, the power-up sequence is initiated by driving one of the control input pins high, followed
by the rest of pins in order. Figure 5-10 is an example where CTL1–CTL4 are defined to control four
groups of VRs, while GPO3 and GPO4 are defined to provide a PGOOD status of two groups. The control
input pins do not necessarily have to be pulled up in a staggered manner. For instance, if CTL2 is pulled
up from the preceding group of VRs before PGOOD has been asserted at GPO1, the BUCK4 enable will
be delayed until the PGOOD is asserted.
5.8.5
Power-Down Sequence
The power-down sequence can follow the CTLx pins, or be controlled with the I2C commands. If the
internal PGs are used for sequencing or if some rails need to ramp down before others a delay can be
added to the deassertion low of the internal enable of the subjected rail. This delay can be independent of
the power-up delay option. Thus, power-up and power-down sequences can be different or similar to
match the specific application sequences required.
Refer to Figure 5-11 for an example of a power-down sequence demonstrating the delay disable of
BUCK1 and BUCK2.
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CTL6
VTT
CTL5
SWA1
SWB1
SWB2
CTL4
GPO3
LDOA2
LDOA3
CTL2
GPO4
BUCK6
BUCK5
BUCK4
CTL1
BUCK6
2 ms
BUCK2
4 ms
BUCK1
Figure 5-11. Generic Power-Down Sequence Example
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5.8.6
SWCS142 – JULY 2018
Sleep State Entry and Exit
Normal State
Normal State
Sleep State
1.8 V
CTL6
0V
1.8 V
CTL1-CTL4
1.8V
GPO1-GPO4
BUCK1_VID
BUCK1_DECAY = 1
BUCK1
BUCK1_VID
BUCK1_SLP_VID
BUCK1_DECAY = 0
Figure 5-12. Sleep State Entry and Exit Sequence Example
Figure 5-12 shows an example where BUCK1 is defined to enter Sleep State in response to CTL6 going
low.
NOTE
All PGOODs from GPO1–GPO4 can stay asserted during the entry and the exit. Depending
on status of the BUCK1_DECAY bit defined in the BUCK1CTRL register, BUCK1 output will
either decay or slew down to a new voltage defined in BUCK1_SLP_VID[6:0].
5.8.7
Emergency Shutdown
5.4 V
VSYS
GPOx
444 ns (nominal with ± 1 ± % variation)
BUCKx
LDOAx
SWx
VTT
Figure 5-13. Emergency Shutdown Sequence
When VSYS crosses below VSYS_UVLO_5V, all Power Good pins will be deasserted, and after 444 ns (nom) of
delay all VRs will shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure
timely decay of all VR outputs. Other conditions that will cause emergency shutdown are the die
temperature rising above the critical temperature threshold (TCRIT), deassertion of Power Good of any rail
(configurable), or failure of any rail to reach power good within 10 ms of being enabled (configurable). If
PMIC was shutdown by UVLO, it will wait until VSYS rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS before
reloading the default OTP and checking the state of the CTLx pins. If PMIC was shutdown by temperature,
it will wait until temperature drops below TCRIT – TCRIT_HYS before reloading OTP and checking the state of
the CTLx pins. If the PMIC was shutdown by power fault, it will reload OTP after disabling all rails and
check the state of the CTLx pins once OTP has finished reloading.
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5.9
5.9.1
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Device Functional Modes
Off Mode
When power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V
nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than
VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while it is still less than VSYS_UVLO_5V +
VSYS_UVLO_5V_HYS, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and
regulated at target values.
5.9.2
Standby Mode
When power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters
standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and
I2C interface and CTL pins are ready to respond. All default registers defined in Section 5.11 should have
by now been loaded from one-time programmable (OTP) memory. Quiescent current consumption in
standby mode is specified in Section 4.5.
5.9.3
Active Mode
The device proceeds to active mode when any output rail is enabled either via an input pin as discussed
in Section 5.8 or by writing to EN bits through I2C. Output regulation voltage can also be changed by
writing to VID bits defined in Section 5.11.
5.10 I2C Interface
The I2C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see
I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA)
and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled
high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, DATA and CLK. A
master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits
data on the bus under control of the master device.
The PMIC works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents are loaded when VSYS
higher than VSYS_UVLO_5V is applied to the PMIC. The I2C interface is running from an internal oscillator that
is automatically enabled when there is an access to the interface.
The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred
to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it
is referred to as H/S-mode.
The PMIC device supports 7-bit addressing; however, 10-bit addressing and general call address are not
supported. The default device address is 0x5E, though it can be modified by programming. The
programming registers are located in device address 0x38, which cannot be changed.
38
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5.10.1 F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high (see Figure 5-14). All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 5-15). All devices recognize the address sent by the master and compare it to their internal fixed
addresses. Only the slave device with a matching address generates an acknowledge (see Figure 5-16),
by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this
acknowledge, the master knows that the communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data
from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the
transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on
which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can
continue as long as necessary.
To signal the end of the data transfer, the master
low to high while the SCL line is high (see
communication link with the addressed slave.
condition. Upon the receipt of a stop condition, all
a start condition followed by a matching address.
generates a stop condition by pulling the SDA line from
Figure 5-14). This releases the bus and stops the
All I2C-compatible devices must recognize the stop
devices know that the bus is released, and they wait for
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 5-14. START and STOP Conditions
SDA
SCL
Data Valid
Change of Data Allowed
Figure 5-15. Bit Transfer on the I2C Bus
Detailed Description
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Data Output at
Transmitter
Not ACK
Data Output at
Receiver
ACK
SCL from Master
1
2
8
9
S
START
Condition
Clock pulse for ACK
Figure 5-16. Acknowledge on the I2C Bus
Generate ACK Signal
SDA
MSB
ACK Signal From Slave
Address
R/ W
SCL
1
2
7
8
9
1
2
3-8
ACK
S or Sr
Byte Complete, Interrupt
Within Slave
9
ACK
Clock Line Held Low While
Interrupts Are Serviced
START or
Repeated START Condition
P or Sr
STOP or
Repeated START Condition
Figure 5-17. I2C Bus Protocol
40
Detailed Description
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SCL
SDA
A6
START
A5
A4
A0
R /W
ACK
0
0
R7
R6
R5
R0
ACK
D7
D6
D5
D0
0
Slave Address
ACK
0
Register Address
Data
STOP
Figure 5-18. I2C Interface WRITE to TPS650861 in F/S Mode
SCL
SDA
A6
A0
R/ W ACK
0
START
0
Slave Address
R7
R0
ACK
A6
A0
0
R/ W
ACK
1
0
Slave Address
Register Address
D7
D0
ACK
0
Slave Drives
the Data
Master
Drives ACK
and Stop
STOP
Repeated
START
Figure 5-19. I2C Interface READ from TPS650861 in F/S Mode
(Only Repeated START is Supported)
Detailed Description
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5.11 I2C Address: 0x5E Register Maps
5.11.1 Register Map Summary
This section describes the registers that can be accessed using I2C address 0x5E. These registers can be
accessed without putting the device into programming mode. The DEVICEID1 and DEVICEID2 registers
can only be written to while the device is in programming mode. The I2C address can be changed if
necessary from the default 0x5E using the I2C_SLAVE_ADDR register (see Section 5.12.39). See the
TPS65086100 OTP Memory Programming Guide for more information on putting the device into
programming mode.Do not attempt to write a RESERVED R/W bit to the opposite value. When the reset
value of a bit register is 0bX, it means the bit value is coming from the OTP memory.
Table 5-6. Register Map Summary
42
Address
Name
Short Description
00h
DEVICEID1
Device ID code indicating revision
01h
DEVICEID2
Device ID code indicating revision
02h
IRQ
Interrupt statuses
03h
IRQ_MASK
Interrupt masking
04h
PMIC_STAT
PMIC temperature indicator
05h
SHUTDNSRC
Shutdown root cause indicator bits
20h
BUCK1CTRL
BUCK1 decay control and voltage select
21h
BUCK2CTRL
BUCK2 decay control and voltage select
22h
BUCK3DECAY
BUCK3 decay control
23h
BUCK3VID
BUCK3 voltage select
24h
BUCK3SLPCTRL
25h
BUCK4CTRL
BUCK4 control
26h
BUCK5CTRL
BUCK5 control
27h
BUCK6CTRL
BUCK6 control
28h
LDOA2CTRL
LDOA2 control
29h
LDOA3CTRL
LDOA3 control
40h
DISCHCTRL1
Discharge resistors for each rail control
41h
DISCHCTRL2
Discharge resistors for each rail control
42h
DISCHCTRL3
Discharge resistors for each rail control
43h
PG_DELAY1
System Power Good on GPO3 (if GPO3 is programmed to be system PG)
BUCK3 voltage select for sleep state
91h
FORCESHUTDN
Software force shutdown
92h
BUCK1SLPCTRL
BUCK1 voltage select for sleep state
93h
BUCK2SLPCTRL
BUCK2 voltage select for sleep state
94h
BUCK4VID
95h
BUCK4SLPVID
BUCK4 voltage select
96h
BUCK5VID
97h
BUCK5SLPVID
98h
BUCK6VID
99h
BUCK6SLPVID
9Ah
LDOA2VID
LDOA2 voltage select
LDOA3 voltage select
BUCK4 voltage select for sleep state
BUCK5 voltage select
BUCK5 voltage select for sleep state
BUCK6 voltage select
BUCK6 voltage select for sleep state
9Bh
LDOA3VID
9Ch
BUCK123CTRL
9Dh
PG_DELAY2
System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG)
9Fh
SWVTT_DIS
SWs and VTT I2C disable bits
A0h
I2C_RAIL_EN1
A1h
I2C_RAIL_EN2/GPOCTRL
A2h
PWR_FAULT_MASK1
BUCK1, 2, and 3 disable and BUCK1, and 2 PFM/PWM mode control
I2C Enable control of individual rails
I2C Enable control of individual rails and I2C controlled GPOs, high or low
Power fault masking for individual rails
Detailed Description
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Table 5-6. Register Map Summary (continued)
Address
Name
A3h
PWR_FAULT_MASK2
Short Description
A4h
GPO1PG_CTRL1
Power good tree control for GPO1
A5h
GPO1PG_CTRL2
Power good tree control for GPO1
A6h
GPO4PG_CTRL1
Power good tree control for GPO4
A7h
GPO4PG_CTRL2
Power good tree control for GPO4
A8h
GPO2PG_CTRL1
Power good tree control for GPO2
A9h
GPO2PG_CTRL2
Power good tree control for GPO2
AAh
GPO3PG_CTRL1
Power good tree control for GPO3
ABh
GPO3PG_CTRL2
Power good tree control for GPO3
ACh
MISCSYSPG
ADh
VTT_DISCH_CTRL
AEh
LDOA1_SWB2_CTRL
B0h
PG_STATUS1
Power good statuses for individual rails
B1h
PG_STATUS2
Power good statuses for individual rails
B2h
PWR_FAULT_STATUS1
Power fault statuses for individual rails
B3h
PWR_FAULT_STATUS2
Power fault statuses for individual rails
B4h
TEMPCRIT
Critical temperature indicators
B5h
TEMPHOT
Hot temperature indicators
Power fault masking for individual rails
Power good tree control with CTL3 and CTL6 for GPO
Discharge resistor setting for VTT LDO
LDOA1 and SWB2 control for discharge, voltage selection, and enable
Complex bit access types are encoded to fit into small table cells. Table 5-7 shows the codes that are
used for access types in this section.
Table 5-7. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
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5.11.2 DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
Figure 5-20. DEVICEID1 Register
Bit
Bit Name
TPS65086100
Access
7
PART_
NUMBER[7]
0
R
6
PART_
NUMBER[6]
0
R
5
PART_
NUMBER[5]
0
R
4
PART_
NUMBER[4]
0
R
3
PART_
NUMBER[3]
0
R
2
PART_
NUMBER[2]
0
R
1
PART_
NUMBER[1]
0
R
0
PART_
NUMBER[0]
0
R
Table 5-8. DEVICEID1 Register Descriptions
Bit
Field
Type Reset
Description
7:4
PART_NUMBER[7:4]
R
X
Device part number ID
0000: TPS65086x0x
0001: TPS65086x1x
...
1111: TPS65086xFx
3:0
PART_NUMBER[3:0]
R
X
Device part number ID
0000: TPS65086xx0
0001: TPS65086xx1
...
1111: TPS65086xxF
5.11.3 DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
Figure 5-21. DEVICEID2 Register
Bit
Bit Name
TPS65086100
Access
7
6
REVID[1]
REVID[0]
0
R
0
R
5
OTP_
VERSION[1]
0
R
4
3
2
OTP_
PART_
PART_
VERSION[0] NUMBER[11] NUMBER[10]
0
0
0
R
R
R
1
PART_
NUMBER[9]
0
R
0
PART_
NUMBER[8]
1
R
Table 5-9. DEVICEID2 Register Descriptions
Bit
Field
Type Reset
Description
7:6
REVID[1:0]
R
X
Silicon revision ID
5:4
OTP_VERSION[1:0]
R
X
OTP variation ID
00: A
01: B
10: C
11: D
3:0
PART_NUMBER[11:8]
R
X
Device part number ID
0001: TPS650861xx
44
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5.11.4 IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
Figure 5-22. IRQ Register
Bit
Bit Name
TPS650861
Access
7
FAULT
0
R/W
6
RESERVED
0
R
5
RESERVED
0
R
4
RESERVED
0
R
3
SHUTDN
0
R/W
2
RESERVED
0
R
1
RESERVED
0
R
0
DIETEMP
0
R/W
Table 5-10. IRQ Register Descriptions
Bit
Field
Type Reset
Description
7
FAULT
R/W
0
Fault interrupt. Asserted when either condition occurs: power fault of any rail, or
die temperature crosses over the critical temperature threshold (TCRIT). The
user can read Reg. 0xB2–0xB6 to determine what has caused the interrupt.
0: Not asserted
1: Asserted. Host to write 1b to clear.
3
SHUTDN
R/W
0
Asserted when PMIC shuts down. To clear indicator, SHUTDNSRC must be
cleared first, see Section 5.11.7
0: Not asserted.
1: Asserted. Host to write 1b to clear.
0
DIETEMP
R/W
0
Die temp interrupt. Asserted when PMIC die temperature crosses above the hot
temperature threshold (THOT).
0: Not asserted.
1: Asserted. Host to write 1b to clear.
5.11.5 IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
Figure 5-23. IRQ_MASK Register
Bit
Bit Name
TPS650861
Access
7
MFAULT
1
R/W
6
RESERVED
1
R
5
RESERVED
1
R
4
RESERVED
1
R
3
msHUTDN
1
R/W
2
RESERVED
1
R
1
RESERVED
1
R
0
MDIETEMP
1
R/W
Table 5-11. IRQ_MASK Register Descriptions
Bit
Field
Type Reset
Description
7
MFAULT
R/W
1
FAULT interrupt mask.
0: Not masked.
1: Masked.
3
msHUTDN
R/W
1
PMIC shutdown event interrupt mask
0: Not masked.
1: Masked.
0
MDIETEMP
R/W
1
Die temp interrupt mask.
0: Not masked.
1: Masked.
Detailed Description
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5.11.6 PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
Figure 5-24. PMICSTAT Register
Bit
Bit Name
TPS650861
Access
7
RESERVED
0
R
6
RESERVED
0
R
5
RESERVED
0
R
4
RESERVED
0
R
3
RESERVED
0
R
2
RESERVED
0
R
1
RESERVED
0
R
0
SDIETEMP
0
R
Table 5-12. PMICSTAT Register Descriptions
Bit
Field
Type Reset
Description
0
SDIETEMP
R
PMIC die temperature status.
0: PMIC die temperature is below THOT.
1: PMIC die temperature is above THOT.
0
5.11.7 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
Figure 5-25. SHUTDNSRC Register
Bit
Bit Name
TPS650861
Access
7
RESERVED
0
R
6
RESERVED
0
R
5
RESERVED
0
R
4
RESERVED
0
R
3
COLDOFF
0
R/W
2
UVLO
0
R/W
1
PWR_FAULT
0
R/W
0
CRITTEMP
0
R/W
Table 5-13. SHUTDNSRC Register Descriptions
Bit
Field
Type Reset
Description
3
COLDOFF
R/W
0
Set by PMIC cleared by host. Host to write 1b to clear.
0: Cleared
1: N/A. Not enabled for existing OTPs.
2
UVLO
R/W
0
Set by PMIC cleared by host. Host to write 1b to clear.
0: Cleared
1: PMIC was shut down due to a UVLO event (VSYS crosses below 5.4 V).
Assertion of this bit sets the SHUTDN bit in Section 5.11.4.
1
PWR_FAULT
R/W
0
Set by PMIC cleared by host. Host to write 1b to clear.
0: Cleared
1: PMIC was shut down due to an unmasked power fault event. Assertion of
this bit sets the SHUTDN bit in Section 5.11.4. The source of the power fault
can be determined from the PWR_FAULT registers (0xB2 and 0xB3).
Overcurrent protection will limit IOUT and typically cause a power fault as VOUT
droops.
0
CRITTEMP
R/W
0
Set by PMIC cleared by host. Host to write 1b to clear.
0: Cleared
1: PMIC was shut down due to the rise of PMIC die temperature above critical
temperature threshold (TCRIT). Assertion of this bit sets the SHUTDN bit in
Section 5.11.4.
46
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5.11.8 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
Figure 5-26. BUCK1CTRL Register
Bit
Bit Name
TPS65086100
Access
7
BUCK1_
VID[6]
0
R/W
6
BUCK1_
VID[5]
0
R/W
5
BUCK1_
VID[4]
0
R/W
4
BUCK1_
VID[3]
0
R/W
3
BUCK1_
VID[2]
0
R/W
2
BUCK1_
VID[1]
0
R/W
1
BUCK1_
VID[0]
0
R/W
0
BUCK1_
DECAY
0
R/W
Table 5-14. BUCK1CTRL Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK1_VID[6:0]
R/W
X
This field sets the BUCK1 regulator output regulation voltage in
normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges
for VOUT options.
0
BUCK1_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits.
Decay rate depends on total capacitance and load present at the
output.
5.11.9 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
Figure 5-27. BUCK2CTRL Register
Bit
Bit Name
TPS65086100
Access
7
BUCK2_
VID[6]
0
R/W
6
BUCK2_
VID[5]
0
R/W
5
BUCK2_
VID[4]
0
R/W
4
BUCK2_
VID[3]
0
R/W
3
BUCK2_
VID[2]
0
R/W
2
BUCK2_
VID[1]
0
R/W
1
BUCK2_
VID[0]
0
R/W
0
BUCK2_
DECAY
0
R/W
Table 5-15. BUCK2CTRL Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK2_VID[6:0]
R/W
X
This field sets the BUCK2 regulator output regulation voltage in
normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for
VOUT options.
0
BUCK2_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits.
Decay rate depends on total capacitance and load present at the
output.
Detailed Description
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5.11.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
Figure 5-28. BUCK3DECAY Register
Bit
Bit Name
TPS65086100
Access
7
6
5
4
3
2
1
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
BUCK3_
DECAY
0
R/W
Table 5-16. BUCK3DECAY Register Descriptions
Bit
Field
Type
Reset
Description
7:1
SPARE
R/W
X
Unused. Typically mirror BUCK3_VID by default in OTP.
0
BUCK3_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits.
Decay rate depends on total capacitance and load present at the
output.
5.11.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
Figure 5-29. BUCK3VID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK3_
VID[6]
0
R/W
6
BUCK3_
VID[5]
0
R/W
5
BUCK3_
VID[4]
0
R/W
4
BUCK3_
VID[3]
0
R/W
3
BUCK3_
VID[2]
0
R/W
2
BUCK3_
VID[1]
0
R/W
1
BUCK3_
VID[0]
0
R/W
0
RESERVED
0
R
Table 5-17. BUCK3VID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK3_VID[6:0]
R/W
This field sets the BUCK3 regulator output regulation voltage in
normal mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
48
X
Detailed Description
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5.11.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
Figure 5-30. BUCK3SLPCTRL Register
Bit
Bit Name
TPS65086100
Access
7
BUCK3_SLP
_ VID[6]
0
R/W
6
BUCK3_SLP
_ VID[5]
0
R/W
5
BUCK3_SLP
_ VID[4]
0
R/W
4
BUCK3_SLP
_ VID[3]
0
R/W
3
BUCK3_SLP
_ VID[2]
0
R/W
2
BUCK3_SLP
_ VID[1]
0
R/W
1
BUCK3_SLP
_ VID[0]
0
R/W
0
BUCK3_SLP
_ EN
0
R/W
Table 5-18. BUCK3SLPCTRL Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK3_SLP_VID[6:0]
R/W
X
This field sets the BUCK3 regulator output regulation voltage in
sleep mode if BUCK3_SLP_EN = 1b.
See Table 5-3 for 25-mV step ranges for VOUT options.
0
BUCK3_SLP_EN
R/W
X
BUCK3 sleep mode enable. BUCK3 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
0: Disable. Uses BUCK3_VID in all cases.
1: Enabled. Uses BUCK3_SLP_VID when assigned sleep pin is
low.
5.11.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
Figure 5-31. BUCK4CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
BUCK4_SLP
_ EN[1]
0
R/W
4
BUCK4_SLP
_ EN[0]
0
R/W
3
2
RESERVED
RESERVED
1
R/W
1
R/W
1
BUCK4_
MODE
0
R/W
0
BUCK4_DIS
0
R/W
Table 5-19. BUCK4CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5:4
BUCK4_SLP_EN
R/W
X
BUCK4 sleep mode enable. BUCK4 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
00: Disable. Uses BUCK4_VID in all cases.
11: Enabled. Uses BUCK4_SLP_VID when assigned sleep pin is
low.
01,10: Reserved. Do not write these values.
3:2
RESERVED
R/W
11
Reserved bits. Always write to 11.
1
BUCK4_MODE
R/W
X
This field sets the BUCK4 regulator operating mode.
0: Reserved
1: Forced PWM mode
0
BUCK4_DIS
R/W
X
BUCK4 Disable Bit. Writing 0 to this bit forces BUCK4 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
Detailed Description
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5.11.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
Figure 5-32. BUCK5CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
BUCK5_SLP
_EN[1]
0
R/W
4
BUCK5_SLP
_EN[0]
0
R/W
3
2
RESERVED
RESERVED
1
R/W
1
R/W
1
BUCK5_
MODE
0
R/W
0
BUCK5_DIS
0
R/W
Table 5-20. BUCK5CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5:4
BUCK5_SLP_EN
R/W
X
BUCK5 sleep mode enable. BUCK5 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
00: Disable. Uses BUCK5_VID in all cases.
11: Enabled. Uses BUCK5_SLP_VID when assigned sleep pin is
low.
01,10: Reserved. Do not write these values.
3:2
RESERVED
R/W
11
Reserved bits. Always write to 11.
1
BUCK5_MODE
R/W
X
This field sets the BUCK5 regulator operating mode.
0: Reserved
1: Forced PWM mode
0
BUCK5_DIS
R/W
X
BUCK5 Disable Bit. Writing 0 to this bit forces BUCK5 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
5.11.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
Figure 5-33. BUCK6CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
BUCK6_SLP
EN[1]
0
R/W
4
BUCK6_SLP
EN[0]
0
R/W
3
2
RESERVED
RESERVED
1
R/W
1
R/W
1
BUCK6_
MODE
0
R/W
0
BUCK6_DIS
0
R/W
Table 5-21. BUCK6CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5:4
BUCK6_SLP_EN
R/W
X
BUCK6 sleep mode enable. BUCK6 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
00: Disable. Uses BUCK6_VID in all cases.
11: Enabled. Uses BUCK6_SLP_VID when assigned sleep pin is
low.
01,10: Reserved. Do not write these values.
3:2
RESERVED
R/W
11
Reserved bits. Always write to 11.
1
BUCK6_MODE
R/W
X
This field sets the BUCK6 regulator operating mode.
0: Automatic mode
1: Forced PWM mode
0
BUCK6_DIS
R/W
X
BUCK6 Disable Bit. Writing 0 to this bit forces BUCK6 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
50
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5.11.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
Figure 5-34. LDOA2CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
LDOA2_SLP
_EN[1]
0
R/W
4
LDOA2_SLP
_EN[0]
0
R/W
3
2
1
0
RESERVED
RESERVED
RESERVED
LDOA2_DIS
1
R/W
1
R/W
0
R/W
0
R/W
Table 5-22. LDOA2CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5:4
LDOA2_SLP_EN
R/W
X
LDOA2 sleep mode enable. LDOA2 is factory configured to switch
to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
00: Disable. Uses LDOA2_VID in all cases.
11: Enabled. Uses LDOA2_SLP_VID when assigned sleep pin is
low.
01,10: Reserved. Do not write these values.
3:1
RESERVED
R/W
110
Reserved bits. Always write to '110'.
0
LDOA2_DIS
R/W
X
LDOA2 Disable Bit. Writing 0 to this bit forces LDOA2 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
5.11.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
Figure 5-35. LDOA3CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
LDOA3_SLP
_EN[1]
0
R/W
4
LDOA3_SLP
_EN[0]
0
R/W
3
2
1
0
RESERVED
RESERVED
RESERVED
LDOA3_DIS
1
R/W
1
R/W
0
R/W
0
R/W
Table 5-23. LDOA3CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5:4
LDOA3_SLP_EN
R/W
X
LDOA3 sleep mode enable. LDOA3 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
00: Disable. Uses LDOA3_VID in all cases.
11: Enabled. Uses LDOA3_SLP_VID when assigned sleep pin is
low.
01,10: Reserved. Do not write these values.
3:1
RESERVED
R/W
110
Reserved bits. Always write to '110'.
0
LDOA3_DIS
R/W
X
LDOA3 Disable Bit. Writing 0 to this bit forces LDOA3 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
Detailed Description
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5.11.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.
Figure 5-36. DISCHCTRL1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK4_
DISCHG[1]
0
R/W
6
BUCK4_
DISCHG[0]
0
R/W
5
BUCK3_
DISCHG[1]
0
R/W
4
BUCK3_
DISCHG[0]
0
R/W
3
BUCK2_
DISCHG[1]
0
R/W
2
BUCK2_
DISCHG[0]
0
R/W
1
BUCK1_
DISCHG[1]
0
R/W
0
BUCK1_
DISCHG[0]
0
R/W
Table 5-24. DISCHCTRL1 Register Descriptions
Bit
Field
Type
Reset
Description
7:6
BUCK4_DISCHG[1:0]
R/W
X
BUCK4 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5:4
BUCK3_DISCHG[1:0]
R/W
X
BUCK3 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3:2
BUCK2_DISCHG[1:0]
R/W
X
BUCK2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1:0
BUCK1_DISCHG[1:0]
R/W
X
BUCK1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
52
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5.11.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.
Figure 5-37. DISCHCTRL2 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2_
DISCHG[1]
0
R/W
6
LDOA2_
DISCHG[0]
0
R/W
5
SWA1_
DISCHG[1]
0
R/W
4
SWA1_
DISCHG[0]
0
R/W
3
BUCK6_
DISCHG[1]
0
R/W
2
BUCK6_
DISCHG[0]
0
R/W
1
BUCK5_
DISCHG[1]
0
R/W
0
BUCK5_
DISCHG[0]
0
R/W
Table 5-25. DISCHCTRL2 Register Descriptions
Bit
Field
Type
Reset
Description
7:6
LDOA2_DISCHG[1:0]
R/W
X
LDOA2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5:4
SWA1_DISCHG[1:0]
R/W
X
SWA1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3:2
BUCK6_DISCHG[1:0]
R/W
X
BUCK6 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1:0
BUCK5_DISCHG[1:0]
R/W
X
BUCK5 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
Detailed Description
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5.11.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
All xx_DISCHG[1:0] bits internally set to 00 whenever the corresponding VR is enabled.
Figure 5-38. DISCHCTRL3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R
0
R
5
SWB2_
DISCHG[1]
0
R/W
4
SWB2_
DISCHG[0]
0
R/W
3
SWB1_
DISCHG[1]
0
R/W
2
SWB1_
DISCHG[0]
0
R/W
1
LDOA3_
DISCHG[1]
0
R/W
0
LDOA3_
DISCHG[0]
0
R/W
Table 5-26. DISCHCTRL3 Register Descriptions
Bit
Field
Type
Reset
Description
5:4
SWB2_DISCHG[1:0]
R/W
X
SWB2 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3:2
SWB1_DISCHG[1:0]
R/W
X
SWB1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
1:0
LDOA3_DISCHG[1:0]
R/W
X
LDOA3 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5.11.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to
GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC
can be programmed for system PG, level shifter or I2C controller GPO.
Figure 5-39. PG_DELAY1 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
4
3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
R
0
R
0
R
0
R
0
R
2
GPO3_PG_
DELAY[2]
0
R/W
1
GPO3_PG_
DELAY[1]
0
R/W
0
GPO3_PG_
DELAY[0]
0
R/W
Table 5-27. PG_DELAY1 Register Descriptions
Bit
Field
Type Reset
Description
2:0
GPO3_PG_DELAY[2:0]
R/W
Programmable delay Power Good or level shifter for GPO3 pin.
Measured from the moment when all rails grouped to this pin
reach their regulation range. All values have ±10% variation.
000: 2.5 ms
001: 5.0 ms
010: 10 ms
011: 15 ms
100: 20 ms
101: 50 ms
110: 75 ms
111: 100 ms
—: Bits not used. If GPO3 is controlled by I2C rather than PG and
is not used internally for VTT LDO enable, these bits have no
impact. Default is set to 0b.
54
X
Detailed Description
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5.11.22 FORCESHUTDN: Force Emergency Shutdown Control Register
(offset = 91h) [reset = 0000 0000]
Figure 5-40. FORCESHUTDN Register
Bit
Bit Name
TPS650861
Access
7
RESERVED
0
R
6
RESERVED
0
R
5
RESERVED
0
R
4
RESERVED
0
R
3
RESERVED
0
R
2
RESERVED
0
R
1
RESERVED
0
R
0
SDWN
0
R/W
Table 5-28. FORCESHUTDN Register Descriptions
Bit
Field
Type Reset
Description
0
SDWN
R/W
Forces reset of the PMIC and reset of all registers. The bit is self-clearing.
PMIC does not generate I2C ACK for this command because it goes into
emergency shutdown.
0: No action.
1: PMIC initiates emergency shutdown.
0
5.11.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
Figure 5-41. BUCK1SLPCTRL Register
Bit
Bit Name
TPS65086100
Access
7
BUCK1_
SLP_ VID[6]
0
R/W
6
BUCK1_
SLP_ VID[5]
0
R/W
5
BUCK1_
SLP_ VID[4]
0
R/W
4
BUCK1_
SLP_ VID[3]
0
R/W
3
BUCK1_
SLP_ VID[2]
0
R/W
2
BUCK1_
SLP_ VID[1]
0
R/W
1
BUCK1_
SLP_ VID[0]
0
R/W
0
BUCK1_
SLP_ EN
0
R/W
Table 5-29. BUCK1SLPCTRL Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK1_SLP_VID[6:0]
R/W
X
This field sets the BUCK1 regulator output regulation voltage in
normal mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
0
BUCK1_SLP_EN
R/W
X
BUCK1 sleep mode enable. BUCK1 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
0: Disable. Uses BUCK1_VID in all cases.
1: Enabled. Uses BUCK1_SLP_VID when assigned sleep pin is
low.
Detailed Description
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5.11.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
Figure 5-42. BUCK2SLPCTRL Register
Bit
Bit Name
TPS65086100
Access
7
BUCK2_SLP
_ VID[6]
0
R/W
6
BUCK2_SLP
_ VID[5]
0
R/W
5
BUCK2_SLP
_ VID[4]
0
R/W
4
BUCK2_SLP
_ VID[3]
0
R/W
3
BUCK2_SLP
_ VID[2]
0
R/W
2
BUCK2_SLP
_ VID[1]
0
R/W
1
BUCK2_SLP
_ VID[0]
0
R/W
0
BUCK2_SLP
_ EN
0
R/W
Table 5-30. BUCK2SLPCTRL Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK2_SLP_VID[6:0]
R/W
X
This field sets the BUCK2 regulator output regulation voltage in
normal mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
0
BUCK2_SLP_EN
R/W
X
BUCK2 sleep mode enable. BUCK2 is factory configured to
switch to sleep mode voltage either by CTL3/SLPENB1 pin or by
CTL6/SLPENB2 pin.
0: Disable. Uses BUCK2_VID in all cases.
1: Enabled. Uses BUCK2_SLP_VID when assigned sleep pin is
low.
5.11.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
Figure 5-43. BUCK4VID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK4_
VID[6]
0
R/W
6
BUCK4_
VID[5]
0
R/W
5
BUCK4_
VID[4]
0
R/W
4
BUCK4_
VID[3]
0
R/W
3
BUCK4_
VID[2]
0
R/W
2
BUCK4_
VID[1]
0
R/W
1
BUCK4_
VID[0]
0
R/W
0
BUCK4_
DECAY
0
R/W
Table 5-31. BUCK4VID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK4_VID[6:0]
R/W
X
This field sets the BUCK4 regulator output regulation voltage in
normal mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
0
BUCK4_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits.
Decay rate depends on total capacitance and load present at the
output.
56
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5.11.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
Figure 5-44. BUCK4SLPVID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK4_SLP
_ VID[6]
0
R/W
6
BUCK4_SLP
_ VID[5]
0
R/W
5
BUCK4_SLP
_ VID[4]
0
R/W
4
BUCK4_SLP
_ VID[3]
0
R/W
3
BUCK4_SLP
_ VID[2]
0
R/W
2
BUCK4_SLP
_ VID[1]
0
R/W
1
BUCK4_SLP
_ VID[0]
0
R/W
0
RESERVED
0
R
Table 5-32. BUCK4SLPVID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK4_SLP_VID[6:0]
R/W
This field sets the BUCK4 regulator output regulation voltage in
sleep mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
X
5.11.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
Figure 5-45. BUCK5VID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK5_
VID[6]
0
R/W
6
BUCK5_
VID[5]
0
R/W
5
BUCK5_
VID[4]
0
R/W
4
BUCK5_
VID[3]
0
R/W
3
BUCK5_
VID[2]
0
R/W
2
BUCK5_
VID[1]
0
R/W
1
BUCK5_
VID[0]
0
R/W
0
BUCK5_
DECAY
0
R/W
Table 5-33. BUCK5VID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK5_VID[6:0]
R/W
X
This field sets the BUCK5 regulator output regulation voltage in
normal mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
0
BUCK5_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID
bits. Decay rate depends on total capacitance and load present
at the output.
Detailed Description
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5.11.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
Figure 5-46. BUCK5SLPVID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK5_SLP
_ VID[6]
0
R/W
6
BUCK5_SLP
_ VID[5]
0
R/W
5
BUCK5_SLP
_ VID[4]
0
R/W
4
BUCK5_SLP
_ VID[3]
0
R/W
3
BUCK5_SLP
_ VID[2]
0
R/W
2
BUCK5_SLP
_ VID[1]
0
R/W
1
BUCK5_SLP
_ VID[0]
0
R/W
0
RESERVED
0
R
Table 5-34. BUCK5SLPVID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK5_SLP_VID[6:0]
R/W
This field sets the BUCK5 regulator output regulation voltage in
sleep mode.
See Table 5-3 for 25-mV step ranges for VOUT options.
X
5.11.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
Figure 5-47. BUCK6VID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK6_
VID[6]
0
R/W
6
BUCK6_
VID[5]
0
R/W
5
BUCK6_
VID[4]
0
R/W
4
BUCK6_
VID[3]
0
R/W
3
BUCK6_
VID[2]
0
R/W
2
BUCK6_
VID[1]
0
R/W
1
BUCK6_
VID[0]
0
R/W
0
BUCK6_
DECAY
0
R/W
Table 5-35. BUCK6VID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK6_VID[6:0]
R/W
X
This field sets the BUCK6 regulator output regulation voltage in
normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for
VOUT options.
0
BUCK6_DECAY
R/W
X
Decay Bit
0: The output slews down to a lower voltage set by the VID bits.
1: The output decays down to a lower voltage set by the VID bits.
Decay rate depends on total capacitance and load present at the
output.
58
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5.11.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
Figure 5-48. BUCK6SLPVID Register
Bit
Bit Name
TPS65086100
Access
7
BUCK6_SLP
_ VID[6]
0
R/W
6
BUCK6_SLP
_ VID[5]
0
R/W
5
BUCK6_SLP
_ VID[4]
0
R/W
4
BUCK6_SLP
_ VID[3]
0
R/W
3
BUCK6_SLP
_ VID[2]
0
R/W
2
BUCK6_SLP
_ VID[1]
0
R/W
1
BUCK6_SLP
_ VID[0]
0
R/W
0
RESERVED
0
R
Table 5-36. BUCK6SLPVID Register Descriptions
Bit
Field
Type Reset
Description
7:1
BUCK6_SLP_VID[6:0]
R/W
This field sets the BUCK6 regulator output regulation voltage in
normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges
for VOUT options.
X
5.11.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
Figure 5-49. LDOA2VID Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2_SLP
_VID[3]
0
R/W
6
LDOA2_SLP
_VID[2]
0
R/W
5
LDOA2_SLP
_VID[1]
0
R/W
4
LDOA2_SLP
_VID[0]
0
R/W
3
LDOA2_
VID[3]
0
R/W
2
LDOA2_
VID[3]
0
R/W
1
LDOA2_
VID[1]
0
R/W
0
LDOA2_
VID[0]
0
R/W
Table 5-37. LDOA2VID Register Descriptions
Bit
Field
Type Reset
Description
7:4
LDOA2_SLP_VID[3:0]
R/W
X
This field sets the LDOA2 regulator output regulation voltage in
sleep mode.
See Table 5-5 for Vout options.
3:0
LDOA2_VID[3:0]
R/W
X
This field sets the LDOA2 regulator output regulation voltage in
normal mode.
See Table 5-5 for Vout options.
Detailed Description
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5.11.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
Figure 5-50. LDOA3VID Register
Bit
Bit Name
TPS65086100
Access
7
LDOA3_SLP
_ VID[3]
0
R/W
6
LDOA3_SLP
_ VID[2]
0
R/W
5
LDOA3_SLP
_ VID[1]
0
R/W
4
LDOA3_SLP
_ VID[0]
0
R/W
3
LDOA3_
VID[3]
0
R/W
2
LDOA3_
VID[3]
0
R/W
1
LDOA3_
VID[1]
0
R/W
0
LDOA3_
VID[0]
0
R/W
Table 5-38. LDOA3VID Register Descriptions
Bit
Field
Type Reset
Description
7:4
LDOA3_SLP_VID[3:0]
R/W
X
This field sets the LDOA3 regulator output regulation voltage in
sleep mode.
See Table 5-5 for Vout options.
3:0
LDOA3_VID[3:0]
R/W
X
This field sets the LDOA3 regulator output regulation voltage in
normal mode.
See Table 5-5 for Vout options.
5.11.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
Figure 5-51. BUCK123CTRL Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
TPS65086100
Access
5
BUCK3
_MODE
0
R/W
4
BUCK2
_MODE
0
R/W
3
BUCK1
_MODE
0
R/W
2
BUCK3
_DIS
0
R/W
1
BUCK2
_DIS
0
R/W
0
BUCK1
_DIS
0
R/W
Table 5-39. BUCK123CTRL Register Descriptions
Bit
Field
Type
Reset
Description
5
BUCK3_MODE
R/W
X
This field sets the BUCK3 regulator operating mode.
0: Reserved
1: Forced PWM mode
4
BUCK2_MODE
R/W
X
This field sets the BUCK2 regulator operating mode.
0: Automatic mode
1: Forced PWM mode
3
BUCK1_MODE
R/W
X
This field sets the BUCK1 regulator operating mode.
0: Automatic mode
1: Forced PWM mode
2
BUCK3_DIS
R/W
X
BUCK3 Disable Bit. Writing 0 to this bit forces BUCK3 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
1
BUCK2_DIS
R/W
X
BUCK2 Disable Bit. Writing 0 to this bit forces BUCK2 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
0
BUCK1_DIS
R/W
X
BUCK1 Disable Bit. Writing 0 to this bit forces BUCK1 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable
1: Enable
60
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5.11.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
Programmable Power Good delay for GPO1, GPO2, and GPO4 pins, measured from the moment when
all VRs assigned to respective GPO reach their regulation range to Power Good assertion. This is an
optional register as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.
Figure 5-52. PG_DELAY2 Register
Bit
Bit Name
TPS65086100
Access
7
GPO2_PG_
DELAY[2]
0
R/W
6
GPO2_PG_
DELAY[1]
0
R/W
5
GPO2_PG_
DELAY[0]
0
R/W
4
GPO4_PG_
DELAY[2]
0
R/W
3
GPO4_PG_
DELAY[1]
0
R/W
2
GPO4_PG_
DELAY[0]
0
R/W
1
GPO1_PG_
DELAY[1]
0
R/W
0
GPO1_PG_
DELAY[0]
0
R/W
Table 5-40. PG_DELAY2 Register Descriptions
Bit
Field
Type Reset
Description
7:5
GPO2_PG_DELAY[2:0]
R/W
X
Programmable delay Power Good or level shifter for GPO2 pin.
Measured from the moment when all rails grouped to this pin
reach their regulation range. All values have ±10% variation.
000: 0 ms
001: 5.0 ms
010: 10 ms
011: 15 ms
100: 20 ms
101: 50 ms
110: 75 ms
111: 100 ms
—: Bits not used. If GPO2 is controlled by I2C rather than PG and
is not used internally for VTT LDO enable, these bits have no
impact. Default is set to 0b.
4:2
GPO4_PG_DELAY[2:0]
R/W
X
Programmable delay Power Good or level shifter for GPO4 pin.
Measured from the moment when all rails grouped to this pin
reach their regulation range. All values have ±10% variation.
000: 0 ms
001: 5.0 ms
010: 10 ms
011: 15 ms
100: 20 ms
101: 50 ms
110: 75 ms
111: 100 ms
—: Bits not used. If GPO4 is controlled by I2C rather than PG,
these bits have no impact. Default is set to 0b.
1:0
GPO1_PG_DELAY[1:0]
R/W
X
Programmable delay Power Good or level shifter for GPO1 pin.
Measured from the moment when all rails grouped to this pin
reach their regulation range. All values have ±10% variation.
00: 0 ms
01: 5.0 ms
10: 10 ms
11: 15 ms
—: Bits not used. If GPO1 is controlled by I2C rather than PG,
these bits have no impact. Default is set to 0b.
Detailed Description
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5.11.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
Figure 5-53. SWVTT_DIS Register
Bit
Bit Name
TPS65086100
Access
7
SWB2_LDO
A1_DIS
0
R/W
6
5
4
3
2
1
0
SWB1_DIS
SWA1_DIS
VTT_DIS
Reserved
Reserved
Reserved
Reserved
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Table 5-41. SWVTT_DIS Register Descriptions
Bit
Field
Type
Reset
Description
7
SWB2_LDOA1_DIS
R/W
X
SWB2 or LDOA1 Disable Bit. Writing 0 to this bit forces
SWB2 or LDOA1 to turn off regardless of any control input
pin (CTL1–CTL6) status. OTP setting selects either SWB2
or LDOA1.
0: Disable.
1: Enable.
SWB2 for: OTP Dependent
LDOA1 for: OTP Dependent
6
SWB1_DIS
R/W
X
SWB1 Disable Bit. Writing 0 to this bit forces SWB1 to
turn off regardless of any control input pin (CTL1–CTL6)
status.
0: Disable.
1: Enable.
5
SWA1_DIS
R/W
X
SWA1 Disable Bit. Writing 0 to this bit forces SWA1 to
turn off regardless of any control input pin (CTL1–CTL6)
status.
0: Disable.
1: Enable.
4
VTT_DIS
R/W
X
VTT Disable Bit. Writing 0 to this bit forces VTT to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
3:0
Reserved
R/W
0000
Reserved bits. Always write to 0000.
62
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5.11.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
Figure 5-54. I2C_RAIL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2_EN
0
R/W
6
SWA1_EN
0
R/W
5
BUCK6_EN
0
R/W
4
BUCK5_EN
0
R/W
3
BUCK4_EN
0
R/W
2
BUCK3_EN
0
R/W
1
BUCK2_EN
0
R/W
0
BUCK1_EN
0
R/W
Table 5-42. I2C_RAIL_EN1 Register Descriptions
Bit
Field
Type
Reset
Description
7
LDOA2_EN
R/W
X
LDOA2 I2C Enable
0: LDOA2 is enabled or disabled by one of the control input pins
or internal PG signal.
1: LDOA2 is forced on unless LDOA2_DIS = 0b.
6
SWA1_EN
R/W
X
SWA1 I2C Enable
0: SWA1 is enabled or disabled by one of the control input pins
or internal PG signal.
1: SWA1 is forced on unless SWA1_DIS = 0b.
5
BUCK6_EN
R/W
X
BUCK6 I2C Enable
0: BUCK6 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK6 is forced on unless BUCK6_DIS = 0b.
4
BUCK5_EN
R/W
X
BUCK5 I2C Enable
0: BUCK5 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK5 is forced on unless BUCK5_DIS = 0b.
3
BUCK4_EN
R/W
X
BUCK4 I2C Enable
0: BUCK4 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK4 is forced on unless BUCK4_DIS = 0b.
2
BUCK3_EN
R/W
X
BUCK3 I2C Enable
0: BUCK3 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK3 is forced on unless BUCK3_DIS = 0b.
1
BUCK2_EN
R/W
X
BUCK2 I2C Enable
0: BUCK2 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK2 is forced on unless BUCK2_DIS = 0b.
0
BUCK1_EN
R/W
X
BUCK1 I2C Enable
0: BUCK1 is enabled or disabled by one of the control input pins
or internal PG signal.
1: BUCK1 is forced on unless BUCK1_DIS = 0b.
Detailed Description
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5.11.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register
(offset = A1h) [reset = X]
Figure 5-55. I2C_RAIL_EN2/GPOCTRL Register
Bit
Bit Name
TPS65086100
Access
7
6
5
4
3
GPO4_LVL
GPO3_LVL
GPO2_LVL
GPO1_LVL
VTT_EN
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
2
SWB2_LDO
A1_EN
0
R/W
1
0
SWB1_EN
LDOA3_EN
0
R/W
0
R/W
Table 5-43. I2C_RAIL_EN2/GPOCTRL Register Descriptions
Bit
Field
Type
Reset
Description
7
GPO4_LVL
R/W
X
The field is to set GPO4 pin output if the pin is factoryconfigured as an I2C controlled open-drain general-purpose
output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
—: Bit not used in this version; GPO4 is controlled by GPO4 PG
tree. Default is set to 0b.
6
GPO3_LVL
R/W
X
The field is to set GPO3 pin output if the pin is factoryconfigured as either an I2C controlled open-drain or a push-pull
general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
—: Bit not used in this version; GPO3 is controlled by GPO3 PG
tree. Default is set to 0b.
5
GPO2_LVL
R/W
X
The field is to set GPO2 pin output if the pin is factoryconfigured as either an I2C controlled open-drain or a push-pull
general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
—: Bit not used in this version; GPO2 is controlled by GPO2 PG
tree. Default is set to 0b.
4
GPO1_LVL
R/W
X
The field is to set GPO1 pin output if the pin is factoryconfigured as either an I2C controlled open-drain or a push-pull
general-purpose output.
0: The pin is driven to logic low.
1: The pin is driven to logic high.
—: Bit not used in this version; GPO1 is controlled by GPO1 PG
tree. Default is set to 0b.
3
VTT_EN
R/W
X
VTT LDO I2C Enable
0: VTT LDO is enabled or disabled by one of the control input
pins or internal PG signals.
1: VTT LDO is forced on unless VTT_DIS = 0b.
2
SWB2_LDOA1_EN
R/W
X
SWB2 or LDOA1 I2C Enable. Internal setting selects either
SWB2 or LDOA1.
0: SWB2 or LDOA1 is enabled or disabled by one of the control
input pins or internal PG signals.
1: SWB2 or LDOA1 is forced on unless SWB2_LDOA1_DIS =
0b.
SWB2 for: OTP Dependent
LDOA1 for: OTP Dependent
1
SWB1_EN
R/W
X
SWB1 I2C Enable
0: SWB1 is enabled or disabled by one of the control input pins
or internal PG signals.
1: SWB1 is forced on unless SWB1_DIS = 0b.
0
LDOA3_EN
R/W
X
LDOA3 I2C Enable
0: LDOA3 is enabled or disabled by one of the control input pins
or internal PG signals.
1: LDOA3 is forced on unless LDOA3_DIS = 0b.
64
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5.11.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
Figure 5-56. PWR_FAULT_MASK1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2_
FLTmsK
0
R/W
6
SWA1_
FLTmsK
0
R/W
5
BUCK6_
FLTmsK
0
R/W
4
BUCK5_
FLTmsK
0
R/W
3
BUCK4_
FLTmsK
0
R/W
2
BUCK3_
FLTmsK
0
R/W
1
BUCK2_
FLTmsK
0
R/W
0
BUCK1_
FLTmsK
0
R/W
Table 5-44. PWR_FAULT_MASK1 Register Descriptions
Bit
Field
Type
Reset
Description
7
LDOA2_FLTmsK
R/W
X
LDOA2 Power Fault Mask. When masked, power fault from
LDOA2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
6
SWA1_FLTmsK
R/W
X
SWA1 Power Fault Mask. When masked, power fault from SWA1
does not cause PMIC to shutdown.
0: Not Masked
1: Masked
5
BUCK6_FLTmsK
R/W
X
BUCK6 Power Fault Mask. When masked, power fault from
BUCK6 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
4
BUCK5_FLTmsK
R/W
X
BUCK5 Power Fault Mask. When masked, power fault from
BUCK5 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
3
BUCK4_FLTmsK
R/W
X
BUCK4 Power Fault Mask. When masked, power fault from
BUCK4 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
2
BUCK3_FLTmsK
R/W
X
BUCK3 Power Fault Mask. When masked, power fault from
BUCK3 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
1
BUCK2_FLTmsK
R/W
X
BUCK2 Power Fault Mask. When masked, power fault from
BUCK2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
0
BUCK1_FLTmsK
R/W
X
BUCK1 Power Fault Mask. When masked, power fault from
BUCK1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
Detailed Description
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5.11.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
Figure 5-57. PWR_FAULT_MASK2 Register
Bit
Bit Name
7
6
5
RESERVED
RESERVED
RESERVED
0
R
0
R/W
0
R/W
TPS65086100
Access
4
LDOA1_
FLTmsK
0
R/W
3
VTT_
FLTmsK
0
R/W
2
SWB2_
FLTmsK
0
R/W
1
SWB1_
FLTmsK
0
R/W
0
LDOA3_
FLTmsK
0
R/W
Table 5-45. PWR_FAULT_MASK2 Register Descriptions
Bit
Field
Type
Reset
Description
6
RESERVED
R/W
0
Reserved bit. Always write to 0b.
5
RESERVED
R/W
1
Reserved bit. Always write to 1b.
4
LDOA1_FLTmsK
R/W
X
LDOA1 Power Fault Mask. When masked, power fault from
LDOA1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
3
VTT_FLTmsK
R/W
X
VTT LDO Power Fault Mask. When masked, power fault from
VTT LDO does not cause PMIC to shutdown.
0: Not Masked
1: Masked
2
SWB2_FLTmsK
R/W
X
SWB2 Power Fault Mask. When masked, power fault from
SWB2 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
1
SWB1_FLTmsK
R/W
X
SWB1 Power Fault Mask. When masked, power fault from
SWB1 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
0
LDOA3_FLTmsK
R/W
X
LDOA3 Power Fault Mask. When masked, power fault from
LDOA3 does not cause PMIC to shutdown.
0: Not Masked
1: Masked
66
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5.11.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
Figure 5-58. GPO1PG_CTRL1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2
_msK
0
R/W
6
SWA1
_msK
0
R/W
5
BUCK6
_msK
0
R/W
4
BUCK5
_msK
0
R/W
3
BUCK4
_msK
0
R/W
2
BUCK3
_msK
0
R/W
1
BUCK2
_msK
0
R/W
0
BUCK1
_msK
0
R/W
Table 5-46. GPO1PG_CTRL1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_msK
R/W
X
0: LDOA2 PG is part of Power Good tree of GPO1 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
6
SWA1_msK
R/W
X
0: SWA1 PG is part of Power Good tree of GPO1 pin.
1: SWA1 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
5
BUCK6_msK
R/W
X
0: BUCK6 PG is part of Power Good tree of GPO1 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
4
BUCK5_msK
R/W
X
0: BUCK5 PG is part of Power Good tree of GPO1 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
3
BUCK4_msK
R/W
X
0: BUCK4 PG is part of Power Good tree of GPO1 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
2
BUCK3_msK
R/W
X
0: BUCK3 PG is part of Power Good tree of GPO1 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
1
BUCK2_msK
R/W
X
0: BUCK2 PG is part of Power Good tree of GPO1 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
0
BUCK1_msK
R/W
X
0: BUCK1 PG is part of Power Good tree of GPO1 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
Detailed Description
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5.11.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
Figure 5-59. GPO1PG_CTRL2 Register
Bit
Bit Name
7
6
5
4
3
CTL5_msK
CTL4_msK
CTL2_msK
CTL1_msK
VTT_msK
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
TPS65086100
Access
2
SWB2_LDO
A1_msK
0
R/W
1
0
SWB1_msK
LDOA3_msK
0
R/W
0
R/W
Table 5-47. GPO1PG_CTRL2 Register Descriptions
Bit
Field
Type Reset
Description
7
CTL5_msK
R/W
X
0: CTL5 pin status is part of Power Good tree of GPO1 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO1 pin
and is ignored.
6
CTL4_msK
R/W
X
0: CTL4 pin status is part of Power Good tree of GPO1 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO1 pin
and is ignored.
5
CTL2_msK
R/W
X
0: CTL2 pin status is part of Power Good tree of GPO1 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO1 pin
and is ignored.
4
CTL1_msK
R/W
X
0: CTL1 pin status is part of Power Good tree of GPO1 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO1 pin
and is ignored.
3
VTT_msK
R/W
X
0: VTT LDO PG is part of Power Good tree of GPO1 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO1 pin
and is ignored.
2
SWB2_LDOA1_msK
R/W
X
0: SWB2_LDOA1 PG is part of Power Good tree of GPO1 pin.
1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO1
pin and is ignored.
SWB2 for: OTP Dependent
LDOA1 for:OTP Dependent
1
SWB1_msK
R/W
X
0: SWB1 PG is part of Power Good tree of GPO1 pin.
1: SWB1 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
0
LDOA3_msK
R/W
X
0: LDOA3 PG is part of Power Good tree of GPO1 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO1 pin and
is ignored.
68
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5.11.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
Figure 5-60. GPO4PG_CTRL1 Register
Bit
7
Bit Name
LDOA2_msK
TPS65086100
Access
0
R/W
6
SWA1
_msK
0
R/W
5
BUCK6
_msK
0
R/W
4
BUCK5
_msK
0
R/W
3
BUCK4
_msK
0
R/W
2
BUCK3
_msK
0
R/W
1
BUCK2
_msK
0
R/W
0
BUCK1
_msK
0
R/W
Table 5-48. GPO4PG_CTRL1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_msK
R/W
X
0: LDOA2 PG is part of Power Good tree of GPO4 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
6
SWA1_msK
R/W
X
0: SWA1 PG is part of Power Good tree of GPO4 pin.
1: SWA1 PG is NOT part of Power Good tree of GPO4 pin and
is ignored.
5
BUCK6_msK
R/W
X
0: BUCK6 PG is part of Power Good tree of GPO4 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
4
BUCK5_msK
R/W
X
0: BUCK5 PG is part of Power Good tree of GPO4 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
3
BUCK4_msK
R/W
X
0: BUCK4 PG is part of Power Good tree of GPO4 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
2
BUCK3_msK
R/W
X
0: BUCK3 PG is part of Power Good tree of GPO4 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
1
BUCK2_msK
R/W
X
0: BUCK2 PG is part of Power Good tree of GPO4 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
0
BUCK1_msK
R/W
X
0: BUCK1 PG is part of Power Good tree of GPO4 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
Detailed Description
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5.11.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
Figure 5-61. GPO4PG_CTRL2 Register
Bit
Bit Name
7
6
5
4
3
CTL5_msK
CTL4_msK
CTL2_msK
CTL1_msK
VTT_msK
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
TPS65086100
Access
2
SWB2_LDO
A1_msK
0
R/W
1
0
SWB1_msK
LDOA3_msK
0
R/W
0
R/W
Table 5-49. GPO4PG_CTRL2 Register Descriptionsr
Bit
Field
Type Reset
Description
7
CTL5_msK
R/W
X
0: CTL5 pin status is part of Power Good tree of GPO4 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO4 pin
and is ignored.
6
CTL4_msK
R/W
X
0: CTL4 pin status is part of Power Good tree of GPO4 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO4 pin
and is ignored.
5
CTL2_msK
R/W
X
0: CTL2 pin status is part of Power Good tree of GPO4 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO4 pin
and is ignored.
4
CTL1_msK
R/W
X
0: CTL1 pin status is part of Power Good tree of GPO4 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO4 pin
and is ignored.
3
VTT_msK
R/W
X
0: VTT LDO PG is part of Power Good tree of GPO4 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO4 pin
and is ignored.
2
SWB2_LDOA1_msK
R/W
X
0: SWB2_LDOA1 PG is part of Power Good tree of GPO4 pin.
1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO4
pin and is ignored.
SWB2 for: OTP Dependent
LDOA1 for: OTP Dependent
1
SWB1_msK
R/W
X
0: SWB1 PG is part of Power Good tree of GPO4 pin.
1: SWB1 PG is NOT part of Power Good tree of GPO4 pin and
is ignored.
0
LDOA3_msK
R/W
X
0: LDOA3 PG is part of Power Good tree of GPO4 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO4 pin and
is ignored.
70
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5.11.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
Figure 5-62. GPO2PG_CTRL1 Register
Bit
7
Bit Name
LDOA2_msK
TPS65086100
Access
0
R/W
6
SWA1
_msK
0
R/W
5
BUCK6
_msK
0
R/W
4
BUCK5
_msK
0
R/W
3
BUCK4
_msK
0
R/W
2
BUCK3
_msK
0
R/W
1
BUCK2
_msK
0
R/W
0
BUCK1
_msK
0
R/W
Table 5-50. GPO2PG_CTRL1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_msK
R/W
X
0: LDOA2 PG is part of Power Good tree of GPO2 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
6
SWA1_msK
R/W
X
0: SWA1 PG is part of Power Good tree of GPO2 pin.
1: SWA1 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
5
BUCK6_msK
R/W
X
0: BUCK6 PG is part of Power Good tree of GPO2 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
4
BUCK5_msK
R/W
X
0: BUCK5 PG is part of Power Good tree of GPO2 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
3
BUCK4_msK
R/W
X
0: BUCK4 PG is part of Power Good tree of GPO2 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
2
BUCK3_msK
R/W
X
0: BUCK3 PG is part of Power Good tree of GPO2 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
1
BUCK2_msK
R/W
X
0: BUCK2 PG is part of Power Good tree of GPO2 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
0
BUCK1_msK
R/W
X
0: BUCK1 PG is part of Power Good tree of GPO2 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
Detailed Description
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5.11.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
Figure 5-63. GPO2PG_CTRL2 Register
Bit
Bit Name
7
6
5
4
3
CTL5_msK
CTL4_msK
CTL2_msK
CTL1_msK
VTT_msK
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
TPS65086100
Access
2
SWB2_LDO
A1_msK
0
R/W
1
SWB1_msK
0
R/W
0
LDOA3_
msK
0
R/W
Table 5-51. GPO2PG_CTRL2 Register Descriptions
Bit
Field
Type Reset
Description
7
CTL5_msK
R/W
X
0: CTL5 pin status is part of Power Good tree of GPO2 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO2
pin and is ignored.
6
CTL4_msK
R/W
X
0: CTL4 pin status is part of Power Good tree of GPO2 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO2
pin and is ignored.
5
CTL2_msK
R/W
X
0: CTL2 pin status is part of Power Good tree of GPO2 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO2
pin and is ignored.
4
CTL1_msK
R/W
X
0: CTL1 pin status is part of Power Good tree of GPO2 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO2
pin and is ignored.
3
VTT_msK
R/W
X
0: VTT LDO PG is part of Power Good tree of GPO2 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
2
SWB2_LDOA1_msK
R/W
X
0: SWB2_LDOA1 PG is part of Power Good tree of GPO2 pin.
1: SWB2_LDOA1 PG is NOT part of Power Good tree of
GPO2 pin and is ignored.
SWB2 for: OTP Dependent
LDOA1 for: OTP Dependent
1
SWB1_msK
R/W
X
0: SWB1 PG is part of Power Good tree of GPO2 pin.
1: SWB1 PG is NOT part of Power Good tree of GPO2 pin and
is ignored.
0
LDOA3_msK
R/W
X
0: LDOA3 PG is part of Power Good tree of GPO2 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO2 pin
and is ignored.
72
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5.11.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
Figure 5-64. GPO3PG_CTRL1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2
_msK
0
R/W
6
SWA1
_msK
0
R/W
5
BUCK6
_msK
0
R/W
4
BUCK5
_msK
0
R/W
3
BUCK4
_msK
0
R/W
2
BUCK3
_msK
0
R/W
1
BUCK2
_msK
0
R/W
0
BUCK1
_msK
0
R/W
Table 5-52. GPO3PG_CTRL1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_msK
R/W
X
0: LDOA2 PG is part of Power Good tree of GPO3 pin.
1: LDOA2 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
6
SWA1_msK
R/W
X
0: SWA1 PG is part of Power Good tree of GPO3 pin.
1: SWA1 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
5
BUCK6_msK
R/W
X
0: BUCK6 PG is part of Power Good tree of GPO3 pin.
1: BUCK6 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
4
BUCK5_msK
R/W
X
0: BUCK5 PG is part of Power Good tree of GPO3 pin.
1: BUCK5 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
3
BUCK4_msK
R/W
X
0: BUCK4 PG is part of Power Good tree of GPO3 pin.
1: BUCK4 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
2
BUCK3_msK
R/W
X
0: BUCK3 PG is part of Power Good tree of GPO3 pin.
1: BUCK3 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
1
BUCK2_msK
R/W
X
0: BUCK2 PG is part of Power Good tree of GPO3 pin.
1: BUCK2 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
0
BUCK1_msK
R/W
X
0: BUCK1 PG is part of Power Good tree of GPO3 pin.
1: BUCK1 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
Detailed Description
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5.11.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
Figure 5-65. GPO3PG_CTRL2 Register
Bit
Bit Name
7
6
5
4
3
CTL5_msK
CTL4_msK
CTL2_msK
CTL1_msK
VTT_msK
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
TPS65086100
Access
2
SWB2_LDO
A1_msK
0
R/W
1
0
SWB1_msK
LDOA3_msK
0
R/W
0
R/W
Table 5-53. GPO3PG_CTRL2 Register Descriptions
Bit
Field
Type Reset
Description
7
CTL5_msK
R/W
X
0: CTL5 pin status is part of Power Good tree of GPO3 pin.
1: CTL5 pin status is NOT part of Power Good tree of GPO3 pin
and is ignored.
6
CTL4_msK
R/W
X
0: CTL4 pin status is part of Power Good tree of GPO3 pin.
1: CTL4 pin status is NOT part of Power Good tree of GPO3 pin
and is ignored.
5
CTL2_msK
R/W
X
0: CTL2 pin status is part of Power Good tree of GPO3 pin.
1: CTL2 pin status is NOT part of Power Good tree of GPO3 pin
and is ignored.
4
CTL1_msK
R/W
X
0: CTL1 pin status is part of Power Good tree of GPO3 pin.
1: CTL1 pin status is NOT part of Power Good tree of GPO3 pin
and is ignored.
3
VTT_msK
R/W
X
0: VTT LDO PG is part of Power Good tree of GPO3 pin.
1: VTT LDO PG is NOT part of Power Good tree of GPO3 pin
and is ignored.
2
SWB2_LDOA1_msK
R/W
X
0: SWB2_LDOA1 PG is part of Power Good tree of GPO3 pin.
1: SWB2_LDOA1 PG is NOT part of Power Good tree of GPO3
pin and is ignored.
SWB2 for: OTP Dependent
LDOA1 for: OTP Dependent
1
SWB1_msK
R/W
X
0: SWB1 PG is part of Power Good tree of GPO3 pin.
1: SWB1 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
0
LDOA3_msK
R/W
X
0: LDOA3 PG is part of Power Good tree of GPO3 pin.
1: LDOA3 PG is NOT part of Power Good tree of GPO3 pin and
is ignored.
74
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5.11.48 MISCSYSPG Register (offset = ACh) [reset = X]
Figure 5-66. MISCSYSPG Register
Bit
Bit Name
TPS65086100
Access
7
GPO1_
CTL3_msK
0
R/W
6
GPO1_
CTL6_msK
0
R/W
5
GPO4_
CTL3_msK
0
R/W
4
GPO4_
CTL6_msK
0
R/W
3
GPO2_
CTL3_msK
0
R/W
2
GPO2_
CTL6_msK
0
R/W
1
GPO3_
CTL3_msK
0
R/W
0
GPO3_
CTL6_msK
0
R/W
Table 5-54. MISCSYSPG Register Descriptions
Bit
Field
Type Reset
Description
7
GPO1_CTL3_msK
R/W
X
0: CTL3 pin status is part of Power Good tree of GPO1 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO1 pin.
6
GPO1_CTL6_msK
R/W
X
0: CTL6 pin status is part of Power Good tree of GPO1 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO1 pin.
5
GPO4_CTL3_msK
R/W
X
0: CTL3 pin status is part of Power Good tree of GPO4 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO4 pin.
4
GPO4_CTL6_msK
R/W
X
0: CTL6 pin status is part of Power Good tree of GPO4 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO4 pin.
3
GPO2_CTL3_msK
R/W
X
0: CTL3 pin status is part of Power Good tree of GPO2 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO2 pin.
2
GPO2_CTL6_msK
R/W
X
0: CTL6 pin status is part of Power Good tree of GPO2 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO2 pin.
1
GPO3_CTL3_msK
R/W
X
0: CTL3 pin status is part of Power Good tree of GPO3 pin.
1: CTL3 pin status is NOT part of Power Good tree of GPO3pin.
0
GPO3_CTL6_msK
R/W
X
0: CTL6 pin status is part of Power Good tree of GPO3 pin.
1: CTL6 pin status is NOT part of Power Good tree of GPO3 pin.
Detailed Description
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5.11.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
Figure 5-67. VTT_DISCH_CTRL Register
Bit
Bit Name
7
6
5
RESERVED
RESERVED
RESERVED
0
R/W
1
R/W
0
R/W
TPS65086100
Access
4
VTT_
DISCHG
0
R/W
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
0
R/W
0
R/W
0
R/W
0
R/W
Table 5-55. VTT_DISCH_CTRL Register Descriptions
Bit
Field
Type Reset
Description
7:5
RESERVED
R/W
X
Reserved bits. Always write to match OTP settings.
4
VTT_DISCHG
R/W
X
0: no discharge
1: 100 Ω
3:0
RESERVED
R/W
X
Reserved bits. Always write to match OTP settings.
5.11.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
Figure 5-68. LDOA1_SWB2_CTRL Register
Bit
Bit Name
TPS65086100
Access
7
LDOA1_
DISCHG[1]
0
R/W
6
LDOA1_
DISCHG[0]
0
R/W
5
LDOA1_SWB2_
SDWN_CONFIG
0
R/W
4
LDOA1_
VID[3]
0
R/W
3
LDOA1_
VID[2]
0
R/W
2
LDOA1_
VID[1]
0
R/W
1
LDOA1_
VID[0]
0
R/W
0
LDOA1_
SWB2_EN
0
R/W
Table 5-56. LDOA1_SWB2_CTRL Register Descriptions
Bit
Field
Type Reset
Description
7:6
LDOA1_DISCHG[1:0]
R/W
X
LDOA1 discharge resistance
00: no discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
5
LDOA1_SWB2_SDWN_CON R/W
FIG
X
Control for Disabling LDOA1 or SWB2 (OTP dependent) during
Emergency Shutdown. When LDOA1 is used in sequence and
SWB1 and SWB2 are not merged, this will control SWB2.
0: LDOA1 or SWB2 will turn off during Emergency Shutdown for
factory-programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.
1: LDOA1 or SWB2 is controlled by LDOA1_SWB2_EN bit only.
LDOA1 for: OTP Dependent
SWB2 for: OTP Dependent
Unused for: OTP Dependent
4:1
LDOA1_VID[3:0]
R/W
X
This field sets the LDOA1 regulator output regulation voltage.
See Table 5-4 for VOUT options.
0
LDOA1_SWB2_EN
R/W
X
LDOA1 or SWB2 Enable Bit.
0: Disable.
1: Enable.
LDOA1 for: OTP Dependent
SWB2 for: OTP Dependent
Unused for: OTP Dependent
76
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5.11.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
Figure 5-69. PG_STATUS1 Register
Bit
Bit Name
Access
7
LDOA2_
PGOOD
0
R
6
SWA1_
PGOOD
0
R
5
BUCK6_
PGOOD
0
R
4
BUCK5_
PGOOD
0
R
3
BUCK4_
PGOOD
0
R
2
BUCK3_
PGOOD
0
R
1
BUCK2_
PGOOD
0
R
0
BUCK1_
PGOOD
0
R
Table 5-57. PG_STATUS1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_PGOOD
R
0
LDOA2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
6
SWA1_PGOOD
R
0
SWA1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
5
BUCK6_PGOOD
R
0
BUCK6 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4
BUCK5_PGOOD
R
0
BUCK5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3
BUCK4_PGOOD
R
0
BUCK4 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
2
BUCK3_PGOOD
R
0
BUCK3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
1
BUCK2_PGOOD
R
0
BUCK2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0
BUCK1_PGOOD
R
0
BUCK1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
Detailed Description
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5.11.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
Figure 5-70. PG_STATUS2 Register
Bit
Bit Name
7
6
RESERVED
RESERVED
0
R
0
R
Access
5
LDO5
_PGOOD
0
R
4
LDOA1
_PGOOD
0
R
3
VTT
_PGOOD
0
R
2
SWB2
_PGOOD
0
R
1
SWB1
_PGOOD
0
R
0
LDOA3
_PGOOD
0
R
Table 5-58. PG_STATUS2 Register Descriptions
Bit
Field
Type Reset
Description
5
LDO5_PGOOD
R
0
LDO5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4
LDOA1_PGOOD
R
0
LDOA1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3
VTT_PGOOD
R
0
VTT LDO Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
2
SWB2_PGOOD
R
0
SWB2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
1
SWB1_PGOOD
R
0
SWB1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0
LDOA3_PGOOD
R
0
LDOA3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
78
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5.11.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset =
0000 0000]
Figure 5-71. PWR_FAULT_STATUS1 Register
Bit
Bit Name
Access
7
LDOA2_
PWRFLT
0
R/W
6
SWA1_
PWRFLT
0
R/W
5
BUCK6_
PWRFLT
0
R/W
4
BUCK5_
PWRFLT
0
R/W
3
BUCK4_
PWRFLT
0
R/W
2
BUCK3_
PWRFLT
0
R/W
1
BUCK2_
PWRFLT
0
R/W
0
BUCK1_
PWRFLT
0
R/W
Table 5-59. PWR_FAULT_STATUS1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_PWRFLT
R
0
This fields indicates that LDOA2 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
6
SWA1_PWRFLT
R
0
This fields indicates that SWA1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
5
BUCK6_PWRFLT
R
0
This fields indicates that BUCK6 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
4
BUCK5_PWRFLT
R
0
This fields indicates that BUCK5 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3
BUCK4_PWRFLT
R
0
This fields indicates that BUCK4 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
2
BUCK3_PWRFLT
R
0
This fields indicates that BUCK3 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
1
BUCK2_PWRFLT
R
0
This fields indicates that BUCK2 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0
BUCK1_PWRFLT
R
0
This fields indicates that BUCK1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
Detailed Description
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5.11.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset =
0000 0000]
Figure 5-72. PWR_FAULT_STATUS2 Register
Bit
Bit Name
7
6
5
RESERVED
RESERVED
RESERVED
0
R
0
R
0
R/W
Access
4
LDOA1_
PWRFLT
0
R/W
3
VTT_
PWRFLT
0
R/W
2
SWB2_
_PWRFLT
0
R/W
1
SWB1_
PWRFLT
0
R/W
0
LDOA3_
PWRFLT
0
R/W
Table 5-60. PWR_FAULT_STATUS2 Register Descriptions
Bit
Field
Type Reset
Description
4
LDOA1_PWRFLT
R/W
0
This fields indicates that LDOA1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3
VTT_PWRFLT
R/W
0
This fields indicates that VTT LDO has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
2
SWB2_PWRFLT
R/W
0
This fields indicates that SWB2 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
1
SWB1_PWRFLT
R/W
0
This fields indicates that SWB1 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0
LDOA3_PWRFLT
R/W
0
This fields indicates that LDOA3 has lost its regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
80
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5.11.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL
temperature threshold (TCRIT). There are 5 temperature sensors across the die.
Figure 5-73. TEMPCRIT Register
Bit
Bit Name
Access
7
6
5
4
3
2
1
RESERVED
RESERVED
RESERVED
DIE_CRIT
VTT_CRIT
TOP-RIGHT
_CRIT
TOP-LEFT
_CRIT
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
BOTTOMRIGHT
_CRIT
0
R/W
Table 5-61. TEMPCRIT Register Descriptions
Bit
Field
Type Reset
Description
4
DIE_CRIT
R/W
0
Temperature of rest of die has exceeded TCRIT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
3
VTT_CRIT
R/W
0
Temperature of VTT LDO has exceeded TCRIT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
2
TOP-RIGHT_CRIT
R/W
0
Temperature of die Top-Right has exceeded TCRIT. Top-Right corner of die
from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1
TOP-LEFT_CRIT
R/W
0
Temperature of die Top-Left has exceeded TCRIT.Top-Left corner of die from
top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0
BOTTOM-RIGHT_CRIT
R/W
0
Temperature of die Bottom-Right has exceeded TCRIT. Bottom-Right corner of
die from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
Detailed Description
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5.11.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature
threshold (THOT). There are 5 temperature sensors across the die.
Figure 5-74. TEMPHOT Register
Bit
Bit Name
Access
7
6
5
4
3
2
1
RESERVED
RESERVED
RESERVED
DIE_HOT
VTT_HOT
TOP-RIGHT
_HOT
TOP-LEFT
_HOT
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
BOTTOMRIGHT
_HOT
0
R/W
Table 5-62. TEMPHOT Register Descriptions
Bit
Field
Type Reset
Description
4
DIE_HOT
R/W
0
Temperature of rest of die has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
3
VTT_HOT
R/W
0
Temperature of VTT LDO has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
2
TOP-RIGHT_HOT
R/W
0
Temperature of Top-Right has exceeded THOT. Top-Right corner of die from top
view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1
TOP-LEFT_HOT
R/W
0
Temperature of Top-Left has exceeded THOT. Top-Left corner of die from top
view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0
BOTTOM-RIGHT_HOT
R/W
0
Temperature of Bottom-Right has exceeded THOT. Bottom-Right corner of die
from top view given pin1 is in Top-Left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
82
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5.11.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
Asserted when overcurrent condition is detected from a LSD FET.
Figure 5-75. OC_STATUS Register
Bit
Bit Name
7
6
5
4
3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
R
0
R
0
R
0
R
0
R
Access
2
BUCK6
_OC
0
R/W
1
BUCK2
_OC
0
R/W
0
BUCK1
_OC
0
R/W
Table 5-63. OC_STATUS Register Descriptions
Bit
Field
Type Reset
Description
2
BUCK6_OC
R/W
0
BUCK6 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1
BUCK2_OC
R/W
0
BUCK2 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0
BUCK1_OC
R/W
0
BUCK1 LSD FET overcurrent has been detected.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
5.12 I2C Address: 0x38 Register Maps
5.12.1 Register Map Summary
This section describes the registers that can be accessed using I2C address 0x38. These registers can
only be accessed by putting the device into programming mode. See the TPS65086100 OTP Memory
Programming Guide for more information on putting the device into programming mode. It is
recommended to use the OTP generator tool to make changes to these OTP settings. Do not attempt to
write a RESERVED R/W bit to the opposite value. When the reset value of a bit register is 0bX, it means
the bit value is coming from the OTP memory.
NOTE
There are additional registers not shown that are set by the OTP generator tool.
Table 5-64.
Address
Name
Short Description
02h
OTP_CTRL1
OTP control register for
programming.
03h
OTP_CTRL2
OTP control register for selecting
OTP bank.
07h
BUCK1_CTRL_EN1
BUCK1 enable control register 1.
08h
BUCK1_CTRL_EN2
BUCK1 enable control register 2.
09h
BUCK1_CTRL_EN3
BUCK1 enable control register 3.
0Ah
BUCK2_CTRL_EN1
BUCK2 enable control register 1.
0Bh
BUCK2_CTRL_EN2
BUCK2 enable control register 2.
0Ch
BUCK2_CTRL_EN3
BUCK2 enable control register 3.
0Dh
BUCK3_CTRL_EN1
BUCK3 enable control register 1.
0Eh
BUCK3_CTRL_EN2
BUCK3 enable control register 2.
0Fh
BUCK3_CTRL_EN3
BUCK3 enable control register 3.
10h
BUCK4_CTRL_EN1
BUCK4 enable control register 1.
11h
BUCK4_CTRL_EN2
BUCK4 enable control register 2.
Detailed Description
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Table 5-64. (continued)
84
Address
Name
Short Description
12h
BUCK4_CTRL_EN3
BUCK4 enable control register 3.
13h
BUCK5_CTRL_EN1
BUCK5 enable control register 1.
14h
BUCK5_CTRL_EN2
BUCK5 enable control register 2.
15h
BUCK5_CTRL_EN3
BUCK5 enable control register 3.
16h
BUCK6_CTRL_EN1
BUCK6 enable control register 1.
17h
BUCK6_CTRL_EN2
BUCK6 enable control register 2.
18h
BUCK6_CTRL_EN3
BUCK6 enable control register 3.
19h
SWA1_CTRL_EN1
SWA1 enable control register 1.
1Ah
SWA1_CTRL_EN2
SWA1 enable control register 2.
1Bh
SWA1_CTRL_EN3
SWA1 enable control register 3.
1Ch
LDOA2_CTRL_EN1
LDOA2 enable control register 1.
1Dh
LDOA2_CTRL_EN2
LDOA2 enable control register 2.
1Eh
LDOA2_CTRL_EN3
LDOA2 enable control register 3.
1Fh
LDOA3_CTRL_EN1
LDOA3 enable control register 1.
20h
LDOA3_CTRL_EN2
LDOA3 enable control register 2.
21h
LDOA3_CTRL_EN3
LDOA3 enable control register 3.
22h
SWB1_CTRL_EN1
SWB1 enable control register 1.
23h
SWB1_CTRL_EN2
SWB1 enable control register 2.
24h
SWB1_CTRL_EN3
SWB1 enable control register 3.
25h
SWB2_LDOA1_CTRL_EN1
SWB2 or LDOA1 enable control
register 1.
26h
SWB2_LDOA1_CTRL_EN2
SWB2 or LDOA1 enable control
register 2.
27h
SWB2_LDOA1_CTRL_EN3
SWB2 or LDOA1 enable control
register 3.
29h
SLP_PIN
Sleep pin select for BUCK1-6,
LDOA2, and LDOA3.
2Ah
OUTPUT_MODE
GPO output mode control.
5Fh
I2C_SLAVE_ADDR
I2C address control
Detailed Description
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5.12.2 OTP_CTRL1 (offset = 02h) [reset = 0010 0000]
Figure 5-76. OTP_CTRL1 Register
Bit
Bit Name
TPS65086100
Access
7
PROGRAMM
ING_STATE
0
R/W
6
5
4
3
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
PROGRAM_
OTP
0
R/W
0
RESERVED
0
R/W
Table 5-65. OTP_CTRL1 Register Descriptions
Bit
Field
Type Reset
Description
7
PROGRAMMING_STATE
R/W
0
0: Programming mode not enabled (unless 7 V is applied to CTL4 pin).
1: Programming mode enabled, regardless of CTL4 pin voltage.
1
PROGRAM_OTP
R/W
0
Burns current register settings into selected OTP bank. Self clearing.
0: Not asserted.
1: Asserted.
Detailed Description
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5.12.3 OTP_CTRL2 (offset = 03h) [reset = X]
Figure 5-77. OTP_CTRL2 Register
Bit
Bit Name
7
6
5
4
3
2
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
TPS65086100
Access
0
OTP_
BANK
0
R/W
Table 5-66. OTP_CTRL2 Register Descriptions
Bit
Field
Type Reset
Description
0
OTP_BANK
R/W
Determines which OTP bank to program into when PROGRAM_OTP is
asserted.
0: Bank 0.
1: Bank 1.
86
X
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5.12.4 BUCK1_CTRL_EN1 (offset = 07h) [reset = X]
Figure 5-78. BUCK1_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK1_
LDOA3_
PGM
0
R/W
6
BUCK1_
LDOA2_
PGM
0
R/W
5
BUCK1_
SWA1_PGM
0
R/W
4
BUCK1_
BUCK6_
PGM
0
R/W
3
BUCK1_
BUCK5_
PGM
0
R/W
2
BUCK1_
BUCK4_
PGM
0
R/W
1
BUCK1_
BUCK3_
PGM
0
R/W
0
BUCK1_
BUCK2_
PGM
0
R/W
Table 5-67. BUCK1_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK1_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK1_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK1_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK1_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3
BUCK1_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
2
BUCK1_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
1
BUCK1_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
0
BUCK1_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.5 BUCK1_CTRL_EN2 (offset = 08h) [reset = X]
Figure 5-79. BUCK1_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
BUCK1_
STEP_SIZE
1
R/W
1
R/W
0
R/W
4
BUCK1_
PINEN_
SEL[2]
0
R/W
3
BUCK1_
PINEN_
SEL[1]
0
R/W
2
BUCK1_
PINEN_
SEL[0]
0
R/W
1
BUCK1_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK1_
SWB1_PGM
0
R/W
Table 5-68. BUCK1_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
5
BUCK1_STEP_SIZE (1)
R/W
X
BUCK1 step size.
0: 10 mV
1: 25 mV
4:2
BUCK1_PINEN_SEL[2:0]
R/W
X
BUCK1 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK1_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK1_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
(1)
88
Should only be changed using the OTP generator tool.
Detailed Description
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5.12.6 BUCK1_CTRL_EN3 (offset = 09h) [reset = X]
Figure 5-80. BUCK1_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK1_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK1_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK1_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK1_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK1_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK1_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-69. BUCK1_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK1_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK1_RISING
_EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.7 BUCK2_CTRL_EN1 (offset = 0Ah) [reset = X]
Figure 5-81. BUCK2_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK2_
LDOA3_
PGM
0
R/W
6
BUCK2_
LDOA2_
PGM
0
R/W
5
BUCK2_
SWA1_PGM
0
R/W
4
BUCK2_
BUCK6_
PGM
0
R/W
3
BUCK2_
BUCK5_
PGM
0
R/W
2
BUCK2_
BUCK4_
PGM
0
R/W
1
BUCK2_
BUCK3_
PGM
0
R/W
0
BUCK2_
BUCK1_
PGM
0
R/W
Table 5-70. BUCK2_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK2_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK2_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK2_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK2_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3
BUCK2_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
2
BUCK2_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
1
BUCK2_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
0
BUCK2_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
90
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5.12.8 BUCK2_CTRL_EN2 (offset = 0Bh) [reset = X]
Figure 5-82. BUCK2_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
BUCK2_
STEP_SIZE
1
R/W
1
R/W
0
R/W
4
BUCK2_
PINEN_
SEL[2]
0
R/W
3
BUCK2_
PINEN_
SEL[1]
0
R/W
2
BUCK2_
PINEN_
SEL[0]
0
R/W
1
BUCK2_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK2_
SWB1_PGM
0
R/W
Table 5-71. BUCK2_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
5
BUCK2_STEP_SIZE (1)
R/W
X
BUCK2 step size.
0: 10 mV
1: 25 mV
4:2
BUCK2_PINEN_SEL[2:0]
R/W
X
BUCK2 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK2_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK2_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
(1)
Should only be changed using the OTP generator tool.
Detailed Description
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5.12.9 BUCK2_CTRL_EN3 (offset = 0Ch) [reset = X]
Figure 5-83. BUCK2_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK2_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK2_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK2_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK2_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK2_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK2_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-72. BUCK2_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK2_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK2 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK2_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK2 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
92
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5.12.10 BUCK3_CTRL_EN1 (offset = 0Ah) [reset = X]
Figure 5-84. BUCK3_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK3_
LDOA3_
PGM
0
R/W
6
BUCK3_
LDOA2_
PGM
0
R/W
5
BUCK3_
SWA1_PGM
0
R/W
4
BUCK3_
BUCK6_
PGM
0
R/W
3
BUCK3_
BUCK5_
PGM
0
R/W
2
BUCK3_
BUCK4_
PGM
0
R/W
1
BUCK3_
BUCK2_
PGM
0
R/W
0
BUCK3_
BUCK1_
PGM
0
R/W
Table 5-73. BUCK3_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK3_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK3_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK3_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK3_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3
BUCK3_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
2
BUCK3_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
1
BUCK3_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
BUCK3_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.11 BUCK3_CTRL_EN2 (offset = 0Eh) [reset = X]
Figure 5-85. BUCK3_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
RESERVED
0
R/W
0
R/W
0
R/W
4
BUCK3_
PINEN_
SEL[2]
0
R/W
3
BUCK3_
PINEN_
SEL[1]
0
R/W
2
BUCK3_
PINEN_
SEL[0]
0
R/W
1
BUCK3_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK3_
SWB1_PGM
0
R/W
Table 5-74. BUCK3_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
4:2
BUCK3_PINEN_SEL[2:0]
R/W
X
BUCK3 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK3_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK3_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
94
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5.12.12 BUCK3_CTRL_EN3 (offset = 0Fh) [reset = X]
Figure 5-86. BUCK3_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK3_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK3_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK3_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK3_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK3_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK3_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-75. BUCK3_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK3_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK3 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK3_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK3 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.13 BUCK4_CTRL_EN1 (offset = 10h) [reset = X]
Figure 5-87. BUCK4_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK4_
LDOA3_
PGM
0
R/W
6
BUCK4_
LDOA2_
PGM
0
R/W
5
BUCK4_
SWA1_PGM
0
R/W
4
BUCK4_
BUCK6_
PGM
0
R/W
3
BUCK4_
BUCK5_
PGM
0
R/W
2
BUCK4_
BUCK3_
PGM
0
R/W
1
BUCK4_
BUCK2_
PGM
0
R/W
0
BUCK4_
BUCK1_
PGM
0
R/W
Table 5-76. BUCK4_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK4_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK4_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK4_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK4_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3
BUCK4_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
2
BUCK4_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
BUCK4_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
BUCK4_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
96
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5.12.14 BUCK4_CTRL_EN2 (offset = 11h) [reset = X]
Figure 5-88. BUCK4_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
RESERVED
1
R/W
0
R/W
0
R/W
4
BUCK4_
PINEN_
SEL[2]
0
R/W
3
BUCK4_
PINEN_
SEL[1]
0
R/W
2
BUCK4_
PINEN_
SEL[0]
0
R/W
1
BUCK4_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK4_
SWB1_PGM
0
R/W
Table 5-77. BUCK4_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
4:2
BUCK4_PINEN_SEL[2:0]
R/W
X
BUCK4 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK4_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK4_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.15 BUCK4_CTRL_EN3 (offset = 12h) [reset = X]
Figure 5-89. BUCK4_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK4_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK4_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK4_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK4_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK4_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK4_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-78. BUCK4_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK4_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK4 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK4_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK4 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
98
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5.12.16 BUCK5_CTRL_EN1 (offset = 13h) [reset = X]
Figure 5-90. BUCK5_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK5_
LDOA3_
PGM
0
R/W
6
BUCK5_
LDOA2_
PGM
0
R/W
5
BUCK5_
SWA1_PGM
0
R/W
4
BUCK5_
BUCK6_
PGM
0
R/W
3
BUCK5_
BUCK4_
PGM
0
R/W
2
BUCK5_
BUCK3_
PGM
0
R/W
1
BUCK5_
BUCK2_
PGM
0
R/W
0
BUCK5_
BUCK1_
PGM
0
R/W
Table 5-79. BUCK5_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK5_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK5_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK5_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK5_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
3
BUCK5_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
BUCK5_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
BUCK5_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
BUCK5_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.17 BUCK5_CTRL_EN2 (offset = 14h) [reset = X]
Figure 5-91. BUCK5_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
RESERVED
0
R/W
0
R/W
0
R/W
4
BUCK5_
PINEN_
SEL[2]
0
R/W
3
BUCK5_
PINEN_
SEL[1]
0
R/W
2
BUCK5_
PINEN_
SEL[0]
0
R/W
1
BUCK5_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK5_
SWB1_PGM
0
R/W
Table 5-80. BUCK5_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
4:2
BUCK5_PINEN_SEL[2:0]
R/W
X
BUCK5 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK5_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK5_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
100
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5.12.18 BUCK5_CTRL_EN3 (offset = 15h) [reset = X]
Figure 5-92. BUCK5_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK5_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK5_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK5_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK5_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK5_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK5_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-81. BUCK5_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK5_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK5 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK5_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK5 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.19 BUCK6_CTRL_EN1 (offset = 16h) [reset = X]
Figure 5-93. BUCK6_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK6_
LDOA3_
PGM
0
R/W
6
BUCK6_
LDOA2_
PGM
0
R/W
5
BUCK6_
SWA1_PGM
0
R/W
4
BUCK6_
BUCK5_
PGM
0
R/W
3
BUCK6_
BUCK4_
PGM
0
R/W
2
BUCK6_
BUCK3_
PGM
0
R/W
1
BUCK6_
BUCK2_
PGM
0
R/W
0
BUCK6_
BUCK1_
PGM
0
R/W
Table 5-82. BUCK6_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK6_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
BUCK6_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
BUCK6_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
BUCK6_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
BUCK6_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
BUCK6_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
BUCK6_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
BUCK6_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
102
Detailed Description
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5.12.20 BUCK6_CTRL_EN2 (offset = 17h) [reset = X]
Figure 5-94. BUCK6_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
BUCK6_
STEP_SIZE
1
R/W
1
R/W
0
R/W
4
BUCK6_
PINEN_
SEL[2]
0
R/W
3
BUCK6_
PINEN_
SEL[1]
0
R/W
2
BUCK6_
PINEN_
SEL[0]
0
R/W
1
BUCK6_
SWB2_LDO
A1_PGM
0
R/W
0
BUCK6_
SWB1_PGM
0
R/W
Table 5-83. BUCK6_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
5
BUCK6_STEP_SIZE (1)
R/W
X
BUCK6 step size.
0: 10 mV
1: 25 mV
4:2
BUCK6_PINEN_SEL[2:0]
R/W
X
BUCK6 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
BUCK6_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
BUCK6_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
(1)
Should only be changed using the OTP generator tool.
Detailed Description
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5.12.21 BUCK6_CTRL_EN3 (offset = 18h) [reset = X]
Figure 5-95. BUCK6_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
BUCK6_
FALLING_
EDGE_
DLY[2]
0
R/W
4
BUCK6_
FALLING_
EDGE_
DLY[1]
0
R/W
3
BUCK6_
FALLING_
EDGE_
DLY[0]
0
R/W
2
BUCK6_
RISING_
EDGE_
DLY[2]
0
R/W
1
BUCK6_
RISING_
EDGE_
DLY[1]
0
R/W
0
BUCK6_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-84. BUCK6_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
BUCK6_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of BUCK6 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
BUCK6_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of BUCK6 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
104
Detailed Description
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5.12.22 SWA1_CTRL_EN1 (offset = 19h) [reset = X]
Figure 5-96. SWA1_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
SWA1_
LDOA3_
PGM
0
R/W
6
SWA1_
LDOA2_
PGM
0
R/W
5
SWA1_
BUCK6_
PGM
0
R/W
4
SWA1_
BUCK5_
PGM
0
R/W
3
SWA1_
BUCK4_
PGM
0
R/W
2
SWA1_
BUCK3_
PGM
0
R/W
1
SWA1_
BUCK2_
PGM
0
R/W
0
SWA1_
BUCK1_
PGM
0
R/W
Table 5-85. SWA1_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
SWA1_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
SWA1_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
SWA1_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
SWA1_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
SWA1_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
SWA1_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
SWA1_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
SWA1_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.23 SWA1_CTRL_EN2 (offset = 1Ah) [reset = X]
Figure 5-97. SWA1_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
SWA1_
PG_SEL[1]
SWA1_
PG_SEL[0]
0
R/W
0
R/W
0
R/W
4
SWA1_
PINEN_
SEL[2]
0
R/W
3
SWA1_
PINEN_
SEL[1]
0
R/W
2
SWA1_
PINEN_
SEL[0]
0
R/W
1
SWA1_
SWB2_LDO
A1_PGM
0
R/W
0
SWA1_
SWB1_PGM
0
R/W
Table 5-86. SWA1_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
6:5
SWA1_PG_SEL[1:0]
R/W
X
SWA1 PGOOD select..
00: 1.5 V
01: 1.8 V
10: 2.5 V
11: 3.3 V
4:2
SWA1_PINEN_SEL[2:0]
R/W
X
SWA1 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
SWA1_SWB2_LDOA1_PGM
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
SWA1_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
106
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5.12.24 SWA1_CTRL_EN3 (offset = 1Bh) [reset = X]
Figure 5-98. SWA1_CTRL_EN3 Register
Bit
Bit Name
7
6
RESERVED
VTT_EN
_SEL
0
R/W
0
R/W
TPS65086100
Access
5
SWA1_
FALLING_
EDGE_
DLY[2]
0
R/W
4
SWA1_
FALLING_
EDGE_
DLY[1]
0
R/W
3
SWA1_
FALLING_
EDGE_
DLY[0]
0
R/W
2
SWA1_
RISING_
EDGE_
DLY[2]
0
R/W
1
SWA1_
RISING_
EDGE_
DLY[1]
0
R/W
0
SWA1_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-87. SWA1_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
6
VTT_EN_SEL
R/W
X
Pin Select for VTT EN Logic
0: CTL3
1: CTL6
5:3
SWA1_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of SWA1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
SWA1_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of SWA1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.25 LDOA2_CTRL_EN1 (offset = 1Ch) [reset = X]
Figure 5-99. LDOA2_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA2_
LDOA3_
PGM
0
R/W
6
LDOA2_
SWA1_
PGM
0
R/W
5
LDOA2_
BUCK6_
PGM
0
R/W
4
LDOA2_
BUCK5_
PGM
0
R/W
3
LDOA2_
BUCK4_
PGM
0
R/W
2
LDOA2_
BUCK3_
PGM
0
R/W
1
LDOA2_
BUCK2_
PGM
0
R/W
0
LDOA2_
BUCK1_
PGM
0
R/W
Table 5-88. LDOA2_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
LDOA2_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
LDOA2_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
LDOA2_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
LDOA2_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
LDOA2_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
LDOA2_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
LDOA2_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
108
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5.12.26 LDOA2_CTRL_EN2 (offset = 1Dh) [reset = X]
Figure 5-100. LDOA2_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
RESERVED
RESERVED
0
R/W
1
R/W
0
R/W
4
LDOA2_
PINEN_
SEL[2]
0
R/W
3
LDOA2_
PINEN_
SEL[1]
0
R/W
2
LDOA2_
PINEN_
SEL[0]
0
R/W
1
LDOA2_
SWB2_LDO
A1_PGM
0
R/W
0
LDOA2_
SWB1_PGM
0
R/W
Table 5-89. LDOA2_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
4:2
LDOA2_PINEN_SEL[2:0]
R/W
X
LDOA2 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
LDOA2_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
LDOA2_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.27 LDOA2_CTRL_EN3 (offset = 1Eh) [reset = X]
Figure 5-101. LDOA2_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
ECLDO_
DLY[1]
ECLDO_
DLY[0]
0
R/W
0
R/W
5
LDOA2_
FALLING_
EDGE_
DLY[2]
0
R/W
4
LDOA2_
FALLING_
EDGE_
DLY[1]
0
R/W
3
LDOA2_
FALLING_
EDGE_
DLY[0]
0
R/W
2
LDOA2_
RISING_
EDGE_
DLY[2]
0
R/W
1
LDOA2_
RISING_
EDGE_
DLY[1]
0
R/W
0
LDOA2_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-90. LDOA2_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
7:6
LDOA1_SWB2_
DLY[1:0]
R/W
X
Sets the off time for LDOA1 during shutdown (all Values have 10% variations).
00: 1 ms
01: 5 ms
10: 10 ms
11: 100 ms
5:3
LDOA2_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of LDOA2 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
LDOA2_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of LDOA2 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
110
Detailed Description
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5.12.28 LDOA3_CTRL_EN1 (offset = 1Fh) [reset = X]
Figure 5-102. LDOA3_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
LDOA3_
LDOA2_
PGM
0
R/W
6
LDOA3_
SWA1_
PGM
0
R/W
5
LDOA3_
BUCK6_
PGM
0
R/W
4
LDOA3_
BUCK5_
PGM
0
R/W
3
LDOA3_
BUCK4_
PGM
0
R/W
2
LDOA3_
BUCK3_
PGM
0
R/W
1
LDOA3_
BUCK2_
PGM
0
R/W
0
LDOA3_
BUCK1_
PGM
0
R/W
Table 5-91. LDOA3_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA3_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
LDOA3_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
LDOA3_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
LDOA3_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
LDOA3_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
LDOA3_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
LDOA3_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
LDOA3_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.29 LDOA3_CTRL_EN2 (offset = 20h) [reset = X]
Figure 5-103. LDOA3_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
BUCK6_
VSEL_
OPTION
0
R/W
6
5
RESERVED
RESERVED
0
R/W
0
R/W
4
LDOA3_
PINEN_
SEL[2]
0
R/W
3
LDOA3_
PINEN_
SEL[1]
0
R/W
2
LDOA3_
PINEN_
SEL[0]
0
R/W
1
LDOA3_
SWB2_LDO
A1_PGM
0
R/W
0
LDOA3_
SWB1_PGM
0
R/W
Table 5-92. LDOA3_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
7
BUCK6_VSEL_OPTION
R/W
X
Determines whether high level on CTRL2 can set BUCK6 to 1.2 V. If step size
is 25 mV the voltage will be 2.4 V. SLP pin will override this voltage.
0: CTRL2 has no effect.
1: CTRL2 controls output voltage.
4:2
LDOA3_PINEN_SEL[2:0]
R/W
X
LDOA3 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
LDOA3_SWB2_LDOA1_PG
M
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
LDOA3_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB1 PGOOD is part of Enable Logic.
1: SWB1 PGOOD is masked and is not part of enable logic.
112
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5.12.30 LDOA3_CTRL_EN3 (offset = 21h) [reset = X]
Figure 5-104. LDOA3_CTRL_EN3 Register
Bit
Bit Name
7
6
SWB12_EN
LDOA1_
SWB2
0
R/W
0
R/W
TPS65086100
Access
5
LDOA3_
FALLING_
EDGE_
DLY[2]
0
R/W
4
LDOA3_
FALLING_
EDGE_
DLY[1]
0
R/W
3
LDOA3_
FALLING_
EDGE_
DLY[0]
0
R/W
2
LDOA3_
RISING_
EDGE_
DLY[2]
0
R/W
1
LDOA3_
RISING_
EDGE_
DLY[1]
0
R/W
0
LDOA3_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-93. LDOA3_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
7
SWB12_EN
R/W
X
If set, combines the Enable logic for SWB1 and SWB2.
0: Normal functionality.
1: Enable logic for SWB1 is also used to enable SWB2.
6
LDOA1_SWB2
R/W
X
Used to swap enable logic for LDOA1 and SWB2.
0: Normal functionality.
1: Enable logic for SWB2 (SWB2_LDOA1_CTRL_EN1,
SWB2_LDOA1_CTRL_EN2, SWB2_LDOA1_CTRL_EN3, SWB2_LDOA1_msK,
SWB2_LDOA1_EN, SWB2_LDOA1_DIS) is used for LDOA1 and Enable logic
for LDOA1 (LDOA1_SWB2_EN,
LDOA1_SWB2_DLY,LDOA1_SWB2_SDWN_CON FIG) is used for SWB2.
5:3
LDOA3_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of LDOA3 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
LDOA3_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of LDOA3 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.31 SWB1_CTRL_EN1 (offset = 22h) [reset = X]
Figure 5-105. SWB1_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
SWB1_
LDOA2_
PGM
0
R/W
6
SWB1_
SWA1_
PGM
0
R/W
5
SWB1_
BUCK6_
PGM
0
R/W
4
SWB1_
BUCK5_
PGM
0
R/W
3
SWB1_
BUCK4_
PGM
0
R/W
2
SWB1_
BUCK3_
PGM
0
R/W
1
SWB1_
BUCK2_
PGM
0
R/W
0
SWB1_
BUCK1_
PGM
0
R/W
Table 5-94. SWB1_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
SWB1_LDOA2_PGM
R/W
X
LDOA2 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
6
SWB1_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
5
SWB1_BUCK6_PGM
R/W
X
BUCK6 PGOOD masked
0: BUCK6 PGOOD is part of Enable Logic.
1: BUCK6 PGOOD is masked and is not part of enable logic.
4
SWB1_BUCK5_PGM
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
SWB1_BUCK4_PGM
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
SWB1_BUCK3_PGM
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
SWB1_BUCK2_PGM
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
SWB1_BUCK1_PGM
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
114
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5.12.32 SWB1_CTRL_EN2 (offset = 23h) [reset = X]
Figure 5-106. SWB1_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
SWB1_
PG_SEL[1]
SWB1_
PG_SEL[0]
1
R/W
0
R/W
0
R/W
4
SWB1_
PINEN_
SEL[2]
0
R/W
3
SWB1_
PINEN_
SEL[1]
0
R/W
2
SWB1_
PINEN_
SEL[0]
0
R/W
1
SWB1_
SWB2_LDO
A1_PGM
0
R/W
0
SWB1_
LDOA3_PG
M
0
R/W
Table 5-95. SWB1_CTRL_EN2 Register Descriptions
Bit
Field
Type Reset
Description
6:5
SWB1_PG_SEL[2:0]
R/W
X
SWB1 PGOOD select..
00: 1.5 V
01: 1.8 V
10: 2.5 V
11: 3.3 V
4:2
SWB1_PINEN_SEL[2:0]
R/W
X
SWB1 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
SWB1_SWB2_LDOA1_PGM
R/W
X
SWB2_LDOA1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
SWB1_LDOA3_PGM
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.33 SWB1_CTRL_EN3 (offset = 24h) [reset = X]
Figure 5-107. SWB1_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
SWB1_
FALLING_
EDGE_
DLY[2]
0
R/W
4
SWB1_
FALLING_
EDGE_
DLY[1]
0
R/W
3
SWB1_
FALLING_
EDGE_
DLY[0]
0
R/W
2
SWB1_
RISING_
EDGE_
DLY[2]
0
R/W
1
SWB1_
RISING_
EDGE_
DLY[1]
0
R/W
0
SWB1_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-96. SWB1_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
SWB1_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of SWB1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
SWB1_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of SWB1 Enable pin (all Values have 10% variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
116
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5.12.34 SWB2_LDOA1_CTRL_EN1 (offset = 25h) [reset = X]
Figure 5-108. SWB2_LDOA1_CTRL_EN1 Register
Bit
Bit Name
TPS65086100
Access
7
SWB2_LDO
A1_
LDOA2_
PGM
0
R/W
6
SWB2_LDO
A1_
SWA1_
PGM
0
R/W
5
SWB2_LDO
A1_
BUCK6_PG
M
0
R/W
4
SWB2_LDO
A1_
BUCK5_
PGM
0
R/W
3
SWB2_LDO
A1_
BUCK4_
PGM
0
R/W
2
SWB2_LDO
A1_
BUCK3_
PGM
0
R/W
1
SWB2_LDO
A1_
BUCK2_
PGM
0
R/W
0
SWB2_LDO
A1_
BUCK1_
PGM
0
R/W
Table 5-97. SWB2_LDOA1_CTRL_EN1 Register Descriptions
Bit
Field
Type Reset
Description
7
SWB2_LDOA1_LDOA2_PG
M
R/W
X
LDOA2 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
6
SWB2_LDOA1_SWA1_PGM
R/W
X
SWA1 PGOOD masked
0: LDOA2 PGOOD is part of Enable Logic.
1: LDOA2 PGOOD is masked and is not part of enable logic.
5
SWB2_LDOA1_BUCK6_PG
M
R/W
X
BUCK6 PGOOD masked
0: SWA1 PGOOD is part of Enable Logic.
1: SWA1 PGOOD is masked and is not part of enable logic.
4
SWB2_LDOA1_BUCK5_PG
M
R/W
X
BUCK5 PGOOD masked
0: BUCK5 PGOOD is part of Enable Logic.
1: BUCK5 PGOOD is masked and is not part of enable logic.
3
SWB2_LDOA1_BUCK4_PG
M
R/W
X
BUCK4 PGOOD masked
0: BUCK4 PGOOD is part of Enable Logic.
1: BUCK4 PGOOD is masked and is not part of enable logic.
2
SWB2_LDOA1_BUCK3_PG
M
R/W
X
BUCK3 PGOOD masked
0: BUCK3 PGOOD is part of Enable Logic.
1: BUCK3 PGOOD is masked and is not part of enable logic.
1
SWB2_LDOA1_BUCK2_PG
M
R/W
X
BUCK2 PGOOD masked
0: BUCK2 PGOOD is part of Enable Logic.
1: BUCK2 PGOOD is masked and is not part of enable logic.
0
SWB2_LDOA1_BUCK1_PG
M
R/W
X
BUCK1 PGOOD masked
0: BUCK1 PGOOD is part of Enable Logic.
1: BUCK1 PGOOD is masked and is not part of enable logic.
Detailed Description
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5.12.35 SWB2_LDOA1_CTRL_EN2 (offset = 26h) [reset = X]
Figure 5-109. SWB2_LDOA1_CTRL_EN2 Register
Bit
Bit Name
TPS65086100
Access
7
6
5
RESERVED
SWB2_LDO
A1_
PG_SEL[1]
SWB2_LDO
A1_
PG_SEL[0]
0
R/W
0
R/W
0
R/W
4
SWB2_LDO
A1_
PINEN_
SEL[2]
0
R/W
3
SWB2_LDO
A1_
PINEN_
SEL[1]
0
R/W
2
SWB2_LDO
A1_
PINEN_
SEL[0]
0
R/W
1
SWB2_LDO
A1_
SWB1_PGM
0
R/W
0
SWB2_LDO
A1_
LDOA3_PG
M
0
R/W
Table 5-98. SWB2_LDOA1_CTRL_EN2 Register Descriptions
Bit
Field
6:5
SWB2_LDOA1_PG_SEL[1:0] R/W
X
SWB2_LDOA1 PGOOD select..
00: 1.5 V
01: 1.8 V
10: 2.5 V
11: 3.3 V
4:2
SWB2_LDOA1_PINEN_
SEL[2:0]
R/W
X
SWB2_LDOA1 Enable pin select.
000: CTL1
001: CTL2
010: CTL5
011: CTL4
100: CTL3
101: CTL3 and CTL4
110: CTL6
111: 1 is inserted into CTL MUX. No pin is required to enable.
1
SWB2_LDOA1_SWB1_PGM
R/W
X
SWB1 PGOOD masked
0: SWB2_LDOA1 PGOOD is part of Enable Logic.
1: SWB2_LDOA1 PGOOD is masked and is not part of enable logic.
0
SWB2_LDOA1_LDOA3_PG
M
R/W
X
LDOA3 PGOOD masked
0: LDOA3 PGOOD is part of Enable Logic.
1: LDOA3 PGOOD is masked and is not part of enable logic.
118
Type Reset
Description
Detailed Description
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5.12.36 SWB2_LDOA1_CTRL_EN3 (offset = 27h) [reset = X]
Figure 5-110. SWB2_LDOA1_CTRL_EN3 Register
Bit
Bit Name
TPS65086100
Access
7
6
RESERVED
RESERVED
0
R/W
0
R/W
5
SWB2_LDO
A1_
FALLING_
EDGE_
DLY[2]
0
R/W
4
SWB2_LDO
A1_
FALLING_
EDGE_
DLY[1]
0
R/W
3
SWB2_LDO
A1_
FALLING_
EDGE_
DLY[0]
0
R/W
2
SWB2_LDO
A1_
RISING_
EDGE_
DLY[2]
0
R/W
1
SWB2_LDO
A1_
RISING_
EDGE_
DLY[1]
0
R/W
0
SWB2_LDO
A1_
RISING_
EDGE_
DLY[0]
0
R/W
Table 5-99. SWB2_LDOA1_CTRL_EN3 Register Descriptions
Bit
Field
Type Reset
Description
5:3
SWB2_LDOA1_FALLING_
EDGE_DLY[2:0]
R/W
X
Delay for falling edge of SWB2_LDOA1 Enable pin (all Values have 10%
variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
2:0
SWB2_LDOA1_RISING_
EDGE_DLY[2:0]
R/W
X
Delay for rising edge of SWB2_LDOA1 Enable pin (all Values have 10%
variations).
000: No Delay.
001: 2 ms Delay.
010: 4 ms Delay.
011: 8 ms Delay.
100: 16 ms Delay.
101: 24 ms Delay.
110: 32 ms Delay.
111: 64 ms Delay.
Detailed Description
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5.12.37 SLP_PIN (offset = 29h) [reset = X]
Figure 5-111. SLP_PIN Register
Bit
Bit Name
TPS65086100
Access
7
LDOA3_
SLP_PIN
0
R/W
6
LDOA2_
SLP_PIN
0
R/W
5
BUCK6_
SLP_PIN
0
R/W
4
BUCK5_
SLP_PIN
0
R/W
3
BUCK4_
SLP_PIN
0
R/W
2
BUCK3_
SLP_PIN
0
R/W
1
BUCK2_
SLP_PIN
0
R/W
0
BUCK1_
SLP_PIN
0
R/W
Table 5-100. SLP_PIN Register Descriptions
Bit
Field
Type Reset
Description
7
LDOA3_SLP_PIN
R/W
X
LDOA3 SLP pin.
0: CTL3
1: CTL6
6
LDOA2_SLP_PIN
R/W
X
LDOA2 SLP pin.
0: CTL3
1: CTL6
5
BUCK6_SLP_PIN
R/W
X
BUCK6 SLP pin.
0: CTL3
1: CTL6
4
BUCK5_SLP_PIN
R/W
X
BUCK5 SLP pin.
0: CTL3
1: CTL6
3
BUCK4_SLP_PIN
R/W
X
BUCK4 SLP pin.
0: CTL3
1: CTL6
2
BUCK3_SLP_PIN
R/W
X
BUCK3 SLP pin.
0: CTL3
1: CTL6
1
BUCK2_SLP_PIN
R/W
X
BUCK2 SLP pin.
0: CTL3
1: CTL6
0
BUCK1_SLP_PIN
R/W
X
BUCK1 SLP pin.
0: CTL3
1: CTL6
120
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5.12.38 OUTPUT_MODE (offset = 2Ah) [reset = X]
Figure 5-112. OUTPUT_MODE Register
Bit
Bit Name
TPS65086100
Access
7
GPO4_CTL
0
R/W
6
GPO3_CTL
0
R/W
5
GPO2_CTL
0
R/W
4
GPO1_CTL
0
R/W
3
RESERVED
0
R/W
2
GPO3_MD
0
R/W
1
GPO2_MD
0
R/W
0
GPO1_MD
0
R/W
Table 5-101. OUTPUT_MODE Register Descriptions
Bit
Field
Type Reset
Description
7
GPO4_CTL
R/W
X
GPO4 output control.
0: PGOOD logic
1: I2C register
6
GPO3_CTL
R/W
X
GPO3 output control.
0: PGOOD logic
1: I2C register
5
GPO2_CTL
R/W
X
GPO2 output control.
0: PGOOD logic
1: I2C register
4
GPO1_CTL
R/W
X
GPO1 output control.
0: PGOOD logic
1: I2C register
2
GPO3_MD
R/W
X
GPO3 mode.
0: Push-pull
1: Open drain
1
GPO2_MD
R/W
X
GPO2 mode.
0: Push-pull
1: Open drain
0
GPO1_MD
R/W
X
GPO1 mode.
0: Push-pull
1: Open drain
Detailed Description
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5.12.39 I2C_SLAVE_ADDR (offset = 5Fh) [reset = X]
Figure 5-113. I2C_SLAVE_ADDR Register
Bit
Bit Name
TPS65086100
Access
7
SLV_
ADDR_SEL
0
R/W
6
SLV_
ADDR[6]
0
R/W
5
SLV_
ADDR[5]
0
R/W
4
SLV_
ADDR[4]
0
R/W
3
SLV_
ADDR[3]
0
R/W
2
SLV_
ADDR[2]
0
R/W
1
SLV_
ADDR[1]
0
R/W
0
SLV_
ADDR[0]
0
R/W
Table 5-102. I2C_SLAVE_ADDR Register Descriptions
Bit
Field
Type Reset
Description
7
SLV_ADDR_SEL
R/W
X
Slave address select bit.
0: Use default 0x5E address
1: Use programmable slave address
6:0
SLV_ADDR[6:0]
R/W
X
6 bit programmable slave address.
0000000: Reserved due to I2C standard specifications.
...
0001000: Reserved due to I2C standard specifications.
0001001: 0x08
...
0110111: 0x37
0111000: Reserved for registers accessible by I2C address 0x38.
0111001: 0x39
...
1110111: 0x77
1111000: Reserved due to I2C standard specifications.
...
1111111: Reserved due to I2C standard specifications.
122
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6 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Application Information
For a detailed description about application usage, refer to the TPS65086x Design Guide and to the
TPS65086x Schematic and Layout Checklist.
6.2
6.2.1
Typical Application
Typical Application Example
This section describes the general application information and provides a more detailed description on the
PMIC that powers a generic multicore-processor application. An example system block diagram for the
device powering an SoC and the rest of platform is shown in Figure 6-1. The functional block diagram in
Figure 5-1 outlines the typical external components necessary for proper device functionality.
Applications, Implementation, and Layout
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PMIC
Example SoC
PLATFORM
VIN
BUCK1
EXT FET
VCORE
VIN
BUCK2
5V Supply
EXT FET
VGPU
BUCK3 3A
VCCIO
BUCK4 3A
VCPU1
BUCK5 3A
Note: An LDO or
Buck Can Supply
the VPP Rail if
Needed for DDR.
VCPU2
VIN
BUCK6
EXT FET
VTT LDO ±0.5A
LDO5V or
5V Supply
VDDQ, VDD1&2
VDDQ, VDD1&2
VREF, VTT
VREF, VTT
DDR
DDR
LDOA1 0.2A
VSUPP1
LDOA2 0.6A
VSUPP2
LDOA3 0.6A
VSUPP3
Input up to 3.3V
SWA1 0.3A
VSUPP4
Input up to 3.3V
SWB1 0.3A
VSUPP5
SWB2 0.3A
VSUPP6
1.8V
VIN
VSYS
LDO5V
LDO5
5V Supply
PG_5V
LDO3P3
IRQB
GPO1 ± GPO4
CTL1 ± CTL6
SDA
SCL
Copyright © 2017, Texas Instruments Incorporated
Figure 6-1. Typical Application Example
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Design Requirements
The PMIC requires decoupling caps on the supply pins. Follow the values for recommended capacitance
on these supplies given in Section 4. The controllers, converter, LDOs, and some other features can be
adjusted to meet specific application needs. Section 6.2.1.2 describes how to design and adjust the
external components to achieve desired performance.
6.2.1.2
Detailed Design Procedure
6.2.1.2.1 Controller Design Procedure
Designing the controller can be broken down into the following steps:
1. Design the output filter
2. Select the FETs
3. Select the bootstrap capacitor
4. Select the input capacitors
5. Set the current limits
Controllers BUCK1, BUCK2, and BUCK6 require a 5-V supply and capacitors at their corresponding
DRV5V_x_x pins. For most applications, the DRV5V_x_x input should come from the LDO5P0 pin to
ensure uninterrupted supply voltage; a 2.2-µF, X5R, 20%, 10-V, or similar capacitor must be used for
decoupling.
VSYS
DRVHx
BOOT1
LDO5V
DRV5V_x_x
VOUT
LOUT
SWx
COUT
Controller
DRVLx
PGNDSNSx
Control
from SOC
FBVOUTx
RILIM
<FBGND2>(1)
ILIMx
PowerPADTM
Copyright © 2017, Texas Instruments Incorporated
(1)
<FBGND2> is only present for BUCK2.
Figure 6-2. Controller Diagram
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6.2.1.2.1.1 Selecting the Inductor
Placement of an inductor is required between the external FETs and the output capacitors. Together, the
inductor and output capacitors make the double-pole that contributes to stability. In addition, the inductor
is directly responsible for the output ripple, efficiency, and transient performance. As the inductance used
increases, the ripple current decreases, which typically results in an increased efficiency. However, with
an increase in inductance used, the transient performance decreases. Finally, the inductor selected must
be rated for appropriate saturation current, core losses, and DC resistance (DCR).
Equation 5 shows the calculation for the recommended inductance for the controller.
VOUT u (VIN VOUT )
L
VIN u fsw u IOUT(MAX) u KIND
where
•
•
•
•
•
VOUT is the typical output voltage
VIN is the typical input voltage
fSW is the typical switching frequency when loaded, 1 MHz unless otherwise noted
IOUT(MAX) is the maximum load current
KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value
from 0.2 to 0.4. Higher values have improved transient performance, lower values have improved
efficiency
(5)
With the chosen inductance value, the peak current for the inductor in steady state operation, IL(max), can
be calculated using Equation 6. The rated saturation current of the inductor must be higher than the IL(max)
current.
(VIN VOUT ) u VOUT
IL(MAX) IOUT(MAX)
2 u VIN u fsw u L
(6)
6.2.1.2.1.2 Selecting the Output Capacitors
TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple.
The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from
their wide variation in capacitance over temperature, become resistive at high frequencies.
At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on
the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize
the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage
ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of
ceramic capacitors drops with increasing DC bias voltage.
TI recommends the use of small ceramic capacitors placed between the inductor and load with many vias
to the PGND plane for the output capacitors of the BUCK controllers. This solution typically provides the
smallest and lowest cost solution available for D-CAP2 controllers.
The selection of the output capacitor is typically driven by the output transient response. Equation 7 and
Equation 8 provide a rough estimate of the minimum required capacitance to ensure proper transient
response. Because the transient response is significantly affected by the board layout, some
experimentation is expected in order to confirm that values derived in this section are applicable to any
particular use case. These are not meant to be an absolute requirement, but rather a rough starting point.
Alternatively, some known combination values from which to begin are provided in Table 6-1. VUNDER and
VOVER values should be greater than or equal to 3% of VOUT setting in order for equations to be
meaningful. The equations provide some margin so that actual capacitance requirement may be lower
than calculated.
COUT !
ITRAN(MAX)2 u L
(VIN
VOUT ) u VUNDER
where
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•
•
•
•
•
ITRAN(max) is the maximum load current step
L is the chosen inductance
VIN is the maximum input voltage
VOUT is the minimum programmed output voltage
VUNDER is the maximum allowable undershoot from programmed voltage
(7)
2
COUT !
ITRAN(MAX) u L
VOUT u VOVER
where
•
VOVER is the maximum allowable overshoot from programmed voltage
(8)
Another key performance factor can be the ripple voltage while in pulsed frequency modulation mode, also
known as discontinuous conduction mode. At light load, the controller will disable the low side FET once it
detects a zero-crossing event on the inductor current. It will stay disabled until VOUT crosses below the set
VID threshold. This architecture allows significant power savings at light load conditions by minimizing
power loss through the low side FET and through switching. The disadvantage is that there is higher
voltage ripple since the ripple current is only positive. Additionally, for even higher efficiency, TON(PFM) for
this device is typically 80% longer than TON(PWM), which can be calculated by dividing the duty cycle by the
switching frequency. An estimate for the required capacitance for a given allowable ripple voltage at light
load is shown in Equation 9. ESR of the output capacitor is neglected here because ceramic capacitors,
which typically have low ESR, are recommended. VOVER should not be set lower than 3% of VOUT value.
COUT !
TON _ EXT 2 u VOUT u VIN
VOUT
2
u 9IN u ¦SW u 9OVER u /
where
•
•
•
•
•
•
TON_EXT is the PFM on time extension constant, 1.8 unless otherwise noted in the part number specific
section
VOUT is the maximum programmed output voltage
VIN is the maximum input voltage
fSW is the typical switching frequency when loaded, 1 MHz unless otherwise noted
VOVER is the maximum allowable overshoot from programmed voltage
L is the chosen inductance
(9)
In cases where the transient current change is very low and ripple voltage allowance is large, the DC
stability may become important. DCAP2 is a very stable architecture so this value is likely to be the
smallest of those calculated. Equation 10 approximates the amount of capacitance necessary to maintain
DC stability. Again, this is provided as a starting point; actual values will vary on a board-to-board case.
V
u 50 Ps
COUT ! OUT
VIN u fSW u L
where
•
•
•
•
•
VOUT is the maximum programmed output voltage
50 µs is based on internal ramp setup
VIN is the minimum input voltage
fSW is the typical switching frequency
L is the chosen inductance
(10)
Choosing the maximum valuable between Equation 7, Equation 8, Equation 9, and Equation 10 is
recommended as a starting point to get the desired performance. All equations are estimates and have
not been validated at all variable corners. Removing excess capacitance or adding extra capacitance may
be necessary during board evaluation. Testing can typically be performed on the evaluation module or on
prototype boards.
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Table 6-1. Known LC Combinations for 1 µs Load Rise and Fall Time
ITRAN(max)
L (µH)
VOUT (V)
VUNDER (V)
VOVER (V)
COUT(µF)
3.5
0.47
1
0.05
0.05
110
4
0.47
1
0.05
0.05
220
5
0.47
1.35
0.068
0.068
220
8
0.33
1
0.05
0.06
440
20
0.22
1
0.05
0.16
550
(A)
6.2.1.2.1.3 Selecting the FETs
This controller is designed to drive two NMOS FETs. Typically, lower RDSON values are better for
improving the overall efficiency of the controller, however higher gate charge thresholds will result in lower
efficiency so the two need to be balanced for optimal performance. As the RDSON for the low-side FET
decreases, the minimum current limit increases; therefore, ensure selection of the appropriate values for
the FETs, inductor, output capacitors, and current limit resistor. TI's CSD85301Q2, CSD87331Q3D,
CSD87381P, CSD87588N, and CSD87350Q5D devices are recommended for the controllers, depending
on the required maximum current.
6.2.1.2.1.4 Bootstrap Capacitor
To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a
capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends
placing ceramic capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,
10-V capacitor is used for the controllers.
TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and
turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common
practice for controller design.
6.2.1.2.1.5 Setting the Current Limit
The current-limiting resistor value must be chosen based on Equation 1.
6.2.1.2.1.6 Selecting the Input Capacitors
Due to the nature of the switching controller with a pulsating input current, a low ESR input capacitor is
required for best input-voltage filtering and also for minimizing the interference with other circuits caused
by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x
pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is
recommended for most applications. To achieve the low ESR requirement, a ceramic capacitor is
recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be
considered. For better input-voltage filtering, the input capacitor can be increased without any limit.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS
and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata
GRM21BR61E226ME44: 22-µF, 0805, 25-V, ±20%, or similar capacitors.
6.2.1.2.2 Converter Design Procedure
Designing the converter has only two steps: design the output filter and select the input capacitors.
Figure 6-3 shows a diagram of the converter.
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VIN_BUCK345_ANA
PVINx
LXx
CIN
LOUT
VOUT
FBx
Converter
PowerPADTM
Control from SOC
Copyright © 2017, Texas Instruments Incorporated
Figure 6-3. Converter Diagram
6.2.1.2.2.1 Selecting the Inductor
Internal parameters for the converters are optimized for either a 0.47 µH or 1 µH inductor, however it is
possible to use other inductor values as long as they are chosen carefully and thoroughly tested. The
equations from Section 6.2.1.2.1.1 can be utilized again with the parameters changed to match those of
the converters. Switching frequency estimates can be found in Section 4.15.
6.2.1.2.2.2 Selecting the Output Capacitors
Ceramic capacitors with low ESR values are recommended because they provide the lowest output
voltage ripple. The output capacitor requires either an X7R or X5R rating. Y5V and Z5U capacitors, aside
from the wide variation in capacitance over temperature, become resistive at high frequencies.
For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors
between the inductor and load with many vias to the PGND plane. This solution typically provides the
smallest and lowest-cost solution available.
The minimum output capacitance recommended is 22 µF for stability. Equation 7 and Equation 8 can be
used to estimate the required output capacitance for a given load transient. Note that VIN will be different
for the converters and that the switching frequency can be estimated using Section 4.15. Equation 9 can
be neglected for converters as there is no on time extension and the VIN - VOUT term is typically smaller.
6.2.1.2.2.3 Selecting the Input Capacitors
Due to the nature of the switching converter with a pulsating input current, a low ESR input capacitor is
required for best input-voltage filtering and for minimizing the interference with other circuits caused by
high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for
most applications. A ceramic capacitor is recommended to achieve the low ESR requirement. However,
the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. The input
capacitor can be increased without any limit for better input-voltage filtering.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10-µF, 0402, 10-V,
±20%, or similar capacitor.
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6.2.1.2.3 LDO Design Procedure
The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, it is
recommended to use ceramic capacitors to maintain a high amount of capacitance with low ESR on the
VTT LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the
GRM188R60J226MEA0 from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred
input capacitor for the VTT LDO is the CL05A106MP5NUNC from Samsung (10-µF, 0402, 10-V, ±20%, or
similar capacitor).
The remaining LDOs must have input and output capacitors chosen based on the values in Section 4.9.
6.2.1.3
Application Curves
FET = CSD87588N
L = PIMB062D-R22ms
COUT = 2 × 300 µF + 1 × 22 µF
Figure 6-4. BUCK2 Controller Load Transient
6.2.1.4
L = PIFE32251B-R47ms
COUT = 4 × 22 µF
Figure 6-5. BUCK3 Converter Load Transient
Layout
6.2.1.4.1 Layout Guidelines
For a detailed description regarding layout recommendations, refer to the TPS65086x Design Guide and
to the TPS65086x Schematic and Layout Checklist. For all switching power supplies, the layout is an
important step in the design, especially at high peak currents and high switching frequencies. If the layout
is not carefully done, the regulator can have stability problems and EMI issues. Therefore, use wide and
short traces for the main current path and for the power ground tracks. The input capacitors, output
capacitors, and inductors must be placed as close as possible to the device. Use a common-ground node
for power ground and use a different, isolated node for control ground to minimize the effects of ground
noise. Connect these ground nodes close to the AGND pin by one or two vias. Use of the design guide is
highly encouraged in addition to the following list of other basic requirements:
• Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.
• To ensure proper sensing based on FET RDSON, PGNDSNSx must not connect to PGND until very
close to the PGND pin of the FET.
• All inductors, input and output capacitors, and FETs for the converters and controller must be on the
same board layer as the IC.
• To achieve the best regulation performance, place feedback connection points near the output
capacitors and minimize the control feedback loop as much as possible.
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•
•
•
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Bootstrap capacitors must be placed close to the device.
The internal reference regulators must have their input and output capacitors placed close to the
device pins.
Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with
DRVLx, which provides optimal driver loops.
6.2.1.4.2 Layout Example
VREF Capacitor
BUCK2
BUCK3
BUCK5
BUCK4
VTT
BUCK6
BUCK1
Figure 6-6. EVM Layout Example With All Components on the Top Layer
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VIN 5-V Application
The PMIC can be operated by a 5-V input voltage to the system because the power path of the controller
does not go through the device itself. The concept is simple: supply the controller VINs with the 5-V input,
and supply the VSYS with a 5.8-V step-up of the 5 V with a boost or charge pump. The 5.8 V is
recommended because the UVLO of the internal LDO5 is at 5.6 V and the device measures the voltage at
VSYS and determines the optimum internal compensation and controller settings thus, it is ideal the VSYS
be close to the VIN of the controllers.
PMIC
5V Supply
VIN
Example SoC
BUCK1
EXT FET
VIN
VCORE
BUCK2
EXT FET
VGPU
PLATFORM
BUCK3 3.5A
VCCIO
BUCK4 3A
VCPU1
BUCK5 3A
VCPU2
Note: An LDO or Buck
Can Supply the VPP
Rail if Needed for DDR.
VDDQ, VDD1&2
VDDQ, VDD1&2
VREF, VTT
VREF, VTT
DDR
DDR
VIN
BUCK6
EXT FET
VTT LDO ±0.5A
LDO5V or
5V Supply
LDOA1 0.2A
VSUPP1
LDOA2 0.6A
VSUPP2
LDOA3 0.6A
VSUPP3
Input up to 3.3V
SWA1 0.3A
VSUPP4
Input up to 3.3V
SWB1 0.3A
VSUPP5
SWB2 0.3A
VSUPP6
1.8V
VIN
Supply Diode Needed if
Charge Pump or
Pre-bias is Not Supported
Boost
VSYS = Vout Vf
40 mA ± 440 mA
5V
LDO5V
VSYS
LDO5
5V
PG_5V
CTL1
LDO3P3
IRQB
CTL2
GPO1
CTL3
GPO2
CTL4
GPO3
CTL5
GPO4
CTL6
DATA
SCLK
Copyright © 2017, Texas Instruments Incorporated
Figure 6-7. VIN 5-V Application
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Design Requirements
The PMIC requires a step-up voltage from the 5-V input to 5.8 V for the VSYS supply. TI recommends
keeping the VSYS near 5.8 V for optimization of the controllers.
Depending on the application use cases, the supply current to the VSYS can require from 40 mA with the
drivers being supplied by the 5-V input to 440 mA with the drivers being supplied by the LDO5 and the
LDOA1 being operated at max loading. This means that a charge pump may be used in some applications
like the 5-V input but in others, a small boost may be required.
A Schottky diode from the 5-V input to the VSYS is recommended to ensure the VSYS is biased and the
internal reference LDOs are on before the step-up regulator is enabled or fully ramped up. If the step-up
cannot tolerate pre-bias condition then, 2 diodes may be needed to prevent the initial 5-V supply biasing
the output of the step-up.
6.2.2.2
Design Procedure
To design a 5-V input application, first provide a step-up voltage from the 5-V input to the VSYS. Design
the step-up to output a voltage near 5.8 V. Next, route the 5-V input to the controller and converter VINs.
Thus, all power paths (all high currents) are routed through the controllers or directly to the converters.
None of the high currents are required from the step-up supply. After the input stage is complete, the rest
of the system can be designed as normal following the typical application procedure, using 5 V as the
input value to the controllers.
6.2.2.3
Application Curves
100%
100%
95%
95%
90%
90%
85%
80%
80%
Efficiency
Efficiency (%)
85%
75%
70%
75%
70%
65%
60%
65%
55%
Vout = 1 V
Vout = 1.8 V
Vout = 2.5 V
Vout = 3.3 V
60%
55%
50%
0.1
0.2
0.3 0.40.5 0.7 1
Iout (A)
2
3
VOUT = 1 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
50%
45%
4 5 6 7
40%
0.1
0.2
D010
FET = CSD87381P L = PIMB061H-R47ms
Figure 6-8. BUCK1 Efficiency at VIN = 5 V in Auto Mode
0.3 0.40.5 0.7 1
Load (A)
FET = CSD87381P
2
3
4 5 6 7
tps6
L = PIMB061H-R47ms
Figure 6-9. Example BUCK1 Efficiency at VIN = 5 V in Forced
PWM Mode
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Power Supply Coupling and Bulk Capacitors
This device is designed to work with several different input voltages. The minimum voltage on the VSYS
pin is 5.6 V for the device to start up; however, this is a low power rail. The input to the FETs must be
from 4.5 V to 21 V as long as the proper BOM choices are made. Input to the converters should be
between 3.3 V and 5 V. For the device to output maximum power, the input power must be sufficient. For
the controllers, VIN must be able to supply sufficient input current for the output power of the application.
For the converters, PVINx must be able to typically supply 2 A.
A best practice here is to determine power usage by the system and back-calculate the necessary power
input based on expected efficiency values.
6.4
Do's and Don'ts
•
•
•
•
•
•
134
Connect the LDO5V output to the DRV5V_x_x inputs for situations where an external 5-V supply is not
initially available or is not available the entire time PMIC is on. If the external 5-V supply is always
present, then DRV5V_x_x can be directly connected to remove the V5ANA-to-LDO5P0 load switch
RDSON.
Ensure that none of the control pins are potentially floating.
Include 0-Ω resistors on the DRVH or BOOT pins of controllers on prototype boards, which allows for
slowing the controllers if the system is unable to handle the noise generated by the large switching or if
switching voltage is too large due to layout.
Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here
causes reference circuits to regulate incorrectly.
Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may
turn on the HS FET passing the input to the output until VSYS is biased.
Do not change the values of the reserved bits when writing I2C. This can have unexpected
consequences. Expected values for each OTP are shown in the register map.
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7 Device and Documentation Support
7.1
7.1.1
Device Support
Development Support
For documentation related to device development see the following:
• Texas Instruments, TPS65086x Schematic and Layout Checklist
• Texas Instruments, TPS65086x Design Guide
7.2
7.2.1
Documentation Support
Related Documentation
For related documentation see the following:
• Texas Instruments, CSD85301Q2 20 V Dual N-Channel NexFET™ Power MOSFETs data sheet
• Texas Instruments, CSD87331Q3D Synchronous Buck NexFET™ Power Block data sheet
• Texas Instruments, CSD87588N Synchronous Buck NexFET™ Power Block II data sheet
• Texas Instruments, CSD87381P Synchronous Buck NexFET™ Power Block II data sheet
• Texas Instruments, CSD87350Q5D Synchronous Buck NexFET™ Power Block data sheet
• Texas Instruments, MSP430G2121 Mixed Signal Microcontroller data sheet
• Texas Instruments, Power management integrated buck controllers for distant point-of-load
applications white paper
• Texas Instruments, TPS65086x Evaluation Module user's guide
7.3
Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
7.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
7.5
Trademarks
D-CAP2, D-CAP, NexFET, E2E are trademarks of Texas Instruments.
NXP is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
136
Mechanical, Packaging, and Orderable Information
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Copyright © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65086100RSKR
ACTIVE
VQFN
RSK
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
T65086100
PG1.0
TPS65086100RSKT
ACTIVE
VQFN
RSK
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
T65086100
PG1.0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65086100RSKR
VQFN
RSK
64
2000
330.0
16.4
8.3
8.3
1.1
12.0
16.0
Q2
TPS65086100RSKT
VQFN
RSK
64
250
180.0
16.4
8.3
8.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jul-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65086100RSKR
VQFN
RSK
64
2000
367.0
367.0
38.0
TPS65086100RSKT
VQFN
RSK
64
250
210.0
185.0
35.0
Pack Materials-Page 2
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