Texas Instruments | UCC21520-Q1, UCC21520A-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver for Automotive (Rev. B) | Datasheet | Texas Instruments UCC21520-Q1, UCC21520A-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver for Automotive (Rev. B) Datasheet

Texas Instruments UCC21520-Q1, UCC21520A-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver for Automotive (Rev. B) Datasheet
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UCC21520-Q1
UCC21520A-Q1
SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
UCC21520-Q1, UCC21520A-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver for
Automotive
1 Features
3 Description
•
•
The UCC21520-Q1 is an isolated dual-channel gate
drivers with 4-A source and 6-A sink peak current. It
is designed to drive power MOSFETs, IGBTs, and
SiC MOSFETs up to 5-MHz with best-in-class
propagation delay and pulse-width distortion.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
Universal: Dual Low-Side, Dual High-Side or HalfBridge Driver
Operating Temperature Range –40 to +125°C
Switching Parameters:
– 19-ns Typical Propagation Delay
– 10-ns Minimum Pulse Width
– 5-ns Maximum Delay Matching
– 6-ns Maximum Pulse-Width Distortion
Common-Mode Transient Immunity (CMTI)
Greater than 100 V/ns
Surge Immunity up to 12.8 kV
Isolation Barrier Life >40 Years
4-A Peak Source, 6-A Peak Sink Output
TTL and CMOS Compatible Inputs
3-V to 18-V Input VCCI Range to Interface with
Both Digital and Analog Controllers
Up to 25-V VDD Output Drive Supply
– 5-V and 8-V VDD UVLO Options
Programmable Overlap and Dead Time
Rejects Input Pulses and Noise Transients
Shorter than 5 ns
Fast Disable for Power Sequencing
Safety-Related Certifications:
– 8000-VPK Reinforced Isolation per DIN V VDE
V 0884-11:2017-01
– 5.7-kVRMS Isolation for 1 Minute per UL 1577
– CSA Certification per IEC 60950-1, IEC 623681, IEC 61010-1 and IEC 60601-1 End
Equipment Standards
– CQC Certification per GB4943.1-2011
2 Applications
•
•
•
•
HEV and BEV Battery Chargers
Isolated Converters in DC-DC and AC-DC Power
Supplies
Motor Drive and DC-to-AC Solar Inverters
Uninterruptible Power Supply (UPS)
The input side is isolated from the two output drivers
by a 5.7-kVRMS reinforced isolation barrier, with a
minimum of 100-V/ns common-mode transient
immunity (CMTI). Internal functional isolation between
the two secondary-side drivers allows a working
voltage of up to 1500 VDC.
Every driver can be configured as two low-side
drivers, two high-side drivers, or a half-bridge driver
with programmable dead time (DT). A disable pin
shuts down both outputs simultaneously, and allows
normal operation when left open or grounded. As a
fail-safe measure, primary-side logic failures force
both outputs low.
Each device accepts VDD supply voltages up to 25
V. A wide input VCCI range from 3 V to 18 V makes
the driver suitable for interfacing with both analog and
digital controllers. All supply voltage pins have under
voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21520-Q1
enables high efficiency, high power density, and
robustness.
Device Comparison(1)
PACKAGE
UVLO Level
UCC21520-Q1
PART NUMBER
DW SOIC (16)
8V
UCC21520A-Q1
DW SOIC (16)
5V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VCCI 3,8
16 VDDA
Driver
INA
1
DIS
5
NC
7
DT
6
MOD
DEMOD
Reinforced Isolation
1
Disable,
UVLO
and
Deadtime
UVLO
15 OUTA
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
Driver
INB
2
GND
4
MOD
DEMOD
UVLO
10 OUTB
9
VSSB
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
UCC21520-Q1
UCC21520A-Q1
SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety-Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 15
7.1
7.2
7.3
7.4
Propagation Delay and Pulse Width Distortion.......
Rising and Falling Time .........................................
Input and Disable Response Time..........................
Programable Dead Time ........................................
15
15
15
16
7.5 Power-up UVLO Delay to OUTPUT........................ 16
7.6 CMTI Testing........................................................... 17
8
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
23
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application .................................................. 26
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 41
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support .......................................
Certifications .........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
41
41
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2018) to Revision B
Page
•
Changed UCC21520A-Q1 Advance Information marketing status to initial release. ............................................................. 1
•
Added detailed description for DISABLE Pin and DT Pin ...................................................................................................... 3
•
Changed tPWD in the switching characteristic section. ............................................................................................................ 9
•
Added feature descriptions for UVLO delay to OUTPUT .................................................................................................... 16
•
Added bullet "It is recommended..." bullet to the component placement in the Layout Guidelines. ................................... 38
Changes from Original (October 2017) to Revision A
Page
•
Added UCC21520A-Q1 device (5V UVLO Option) in this datasheet .................................................................................... 1
•
Added UCC21520A-Q1 Advance Information. ....................................................................................................................... 1
•
Changed tPWD in the switching characteristic section. ............................................................................................................ 9
•
Added typical curves of 5-V UVLO hysteresis and ON-OFF thresholds .............................................................................. 12
2
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
INA
1
16
VDDA
INB
2
15
OUTA
VCCI
3
14
VSSA
GND
4
13
NC
DISABLE
5
12
NC
DT
6
11
VDDB
NC
7
10
OUTB
VCCI
8
9
VSSB
Not to scale
Pin Functions
PIN
NAME
DISABLE
NO.
5
I/O (1)
DESCRIPTION
I
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when
connecting to a micro controller with distance.
DT
6
I
Programmable dead time function.
Tying DT to VCCI allows the outputs to overlap. Leaving DT open sets the dead time to <15
ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time
according to: DT (in ns) = 10 x RDT (in kΩ). It is recommended to parallel a ceramic
capacitor, 2.2 nF or above, close to the DT pin with RDT to achieve better noise immunity.
GND
4
P
Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA
1
I
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
INB
2
I
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is
pulled low internally if left open. It is recommended to tie this pin to ground if not used to
achieve better noise immunity.
NC
7
–
No Internal connection.
NC
12
–
No internal connection.
NC
13
–
No internal connection.
OUTA
15
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB
10
O
Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI
3
P
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
VCCI
8
P
Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA
16
P
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
VDDB
11
P
Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor
located as close to the device as possible.
VSSA
14
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB
9
P
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1)
P =Power, G= Ground, I= Input, O= Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input bias pin supply voltage
VCCI to GND
–0.3
20
V
Driver bias supply
VDDA-VSSA, VDDB-VSSB
–0.3
30
V
OUTA to VSSA, OUTB to VSSB
–0.3
VVDDA+0.3,
VVDDB+0.3
V
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
–2
VVDDA+0.3,
VVDDB+0.3
V
INA, INB, DIS, DT to GND
–0.3
VVCCI+0.3
V
INA, INB Transient for 50ns
–5
VVCCI+0.3
V
Output signal voltage
Input signal voltage
Channel to channel voltage
Junction temperature, TJ
VSSA-VSSB, VSSB-VSSA
(2)
Storage temperature, Tstg
(1)
(2)
1500
V
–40
150
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±4000
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
3
18
V
UCC21520A-Q1 5-V UVLO version
6.5
25
V
UCC21520-Q1 8-V UVLO version
9.2
25
V
Ambient Temperature
–40
125
°C
Junction Temperature
–40
130
°C
VCCI
VCCI Input supply voltage
VDDA,
VDDB
Driver output bias supply
VDDA,
VDDB
Driver output bias supply
TA
TJ
4
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UNIT
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
6.4 Thermal Information
UCC21520-Q1
THERMAL METRIC (1)
DW-16 (SOIC)
UNIT
RθJA
Junction-to-ambient thermal resistance
67.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.4
°C/W
RθJB
Junction-to-board thermal resistance
32.1
°C/W
ψJT
Junction-to-top characterization parameter
18.0
°C/W
ψJB
Junction-to-board characterization parameter
31.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Ratings
PD
Power dissipation by UCC21520-Q1
PDI
Power dissipation by transmitter side of
UCC21520-Q1
PDA, PDB
Power dissipation by each driver side of
UCC21520-Q1
VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3 V,
3 MHz 50% duty cycle square wave 1-nF
load
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VALUE
UNIT
1.05
W
0.05
W
0.5
W
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6.6 Insulation Specifications
VALUE
UNIT
CLR
PARAMETER
External clearance (1)
Shortest pin-to-pin distance through air
TEST CONDITIONS
>8
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
>8
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 10.5 µm)
>21
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
V
Material group
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
I
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
VIOTM
Maximum transient isolation
voltage
VIOSM
Maximum surge isolation
voltage (3)
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB), test (See Figure 1)
1500
VRMS
DC voltage
2121
VDC
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
8000
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;
<5
Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s
Method a, After environmental tests subgroup 1.
Vini = VIOTM, tini = 60s;
Apparent charge (4)
qpd
<5
pC
Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s
Method b1; At routine
preconditioning (type test)
test
(100%
production)
and
<5
Vini = 1.2 × VIOTM; tini = 1s;
Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output (5)
VIO = 0.4 sin (2πft), f =1 MHz
1.2
VIO = 500 V at TA = 25°C
> 1012
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS =150°C
> 109
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Certified according to DIN V VDE V
0884-11:2017-01,
and DIN EN 60950-1 (VDE 0805
Teil 1):2014-08
Certified according to IEC 60950-1, IEC
62368-1, IEC 61010-1 and IEC 60601-1
Recognized under UL
1577 Component
Recognition Program
Certified according to GB
4943.1-2011
Reinforced Insulation Maximum
Transient Isolation voltage, 8000
VPK;
Maximum Repetitive Peak Isolation
Voltage, 2121 VPK;
Maximum Surge Isolation Voltage,
8000 VPK
Reinforced insulation per CSA 60950-107+A1+A2 and IEC 60950-1 2nd
Ed.+A1+A2, 800 VRMS maximum working
voltage (pollution degree 2, material group I)
Reinforced insulation per CSA 62368-1-14
and IEC 62368-1 2nd Ed., 800 VRMS
maximum working voltage (pollution degree
2, material group I);
Basic insulation per CSA 61010-1-12+A1
and IEC 61010-1 3rd Ed., 600 VRMS
maximum working voltage (pollution degree
2, material group III);
2 MOPP (Means of Patient Protection) per
CSA 60601- 1:14 and IEC 60601-1
Ed.3+A1, 250 VRMS maximum working
voltage
Single protection, 5700
VRMS
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate 660 VRMS
maximum working voltage
Certification number: 40040142
Master contract number : 220991
File number: E181974
Certificate number:
CQC16001155011
6.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
RθJA = 67.3ºC/W, VDDA/B = 12 V, TA =
25°C, TJ = 150°C
IS
Safety output supply
current
Safety supply power
TS
Safety temperature (1)
(1)
MIN
TYP
MAX
UNIT
DRIVER A,
DRIVER B
75
mA
DRIVER A,
DRIVER B
36
mA
INPUT
50
RθJA = 67.3ºC/W, TA = 25°C, TJ = 150°C
DRIVER A
900
See Figure 3
DRIVER B
900
TOTAL
1850
See Figure 2
RθJA = 67.3ºC/W, VDDA/B = 25 V, TA =
25°C, TJ = 150°C
See Figure 2
PS
SIDE
150
mW
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current
VINA = 0 V, VINB = 0 V
1.0
1.8
mA
IVCCI
VCCI operating current
(f = 500 kHz) current per channel,
COUT = 100 pF
2.0
mA
IVDDA,
IVDDB
VDDA and VDDB operating current
(f = 500 kHz) current per channel,
COUT = 100 pF
2.5
mA
VCCI UVLO THRESHOLDS
VVCCI_ON
Rising threshold
2.55
2.7
2.85
V
VVCCI_OFF
Falling threshold VCCI_OFF
2.35
2.5
2.65
V
VVCCI_HYS
Threshold hysteresis
0.2
V
UCC21520A-Q1 VDD UVLO THRESHOLDS (5-V UVLO Version)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
5.7
6.0
6.3
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
5.4
5.7
6
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.3
V
UCC21520-Q1 VDD UVLO THRESHOLDS (8-V UVLO Version)
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
8.3
8.7
9.2
V
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
7.8
8.2
8.7
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
0.5
V
INA, INB AND DISABLE
VINAH, VINBH,
VDISH
Input high voltage
1.6
1.8
2
V
VINAL, VINBL,
VDISL
Input low voltage
0.8
1
1.2
V
VINA_HYS,
VINB_HYS,
VDIS_HYS
Input hysteresis
VINA, VINB
Negative transient, ref to GND, 50
ns pulse
8
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0.8
Not production tested, bench test
only
–5
V
V
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
IOA+, IOB+
Peak output source current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
4
A
IOA-, IOB-
Peak output sink current
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
6
A
ROHA, ROHB
Output resistance at high state
IOUT = –10 mA, TA = 25°C, ROHA,
ROHB do not represent drive pullup performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
Output resistance at low state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VOHA, VOHB
Output voltage at high state
VVDDA, VVDDB = 12 V, IOUT = –10
mA, TA = 25°C
11.95
V
VOLA, VOLB
Output voltage at low state
VVDDA, VVDDB = 12 V, IOUT = 10
mA, TA = 25°C
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
Pull DT pin to VCCI
DT pin is left open, min spec
characterized only, tested for
outliers
Dead time
RDT = 20 kΩ
Overlap determined by INA INB
0
160
-
8
15
ns
200
240
ns
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
tRISE
Output rise time, 20% to 80%
measured points
COUT = 1.8 nF
tFALL
Output fall time, 90% to 10%
measured points
COUT = 1.8 nF
tPWmin
Minimum pulse width
tPDHL
Propagation delay from INx to OUTx
falling edges
tPDLH
Propagation delay from INx to OUTx
rising edges
tPWD
Pulse width distortion |tPDLH – tPDHL|
tDM
Propagation delays matching
between VOUTA, VOUTB
f = 100 kHz
|CMH|
High-level common-mode transient
immunity
INA and INB both are tied to VCCI;
VCM=1500V; (See CMTI Testing)
100
|CML|
Low-level common-mode transient
immunity
INA and INB both are tied to GND;
VCM=1500V; (See CMTI Testing)
100
TYP
MAX
6
16
ns
7
12
ns
20
ns
19
30
ns
19
30
ns
6
ns
5
ns
Output off for less than minimum,
COUT = 0 pF
UNIT
V/ns
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6.11 Insulation Characteristics Curves
1.E+11
1.E+10
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
87.5%
1.E+9
Time to Fail (s)
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500
1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
100
2000
IVDDA/B for VDD=12V
IVDDA/B for VDD=25V
80
Safety Limiting Power (mW)
Safety Limiting Current per Channel (mA)
Figure 1. Reinforced Isolation Capacitor
Life Time Projection
60
40
20
0
1200
800
400
0
0
50
100
150
Ambient Temperature (°C)
200
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0
50
D001
Figure 2. Thermal Derating Curve for Safety-Related
Limiting Current
(Current in Each Channel with Both Channels Running
Simultaneously)
10
1600
100
150
Ambient Temperature (°C)
200
D001
Figure 3. Thermal Derating Curve for Safety-Related
Limiting Power
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6.12 Typical Characteristics
20
50
16
40
Current (mA)
Current (mA)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
12
8
4
30
20
10
VDD=12v
VDD=25v
VDD= 12V
VDD= 25V
0
0
0
800
1600
2400
3200
Frequency (kHz)
4000
4800
5600
0
Figure 4. Per Channel Current Consumption vs. Frequency
(No Load, VDD = 12 V or 25 V)
1000
1500
2000
Frequency (kHz)
2500
3000
D001
Figure 5. Per Channel Current Consumption (IVDDA/B) vs.
Frequency (1-nF Load, VDD = 12 V or 25 V)
6
30
50kHz
250kHz
500kHz
1MHz
5
VDD Current (mA)
24
Current (mA)
500
D001
18
12
6
4
3
2
1
VDD= 12V
VDD= 25V
0
10
25
40
55
70
Frequency (kHz)
85
0
-40
100
Figure 6. Per Channel Current Consumption (IVDDA/B) vs.
Frequency (10-nF Load, VDD = 12 V or 25 V)
0
20
2
2
1.6
1.8
1.2
0.8
0.4
40
60
80 100
Temperature (qC)
140
160
D001
1.6
1.4
1.2
VDD= 12V
VDD= 25V
0
-40
120
Figure 7. Per Channel (IVDDA/B) Supply Current Vs.
Temperature (No Load, Different Switching Frequencies)
Current (mA)
Current (mA)
-20
D001
-20
0
20
40
60
80
Temperature (qC)
100
120
VCCI= 3.3V
VCCI= 5V
140
1
-40
-20
0
D001
Figure 8. Per Channel (IVDDA/B) Quiescent Supply Current vs
Temperature (No Load, Input Low, No Switching)
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 9. IVCCI Quiescent Supply Current vs Temperature
(No Load, Input Low, No Switching)
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Typical Characteristics (continued)
25
10
20
8
Resistance (:)
Time (ns)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
15
10
5
6
Output Pull-Up
Output Pull-Down
4
2
tRISE
tFALL
0
0
2
4
6
8
0
-40
10
Load (nF)
Figure 10. Rising and Falling Times vs. Load (VDD = 12 V)
0
28
20
24
19
20
16
20
40
60
80
Temperature (qC)
12
140
D001
17
16
8
-40
Rising Edge (tPDLH)
Falling Edge (tPDHL)
15
-20
0
20
40
60
80
Temperature (qC)
100
120
140
3
6
9
12
15
VCCI (V)
D001
Figure 12. Propagation Delay vs. Temperature
18
D001
Figure 13. Propagation Delay vs. VCCI
5
5
Propagation Delay Matching (ns)
Pulse Width Distortion (ns)
120
18
Rising Edge (tPDLH)
Falling Edge (tPDHL)
3
1
-1
-3
-5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
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2.5
0
-2.5
Rising Edge
Falling Edge
-5
10
13
D001
Figure 14. Pulse Width Distortion vs. Temperature
12
100
Figure 11. Output Resistance vs. Temperature
Propagation Delay (ns)
Propagation Delay (ns)
-20
D001
16
19
VDDA/B (V)
22
25
D001
Figure 15. Propagation Delay Matching (tDM) vs. VDD
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Typical Characteristics (continued)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
350
330
2.5
Hysteresis (mV)
Propagation Delay Matching (ns)
5
0
310
290
-2.5
270
Rising Edge
Falling Edge
-5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
250
-40
140
-20
0
20
D001
Figure 16. Propagation Delay Matching (tDM) vs.
Temperature
40
60
80
Temperature (qC)
100
120
140
D001
Figure 17. VDD 5-V UVLO Hysteresis vs. Temperature
550
6.5
6
Hysterisis (mV)
UVLO Threshold (V)
530
5.5
510
490
470
VVDD_ON
VVDD_OFF
5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
450
-40
140
Figure 18. VDD 5-V UVLO Threshold vs. Temperature
0
20
900
9
860
8
7
40
60
80
Temperature (qC)
100
820
780
VCC=3.3V
VCC=5V
VCC=12V
VVDDA_ON
VVDDA_OFF
5
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
700
-40
-20
0
D001
Figure 20. VDD 8-V UVLO Threshold vs. Temperature
140
D001
740
6
120
Figure 19. VDD 8-V UVLO Hysteresis vs. Temperature
10
IN/DIS Hysterisis (V)
UVLO Threshold (V)
-20
D001
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 21. IN/DIS Hysteresis vs. Temperature
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Typical Characteristics (continued)
1.2
2
1.14
1.92
IN/DIS High Threshold (V)
IN/DIS Low Threshold (V)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
1.08
1.02
0.96
0.9
-40
1.84
1.76
1.68
VCC=3.3V
VCC= 5V
VCC=12V
-20
0
20
40
60
80
Temperature (qC)
100
120
1.6
-40
140
VCC=3.3V
VCC= 5V
VCC=12V
-20
0
20
D001
Figure 22. IN/DIS Low Threshold
40
60
80
Temperature (qC)
100
120
140
D001
Figure 23. IN/DIS High Threshold
5
1500
1200
-6
900
-17
'DT (ns)
Dead Time (ns)
RDT= 20k:
RDT= 100k:
600
-28
-39
300
RDT= 20k:
RDT = 100k:
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
-50
-40
140
-20
0
20
D001
Figure 24. Dead Time vs. Temperature (with RDT = 20 kΩ and
100 kΩ)
40
60
80
Temperature (qC)
100
120
140
D001
Figure 25. Dead Time Matching vs. Temperature (with RDT =
20 kΩ and 100 kΩ)
18
14
Voltage (V)
10
6
2
-2
1 nF Load
10 nF Load
-6
0
100
200
300
400
500
Time (ns)
600
700
800
D001
Figure 26. Typical Output Waveforms
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7 Parameter Measurement Information
7.1 Propagation Delay and Pulse Width Distortion
Figure 27 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the propagation
delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the dead
time function by shorting the DT Pin to VCC.
INA/B
tPDHLA
tPDLHA
tDM
OUTA
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB
Figure 27. Overlapping Inputs, Dead Time Disabled
7.2 Rising and Falling Time
Figure 28 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how
short rising and falling times are achieved see Output Stage
80%
tRISE
90%
tFALL
20%
10%
Figure 28. Rising and Falling Time Criteria
7.3 Input and Disable Response Time
Figure 29 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low
ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more
information, see Disable Pin .
INA
DIS High
Response Time
DIS
DIS Low
Response Time
OUTA
90%
90%
tPDLH
tPDHL
10%
10%
10%
Figure 29. Disable Pin Timing
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7.4 Programable Dead Time
Leaving the DT pin open or tying it to GND through an appropriate resistor (RDT) sets a dead-time interval. For
more details on dead time, refer to Programmable Dead Time (DT) Pin.
INA
INB
90%
OUTA
10%
tPDHL
tPDLH
90%
OUTB
10%
tPDHL
Dead Time
(Set by RDT)
Dead Time
(Determined by Input signals if
longer than DT set by RDT)
Figure 30. Dead-Time Switching Parameters
7.5 Power-up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge
to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40us) and tVDD+ to OUT for VDD UVLO (typically
50us). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and
VDD bias supply is ready. Figure 31 and Figure 32 show the power-up UVLO delay timing diagram for VCCI and
VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will
not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when
either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on
the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to
ensure safe operation during VCCI or VDD brownouts.
VCCI,
INx
VDDx
VVCCI_ON
VVCCI_OFF
VDDx
tVCCI+ to OUT
OUTx
VVDD_ON
tVDD+ to OUT
VVDD_OFF
OUTx
Figure 31. VCCI Power-up UVLO Delay
16
VCCI,
INx
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Figure 32. VDDA/B Power-up UVLO Delay
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7.6 CMTI Testing
Figure 33 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VCC
VCCI
GND
DIS
DT
VCCI
16
2
15
3
14
4
5
Reinforced Isolation
INB
1
Input Logic
INA
VDDA
OUTA
OUTA
VSSA
Functional
Isolation
11
6
10
8
9
VDDB
OUTB
OUTB
VSSB
GND
VSS
Common Mode Surge
Generator
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Figure 33. Simplified CMTI Testing Setup
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8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21520-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and
motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The UCC21520-Q1
has many features that allow it to integrate well with control circuitry and protect the gates it drives such as:
resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input
and output voltages. The UCC21520-Q1 also holds its outputs low when the inputs are left open or when the
input pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and
analog power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full
and independent control of each of the outputs.
8.2 Functional Block Diagram
INA
1
16 VDDA
200 k:
MOD
VCCI
Driver
DEMOD
15 OUTA
UVLO
GND
4
DT
6
DIS
5
UVLO
Reinforced Isolation
VCCI 3,8
Deadtime
Control
14 VSSA
13 NC
Functional Isolation
12 NC
11 VDDB
200 k:
MOD
INB
Driver
DEMOD
UVLO
2
10 OUTB
9
VSSB
200 k:
NC
7
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8.3 Feature Description
8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC21520-Q1 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output low, regardless of
the status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 34 ). In this condition,
the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through
RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.5 V, when no bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
Figure 34. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is
bound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21520-Q1 also has an internal under voltage lock out (UVLO) protection feature. The
device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal will cease to be
delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO for VDD, there is
hystersis (VVCCI_HYS) to ensure stable operation.
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Feature Description (continued)
All versions of the UCC21520-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.
Table 1. UCC21520-Q1 VCCI UVLO Feature Logic
CONDITION
INPUTS
OUTPUTS
INA
INB
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
H
L
L
L
VCCI-GND < VVCCI_ON during device start up
L
H
L
L
VCCI-GND < VVCCI_ON during device start up
H
H
L
L
VCCI-GND < VVCCI_ON during device start up
L
L
L
L
VCCI-GND < VVCCI_OFF after device start up
H
L
L
L
VCCI-GND < VVCCI_OFF after device start up
L
H
L
L
VCCI-GND < VVCCI_OFF after device start up
H
H
L
L
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
Table 2. UCC21520-Q1 VDD UVLO Feature Logic
CONDITION
20
INPUTS
OUTPUTS
INA
INB
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
H
L
L
L
VDD-VSS < VVDD_ON during device start up
L
H
L
L
VDD-VSS < VVDD_ON during device start up
H
H
L
L
VDD-VSS < VVDD_ON during device start up
L
L
L
L
VDD-VSS < VVDD_OFF after device start up
H
L
L
L
VDD-VSS < VVDD_OFF after device start up
L
H
L
L
VDD-VSS < VVDD_OFF after device start up
H
H
L
L
VDD-VSS < VVDD_OFF after device start up
L
L
L
L
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8.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up. See VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes.
Table 3. INPUT/OUTPUT Logic Table (1)
INPUTS
INA
INB
L
L
L
DISABLE
OUTPUTS
NOTE
OUTA
OUTB
L or Left Open
L
L
H
L or Left Open
L
H
H
L
L or Left Open
H
L
H
H
L or Left Open
L
L
DT is left open or programmed with RDT
DT pin pulled to VCCI
If Dead Time function is used, output transitions occur after the
dead time expires. See Programmable Dead Time (DT) Pin
H
H
L or Left Open
H
H
Left Open
Left Open
L or Left Open
L
L
-
X
X
H
L
L
-
(1)
"X" means L, H or left open.
8.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC21520-Q1 are based on a TTL and CMOS compatible inputthreshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logiclevel control signals (Such as those from 3.3-V micro-controllers), since the UCC21520-Q1 has a typical high
threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see
Figure 22,Figure 23). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable operation. If
any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically
200 kΩ (See Functional Block Diagram). However, it is still recommended to ground an input if it is not being
used.
Since the input side of the UCC21520-Q1 is isolated from the output drivers, the input signal amplitude can be
larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility
when integrating with control signal sources, and allows the user to choose the most efficient VDD for their
chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than
VCCI.
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8.3.4 Output Stage
The UCC21520-Q1 output stages feature a pull-up structure which delivers the highest peak-source current
when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power
switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel
MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to
provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning
on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The onresistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21520-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter. Therefore, the value of ROH belies the fast nature of the UCC21520-Q1's turn-on time.
The pull-down structure in the UCC21520-Q1 is simply composed of an N-channel MOSFET. The ROL
parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the
device. Both outputs of the UCC21520-Q1 are capable of delivering 4-A peak source and 6-A peak sink current
pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out
stage which delivers very low drop-out.
VDD
ROH
Input
Signal
ShootThrough
Prevention
Circuitry
RNMOS
OUT
Pull Up
ROL
VSS
Figure 35. Output Stage
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8.3.5 Diode Structure in the UCC21520-Q1
Figure 36 illustrates the multiple diodes involved in the ESD protection components of the UCC21520-Q1. This
provides a pictorial representation of the absolute maximum rating for the device.
VCCI
VDDA
3,8
16
30 V
20 V
INA
1
INB
2
DIS
5
DT
6
20 V
30 V
4
9
GND
VSSB
15
OUTA
14
VSSA
11
VDDB
10
OUTB
Figure 36. ESD Structure
8.4 Device Functional Modes
8.4.1 Disable Pin
Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE pin
allows the UCC21520-Q1 to operate normally. The DISABLE response time is in the range of 20ns and quite
responsive , which is as fast as propagation delay. The DISABLE pin is only functional (and necessary) when
VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DISABLE pin is not used
to achieve better noise immunity, and it is recommended to bypass using a ≈1nF low ESR/ESL capacitor close to
DIS pin when connecting DIS pin to a micro controller with distance.
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Device Functional Modes (continued)
8.4.2 Programmable Dead Time (DT) Pin
The UCC21520-Q1 allows the user to adjust dead time (DT) in the following ways:
8.4.2.1 Tying the DT Pin to VCC
Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.
8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
If the DT pin is left open, the dead time duration (tDT) is set to <15 ns. One can program tDT by placing a resistor,
RDT, between the DT pin and GND. The appropriate RDT value can be determined from from Equation 1, where
RDT is in kΩ and tDT is in ns:
tDT » 10 ´ RDT
(1)
The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when
RDT=100kΩ. Therefore, It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to the chip with
RDT to achieve better noise immunity and better deadtime matching between two channels, especially when the
dead time is larger than 300ns. The major consideration is that the current through the RDT is used to set the
dead time, and this current decreases as RDT increases.
An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead
time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.
If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent
shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead
time logic operating conditions are illustrated and explained in Figure 37:
INA
INB
DT
OUTA
OUTB
A
B
C
D
E
F
Figure 37. Input and Output Logic Relationship With Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,
when INA goes high, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it
immediately sets OUTB high.
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Device Functional Modes (continued)
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls
OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to
OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls
OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to
OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21520-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal
capability of the UCC21520-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a
low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With
integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching
performance; the UCC21520-Q1 enables designers to build smaller, more robust designs for enterprise, telecom,
automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in Figure 38 shows a reference design with the UCC21520-Q1 driving a typical half-bridge
configuration which could be used in several popular power converter topologies such as synchronous buck,
synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VDD
VCC
RBOOT
HV DC-Link
VCC
INA
PWM-A
1
16
2
15
RIN
CIN
VCCI
PC
CVCC
GND
Analog
or
Digital
DIS
Disable
RDIS
CDIS
CDT
•2.2nF
RDT
DT
VCCI
3
4
5
6
8
ROFF
RON
OUTA
CIN
RGS
CBOOT
VSSA
Reinforced Isolation
PWM-B
Input Logic
INB
VDDA
14
SW
Functional
Isolation
VDD
11
10
VDDB
ROFF
RON
OUTB
VSSB
CVDD
RGS
9
VSS
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Figure 38. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 4 lists reference design parameters for the example application: UCC21520-Q1 driving 1200-V SiCMOSFETs in a high side-low side configuration.
Table 4. UCC21520-Q1 Design Requirements
PARAMETER
VALUE
UNITS
Power transistor
C2M0080120D
-
VCC
5.0
V
VDD
20
V
Input signal amplitude
3.3
V
Switching frequency (fs)
100
kHz
DC link voltage
800
V
9.2.2 Detailed Design Procedure
9.2.2.1 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.2 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 800
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
VDD VBDF 20V 2.5V
| 8A
IDBoot pk
RBoot
2.2:
where
•
VBDF is the estimated bootstrap diode forward voltage drop at 8 A.
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9.2.2.3 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1.
Limit ringing caused by parasitic inductances/capacitances.
2.
Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3.
Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4.
Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC21520-Q1 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
§
·
VDD VBDF
min ¨ 4A,
¸
¨
RNMOS || ROH RON RGFET _ Int ¸¹
©
IOA
§
VDD
min ¨ 4A,
¨
R
||
R
RON
NMOS
OH
©
IOB
(3)
·
¸
RGFET _ Int ¸¹
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(4)
In this example:
VDD VBDF
RNMOS || ROH RON RGFET _ Int
IOA
IOB
RNMOS || ROH
VDD
RON
RGFET _ Int
20V 0.8V
| 2.4A
1.47: || 5: 2.2: 4.6:
(5)
20V
1.47: || 5: 2.2:
(6)
4.6:
| 2.5A
Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
§
·
VDD VBDF VGDF
min ¨ 6A,
¸
¨
ROL ROFF || RON RGFET _ Int ¸¹
©
IOA
§
min ¨ 6A,
¨
ROL
©
IOB
(7)
·
VDD VGDF
¸
ROFF || RON RGFET _ Int ¸¹
where
•
•
•
28
ROFF: External turn-off resistance;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(8)
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In this example,
IOA
ROL
IOB
ROL
VDD VBDF VGDF
ROFF || R ON R GFET _ Int
VDD VGDF
ROFF || R ON RGFET _ Int
20V 0.8V 0.75V
| 3.6A
0.55: 0: 4.6:
(9)
20V-0.75V
| 3.7A
0.55: 0: 4.6:
(10)
Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.4 Estimate Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21520 -Q1 (PGD) and the
power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not
included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21520-Q1, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with
no load. In this example, VVCCI = 5 V and VVDD = 20 V. The current on each power supply, with INA/INB
switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI = 2.5 mA, and IVDDA = IVDDB = 1.5 mA. Therefore,
the PGDQ can be calculated with
PGDQ
VVCCI u IVCCI
VVDDA u IDDA
VVDDB u IDDB | 72mW
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW
2 u VDD u QG u fSW
where
•
QG is the gate charge of the power transistor.
(12)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW
2 u 20V u 60nC u 100kHz
240mW
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QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change
with different testing conditions. The UCC21520-Q1 gate driver loss on the output stage, PGDO, is part of PGSW.
PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss is
dissipated inside the UCC21520-Q1. If there are external turn-on and turn-off resistances, the total loss will be
distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pullup/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however,
it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
PGDO
PGSW §
ROH || RNMOS
u¨
¨
2
© ROH || RNMOS RON RGFET _ Int
ROL
ROL
ROFF || RON RGFET _ Int
·
¸
¸
¹
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520-Q1
gate driver loss can be estimated with:
PGDO
240mW §
5: || 1.47:
u¨
2
5
||
1.47
:
: 2.2: 4.6:
©
·
0.55:
¸ | 30mW
0.55: 0: 4.6: ¹
(15)
Case 2 - Nonlinear Pull-Up/Down Resistor:
PGDO
2 u fSW
TR _ Sys
ª
u « 4A u ³ VDD
0
¬«
TF _ Sys
VOUTA/B t dt
6A u
³
0
º
VOUTA/B t dt »
¼»
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pulldown based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21520Q1, PGD, is:
PGD
PGDQ
PGDO
(17)
which is equal to 102 mW in the design example.
9.2.2.5 Estimating Junction Temperature
The junction temperature (TJ) of the UCC21520-Q1 can be estimated with:
TJ = TC + Y JT ´ PGD
where
•
•
TC is the UCC21520-Q1 case-top temperature measured with a thermocouple or some other instrument, and
ΨJT is the Junction-to-top characterization parameter from the Thermal Information table.
(18)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package
Thermal Metrics application report.
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9.2.2.6 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
9.2.2.6.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
QTotal
QG
IVDD @100kHz No Load
fSW
60nC
1.5mA
100kHz
75nC
where
•
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
(19)
Therefore, the absolute minimum CBoot requirement is:
QTotal
'VVDDA
CBoot
75nC
0.5V
150nF
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
(20)
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot
1 )
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
NOTE
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
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9.2.2.6.3 Select a VDDB Capacitor
Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in
Figure 38) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current
for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If
the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,
with a value over 10 µF, should be used in parallel with CVDD.
9.2.2.7 Dead Time Setting Guidelines
For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor
is important for preventing shoot-through during dynamic switching.
The UCC21520-Q1 dead time specification in the electrical table is defined as the time interval from 90% of one
channel’s falling edge to 10% of the other channel’s rising edge (see
Figure 30). This definition ensures that the dead time setting is independent of the load condition, and
guarantees linearity through manufacture testing. However, this dead time setting may not reflect the dead time
in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off
resistor, DC-Link switching voltage/current, as well as the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC21520-Q1:
DTSetting
DTReq
TF _ Sys
TR _ Sys
TD on
where
•
•
•
•
•
DTsetting: UCC21520-Q1 dead time setting in ns, DTSetting = 10 × RDT(in kΩ).
DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough
margin, or ZVS requirement.
TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.
(22)
In the example, DTSetting is set to 250 ns.
It should be noted that the UCC21520-Q1 dead time setting is decided by the DT pin configuration (See
Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system
conditions. It is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with RDT to
achieve better noise immunity.
32
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UCC21520A-Q1
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
9.2.2.8 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
Figure 39 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
16
1
15
2
VDDA
ROFF
CA1
RZ
OUTA
25 V
+
VA
±
CIN
RON
4
5
6
8
Input Logic
3
Reinforced Isolation
CA2
VSSA
14
VZ = 5.1 V
SW
Functional
Isolation
11
10
VDDB
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
9
Figure 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: UCC21520-Q1 UCC21520A-Q1
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Figure 40 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
16
1
15
2
VDDA
CA1
OUTA
4
5
Input Logic
3
Reinforced Isolation
CA2
VSSA
14
HV DC-Link
ROFF
+
VA+
±
RON
CIN
+
VA±
Functional
Isolation
SW
11
6
10
8
9
VDDB
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
Figure 40. Negative Bias with Two Iso-Bias Power Supplies
34
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The last example, shown in Figure 41, is a single power supply configuration and generates negative bias
through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and
the bootstrap power supply can be used for the high side drive. This design requires the least cost and design
effort among the three solutions. However, this solution has limitations:
1.
The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which means the negative bias
voltage will change when the duty cycle changes. Therefore, converters with a fixed duty cycle (~50%) such as variable frequency
resonant convertors or phase shift convertors favor this solution.
2.
The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range, which means the low side
switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to
refresh the bootstrap capacitor. Therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply
for the high side, like in the other two example circuits.
VDD
RBOOT
HV DC-Link
1
16
2
15
VDDA
Reinforced Isolation
5
Input Logic
4
VZ
OUTA
ROFF
RON
CBOOT
VSSA
3
CZ
CIN
RGS
14
SW
Functional
Isolation
VDD
11
6
10
VDDB
CZ
VZ
OUTB
CVDD
VSSB
8
ROFF
RON
RGS
9
VSS
Copyright © 2017, Texas Instruments Incorporated
Figure 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: UCC21520-Q1 UCC21520A-Q1
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9.2.3 Application Curves
Figure 42 and Figure 43 shows the bench test waveforms for the design example shown in Figure 38 under
these conditions: VCC = 5 V, VDD = 20 V, fSW = 100 kHz, VDC-Link = 0 V.
Channel 1 (Yellow): UCC21520-Q1 INA pin signal.
Channel 2 (Blue): UCC21520-Q1 INB pin signal.
Channel 3 (Pink): Gate-source signal on the high side power transistor.
Channel 4 (Green): Gate-source signal on the low side power transistor.
In Figure 42, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on the
power transistor have a 250-ns dead time, shown in the measurement section of Figure 42. The dead-time
matching is less than 1 ns with the 250-ns dead-time setting.
Figure 43 shows a zoomed-in version of the waveform of Figure 42, with measurements for propagation delay
and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is
measured between the power transistors’ gate and source pins, and is not measured directly from the driver
OUTA and OUTB pins. Due to the split on and off resistors (Ron,Roff) and different sink and source currents,
different rising (16 ns) and falling time (9 ns) are observed in Figure 43.
Figure 42. Bench Test Waveform for INA/B and OUTA/B
36
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Figure 43. Zoomed-In bench-test waveform
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UCC21520A-Q1
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
10 Power Supply Recommendations
The recommended input supply voltage (VCCI) for the UCC21520-Q1 is between 3 V and 18 V. The output bias
supply voltage (VDDA/VDDB) range depends on which version of UCC21520-Q1 one is using. The lower end of
this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each
device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on
UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends
on the maximum gate voltage of the power device being driven by the UCC21520-Q1. The UCC21520-Q1 have
a recommended maximum VDDA/VDDB of 25 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further
suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional
≤100-nF capacitor in parallel for high frequency filtering.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of the UCC21520-Q1, this bypass capacitor has a
minimum recommended value of 100 nF.
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UCC21520A-Q1
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11 Layout
11.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520-Q1.
Below are some key points.
Component Placement:
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be minimized.
• It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of
the UCC21520-Q1.
• It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to
a µC with distance.
Grounding Considerations:
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSBreferenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
High-Voltage Considerations:
• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination
that may compromise the UCC21520-Q1’s isolation performance.
• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could
operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB
layout between the high and low-side PCB traces.
Thermal Considerations:
• A large amount of power may be dissipated by the UCC21520-Q1 if the driving voltage is high, the load is
heavy, or the switching frequency is high (refer to Estimate Gate Driver Power Loss for more details). Proper
PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal
impedance (θJB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see Figure 45 and Figure 46). However, high voltage PCB
considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind
that there shouldn’t be any traces/coppers from different high voltage planes overlapping.
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
11.2 Layout Example
Figure 44 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 44. Layout Example
Figure 45 and Figure 46 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
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Product Folder Links: UCC21520-Q1 UCC21520A-Q1
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UCC21520-Q1
UCC21520A-Q1
SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
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Layout Example (continued)
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
Figure 45. Top Layer Traces and Copper
Figure 46. Bottom Layer Traces and Copper
Figure 47 and Figure 48 are 3D layout pictures with top view and bottom views.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
Figure 47. 3-D PCB Top View
40
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Figure 48. 3-D PCB Bottom View
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: UCC21520-Q1 UCC21520A-Q1
UCC21520-Q1
UCC21520A-Q1
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SLUSCQ2B – OCTOBER 2017 – REVISED JULY 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
12.2 Certifications
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate
Number: 20160516-E181974,
VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance
CQC
Online
Certifications
Number:CQC16001155011
Directory,
"GB4943.1-2011,
Digital
Isolator
Certificate"
Certificate
CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master
Contract Number:220991
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: UCC21520-Q1 UCC21520A-Q1
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UCC21520AQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21520AQ
UCC21520AQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21520AQ
UCC21520QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21520Q
UCC21520QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
UCC21520Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC21520-Q1 :
• Catalog: UCC21520
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC21520AQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
UCC21520QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC21520AQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
UCC21520QDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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