Texas Instruments | TPS63710 Low Noise Synchronous Inverting Buck Converter (Rev. A) | Datasheet | Texas Instruments TPS63710 Low Noise Synchronous Inverting Buck Converter (Rev. A) Datasheet

Texas Instruments TPS63710 Low Noise Synchronous Inverting Buck Converter (Rev. A) Datasheet
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TPS63710
SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
TPS63710 Low Noise Synchronous Inverting Buck Converter
1 Features
3 Description
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•
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The TPS63710 is an inverting step-down dc-dc
converter generating a negative output voltage down
to -5.5 V. It provides an output current up to 1 A,
depending on the input-voltage to output-voltage
ratio. Its filtered reference system gives low 1/f noise
which
is
required
in
high
performance
telecommunication systems.
1
3.1 V to 14 V Input Voltage Range
1 A Output Current
Up to 91% Efficiency
±1.5% Output Voltage Accuracy
Synchronous Rectification
Low 1/f-Noise Reference System
Noise: 22 µVRMS (10 Hz to 100 kHz)
Output Voltage: -1 V to -5.5 V
|VOUT| < 0.7 x VIN
1.5-MHz fixed frequency PWM mode
Thermal Shutdown
5-μA Shutdown Current
3-mm × 3-mm WSON Package
Create a Custom Design Using the TPS63710
With the WEBENCH® Power Designer
The TPS63710 operates with a fixed-frequency PWM
control topology. It has an internal current limit and a
thermal shutdown. The input voltage range of 3.1 V to
14 V allows the TPS63710 to be used in a variety of
applications where a negative output voltage is
generated from a, in absolute value, higher positive
input voltage.
Synchronous rectification provides high efficiency
especially for small output voltages like -1.8 V, which
are typically used as a negative supply voltage for
high performance DACs and ADCs. A fixed switching
frequency of 1.5 MHz allows the use of small external
components and enables a small total solution size.
2 Applications
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•
•
•
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Generic Negative Voltage Supply
ADC and DAC Supply in Telecom Systems
Bias for GaN transistors
Optical Module Laser Diode Bias
Noise Sensitive and Space Limited Applications
Requiring a Negative Supply Voltage
The TPS63710 comes in a 3-mm × 3-mm WSON
package that provides good thermal performance in
applications running at high ambient temperature.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS63710
WSON
3 mm x 3 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
TPS63710
VIN
VIN
CIN
CP
Efficiency vs output current for VOUT = -1.8V
CCP
100
L
EN
90
VOUT
SW
80
COUT
VOUT
CCAP
CAP
R1
FB
+V
CAUX
R2
VAUX
R3
PG
GND
Copyright © 2017, Texas Instruments Incorporated
Efficiency (%)
70
VREF
60
50
40
VIN = 4.5 V
VIN = 5 V
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
30
20
10
0
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS63710
SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
8.3 System Examples .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Original (September 2017) to Revision A
Page
•
Added Feature: Noise: 22 µVRMS (10 Hz to 100 kHz) ............................................................................................................ 1
•
Changed Figure 31 to Figure 34 ......................................................................................................................................... 18
•
Added Figure 35 and Figure 36 ........................................................................................................................................... 19
•
Changed Figure 41 .............................................................................................................................................................. 20
2
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5 Pin Configuration and Functions
8
VOUT
9
SW
10
GND
11
GND
VIN
12
CP
DRR Package
12-Pin WSON
Top View
7
6
CAP
5
FB
4
VREF
3
PG
2
EN
1
VAUX
Exposed Thermal Pad
Table 1. Pin Functions
Pin
I/O
Description
Name
No.
VIN
12
I
Power supply Input. Connect the input capacitor from this pin to GND and place it as close as
possible to the device pins.
VAUX
1
O
Connect the output capacitor of the internal voltage regulator from this pin to GND. VAUX can
be loaded externally with up to 100uA. Do not use this pin for any pulsed load to not couple
noise into the internal supply.
GND
10, 9
Ground Connection. Voltages and signals are referenced to this pin.
CP
11
O
Connect a capacitor from this pin to SW.
SW
8
O
Connect a capacitor from this pin to CP and the inductor from this pin to the output.
FB
5
I
Feedback pin for the voltage divider.
VOUT
7
I
Output voltage sense pin.
CAP
6
O
Reference system bypass capacitor connection. Do not tie anything other than a capacitor to
GND to this pin. Keep any noise sources away from this pin. The capacitor connected to this
pin forms a low-pass filter with an internal filter resistor and also defines the soft-start time.
VREF
4
O
Reference voltage output. Connect a voltage divider between this pin, FB and GND to set the
output voltage. Do not connect any other circuitry to this pin.
EN
2
I
Enable pin. The device is enabled when the pin is connected to a logic high level e.g. VIN. The
device is disabled when the pin is connected to a logic low level. The logic levels are
referenced to the IC´s GND pin.
PG
3
O
Open drain power good output. Connect with a pull-up resistor to a positive voltage up to 5.5 V.
If not used, leave open or connect to GND.
Exposed
Thermal Pad
-
-
The thermal pad must be tied to GND. The pad must be soldered to a GND plane to achieve an
appropriate thermal resistance and for mechanical reliability.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Voltage
(2)
PIN
MIN
MAX
UNIT
VIN, EN
-0.3
15
V
CP (DC)
-0.5
15
V
CP (AC, less than 10ns) (3)
-3
17
V
SW (DC)
-16
0.3
V
SW (AC, less than 10ns)
(3)
-20
1
V
VAUX, PG
-0.3
5.5
V
FB
-3.6
0.3
V
-6
0.3
V
-5.5
0.3
V
5
mA
VOUT
VREF, CAP
Sink Current
PG
Operating junction temperature, TJ
-40
150
°C
Storage temperature, Tstg
-65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND pin.
While switching
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
VIN
Supply Voltage Range
NOM
3.1
Supply voltage slew rate for a VIN step of less than 1V
Supply voltage slew rate for a VIN step of greater or equal than 1V
duty cycle ≤ 70%
MAX
UNIT
14
V
-1
1
V/µs
-0.1
0.1
V/µs
-1
0
IOUT
Output Current
L
Effective Inductance
1.5
2.2
6.2
µH
COUT
Effective Output Capacitance (1) for Tj = -20°C to 125°C
15
44
100
µF
COUT
Effective Output Capacitance (1) for Tj = -40°C to 125°C
22
44
100
µF
4
4.7
(3)
µF
0.08
0.22
1
µF
(1)
CIN
Effective Input Capacitance
CCP
Effective Capacitance on the CP pin required for full output current at ≤ 70% duty
cycle (1) (2)
CAUX
Effective Capacitance from VAUX pin to GND (1)
A
2 x CCP
(1)
µF
20
CCAP
Effective Capacitance from CAP pin to GND
0.01
10
µF
R
Total resistance for R1 + R2 from VREF to GND
100
500
kΩ
TJ
Operating Junction Temperature
-40
125
°C
(1)
(2)
(3)
The values given for all the capacitors are effective capacitance, which includes the dc bias effect. Especially the input capacitor CIN and
the CCP capacitor, which are charged to the input voltage, are strongly effected. Their effective capacitance is much lower based on the
dc voltage applied. Therefore, the nominal capacitor value needs to be larger than the minimum values given in the table. Please check
the manufacturer´s dc bias curves for the effective capacitance vs dc voltage applied.
If a maximum output current below 1A is required, the capacitance can be reduced accordingly. See the application section for details.
The maximum value also includes dc bias at the nominal operating voltage. During start-up when the voltage is 0 V, the effective
capacitance can be higher. Please see the application section for details.
6.4 Thermal Information
TPS63710
THERMAL METRIC (1)
DRR (WSON)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
44.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.7
°C/W
RθJB
Junction-to-board thermal resistance
18.9
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
19.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, over recommended input voltage range. Typical values are at VIN = 5 V and TJ = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I(Q)
Quiescent supply current
IOUT = 0mA, EN = high
ISD
Shutdown supply current
EN = low, TJ = -40°C to 85°C
ISD
Shutdown supply current
EN = low, TJ = -40°C to 125°C
Undervoltage lockout threshold
VIN falling, detected at VAUX
2.55
Undervoltage lockout hysteresis
VIN rising, detected at VAUX
250
Thermal shutdown temperature
Junction temperature rising
160
°C
Thermal shutdown hysteresis
Junction temperature falling
20
°C
VUVLO
TSD
15
(1)
5
(1)
2.6
mA
25
μA
55
μA
2.7
V
350
mV
CONTROL (EN, PG)
VIH
High level input voltage for EN
VIL
Low level input voltage for EN
1
IIN
Input current for EN
EN = high
0.01
RIN
Input resistance for EN
EN = low
400
PG de-glitch time
rising or falling
VOL_PG
PG output low voltage
IPG = 1 mA
ILKG_PG
Input leakage current (PG)
VPG = 5 V
VVAUX
Voltage at VAUX
VIN ≥ 5 V, IVAUX = 100 µA
IVAUX
Current drawn from VAUX
14
V
0.4
V
0.1
μA
kΩ
10
0.07
µs
0.3
V
100
nA
100
μA
3
A
4.6
0
V
POWER SWITCH
ILIM
Switch current limit (LSD)
4 V ≤ VIN < 14 V, duty cycle ≤ 70%
1.4
ILIM
Switch current limit (LSD)
3.1 V < VIN < 4 V, duty cycle ≤ 70%
0.8
RDS(ON)
Switch on-resistance
Maximum duty cycle
ton,min
Minimum on-time
fS
Switching frequency
A
HSD switch, VIN ≥ 5 V
80
130
LSD switch, VIN ≥ 5 V
120
190
40
80
RECT switch, VIN ≥ 5 V
DMAX
2.1
at SW pin
mΩ
70%
130
1400
1500
ns
1600
kHz
OUTPUT
VOUT
Output voltage range
VFB
FB regulation voltage
|VOUT| < 0.7 x VIN
-5.5
-1
V
-0.7 (2)
Output voltage tolerance
(3)
for VOUT ≤ –1.8 V
Output voltage tolerance
(3)
for –1.8 V < VOUT ≤ –1 V
IFB
Feedback input bias current
VFB = –0.7 V
RDIS
Discharge resistance from pin VOUT
to GND
EN = low
-1.5%
V
1.5%
-2%
1.5%
2
100
nA
100
Ω
Line regulation
0.05
%/A
Load regulation
0.02
%/V
tdelay
Start-up delay time from EN = high to
start switching
with CCP = 10 µF
5
ms
tramp
Ramp time from start switching until
device has reached 95% of its
nominal output voltage
CCAP = 47 nF, VOUT = -1.8 V, device
not in current limit during start-up
1
ms
Iramp
Soft-start current into CCAP
(1)
(2)
(3)
6
55
100
145
µA
This specification applies after there has been a high to low transition on EN. If EN is low while the supply voltage is applied, the
shutdown current can be up to 90µA.
Please see the application section for how to set the output voltage.
Tolerance of VFB voltage and error of gain stage - see also "Low Noise Reference System"
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6.6 Typical Characteristics
1
1
0.9
EN Threshold (V)
0.9
EN Threshold (V)
25 °C
85 °C
125 °C
–40 °C
0.8
0.7
0.6
25 °C
85 °C
125 °C
–40 °C
0.5
0.8
0.7
0.6
0.5
0.4
0.4
3
5
7
9
11
Input Voltage (V)
13
3
15
Figure 2. EN Threshold, rising VIN
9
11
Input Voltage (V)
13
15
D018
Figure 3. EN Threshold, falling VIN
90
25 °C
85 °C
125 °C
130
85
120
RDS(ON) (mΩ)
80
75
70
65
110
100
90
60
25 °C
85 °C
55
80
125 °C
–40 °C
70
50
3
5
7
9
11
Input Voltage (V)
13
3
15
5
7
D019
Figure 4. EN Threshold Hysteresis
9
11
Input Voltage (V)
13
15
D023
Figure 5. Resistance of HSD
180
80
25 °C
85 °C
125 °C
170
25 °C
85 °C
125 °C
75
160
70
RDS(ON) (mΩ)
RDS(ON) (mΩ)
7
140
95
EN Threshold Hysteresis (mV)
5
D020
150
140
130
65
60
55
120
50
110
45
100
40
3
5
7
9
11
Input Voltage (V)
13
15
3
D024
Figure 6. Resistance of LSD
5
7
9
11
Input Voltage (V)
13
15
D025
Figure 7. Resistance of RECT
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7 Detailed Description
7.1 Overview
The TPS63710 is a dc-dc converter that generates a negative output voltage using an inverting buck topology. It
operates with an input voltage range of 3.1 V to 14 V and generates a negative output voltage down to -5.5 V. As
it is based on a step-down topology, the input voltage needs to be larger than the negative voltage, in absolute
value, that is generated. The output is controlled by a fixed-frequency, pulse-width-modulated (PWM) regulator.
As there is an inductor in the output path, similar to a step-down converter, the output current is continuous and
the output voltage ripple is low. This makes this topology a perfect solution for noise sensitive applications.
7.2 Functional Block Diagram
SW
CP
VIN
RECT
HSD
Current
Sensor
LSD
Bias
Regulator
VAUX
-
Gate
Control
UVLO
+
_
VREF
+
VBG
FB
_
Modulator
100kΩ
gm
+
CAP
Soft-Start
PG
Oscillator
2.45kΩ
Device
Control
VOUT
+
100Ω
gm
EN
_
22kΩ
Thermal
Shutdown
/EN
GND
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Figure 8. Block Diagram
8
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7.3 Feature Description
7.3.1 Low Noise Reference System
The reference system in the TPS63710 uses an external filter capacitor on the CAP pin. This reduces the lowfrequency (1/f) noise in a range from a lower limit up to around 100kHz. The lower limit is defined by the corner
frequency of the RC filter from the internal 100-kΩ resistor and an external capacitor on the CAP pin. The corner
frequency is defined by Equation 1.
fc =
1
1
=
2p ´ R ´ C 2p ´100kW ´ CCAP
(1)
In order to minimize the noise on the output voltage, the TPS63710 uses an architecture where the output
voltage setting is done by changing the reference voltage which then is filtered. The gain stage therefore does
not have to have a large gain in order to not increase the noise level. VBG is the internal bandgap reference
voltage, optimized for low noise. Its output voltage is amplified and inverted and then filtered. The voltage on the
CAP pin is the reference for the gain stage. The connection from CAP to the external capacitor should be as
short as possible and be kept away from noisy traces. The gain stage has a small gain of 1/0.9. The voltage at
VREF is negative and lower than the output voltage by the gain factor of the gain stage. Please also see Setting
the Output Voltage. Figure 9 shows the low noise architecture.
VBG
+
VREF
CAP
gain =
internal
100kΩ
1
0.9
SW
L
CCAP
R1
COUT
FB
noise filter
gain stage
R2
VOUT
Copyright © 2017, Texas Instruments Incorporated
GND
Figure 9. Low Noise Architecture
7.3.2 Duty Cycle
The duty cycle referred to in this data sheet is the duty cycle at the SW pin. By definition, from the PWM
operation, the CP pin has the inverse duty cycle of 1-D. As a first approximation, the duty cycle is defined as
|VOUT| / VIN. However, the actual duty cycle is larger, due to losses, and must remain below 70% for a robust
design.
7.3.3 Enable
The device is enabled when the EN pin is set to high. With EN set to low, the device shuts down. After EN is set
high, the capacitor CCP (from CP to SW) is pre-charged with about 50mA. After the start-up delay time tdelay, the
device starts switching and ramps the output voltage to its target value. See Soft-Start.
The EN pin must be set externally to high or low. An internal pull-down resistor of about 400 kΩ is connected and
keeps EN low, if a low is detected internally and afterwards the pin is floating. When a high level is detected, the
internal resistor is disconnected. The logic levels are referenced to the IC´s GND pin.
7.3.4 Undervoltage Lockout
An undervoltage lockout circuit prevents the device from starting up and operating, if the supply voltage is too
low. The device automatically shuts down the converter when the VAUX voltage falls below the VUVLO threshold.
There is hysteresis to prevent oscillation with high impedance supply voltage sources. Once the threshold plus
hysteresis is exceeded, the device enters soft-start. Undervoltage lockout is sensed on the VAUX voltage, as this
is the internal supply for the control loop and logic.
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Feature Description (continued)
When VIN ramps down to a voltage too low to maintain the desired output voltage, the absolute value of the
output voltage drops and the power good output goes low. When the output voltage level reaches the voltage on
CCAP, at about 90% of the target output voltage, the device shuts down and initiates a re-start cycle. The
TPS63710 then stays in the start-up state, until the input voltage is high enough to reach the desired output
voltage.
7.3.5 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds the
thermal shutdown temperature TSD, the device turns off the internal power FETs, discharges the output capacitor
and the power good output goes low. It starts operation again when the junction temperature has decreased by
the thermal shutdown hysteresis.
7.3.6 Power Good Output
The TPS63710 has a built-in power good (PG) output to indicate whether or not the output voltage is in
regulation. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain
output that requires a pull-up resistor to any positive voltage up to 5.5 V. It can sink 1 mA of current and maintain
its specified logic low level. PG is low when the device is turned off due to EN = low, undervoltage lockout, or
thermal shutdown. There is a typical de-glitch time of 10 µs on the power good output. The minimum VIN to drive
the PG pin properly is typically 2 V. If not used, the PG pin may be left floating or connected to GND.
VAUX may be used to pull-up the PG pin, but the pull-up resistor must be chosen such that the maximum load of
100 µA on VAUX is not exceeded.
During start-up, the power good signal is gated by the soft-start circuit such that the output is held low as long as
the soft-start is ongoing.
Table 2. Power Good Pin Logic Table
EN
device status
PG state
X
VIN < 2 V
high impedance
low
VIN ≥ 2 V
low
high
2 V ≤ VIN < UVLO OR in thermal shutdown OR VOUT not in
regulation
low
high
VOUT in regulation
high impedance
7.4 Device Functional Modes
7.4.1 Soft-Start
The discharge circuit keeps the output voltage at 0 V when the TPS63710 is disabled. The TPS63710 only
begins the start-up cycle when the output voltage is between +300 mV to -300 mV to ensure a proper start-up.
When the output voltage is not in this range, the device keeps the discharge switch on and waits until the voltage
is within the window.
When the device is enabled, the internal reference is powered up. After the startup delay time when the CCP
capacitor is pre-charged, the device enters soft-start, starts switching and ramps down the output voltage. Softstart is achieved by ramping the reference voltage, hence the output voltage, to its nominal value. This ramp time
is defined by an external capacitor connected to the CAP pin. The capacitor is charged with typically 100 µA by
an internal current source. The ramp time is defined in Equation 2.
tramp = CCAP´VREF
Iramp
=
CCAP´0.9´VOUT
Iramp
(2)
7.4.2 VOUT Discharge
The VOUT pin has a discharge circuit to connect the output to GND, once the device is disabled. This feature
prevents residual voltages on the output capacitor. The discharge circuit becomes active when VIN drops below
VUVLO, EN=low, or thermal shutdown occurs. The minimum supply voltage required to drive the discharge switch
is typically 2 V.
10
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Device Functional Modes (continued)
7.4.3 Current Limit
A current limit protects the device against short circuits at the output. The current limit is scaled down from its
nominal value for input voltages below 4 V. The current limit monitors the peak current in the LSD during the ONtime. If this current is reached during the ON-time, the LSD is turned off and the HSD and RECT turned on to
decrease the current. The next ON-time begins at the next switching cycle.
A short circuit from VIN to GND during operation should be avoided as this leads to a high current discharging
the CCP capacitor through the back-gate diode of the high side switch to GND. When there is an overload on the
output and the output voltage drops below 0.9 times the target output voltage, the device re-starts.
7.4.4 CCP Capacitor Precharge
The CCP capacitor is pre-charged during the start-up delay phase by a current that increases up to 50 mA based
on the voltage of VIN - VCP. When the voltage on CCP reaches approximately the VIN level, the device starts
switching.
7.4.5 PWM Operation
The converter operates with a fixed-frequency, pulse-width-modulated control. In the OFF-time, the rectifier
switch (RECT) and the high-side switch (HSD) are turned on to charge CCP to the input voltage. As well, the
inductor current ramps down, continuing to charge the output capacitor. During the ON-time, the low-side switch
(LSD) is closed and HSD and RECT are opened. CCP inverts the supply voltage onto SW, and the inductor
current is ramped up. The LC output filter filters the SW voltage, just like in a step-down converter. Charging the
CCP capacitor during the OFF-time limits the maximum duty cycle. The upper limit of the duty cycle is 70% to
allow charging the CCP capacitor in the remaining 30%.
Lower negative voltages require higher positive supply voltages. For an output voltage of -1.8 V, a minimum input
voltage of 4.5 V is sufficient while for an output voltage of -3.3 V, the input voltage has to be above 6 V. See
Figure 37 to Figure 39 for the relation of input voltage, output voltage and temperature vs output current.
For high input voltages and, in absolute value, small output voltages, the device operates with its minimum ontime (ton,min) to generate the duty cycle required for this VIN and VOUT ratio. This means that, for such cases, the
switching frequency is lower than fS.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS63710 is intended for systems typically powered by a pre-regulated power supply but can also run on a
battery with a supply voltage range between 3.1 V and 14 V.
8.2 Typical Application
The application covers the input voltage range from 4.5 V to 14 V at the full 1-A output current. The output
capacitors are designed for an output voltage of -1.8 V. With output voltages below -1.8V (larger negative
voltages), the output capacitance has to be increased as described in the Detailed Design Procedure. The
minimum supply voltage is defined by the 70% duty cycle limit, output current and the output voltage. Please see
Figure 37 to Figure 39 for the recommended input voltage levels to generate a specific output voltage.
VIN = 4.5V to 14V
2.2uF / 16V
0603
CIN
3 x 10uF
16V / 0805
TPS63710
VIN
CP
CCP
VOUT = -1.8V
L
2 x 22uF
16V
SW
EN
4.7 uH
2 x 22uF
COUT 10V / 0805
VOUT
VREF
R1
CAP
CCAP
FB
1uF
R2
+V
VAUX
CAUX
R3
100kΩ
PG
GND
220nF
Copyright © 2017, Texas Instruments Incorporated
Figure 10. Typical Application for an Input Voltage up to 14V
8.2.1 Design Requirements
The design of the inverter can be adapted to different output voltages and load currents. The following
components cover an input voltage range up to 9 V. For CIN, a 0603 capacitor close to the device pins is
required in addition to the larger capacitor. As the CCP capacitor has the same voltage across it, its dc bias effect
is similar to CIN. Table 3 gives examples for the schematics optimized for different input and output voltage
ranges.
Table 3. Bill of Materials
Reference
Part Number
Value
IC
TPS63710DRR
CIN
EMK107BB7225KA-T
EMK316BB7226ML-T
Manufacturer
Texas Instruments
2.2 µF / 16 V +
2 x 22 µF / 16 V
Taiyo Yuden
Taiyo Yuden
CCP
EMK212BB7106MG-T
3 x 10 µF / 16V
COUT
C2012X7S1A226M125AC
2 x 22 µF / 10 V
TDK
L
XFL4020-222
2.2 µH
Coilcraft
CCAP
885012206026
1 µF / 10 V
Würth
CAUX
885012206022
220 nF / 10 V
Würth
(1)
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Typical Application (continued)
Table 3. Bill of Materials (continued)
Reference
Part Number
Value
R1
196 kΩ
R2
150 kΩ
R3
100 kΩ
Manufacturer
(1)
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63710 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting the Output Voltage
The output voltage of the TPS63710 converter is adjusted with an external resistor divider connected to the FB
pin. The voltage at the feedback pin is negative and is regulated to -0.7 V. The gain stage adds a gain factor of
1/0.9 such that the output voltage is -0.778 V for -0.7 V of FB voltage. See Low Noise Reference System for
details.
The value of the output voltage is set by the selection of the resistive divider using Equation 3 and VFB_SET =
-0.778 V. Both VOUT and VFB_SET are negative, so the ratio is positive again.
æ VOUT
ö
- 1÷
R1 = R 2 ´ ç
è VFB _ SET ø
(3)
It is recommended to choose resistor values such that R1 + R2 are in a range from 100 kΩ to 500 kΩ. For
example, if an output voltage of -1.8 V is needed and a resistor of 150-kΩ has been chosen for R2, a 196-kΩ
resistor on R1 is required to program the desired output voltage.
Table 4. Recommended Resistor Values
Output Voltage
R1
R2
-1 V
51.1 kΩ
180 kΩ
-1.8 V
196 kΩ
150 kΩ
-2.5 V
287 kΩ
130 kΩ
-5 V
130 kΩ
24 kΩ
For proper regulation, the minimum input voltage should remain at least above the output voltage, per
Equation 4:
VIN ³
1
´ | VOUT |
0 .7
(4)
See Figure 37 to Figure 39 for the recommended input voltage levels to generate a specific output voltage.
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8.2.2.3 Inductor Selection
The basic parameters for choosing an appropriate inductor is saturation current, as well as the dc resistance of
the inductor. The TPS63710 is designed such that it operates with an inductance as given in the recommended
operating conditions. For best performance, a nominal inductance of 2.2 µH should be used for input voltages
below 9 V. For input voltages above 9 V, a nominal inductance of 4.7 µH is preferred to keep the inductor current
ripple at a reasonable level.
Similar to a step-down converter, the inductor along with the output capacitor forms a LC filter. For noisesensitive applications, larger values for the inductance and output capacitance are preferred to get the noise
level at the output to very low values.
The peak inductor current depends on the output load, the input voltage VIN, and the output voltage VOUT. The
average inductor current equals the load current.
The topology can be simplified to an inverter stage followed by a step-down converter. The equations for
calculating the inductor current of a step-down converter therefore also apply. The worst case inductor ripple
current occurs at 50% duty cycle which is when VIN = 2 x |VOUT|. The voltage across the inductor is VIN - |VOUT|,
which is 0.5 x VIN at 50% duty cycle. With this, Equation 5 and dt = 0.5 x 1/fS, the peak to peak inductor ripple
current is defined by Equation 6. The inductor´s saturation current must remain above its peak current which is
calculated in Equation 7. Table 5 shows a list of recommended inductors.
dI
dt
VIN ´ 0.5 1
| VOUT | 1
DIpp =
´ ´ 0 .5 =
´ ´ 0 .5
L
fS
L
fS
1
ILpeak = IOUT + DIpp
2
V = L´
(5)
(6)
(7)
Table 5. List of Inductors
(1)
Suggested Inductor (1)
Input Voltage
Vendor
comment
3.1 V to 9 V
Coilcraft
3.1 V to 9 V
Coilcraft
best performance for low
input voltage
XFL4020-222ME
low cost; small size
DFE252012F-2R2M
XFL3012-222ME
3.1 V to 9 V
Toko
3.1 V to 14 V
Coilcraft
XFL4020-472ME
3.1 V to 14 V
Würth
744 383 570 47
See Third-party Products Disclaimer
8.2.2.4 Capacitor Selection
8.2.2.4.1 CCP Capacitor
The capacitance of CCP determines the maximum output current of TPS63710. Therefore it is selected at first. A
minimum 4-uF of effective capacitance is required to support the full output current of 1 A. Only ceramic
capacitors like X7R, X5R or equivalent are recommended. For applications that require a lower maximum output
current, its value can be reduced linearly. As the voltage at the CCP capacitor is equal to the input voltage VIN,
the dc bias effect has to be taken into account based on the maximum input voltage. Table 6 shows
recommended CCP capacitors.
Table 6. CCP Capacitor Selection
package size
number of capacitors
required for 1A of output
current based on dc bias
effect
Suggested Capacitors (1)
> VIN
0805
2
EMK212BB7106MG-T
> VIN
0805
3
EMK212BB7106MG-T
input voltage
range; VIN
nominal value
voltage rating
3.1 V to 6 V
10 µF
3.1 V to 14 V
10 µF
(1)
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8.2.2.4.2 Input Capacitor
The capacitance of the input capacitor should be at least twice the capacitance of CCP. At least a 22-μF ceramic
input capacitor is recommended for a good transient behavior of the regulator and EMI behavior of the total
power supply circuit. The capacitor must be located as close to the VIN and GND pins as possible. Only ceramic
capacitors like X7R, X5R or equivalent are recommended. A 0603 size 2.2-µF ceramic capacitor in parallel to the
main input capacitor is recommended to reduce high frequency noise. The input capacitance can be increased
without limit. Table 7 shows recommended capacitors.
Table 7. Input Capacitor Selection
input voltage
range; VIN
nominal value
voltage
rating
package size
number of capacitors
required for 1A of
output current based
on dc bias effect
Suggested Capacitors (1)
3.1 V to 6 V
2 x capacitance of CCP
> VIN
1206
2
EMK316BB7226ML-T
3.1 V to 14 V
2 x capacitance of CCP
> VIN
1206
3
EMK316BB7226ML-T
(1)
See Third-party Products Disclaimer
8.2.2.4.3 Output Capacitor
One of the major parameters necessary to define the capacitance value of the output capacitor is the maximum
allowed output voltage ripple of the converter and device stability. Internal device compensation defines the limits
for the capacitance on the output. Only ceramic capacitors like X7R, X5R or equivalent are recommended. Table
Table 8 gives the minimum amount of capacitors required for a given output voltage based on the dc bias effect.
For lowest output voltage ripple, more capacitance can be added up to the maximum value as defined in the
recommended operating conditions.
Table 8. Output Capacitor Selection
output voltage range;
VOUT
nominal value
voltage
rating
package size
number of capacitors
required based on dc
bias effect
-1 V to -3.3 V
22 µF
≥ 6.3 V
0805
2
C2012X7S1A226M125AC
- 1 V to -5.5 V
22 µF
≥ 10 V
0805
3
C2012X7S1A226M125AC
(1)
Suggested Capacitors
(1)
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8.2.3 Application Curves
8.2.3.1 Parameter Measurement Information
The application curves have been taken using the schematic in Figure 10 and BOM according Table 3. Based on
the output voltage, the components given in Table 9 have been changed. The resistor divider is based on
Table 4.
Table 9. Component Selection for VOUT Options
CCP
L
COUT
2 x EMK212BB7106MG-T
XFL4020-222ME
2 x C2012X7S1A226M125AC
-3.3 V and -5 V
3 x EMK212BB7106MG-T
XFL4020-472ME
3 x C2012X7S1A226M125AC
90
100
80
90
70
80
70
60
Efficiency (%)
Efficiency (%)
VOUT
-1 V and -1.8 V
50
40
VIN = 3.3 V
VIN = 4 V
VIN = 5 V
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
30
20
10
60
50
40
VIN = 4.5 V
VIN = 5 V
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
30
20
10
0
0
0
0.1
0.2
VOUT = -1 V
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
0
1
0.1
IOUT = 0 A to 1 A
TA = 25°C
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
90
60
50
40
0.9
1
D004
IOUT = 0 A to 1 A
TA = 25°C
60
50
40
20
VIN = 9 V
VIN = 12 V
VIN = 14 V
10
0
0
0
0.1
0.2
VOUT = -3.3 V
0.3
0.4 0.5 0.6 0.7
Output Current (A)
IOUT = 0 A to 1 A
0.8
0.9
1
0
0.1
0.2
D013
TA = 25°C
VOUT = -5 V
Figure 13. Efficiency vs Output Current
16
0.8
30
VIN = 6 V
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
10
0.4 0.5 0.6 0.7
Output Current (A)
Figure 12. Efficiency vs Output Current
100
20
0.3
VOUT = -1.8 V
Figure 11. Efficiency vs Output Current
30
0.2
D003
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0.3
0.4 0.5 0.6 0.7
Output Current (A)
IOUT = 0 A to 1 A
0.8
0.9
1
D006
TA = 25°C
Figure 14. Efficiency vs Output Current
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-0.99
-1.78
VIN = 3.3 V
VIN = 4 V
VIN = 5 V
VIN = 7 V
-0.992
-0.994
VIN = 9 V
VIN = 12 V
VIN = 14 V
VIN = 4.5 V
VIN = 5 V
VIN = 7 V
VIN = 9 V
-1.785
VIN = 12 V
VIN = 14 V
Output Voltage (V)
Output Voltage (V)
-1.79
-0.996
-0.998
-1
-1.002
-1.004
-1.795
-1.8
-1.805
-1.81
-1.006
-1.815
-1.008
-1.01
-1.82
0
0.1
0.2
VOUT = -1 V
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
0
0.1
0.2
0.3
D009
IOUT = 0 A to 1 A
TA = 25°C
VOUT = -1.8 V
Figure 15. Output Voltage vs Output Current
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
D010
IOUT = 0 A to 1 A
TA = 25°C
Figure 16. Output Voltage vs Output Current
-4.95
-3.27
-4.96
-4.97
Output Voltage (V)
Output Voltage (V)
-3.28
-3.29
-3.3
-3.31
VIN = 6 V
VIN = 7 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
-3.32
0.1
0.2
VOUT = -3.3 V
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
TA = 25°C
IOUT = 100 mA to
900 mA
-5.02
VIN = 9 V
VIN = 12 V
VIN = 14 V
-5.05
1
Figure 17. Output Voltage vs Output Current
VIN = 5 V
VOUT = -1 V
-5
-5.01
-5.04
D017
IOUT = 0 A to 1 A
-4.99
-5.03
-3.33
0
-4.98
TA = 25°C
0
0.1
0.2
VOUT = -5 V
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
IOUT = 0 A to 1 A
0.9
1
D012
TA = 25°C
Figure 18. Output Voltage vs Output Current
VIN = 5 V
VOUT = -1.8 V
Figure 19. Load Transient Response
IOUT = 100 mA to
900 mA
TA = 25°C
Figure 20. Load Transient Response
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VIN = 9 V
VOUT = -3.3 V
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IOUT = 100 mA to
900 mA
TA = 25°C
VIN = 9 V
VOUT = -5 V
IOUT = 0.5 A
TA = 25°C
VIN = 4 V to 5 V to 4 V
VOUT = -1.8 V
Figure 23. Line Transient Response
VIN = 9 V to 12 V to 9 V
VOUT = -3.3 V
IOUT = 0.5 A
IOUT = 0.5 A
TA = 25°C
Figure 24. Line Transient Response
TA = 25°C
VIN = 9 V to 12 V to 9 V
VOUT = -5 V
Figure 25. Line Transient Response
18
TA = 25°C
Figure 22. Load Transient Response
Figure 21. Load Transient Response
VIN = 4 V to 6 V to 4 V
VOUT = -1 V
IOUT = 100 mA to
900 mA
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IOUT = 0.5 A
TA = 25°C
Figure 26. Line Transient Response
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VIN = 5 V
VOUT = -1 V
IOUT = 0.5 A
TA = 25°C
VIN = 5 V
VOUT = -1.8 V
Figure 27. Start-Up Timing
VIN = 9 V
VOUT = -3.3 V
TA = 25°C
Figure 28. Start-Up Timing
IOUT = 0.5 A
TA = 25°C
VIN = 9 V
VOUT = -5 V
Figure 29. Start-Up Timing
VIN = 5 V
VOUT = -1 V
IOUT = 0.5 A
IOUT = 0.5 A
TA = 25°C
Figure 30. Start-Up Timing
IOUT = 1 A
L = 2.2 µH
TA = 25°C
VIN = 5 V
VOUT = -1.8 V
Figure 31. Output Voltage Ripple
IOUT = 1 A
L = 2.2 µH
TA = 25°C
Figure 32. Output Voltage Ripple
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VIN = 9 V
VOUT = -3.3 V
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IOUT = 1 A
L = 2.2 µH
TA = 25°C
VIN = 9 V
VOUT = -5 V
Figure 33. Output Voltage Ripple
VIN = 12 V
VOUT = -1.8 V
IOUT = 1 A
L = 2.2 µH
VIN = 12 V
VOUT = -5 V
1.2
1
1
Output Current (A)
Output Current (A)
1.2
0.8
0.6
0.4
5V
3.3 V
1V
1.8 V
TA = 25°C
0.8
0.6
0.4
VOUT =
VOUT =
VOUT =
VOUT =
0.2
0
5V
3.3 V
1.8 V
1V
0
3
5
7
9
11
Input Voltage (V)
13
15
3
D014
TA = 25°C
Figure 37. Maximum Output Current vs Input Voltage
20
IOUT = 1 A
L = 4.7 µH
Figure 36. Output Voltage Ripple
Figure 35. Output Voltage Ripple
0.2
TA = 25°C
Figure 34. Output Voltage Ripple
TA = 25°C
VOUT =
VOUT =
VOUT =
VOUT =
IOUT = 1 A
L = 4.7 µH
6
9
Input Voltage (V)
12
15
D015
TA = 85°C
Figure 38. Maximum Output Current vs Input Voltage
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1.2
VOUT = -1 V
VOUT = -1.8 V
VOUT = -3.3 V
VOUT = -5 V
V
Output Noise Density (
Output Current (A)
1
0.8
0.6
0.4
VOUT =
VOUT =
VOUT =
VOUT =
0.2
Hz
)
10µ
5V
3.3 V
1V
1.8 V
1µ
100n
0
3
5
7
9
11
Input Voltage (V)
13
10
15
100
1k
Frequency (Hz)
D016
10k
IOUT = 0.2 A
TA = 125°C
100k
D021a
TA = 25°C
Figure 40. Output Noise Density
Figure 39. Maximum Output Current vs Input Voltage
10µ
V
Output Noise Density (
Hz
)
VOUT = -1 V
VOUT = -1.8 V
VOUT = -3.3 V
VOUT = -5 V
Vnoise = 22mVrms
at Vout = -1.8V
BW = 10Hz to 100kHz
1µ
100n
10
100
IOUT = 1 A
1k
Frequency (Hz)
10k
100k
D022a
TA = 25°C
Figure 41. Output Noise Density
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8.3 System Examples
8.3.1 Typical Application for Powering the Negative Rail of a Gallium Nitride (GaN) Power Amplifier
The TPS63710 requires a supply voltage in the range of 8.8 V to 14 V in order to generate an output voltage of
-5 V. The circuit therefore was optimized for this input voltage range. The number of the input, output and CCP
capacitors have been adjusted to compensate for the higher dc bias effect with large input and output voltages.
In addition, the inductor has been changed to 4.7 µH for low inductor current ripple at an input voltage up to 14
V.
2.2uF / 16V
0603
VIN = 8.8V to 14V
CIN
3 x 10uF
TPS63710
VIN
CP
CCP 16V / 0805
VOUT = -5V
L
2 x 22uF
16V
SW
EN
4.7uH
3 x 22uF
COUT 10V / 0805
VOUT
VREF
CCAP
CAP
1uF
CAUX
220nF
130kΩ
R1
24kΩ
R2
FB
+V
VAUX
R3
100kΩ
PG
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 42. Typical Application for an Output Voltage of -5 V
8.3.2 Typical Application for Powering the Negative Rail of an ADC or DAC
Typically, the input voltage to the inverter in applications powering the negative supply of an ADC or DAC is
about 5 V. The circuit therefore was optimized for this input voltage range, because the size and amount of
capacitors depends on the voltage applied to the capacitors. In order not to over-design, the input voltage range
was set to the range required to set a limit for the dc bias of the capacitors. Figure 43 shows a, for an input
voltage of 5-V, optimized design. The minimum input voltage to support the full output current is 4.5 V. The
maximum input voltage is defined by the dc bias characteristic of the input and CCP capacitors. If a higher input
voltage is required, these capacitors have to be adjusted accordingly.
22
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SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
System Examples (continued)
VIN = 4.5V to 6V
2.2uF / 16V
0603
CP
VIN
CIN
2 x 10uF
16V / 0805
TPS63710
CCP
VOUT = -1.8V
L
22uF
16V
SW
EN
2.2 uH
2 x 22uF
COUT 10V / 0805
VOUT
VREF
CCAP
196kΩ
CAP
FB
1uF
CAUX
150kΩ
+V
VAUX
R3
100kΩ
PG
GND
220nF
Copyright © 2017, Texas Instruments Incorporated
Figure 43. Typical Application for VIN ≈ 5 V
8.3.3 Typical Application for Laser Diode Bias
Laser diode bias typically requires a voltage of about -1 V from a 3.3 V supply. The TPS63710 was optimized for
these operating conditions. The passive components have been chosen for a fixed supply voltage of 3.3 V. The
number of the input, output and CCP capacitors have been adjusted for the input and output voltage in this
application.
VIN = 3.3V
2.2uF / 16V
0603
VIN
CIN
10uF
16V / 0805
TPS63710
CP
CCP
VOUT = -1V, 0.8A
L
22uF
10V / 0805
SW
EN
2.2 uH
2 x 22uF
COUT 10V / 0805
VOUT
VREF
CAP
CCAP
1uF
CAUX
220nF
51.1kΩ
R1
180kΩ
R2
FB
+V
VAUX
R3
100kΩ
PG
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Typical Application for an Output Voltage of -1 V
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TPS63710
SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
www.ti.com
9 Power Supply Recommendations
The power supply to the TPS63710 needs to have a current rating according to the input supply voltage, output
voltage and output current of the TPS63710. The peak current requirement on the input depends on the duty
cycle, as CCP is charged during the off-time. Worst case is for the maximum duty cycle of 70% when the OFFtime is at its shortest value of 30%. The peak current on the input can be up to 5 times of the average output
current. A proper input capacitor needs to be placed directly at the VIN and GND pins to supply the peak current
demand of the converter. Slew rates faster than 1 V/µs for a VIN step of less than 1 V and 0.1 V/µs for a VIN step
over the full input voltage range up to 14 V should be avoided, as this leads to a large inrush current through the
CCP capacitor and HSD.
When the input supply of TPS63710 is shorted while the device is enabled, the charge stored on the CCP
capacitor is transferred to the output. This may cause an output voltage undershoot. It is recommended to
disable the TPS63710 by setting the EN pin to low while the supply voltage is within the recommended input
voltage range. This ensures a proper shutdown.
24
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SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
10 Layout
10.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current paths, and for the power-ground
tracks. The input, output and CP capacitors should be placed as close as possible to the IC. Because CVAUX
carries the peak currents of the gate control block, it should have a compact and direct routing to the VAUX and
GND pin 10, staying away from sensitive signals. The CAP, FB, and VREF pins should all be routed close to the
IC in order to keep them away from external noise. The total resistance of the voltage divider R1 + R2 must be
kept in the range as defined in the Recommended Operating Conditions.
The pinout of the device has been defined such that the external components can be placed directly at the pins
to allow for a simplified external layout and good performance. Thermal and electrical vias should be used under
the exposed thermal pad to the GND plane.
10.2 Layout Example
CCP PAC1001
PAC1002
PAC901 PAC902
PAC801 PAC802
VIN
CIN
L
VOUT
SW
VOUT
CP
GND
GND
VIN
PAC401 PAC301 PAC201
PAC1101
COUT
FB
PAC1102
CAP
PG
VREF
EN
VAUX
PANT101
CCAP
CAUX
GND
R3
R2
GND
R1
Figure 45. Recommended Layout
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TPS63710
SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS63710 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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SLVSD44A – SEPTEMBER 2017 – REVISED JULY 2018
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS63710
27
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS63710DRRR
ACTIVE
SON
DRR
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
63710
TPS63710DRRT
ACTIVE
SON
DRR
12
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
63710
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS63710DRRR
SON
DRR
12
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS63710DRRT
SON
DRR
12
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS63710DRRR
SON
DRR
12
3000
367.0
367.0
35.0
TPS63710DRRT
SON
DRR
12
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRR0012C
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
EXPOSED
THERMAL PAD
1.5±0.1
7
6
13
2.5±0.1
SYMM
1
PIN 1 ID
(OPTIONAL)
12
12X
SYMM
12X
(0.1) TYP
10X 0.5
0.5
0.3
2X
2.5
0.3
0.2
0.1
0.05
C A B
4222932/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRR0012C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
12X (0.6)
(R0.05) TYP
SYMM
1
12
12X (0.25)
13
SYMM
(2.5)
(1)
10X (0.5)
6
( 0.2) VIA
TYP
7
(0.5)
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222932/A 05/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRR0012C
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
12X (0.6)
2X (1.38)
1
12
12X (0.25)
2X (1.11)
SYMM
(0.66)
10X (0.5)
7
6
13
SYMM
METAL
TYP
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13
81.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222932/A 05/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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